pcmuio.c revision 75d46fd7816ea5a22971b05e59c356f3964754a9
1/* 2 * pcmuio.c 3 * Comedi driver for Winsystems PC-104 based 48/96-channel DIO boards. 4 * 5 * COMEDI - Linux Control and Measurement Device Interface 6 * Copyright (C) 2006 Calin A. Culianu <calin@ajvar.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19/* 20 * Driver: pcmuio 21 * Description: Winsystems PC-104 based 48/96-channel DIO boards. 22 * Devices: (Winsystems) PCM-UIO48A [pcmuio48] 23 * (Winsystems) PCM-UIO96A [pcmuio96] 24 * Author: Calin Culianu <calin@ajvar.org> 25 * Updated: Fri, 13 Jan 2006 12:01:01 -0500 26 * Status: works 27 * 28 * A driver for the relatively straightforward-to-program PCM-UIO48A and 29 * PCM-UIO96A boards from Winsystems. These boards use either one or two 30 * (in the 96-DIO version) WS16C48 ASIC HighDensity I/O Chips (HDIO). This 31 * chip is interesting in that each I/O line is individually programmable 32 * for INPUT or OUTPUT (thus comedi_dio_config can be done on a per-channel 33 * basis). Also, each chip supports edge-triggered interrupts for the first 34 * 24 I/O lines. Of course, since the 96-channel version of the board has 35 * two ASICs, it can detect polarity changes on up to 48 I/O lines. Since 36 * this is essentially an (non-PnP) ISA board, I/O Address and IRQ selection 37 * are done through jumpers on the board. You need to pass that information 38 * to this driver as the first and second comedi_config option, respectively. 39 * Note that the 48-channel version uses 16 bytes of IO memory and the 96- 40 * channel version uses 32-bytes (in case you are worried about conflicts). 41 * The 48-channel board is split into two 24-channel comedi subdevices. The 42 * 96-channel board is split into 4 24-channel DIO subdevices. 43 * 44 * Note that IRQ support has been added, but it is untested. 45 * 46 * To use edge-detection IRQ support, pass the IRQs of both ASICS (for the 47 * 96 channel version) or just 1 ASIC (for 48-channel version). Then, use 48 * comedi_commands with TRIG_NOW. Your callback will be called each time an 49 * edge is triggered, and the data values will be two sample_t's, which 50 * should be concatenated to form one 32-bit unsigned int. This value is 51 * the mask of channels that had edges detected from your channel list. Note 52 * that the bits positions in the mask correspond to positions in your 53 * chanlist when you specified the command and *not* channel id's! 54 * 55 * To set the polarity of the edge-detection interrupts pass a nonzero value 56 * for either CR_RANGE or CR_AREF for edge-up polarity, or a zero value for 57 * both CR_RANGE and CR_AREF if you want edge-down polarity. 58 * 59 * In the 48-channel version: 60 * 61 * On subdev 0, the first 24 channels channels are edge-detect channels. 62 * 63 * In the 96-channel board you have the following channels that can do edge 64 * detection: 65 * 66 * subdev 0, channels 0-24 (first 24 channels of 1st ASIC) 67 * subdev 2, channels 0-24 (first 24 channels of 2nd ASIC) 68 * 69 * Configuration Options: 70 * [0] - I/O port base address 71 * [1] - IRQ (for first ASIC, or first 24 channels) 72 * [2] - IRQ (for second ASIC, pcmuio96 only - IRQ for chans 48-72 73 * can be the same as first irq!) 74 */ 75 76#include <linux/module.h> 77#include <linux/interrupt.h> 78 79#include "../comedidev.h" 80 81#include "comedi_fc.h" 82 83/* 84 * Register I/O map 85 * 86 * Offset Page 0 Page 1 Page 2 Page 3 87 * ------ ----------- ----------- ----------- ----------- 88 * 0x00 Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O 89 * 0x01 Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O 90 * 0x02 Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O 91 * 0x03 Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O 92 * 0x04 Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O 93 * 0x05 Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O 94 * 0x06 INT_PENDING INT_PENDING INT_PENDING INT_PENDING 95 * 0x07 Page/Lock Page/Lock Page/Lock Page/Lock 96 * 0x08 N/A POL_0 ENAB_0 INT_ID0 97 * 0x09 N/A POL_1 ENAB_1 INT_ID1 98 * 0x0a N/A POL_2 ENAB_2 INT_ID2 99 */ 100#define PCMUIO_PORT_REG(x) (0x00 + (x)) 101#define PCMUIO_INT_PENDING_REG 0x06 102#define PCMUIO_PAGE_LOCK_REG 0x07 103#define PCMUIO_LOCK_PORT(x) ((1 << (x)) & 0x3f) 104#define PCMUIO_PAGE(x) (((x) & 0x3) << 6) 105#define PCMUIO_PAGE_MASK PCMUIO_PAGE(3) 106#define PCMUIO_PAGE_POL 1 107#define PCMUIO_PAGE_ENAB 2 108#define PCMUIO_PAGE_INT_ID 3 109#define PCMUIO_PAGE_REG(x) (0x08 + (x)) 110 111#define PCMUIO_ASIC_IOSIZE 0x10 112#define PCMUIO_MAX_ASICS 2 113 114struct pcmuio_board { 115 const char *name; 116 const int num_asics; 117}; 118 119static const struct pcmuio_board pcmuio_boards[] = { 120 { 121 .name = "pcmuio48", 122 .num_asics = 1, 123 }, { 124 .name = "pcmuio96", 125 .num_asics = 2, 126 }, 127}; 128 129struct pcmuio_asic { 130 spinlock_t pagelock; /* protects the page registers */ 131 spinlock_t spinlock; /* protects member variables */ 132 unsigned int enabled_mask; 133 unsigned int stop_count; 134 unsigned int active:1; 135}; 136 137struct pcmuio_private { 138 struct pcmuio_asic asics[PCMUIO_MAX_ASICS]; 139 unsigned int irq2; 140}; 141 142static inline unsigned long pcmuio_asic_iobase(struct comedi_device *dev, 143 int asic) 144{ 145 return dev->iobase + (asic * PCMUIO_ASIC_IOSIZE); 146} 147 148static inline int pcmuio_subdevice_to_asic(struct comedi_subdevice *s) 149{ 150 /* 151 * subdevice 0 and 1 are handled by the first asic 152 * subdevice 2 and 3 are handled by the second asic 153 */ 154 return s->index / 2; 155} 156 157static inline int pcmuio_subdevice_to_port(struct comedi_subdevice *s) 158{ 159 /* 160 * subdevice 0 and 2 use port registers 0-2 161 * subdevice 1 and 3 use port registers 3-5 162 */ 163 return (s->index % 2) ? 3 : 0; 164} 165 166static void pcmuio_write(struct comedi_device *dev, unsigned int val, 167 int asic, int page, int port) 168{ 169 struct pcmuio_private *devpriv = dev->private; 170 struct pcmuio_asic *chip = &devpriv->asics[asic]; 171 unsigned long iobase = pcmuio_asic_iobase(dev, asic); 172 unsigned long flags; 173 174 spin_lock_irqsave(&chip->pagelock, flags); 175 if (page == 0) { 176 /* Port registers are valid for any page */ 177 outb(val & 0xff, iobase + PCMUIO_PORT_REG(port + 0)); 178 outb((val >> 8) & 0xff, iobase + PCMUIO_PORT_REG(port + 1)); 179 outb((val >> 16) & 0xff, iobase + PCMUIO_PORT_REG(port + 2)); 180 } else { 181 outb(PCMUIO_PAGE(page), iobase + PCMUIO_PAGE_LOCK_REG); 182 outb(val & 0xff, iobase + PCMUIO_PAGE_REG(0)); 183 outb((val >> 8) & 0xff, iobase + PCMUIO_PAGE_REG(1)); 184 outb((val >> 16) & 0xff, iobase + PCMUIO_PAGE_REG(2)); 185 } 186 spin_unlock_irqrestore(&chip->pagelock, flags); 187} 188 189static unsigned int pcmuio_read(struct comedi_device *dev, 190 int asic, int page, int port) 191{ 192 struct pcmuio_private *devpriv = dev->private; 193 struct pcmuio_asic *chip = &devpriv->asics[asic]; 194 unsigned long iobase = pcmuio_asic_iobase(dev, asic); 195 unsigned long flags; 196 unsigned int val; 197 198 spin_lock_irqsave(&chip->pagelock, flags); 199 if (page == 0) { 200 /* Port registers are valid for any page */ 201 val = inb(iobase + PCMUIO_PORT_REG(port + 0)); 202 val |= (inb(iobase + PCMUIO_PORT_REG(port + 1)) << 8); 203 val |= (inb(iobase + PCMUIO_PORT_REG(port + 2)) << 16); 204 } else { 205 outb(PCMUIO_PAGE(page), iobase + PCMUIO_PAGE_LOCK_REG); 206 val = inb(iobase + PCMUIO_PAGE_REG(0)); 207 val |= (inb(iobase + PCMUIO_PAGE_REG(1)) << 8); 208 val |= (inb(iobase + PCMUIO_PAGE_REG(2)) << 16); 209 } 210 spin_unlock_irqrestore(&chip->pagelock, flags); 211 212 return val; 213} 214 215/* 216 * Each channel can be individually programmed for input or output. 217 * Writing a '0' to a channel causes the corresponding output pin 218 * to go to a high-z state (pulled high by an external 10K resistor). 219 * This allows it to be used as an input. When used in the input mode, 220 * a read reflects the inverted state of the I/O pin, such that a 221 * high on the pin will read as a '0' in the register. Writing a '1' 222 * to a bit position causes the pin to sink current (up to 12mA), 223 * effectively pulling it low. 224 */ 225static int pcmuio_dio_insn_bits(struct comedi_device *dev, 226 struct comedi_subdevice *s, 227 struct comedi_insn *insn, 228 unsigned int *data) 229{ 230 int asic = pcmuio_subdevice_to_asic(s); 231 int port = pcmuio_subdevice_to_port(s); 232 unsigned int chanmask = (1 << s->n_chan) - 1; 233 unsigned int mask; 234 unsigned int val; 235 236 mask = comedi_dio_update_state(s, data); 237 if (mask) { 238 /* 239 * Outputs are inverted, invert the state and 240 * update the channels. 241 * 242 * The s->io_bits mask makes sure the input channels 243 * are '0' so that the outputs pins stay in a high 244 * z-state. 245 */ 246 val = ~s->state & chanmask; 247 val &= s->io_bits; 248 pcmuio_write(dev, val, asic, 0, port); 249 } 250 251 /* get inverted state of the channels from the port */ 252 val = pcmuio_read(dev, asic, 0, port); 253 254 /* return the true state of the channels */ 255 data[1] = ~val & chanmask; 256 257 return insn->n; 258} 259 260static int pcmuio_dio_insn_config(struct comedi_device *dev, 261 struct comedi_subdevice *s, 262 struct comedi_insn *insn, 263 unsigned int *data) 264{ 265 int asic = pcmuio_subdevice_to_asic(s); 266 int port = pcmuio_subdevice_to_port(s); 267 int ret; 268 269 ret = comedi_dio_insn_config(dev, s, insn, data, 0); 270 if (ret) 271 return ret; 272 273 if (data[0] == INSN_CONFIG_DIO_INPUT) 274 pcmuio_write(dev, s->io_bits, asic, 0, port); 275 276 return insn->n; 277} 278 279static void pcmuio_reset(struct comedi_device *dev) 280{ 281 const struct pcmuio_board *board = dev->board_ptr; 282 int asic; 283 284 for (asic = 0; asic < board->num_asics; ++asic) { 285 /* first, clear all the DIO port bits */ 286 pcmuio_write(dev, 0, asic, 0, 0); 287 pcmuio_write(dev, 0, asic, 0, 3); 288 289 /* Next, clear all the paged registers for each page */ 290 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_POL, 0); 291 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_ENAB, 0); 292 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_INT_ID, 0); 293 } 294} 295 296/* chip->spinlock is already locked */ 297static void pcmuio_stop_intr(struct comedi_device *dev, 298 struct comedi_subdevice *s) 299{ 300 struct pcmuio_private *devpriv = dev->private; 301 int asic = pcmuio_subdevice_to_asic(s); 302 struct pcmuio_asic *chip = &devpriv->asics[asic]; 303 304 chip->enabled_mask = 0; 305 chip->active = 0; 306 s->async->inttrig = NULL; 307 308 /* disable all intrs for this subdev.. */ 309 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_ENAB, 0); 310} 311 312static void pcmuio_handle_intr_subdev(struct comedi_device *dev, 313 struct comedi_subdevice *s, 314 unsigned triggered) 315{ 316 struct pcmuio_private *devpriv = dev->private; 317 int asic = pcmuio_subdevice_to_asic(s); 318 struct pcmuio_asic *chip = &devpriv->asics[asic]; 319 struct comedi_cmd *cmd = &s->async->cmd; 320 unsigned oldevents = s->async->events; 321 unsigned int val = 0; 322 unsigned long flags; 323 unsigned int i; 324 325 spin_lock_irqsave(&chip->spinlock, flags); 326 327 if (!chip->active) 328 goto done; 329 330 if (!(triggered & chip->enabled_mask)) 331 goto done; 332 333 for (i = 0; i < cmd->chanlist_len; i++) { 334 unsigned int chan = CR_CHAN(cmd->chanlist[i]); 335 336 if (triggered & (1 << chan)) 337 val |= (1 << i); 338 } 339 340 /* Write the scan to the buffer. */ 341 if (comedi_buf_put(s, val) && 342 comedi_buf_put(s, val >> 16)) { 343 s->async->events |= (COMEDI_CB_BLOCK | COMEDI_CB_EOS); 344 } else { 345 /* Overflow! Stop acquisition!! */ 346 /* TODO: STOP_ACQUISITION_CALL_HERE!! */ 347 pcmuio_stop_intr(dev, s); 348 } 349 350 /* Check for end of acquisition. */ 351 if (cmd->stop_src == TRIG_COUNT) { 352 if (chip->stop_count > 0) { 353 chip->stop_count--; 354 if (chip->stop_count == 0) { 355 s->async->events |= COMEDI_CB_EOA; 356 /* TODO: STOP_ACQUISITION_CALL_HERE!! */ 357 pcmuio_stop_intr(dev, s); 358 } 359 } 360 } 361 362done: 363 spin_unlock_irqrestore(&chip->spinlock, flags); 364 365 if (oldevents != s->async->events) 366 comedi_event(dev, s); 367} 368 369static int pcmuio_handle_asic_interrupt(struct comedi_device *dev, int asic) 370{ 371 /* there are could be two asics so we can't use dev->read_subdev */ 372 struct comedi_subdevice *s = &dev->subdevices[asic * 2]; 373 unsigned long iobase = pcmuio_asic_iobase(dev, asic); 374 unsigned int val; 375 376 /* are there any interrupts pending */ 377 val = inb(iobase + PCMUIO_INT_PENDING_REG) & 0x07; 378 if (!val) 379 return 0; 380 381 /* get, and clear, the pending interrupts */ 382 val = pcmuio_read(dev, asic, PCMUIO_PAGE_INT_ID, 0); 383 pcmuio_write(dev, 0, asic, PCMUIO_PAGE_INT_ID, 0); 384 385 /* handle the pending interrupts */ 386 pcmuio_handle_intr_subdev(dev, s, val); 387 388 return 1; 389} 390 391static irqreturn_t pcmuio_interrupt(int irq, void *d) 392{ 393 struct comedi_device *dev = d; 394 struct pcmuio_private *devpriv = dev->private; 395 int handled = 0; 396 397 if (irq == dev->irq) 398 handled += pcmuio_handle_asic_interrupt(dev, 0); 399 if (irq == devpriv->irq2) 400 handled += pcmuio_handle_asic_interrupt(dev, 1); 401 402 return handled ? IRQ_HANDLED : IRQ_NONE; 403} 404 405/* chip->spinlock is already locked */ 406static int pcmuio_start_intr(struct comedi_device *dev, 407 struct comedi_subdevice *s) 408{ 409 struct pcmuio_private *devpriv = dev->private; 410 int asic = pcmuio_subdevice_to_asic(s); 411 struct pcmuio_asic *chip = &devpriv->asics[asic]; 412 struct comedi_cmd *cmd = &s->async->cmd; 413 unsigned int bits = 0; 414 unsigned int pol_bits = 0; 415 int i; 416 417 chip->enabled_mask = 0; 418 chip->active = 1; 419 if (cmd->chanlist) { 420 for (i = 0; i < cmd->chanlist_len; i++) { 421 unsigned int chanspec = cmd->chanlist[i]; 422 unsigned int chan = CR_CHAN(chanspec); 423 unsigned int range = CR_RANGE(chanspec); 424 unsigned int aref = CR_AREF(chanspec); 425 426 bits |= (1 << chan); 427 pol_bits |= ((aref || range) ? 1 : 0) << chan; 428 } 429 } 430 bits &= ((1 << s->n_chan) - 1); 431 chip->enabled_mask = bits; 432 433 /* set pol and enab intrs for this subdev.. */ 434 pcmuio_write(dev, pol_bits, asic, PCMUIO_PAGE_POL, 0); 435 pcmuio_write(dev, bits, asic, PCMUIO_PAGE_ENAB, 0); 436 437 return 0; 438} 439 440static int pcmuio_cancel(struct comedi_device *dev, struct comedi_subdevice *s) 441{ 442 struct pcmuio_private *devpriv = dev->private; 443 int asic = pcmuio_subdevice_to_asic(s); 444 struct pcmuio_asic *chip = &devpriv->asics[asic]; 445 unsigned long flags; 446 447 spin_lock_irqsave(&chip->spinlock, flags); 448 if (chip->active) 449 pcmuio_stop_intr(dev, s); 450 spin_unlock_irqrestore(&chip->spinlock, flags); 451 452 return 0; 453} 454 455static int pcmuio_inttrig_start_intr(struct comedi_device *dev, 456 struct comedi_subdevice *s, 457 unsigned int trig_num) 458{ 459 struct pcmuio_private *devpriv = dev->private; 460 struct comedi_cmd *cmd = &s->async->cmd; 461 int asic = pcmuio_subdevice_to_asic(s); 462 struct pcmuio_asic *chip = &devpriv->asics[asic]; 463 unsigned long flags; 464 int event = 0; 465 466 if (trig_num != cmd->start_arg) 467 return -EINVAL; 468 469 spin_lock_irqsave(&chip->spinlock, flags); 470 s->async->inttrig = NULL; 471 if (chip->active) 472 event = pcmuio_start_intr(dev, s); 473 474 spin_unlock_irqrestore(&chip->spinlock, flags); 475 476 if (event) 477 comedi_event(dev, s); 478 479 return 1; 480} 481 482/* 483 * 'do_cmd' function for an 'INTERRUPT' subdevice. 484 */ 485static int pcmuio_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 486{ 487 struct pcmuio_private *devpriv = dev->private; 488 struct comedi_cmd *cmd = &s->async->cmd; 489 int asic = pcmuio_subdevice_to_asic(s); 490 struct pcmuio_asic *chip = &devpriv->asics[asic]; 491 unsigned long flags; 492 int event = 0; 493 494 spin_lock_irqsave(&chip->spinlock, flags); 495 chip->active = 1; 496 497 /* Set up end of acquisition. */ 498 switch (cmd->stop_src) { 499 case TRIG_COUNT: 500 chip->stop_count = cmd->stop_arg; 501 break; 502 default: 503 /* TRIG_NONE */ 504 chip->stop_count = 0; 505 break; 506 } 507 508 /* Set up start of acquisition. */ 509 if (cmd->start_src == TRIG_INT) 510 s->async->inttrig = pcmuio_inttrig_start_intr; 511 else /* TRIG_NOW */ 512 event = pcmuio_start_intr(dev, s); 513 514 spin_unlock_irqrestore(&chip->spinlock, flags); 515 516 if (event) 517 comedi_event(dev, s); 518 519 return 0; 520} 521 522static int pcmuio_cmdtest(struct comedi_device *dev, 523 struct comedi_subdevice *s, 524 struct comedi_cmd *cmd) 525{ 526 int err = 0; 527 528 /* Step 1 : check if triggers are trivially valid */ 529 530 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT); 531 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT); 532 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW); 533 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); 534 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); 535 536 if (err) 537 return 1; 538 539 /* Step 2a : make sure trigger sources are unique */ 540 541 err |= cfc_check_trigger_is_unique(cmd->start_src); 542 err |= cfc_check_trigger_is_unique(cmd->stop_src); 543 544 /* Step 2b : and mutually compatible */ 545 546 if (err) 547 return 2; 548 549 /* Step 3: check if arguments are trivially valid */ 550 551 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); 552 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0); 553 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0); 554 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); 555 556 if (cmd->stop_src == TRIG_COUNT) 557 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); 558 else /* TRIG_NONE */ 559 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); 560 561 if (err) 562 return 3; 563 564 /* step 4: fix up any arguments */ 565 566 /* if (err) return 4; */ 567 568 return 0; 569} 570 571static int pcmuio_attach(struct comedi_device *dev, struct comedi_devconfig *it) 572{ 573 const struct pcmuio_board *board = dev->board_ptr; 574 struct comedi_subdevice *s; 575 struct pcmuio_private *devpriv; 576 int ret; 577 int i; 578 579 ret = comedi_request_region(dev, it->options[0], 580 board->num_asics * PCMUIO_ASIC_IOSIZE); 581 if (ret) 582 return ret; 583 584 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); 585 if (!devpriv) 586 return -ENOMEM; 587 588 for (i = 0; i < PCMUIO_MAX_ASICS; ++i) { 589 struct pcmuio_asic *chip = &devpriv->asics[i]; 590 591 spin_lock_init(&chip->pagelock); 592 spin_lock_init(&chip->spinlock); 593 } 594 595 pcmuio_reset(dev); 596 597 if (it->options[1]) { 598 /* request the irq for the 1st asic */ 599 ret = request_irq(it->options[1], pcmuio_interrupt, 0, 600 dev->board_name, dev); 601 if (ret == 0) 602 dev->irq = it->options[1]; 603 } 604 605 if (board->num_asics == 2) { 606 if (it->options[2] == dev->irq) { 607 /* the same irq (or none) is used by both asics */ 608 devpriv->irq2 = it->options[2]; 609 } else if (it->options[2]) { 610 /* request the irq for the 2nd asic */ 611 ret = request_irq(it->options[2], pcmuio_interrupt, 0, 612 dev->board_name, dev); 613 if (ret == 0) 614 devpriv->irq2 = it->options[2]; 615 } 616 } 617 618 ret = comedi_alloc_subdevices(dev, board->num_asics * 2); 619 if (ret) 620 return ret; 621 622 for (i = 0; i < dev->n_subdevices; ++i) { 623 s = &dev->subdevices[i]; 624 s->type = COMEDI_SUBD_DIO; 625 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; 626 s->n_chan = 24; 627 s->maxdata = 1; 628 s->range_table = &range_digital; 629 s->insn_bits = pcmuio_dio_insn_bits; 630 s->insn_config = pcmuio_dio_insn_config; 631 632 /* subdevices 0 and 2 can suppport interrupts */ 633 if ((i == 0 && dev->irq) || (i == 2 && devpriv->irq2)) { 634 /* setup the interrupt subdevice */ 635 dev->read_subdev = s; 636 s->subdev_flags |= SDF_CMD_READ; 637 s->len_chanlist = s->n_chan; 638 s->cancel = pcmuio_cancel; 639 s->do_cmd = pcmuio_cmd; 640 s->do_cmdtest = pcmuio_cmdtest; 641 } 642 } 643 644 return 0; 645} 646 647static void pcmuio_detach(struct comedi_device *dev) 648{ 649 struct pcmuio_private *devpriv = dev->private; 650 651 if (devpriv) { 652 pcmuio_reset(dev); 653 654 /* free the 2nd irq if used, the core will free the 1st one */ 655 if (devpriv->irq2 && devpriv->irq2 != dev->irq) 656 free_irq(devpriv->irq2, dev); 657 } 658 comedi_legacy_detach(dev); 659} 660 661static struct comedi_driver pcmuio_driver = { 662 .driver_name = "pcmuio", 663 .module = THIS_MODULE, 664 .attach = pcmuio_attach, 665 .detach = pcmuio_detach, 666 .board_name = &pcmuio_boards[0].name, 667 .offset = sizeof(struct pcmuio_board), 668 .num_names = ARRAY_SIZE(pcmuio_boards), 669}; 670module_comedi_driver(pcmuio_driver); 671 672MODULE_AUTHOR("Comedi http://www.comedi.org"); 673MODULE_DESCRIPTION("Comedi low-level driver"); 674MODULE_LICENSE("GPL"); 675