1/* 2 * Copyright 2003 Digi International (www.digi.com) 3 * Scott H Kilau <Scott_Kilau at digi dot com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 13 * PURPOSE. See the GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * 20 * NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE! 21 * 22 * This is shared code between Digi's CVS archive and the 23 * Linux Kernel sources. 24 * Changing the source just for reformatting needlessly breaks 25 * our CVS diff history. 26 * 27 * Send any bug fixes/changes to: Eng.Linux at digi dot com. 28 * Thank you. 29 * 30 */ 31 32 33#include <linux/kernel.h> 34#include <linux/sched.h> /* For jiffies, task states */ 35#include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */ 36#include <linux/delay.h> /* For udelay */ 37#include <linux/io.h> /* For read[bwl]/write[bwl] */ 38#include <linux/serial.h> /* For struct async_serial */ 39#include <linux/serial_reg.h> /* For the various UART offsets */ 40 41#include "dgnc_driver.h" /* Driver main header file */ 42#include "dgnc_neo.h" /* Our header file */ 43#include "dgnc_tty.h" 44 45static inline void neo_parse_lsr(struct dgnc_board *brd, uint port); 46static inline void neo_parse_isr(struct dgnc_board *brd, uint port); 47static void neo_copy_data_from_uart_to_queue(struct channel_t *ch); 48static inline void neo_clear_break(struct channel_t *ch, int force); 49static inline void neo_set_cts_flow_control(struct channel_t *ch); 50static inline void neo_set_rts_flow_control(struct channel_t *ch); 51static inline void neo_set_ixon_flow_control(struct channel_t *ch); 52static inline void neo_set_ixoff_flow_control(struct channel_t *ch); 53static inline void neo_set_no_output_flow_control(struct channel_t *ch); 54static inline void neo_set_no_input_flow_control(struct channel_t *ch); 55static inline void neo_set_new_start_stop_chars(struct channel_t *ch); 56static void neo_parse_modem(struct channel_t *ch, unsigned char signals); 57static void neo_tasklet(unsigned long data); 58static void neo_vpd(struct dgnc_board *brd); 59static void neo_uart_init(struct channel_t *ch); 60static void neo_uart_off(struct channel_t *ch); 61static int neo_drain(struct tty_struct *tty, uint seconds); 62static void neo_param(struct tty_struct *tty); 63static void neo_assert_modem_signals(struct channel_t *ch); 64static void neo_flush_uart_write(struct channel_t *ch); 65static void neo_flush_uart_read(struct channel_t *ch); 66static void neo_disable_receiver(struct channel_t *ch); 67static void neo_enable_receiver(struct channel_t *ch); 68static void neo_send_break(struct channel_t *ch, int msecs); 69static void neo_send_start_character(struct channel_t *ch); 70static void neo_send_stop_character(struct channel_t *ch); 71static void neo_copy_data_from_queue_to_uart(struct channel_t *ch); 72static uint neo_get_uart_bytes_left(struct channel_t *ch); 73static void neo_send_immediate_char(struct channel_t *ch, unsigned char c); 74static irqreturn_t neo_intr(int irq, void *voidbrd); 75 76 77struct board_ops dgnc_neo_ops = { 78 .tasklet = neo_tasklet, 79 .intr = neo_intr, 80 .uart_init = neo_uart_init, 81 .uart_off = neo_uart_off, 82 .drain = neo_drain, 83 .param = neo_param, 84 .vpd = neo_vpd, 85 .assert_modem_signals = neo_assert_modem_signals, 86 .flush_uart_write = neo_flush_uart_write, 87 .flush_uart_read = neo_flush_uart_read, 88 .disable_receiver = neo_disable_receiver, 89 .enable_receiver = neo_enable_receiver, 90 .send_break = neo_send_break, 91 .send_start_character = neo_send_start_character, 92 .send_stop_character = neo_send_stop_character, 93 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart, 94 .get_uart_bytes_left = neo_get_uart_bytes_left, 95 .send_immediate_char = neo_send_immediate_char 96}; 97 98static uint dgnc_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }; 99 100 101/* 102 * This function allows calls to ensure that all outstanding 103 * PCI writes have been completed, by doing a PCI read against 104 * a non-destructive, read-only location on the Neo card. 105 * 106 * In this case, we are reading the DVID (Read-only Device Identification) 107 * value of the Neo card. 108 */ 109static inline void neo_pci_posting_flush(struct dgnc_board *bd) 110{ 111 readb(bd->re_map_membase + 0x8D); 112} 113 114static inline void neo_set_cts_flow_control(struct channel_t *ch) 115{ 116 unsigned char ier = readb(&ch->ch_neo_uart->ier); 117 unsigned char efr = readb(&ch->ch_neo_uart->efr); 118 119 120 /* Turn on auto CTS flow control */ 121#if 1 122 ier |= (UART_17158_IER_CTSDSR); 123#else 124 ier &= ~(UART_17158_IER_CTSDSR); 125#endif 126 127 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR); 128 129 /* Turn off auto Xon flow control */ 130 efr &= ~(UART_17158_EFR_IXON); 131 132 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 133 writeb(0, &ch->ch_neo_uart->efr); 134 135 /* Turn on UART enhanced bits */ 136 writeb(efr, &ch->ch_neo_uart->efr); 137 138 /* Turn on table D, with 8 char hi/low watermarks */ 139 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 140 141 /* Feed the UART our trigger levels */ 142 writeb(8, &ch->ch_neo_uart->tfifo); 143 ch->ch_t_tlevel = 8; 144 145 writeb(ier, &ch->ch_neo_uart->ier); 146 147 neo_pci_posting_flush(ch->ch_bd); 148} 149 150 151static inline void neo_set_rts_flow_control(struct channel_t *ch) 152{ 153 unsigned char ier = readb(&ch->ch_neo_uart->ier); 154 unsigned char efr = readb(&ch->ch_neo_uart->efr); 155 156 /* Turn on auto RTS flow control */ 157#if 1 158 ier |= (UART_17158_IER_RTSDTR); 159#else 160 ier &= ~(UART_17158_IER_RTSDTR); 161#endif 162 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR); 163 164 /* Turn off auto Xoff flow control */ 165 ier &= ~(UART_17158_IER_XOFF); 166 efr &= ~(UART_17158_EFR_IXOFF); 167 168 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 169 writeb(0, &ch->ch_neo_uart->efr); 170 171 /* Turn on UART enhanced bits */ 172 writeb(efr, &ch->ch_neo_uart->efr); 173 174 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); 175 ch->ch_r_watermark = 4; 176 177 writeb(32, &ch->ch_neo_uart->rfifo); 178 ch->ch_r_tlevel = 32; 179 180 writeb(ier, &ch->ch_neo_uart->ier); 181 182 /* 183 * From the Neo UART spec sheet: 184 * The auto RTS/DTR function must be started by asserting 185 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after 186 * it is enabled. 187 */ 188 ch->ch_mostat |= (UART_MCR_RTS); 189 190 neo_pci_posting_flush(ch->ch_bd); 191} 192 193 194static inline void neo_set_ixon_flow_control(struct channel_t *ch) 195{ 196 unsigned char ier = readb(&ch->ch_neo_uart->ier); 197 unsigned char efr = readb(&ch->ch_neo_uart->efr); 198 199 /* Turn off auto CTS flow control */ 200 ier &= ~(UART_17158_IER_CTSDSR); 201 efr &= ~(UART_17158_EFR_CTSDSR); 202 203 /* Turn on auto Xon flow control */ 204 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON); 205 206 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 207 writeb(0, &ch->ch_neo_uart->efr); 208 209 /* Turn on UART enhanced bits */ 210 writeb(efr, &ch->ch_neo_uart->efr); 211 212 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 213 ch->ch_r_watermark = 4; 214 215 writeb(32, &ch->ch_neo_uart->rfifo); 216 ch->ch_r_tlevel = 32; 217 218 /* Tell UART what start/stop chars it should be looking for */ 219 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 220 writeb(0, &ch->ch_neo_uart->xonchar2); 221 222 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 223 writeb(0, &ch->ch_neo_uart->xoffchar2); 224 225 writeb(ier, &ch->ch_neo_uart->ier); 226 227 neo_pci_posting_flush(ch->ch_bd); 228} 229 230 231static inline void neo_set_ixoff_flow_control(struct channel_t *ch) 232{ 233 unsigned char ier = readb(&ch->ch_neo_uart->ier); 234 unsigned char efr = readb(&ch->ch_neo_uart->efr); 235 236 /* Turn off auto RTS flow control */ 237 ier &= ~(UART_17158_IER_RTSDTR); 238 efr &= ~(UART_17158_EFR_RTSDTR); 239 240 /* Turn on auto Xoff flow control */ 241 ier |= (UART_17158_IER_XOFF); 242 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 243 244 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 245 writeb(0, &ch->ch_neo_uart->efr); 246 247 /* Turn on UART enhanced bits */ 248 writeb(efr, &ch->ch_neo_uart->efr); 249 250 /* Turn on table D, with 8 char hi/low watermarks */ 251 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 252 253 writeb(8, &ch->ch_neo_uart->tfifo); 254 ch->ch_t_tlevel = 8; 255 256 /* Tell UART what start/stop chars it should be looking for */ 257 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 258 writeb(0, &ch->ch_neo_uart->xonchar2); 259 260 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 261 writeb(0, &ch->ch_neo_uart->xoffchar2); 262 263 writeb(ier, &ch->ch_neo_uart->ier); 264 265 neo_pci_posting_flush(ch->ch_bd); 266} 267 268 269static inline void neo_set_no_input_flow_control(struct channel_t *ch) 270{ 271 unsigned char ier = readb(&ch->ch_neo_uart->ier); 272 unsigned char efr = readb(&ch->ch_neo_uart->efr); 273 274 /* Turn off auto RTS flow control */ 275 ier &= ~(UART_17158_IER_RTSDTR); 276 efr &= ~(UART_17158_EFR_RTSDTR); 277 278 /* Turn off auto Xoff flow control */ 279 ier &= ~(UART_17158_IER_XOFF); 280 if (ch->ch_c_iflag & IXON) 281 efr &= ~(UART_17158_EFR_IXOFF); 282 else 283 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF); 284 285 286 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 287 writeb(0, &ch->ch_neo_uart->efr); 288 289 /* Turn on UART enhanced bits */ 290 writeb(efr, &ch->ch_neo_uart->efr); 291 292 /* Turn on table D, with 8 char hi/low watermarks */ 293 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 294 295 ch->ch_r_watermark = 0; 296 297 writeb(16, &ch->ch_neo_uart->tfifo); 298 ch->ch_t_tlevel = 16; 299 300 writeb(16, &ch->ch_neo_uart->rfifo); 301 ch->ch_r_tlevel = 16; 302 303 writeb(ier, &ch->ch_neo_uart->ier); 304 305 neo_pci_posting_flush(ch->ch_bd); 306} 307 308 309static inline void neo_set_no_output_flow_control(struct channel_t *ch) 310{ 311 unsigned char ier = readb(&ch->ch_neo_uart->ier); 312 unsigned char efr = readb(&ch->ch_neo_uart->efr); 313 314 /* Turn off auto CTS flow control */ 315 ier &= ~(UART_17158_IER_CTSDSR); 316 efr &= ~(UART_17158_EFR_CTSDSR); 317 318 /* Turn off auto Xon flow control */ 319 if (ch->ch_c_iflag & IXOFF) 320 efr &= ~(UART_17158_EFR_IXON); 321 else 322 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON); 323 324 /* Why? Becuz Exar's spec says we have to zero it out before setting it */ 325 writeb(0, &ch->ch_neo_uart->efr); 326 327 /* Turn on UART enhanced bits */ 328 writeb(efr, &ch->ch_neo_uart->efr); 329 330 /* Turn on table D, with 8 char hi/low watermarks */ 331 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); 332 333 ch->ch_r_watermark = 0; 334 335 writeb(16, &ch->ch_neo_uart->tfifo); 336 ch->ch_t_tlevel = 16; 337 338 writeb(16, &ch->ch_neo_uart->rfifo); 339 ch->ch_r_tlevel = 16; 340 341 writeb(ier, &ch->ch_neo_uart->ier); 342 343 neo_pci_posting_flush(ch->ch_bd); 344} 345 346 347/* change UARTs start/stop chars */ 348static inline void neo_set_new_start_stop_chars(struct channel_t *ch) 349{ 350 351 /* if hardware flow control is set, then skip this whole thing */ 352 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) || ch->ch_c_cflag & CRTSCTS) 353 return; 354 355 /* Tell UART what start/stop chars it should be looking for */ 356 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); 357 writeb(0, &ch->ch_neo_uart->xonchar2); 358 359 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); 360 writeb(0, &ch->ch_neo_uart->xoffchar2); 361 362 neo_pci_posting_flush(ch->ch_bd); 363} 364 365 366/* 367 * No locks are assumed to be held when calling this function. 368 */ 369static inline void neo_clear_break(struct channel_t *ch, int force) 370{ 371 unsigned long flags; 372 373 spin_lock_irqsave(&ch->ch_lock, flags); 374 375 /* Bail if we aren't currently sending a break. */ 376 if (!ch->ch_stop_sending_break) { 377 spin_unlock_irqrestore(&ch->ch_lock, flags); 378 return; 379 } 380 381 /* Turn break off, and unset some variables */ 382 if (ch->ch_flags & CH_BREAK_SENDING) { 383 if (time_after_eq(jiffies, ch->ch_stop_sending_break) 384 || force) { 385 unsigned char temp = readb(&ch->ch_neo_uart->lcr); 386 387 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 388 neo_pci_posting_flush(ch->ch_bd); 389 ch->ch_flags &= ~(CH_BREAK_SENDING); 390 ch->ch_stop_sending_break = 0; 391 } 392 } 393 spin_unlock_irqrestore(&ch->ch_lock, flags); 394} 395 396 397/* 398 * Parse the ISR register. 399 */ 400static inline void neo_parse_isr(struct dgnc_board *brd, uint port) 401{ 402 struct channel_t *ch; 403 unsigned char isr; 404 unsigned char cause; 405 unsigned long flags; 406 407 if (!brd || brd->magic != DGNC_BOARD_MAGIC) 408 return; 409 410 if (port > brd->maxports) 411 return; 412 413 ch = brd->channels[port]; 414 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 415 return; 416 417 /* Here we try to figure out what caused the interrupt to happen */ 418 while (1) { 419 420 isr = readb(&ch->ch_neo_uart->isr_fcr); 421 422 /* Bail if no pending interrupt */ 423 if (isr & UART_IIR_NO_INT) 424 break; 425 426 /* 427 * Yank off the upper 2 bits, which just show that the FIFO's are enabled. 428 */ 429 isr &= ~(UART_17158_IIR_FIFO_ENABLED); 430 431 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) { 432 /* Read data from uart -> queue */ 433 brd->intr_rx++; 434 ch->ch_intr_rx++; 435 neo_copy_data_from_uart_to_queue(ch); 436 437 /* Call our tty layer to enforce queue flow control if needed. */ 438 spin_lock_irqsave(&ch->ch_lock, flags); 439 dgnc_check_queue_flow_control(ch); 440 spin_unlock_irqrestore(&ch->ch_lock, flags); 441 } 442 443 if (isr & UART_IIR_THRI) { 444 brd->intr_tx++; 445 ch->ch_intr_tx++; 446 /* Transfer data (if any) from Write Queue -> UART. */ 447 spin_lock_irqsave(&ch->ch_lock, flags); 448 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 449 spin_unlock_irqrestore(&ch->ch_lock, flags); 450 neo_copy_data_from_queue_to_uart(ch); 451 } 452 453 if (isr & UART_17158_IIR_XONXOFF) { 454 cause = readb(&ch->ch_neo_uart->xoffchar1); 455 456 /* 457 * Since the UART detected either an XON or 458 * XOFF match, we need to figure out which 459 * one it was, so we can suspend or resume data flow. 460 */ 461 if (cause == UART_17158_XON_DETECT) { 462 /* Is output stopped right now, if so, resume it */ 463 if (brd->channels[port]->ch_flags & CH_STOP) { 464 spin_lock_irqsave(&ch->ch_lock, 465 flags); 466 ch->ch_flags &= ~(CH_STOP); 467 spin_unlock_irqrestore(&ch->ch_lock, 468 flags); 469 } 470 } else if (cause == UART_17158_XOFF_DETECT) { 471 if (!(brd->channels[port]->ch_flags & CH_STOP)) { 472 spin_lock_irqsave(&ch->ch_lock, 473 flags); 474 ch->ch_flags |= CH_STOP; 475 spin_unlock_irqrestore(&ch->ch_lock, 476 flags); 477 } 478 } 479 } 480 481 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) { 482 /* 483 * If we get here, this means the hardware is doing auto flow control. 484 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt. 485 */ 486 brd->intr_modem++; 487 ch->ch_intr_modem++; 488 cause = readb(&ch->ch_neo_uart->mcr); 489 /* Which pin is doing auto flow? RTS or DTR? */ 490 if ((cause & 0x4) == 0) { 491 if (cause & UART_MCR_RTS) { 492 spin_lock_irqsave(&ch->ch_lock, 493 flags); 494 ch->ch_mostat |= UART_MCR_RTS; 495 spin_unlock_irqrestore(&ch->ch_lock, 496 flags); 497 } else { 498 spin_lock_irqsave(&ch->ch_lock, 499 flags); 500 ch->ch_mostat &= ~(UART_MCR_RTS); 501 spin_unlock_irqrestore(&ch->ch_lock, 502 flags); 503 } 504 } else { 505 if (cause & UART_MCR_DTR) { 506 spin_lock_irqsave(&ch->ch_lock, 507 flags); 508 ch->ch_mostat |= UART_MCR_DTR; 509 spin_unlock_irqrestore(&ch->ch_lock, 510 flags); 511 } else { 512 spin_lock_irqsave(&ch->ch_lock, 513 flags); 514 ch->ch_mostat &= ~(UART_MCR_DTR); 515 spin_unlock_irqrestore(&ch->ch_lock, 516 flags); 517 } 518 } 519 } 520 521 /* Parse any modem signal changes */ 522 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 523 } 524} 525 526 527static inline void neo_parse_lsr(struct dgnc_board *brd, uint port) 528{ 529 struct channel_t *ch; 530 int linestatus; 531 unsigned long flags; 532 533 if (!brd) 534 return; 535 536 if (brd->magic != DGNC_BOARD_MAGIC) 537 return; 538 539 if (port > brd->maxports) 540 return; 541 542 ch = brd->channels[port]; 543 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 544 return; 545 546 linestatus = readb(&ch->ch_neo_uart->lsr); 547 548 ch->ch_cached_lsr |= linestatus; 549 550 if (ch->ch_cached_lsr & UART_LSR_DR) { 551 brd->intr_rx++; 552 ch->ch_intr_rx++; 553 /* Read data from uart -> queue */ 554 neo_copy_data_from_uart_to_queue(ch); 555 spin_lock_irqsave(&ch->ch_lock, flags); 556 dgnc_check_queue_flow_control(ch); 557 spin_unlock_irqrestore(&ch->ch_lock, flags); 558 } 559 560 /* 561 * The next 3 tests should *NOT* happen, as the above test 562 * should encapsulate all 3... At least, thats what Exar says. 563 */ 564 565 if (linestatus & UART_LSR_PE) 566 ch->ch_err_parity++; 567 568 if (linestatus & UART_LSR_FE) 569 ch->ch_err_frame++; 570 571 if (linestatus & UART_LSR_BI) 572 ch->ch_err_break++; 573 574 if (linestatus & UART_LSR_OE) { 575 /* 576 * Rx Oruns. Exar says that an orun will NOT corrupt 577 * the FIFO. It will just replace the holding register 578 * with this new data byte. So basically just ignore this. 579 * Probably we should eventually have an orun stat in our driver... 580 */ 581 ch->ch_err_overrun++; 582 } 583 584 if (linestatus & UART_LSR_THRE) { 585 brd->intr_tx++; 586 ch->ch_intr_tx++; 587 spin_lock_irqsave(&ch->ch_lock, flags); 588 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 589 spin_unlock_irqrestore(&ch->ch_lock, flags); 590 591 /* Transfer data (if any) from Write Queue -> UART. */ 592 neo_copy_data_from_queue_to_uart(ch); 593 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) { 594 brd->intr_tx++; 595 ch->ch_intr_tx++; 596 spin_lock_irqsave(&ch->ch_lock, flags); 597 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 598 spin_unlock_irqrestore(&ch->ch_lock, flags); 599 600 /* Transfer data (if any) from Write Queue -> UART. */ 601 neo_copy_data_from_queue_to_uart(ch); 602 } 603} 604 605 606/* 607 * neo_param() 608 * Send any/all changes to the line to the UART. 609 */ 610static void neo_param(struct tty_struct *tty) 611{ 612 unsigned char lcr = 0; 613 unsigned char uart_lcr = 0; 614 unsigned char ier = 0; 615 unsigned char uart_ier = 0; 616 uint baud = 9600; 617 int quot = 0; 618 struct dgnc_board *bd; 619 struct channel_t *ch; 620 struct un_t *un; 621 622 if (!tty || tty->magic != TTY_MAGIC) 623 return; 624 625 un = (struct un_t *) tty->driver_data; 626 if (!un || un->magic != DGNC_UNIT_MAGIC) 627 return; 628 629 ch = un->un_ch; 630 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 631 return; 632 633 bd = ch->ch_bd; 634 if (!bd || bd->magic != DGNC_BOARD_MAGIC) 635 return; 636 637 /* 638 * If baud rate is zero, flush queues, and set mval to drop DTR. 639 */ 640 if ((ch->ch_c_cflag & (CBAUD)) == 0) { 641 ch->ch_r_head = 0; 642 ch->ch_r_tail = 0; 643 ch->ch_e_head = 0; 644 ch->ch_e_tail = 0; 645 ch->ch_w_head = 0; 646 ch->ch_w_tail = 0; 647 648 neo_flush_uart_write(ch); 649 neo_flush_uart_read(ch); 650 651 /* The baudrate is B0 so all modem lines are to be dropped. */ 652 ch->ch_flags |= (CH_BAUD0); 653 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); 654 neo_assert_modem_signals(ch); 655 ch->ch_old_baud = 0; 656 return; 657 658 } else if (ch->ch_custom_speed) { 659 660 baud = ch->ch_custom_speed; 661 /* Handle transition from B0 */ 662 if (ch->ch_flags & CH_BAUD0) { 663 ch->ch_flags &= ~(CH_BAUD0); 664 665 /* 666 * Bring back up RTS and DTR... 667 * Also handle RTS or DTR toggle if set. 668 */ 669 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE)) 670 ch->ch_mostat |= (UART_MCR_RTS); 671 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE)) 672 ch->ch_mostat |= (UART_MCR_DTR); 673 } 674 } else { 675 int iindex = 0; 676 int jindex = 0; 677 678 ulong bauds[4][16] = { 679 { /* slowbaud */ 680 0, 50, 75, 110, 681 134, 150, 200, 300, 682 600, 1200, 1800, 2400, 683 4800, 9600, 19200, 38400 }, 684 { /* slowbaud & CBAUDEX */ 685 0, 57600, 115200, 230400, 686 460800, 150, 200, 921600, 687 600, 1200, 1800, 2400, 688 4800, 9600, 19200, 38400 }, 689 { /* fastbaud */ 690 0, 57600, 76800, 115200, 691 131657, 153600, 230400, 460800, 692 921600, 1200, 1800, 2400, 693 4800, 9600, 19200, 38400 }, 694 { /* fastbaud & CBAUDEX */ 695 0, 57600, 115200, 230400, 696 460800, 150, 200, 921600, 697 600, 1200, 1800, 2400, 698 4800, 9600, 19200, 38400 } 699 }; 700 701 /* Only use the TXPrint baud rate if the terminal unit is NOT open */ 702 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT)) 703 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff; 704 else 705 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff; 706 707 if (ch->ch_c_cflag & CBAUDEX) 708 iindex = 1; 709 710 if (ch->ch_digi.digi_flags & DIGI_FAST) 711 iindex += 2; 712 713 jindex = baud; 714 715 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16)) 716 baud = bauds[iindex][jindex]; 717 else 718 baud = 0; 719 720 if (baud == 0) 721 baud = 9600; 722 723 /* Handle transition from B0 */ 724 if (ch->ch_flags & CH_BAUD0) { 725 ch->ch_flags &= ~(CH_BAUD0); 726 727 /* 728 * Bring back up RTS and DTR... 729 * Also handle RTS or DTR toggle if set. 730 */ 731 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE)) 732 ch->ch_mostat |= (UART_MCR_RTS); 733 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE)) 734 ch->ch_mostat |= (UART_MCR_DTR); 735 } 736 } 737 738 if (ch->ch_c_cflag & PARENB) 739 lcr |= UART_LCR_PARITY; 740 741 if (!(ch->ch_c_cflag & PARODD)) 742 lcr |= UART_LCR_EPAR; 743 744 /* 745 * Not all platforms support mark/space parity, 746 * so this will hide behind an ifdef. 747 */ 748#ifdef CMSPAR 749 if (ch->ch_c_cflag & CMSPAR) 750 lcr |= UART_LCR_SPAR; 751#endif 752 753 if (ch->ch_c_cflag & CSTOPB) 754 lcr |= UART_LCR_STOP; 755 756 switch (ch->ch_c_cflag & CSIZE) { 757 case CS5: 758 lcr |= UART_LCR_WLEN5; 759 break; 760 case CS6: 761 lcr |= UART_LCR_WLEN6; 762 break; 763 case CS7: 764 lcr |= UART_LCR_WLEN7; 765 break; 766 case CS8: 767 default: 768 lcr |= UART_LCR_WLEN8; 769 break; 770 } 771 772 uart_ier = readb(&ch->ch_neo_uart->ier); 773 ier = uart_ier; 774 775 uart_lcr = readb(&ch->ch_neo_uart->lcr); 776 777 if (baud == 0) 778 baud = 9600; 779 780 quot = ch->ch_bd->bd_dividend / baud; 781 782 if (quot != 0 && ch->ch_old_baud != baud) { 783 ch->ch_old_baud = baud; 784 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); 785 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); 786 writeb((quot >> 8), &ch->ch_neo_uart->ier); 787 writeb(lcr, &ch->ch_neo_uart->lcr); 788 } 789 790 if (uart_lcr != lcr) 791 writeb(lcr, &ch->ch_neo_uart->lcr); 792 793 if (ch->ch_c_cflag & CREAD) 794 ier |= (UART_IER_RDI | UART_IER_RLSI); 795 else 796 ier &= ~(UART_IER_RDI | UART_IER_RLSI); 797 798 /* 799 * Have the UART interrupt on modem signal changes ONLY when 800 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set. 801 */ 802 if ((ch->ch_digi.digi_flags & CTSPACE) || 803 (ch->ch_digi.digi_flags & RTSPACE) || 804 (ch->ch_c_cflag & CRTSCTS) || 805 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) || 806 !(ch->ch_c_cflag & CLOCAL)) 807 ier |= UART_IER_MSI; 808 else 809 ier &= ~UART_IER_MSI; 810 811 ier |= UART_IER_THRI; 812 813 if (ier != uart_ier) 814 writeb(ier, &ch->ch_neo_uart->ier); 815 816 /* Set new start/stop chars */ 817 neo_set_new_start_stop_chars(ch); 818 819 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) { 820 neo_set_cts_flow_control(ch); 821 } else if (ch->ch_c_iflag & IXON) { 822 /* If start/stop is set to disable, then we should disable flow control */ 823 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE)) 824 neo_set_no_output_flow_control(ch); 825 else 826 neo_set_ixon_flow_control(ch); 827 } else { 828 neo_set_no_output_flow_control(ch); 829 } 830 831 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) { 832 neo_set_rts_flow_control(ch); 833 } else if (ch->ch_c_iflag & IXOFF) { 834 /* If start/stop is set to disable, then we should disable flow control */ 835 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE)) 836 neo_set_no_input_flow_control(ch); 837 else 838 neo_set_ixoff_flow_control(ch); 839 } else { 840 neo_set_no_input_flow_control(ch); 841 } 842 843 /* 844 * Adjust the RX FIFO Trigger level if baud is less than 9600. 845 * Not exactly elegant, but this is needed because of the Exar chip's 846 * delay on firing off the RX FIFO interrupt on slower baud rates. 847 */ 848 if (baud < 9600) { 849 writeb(1, &ch->ch_neo_uart->rfifo); 850 ch->ch_r_tlevel = 1; 851 } 852 853 neo_assert_modem_signals(ch); 854 855 /* Get current status of the modem signals now */ 856 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 857} 858 859 860/* 861 * Our board poller function. 862 */ 863static void neo_tasklet(unsigned long data) 864{ 865 struct dgnc_board *bd = (struct dgnc_board *) data; 866 struct channel_t *ch; 867 unsigned long flags; 868 int i; 869 int state = 0; 870 int ports = 0; 871 872 if (!bd || bd->magic != DGNC_BOARD_MAGIC) { 873 APR(("poll_tasklet() - NULL or bad bd.\n")); 874 return; 875 } 876 877 /* Cache a couple board values */ 878 spin_lock_irqsave(&bd->bd_lock, flags); 879 state = bd->state; 880 ports = bd->nasync; 881 spin_unlock_irqrestore(&bd->bd_lock, flags); 882 883 /* 884 * Do NOT allow the interrupt routine to read the intr registers 885 * Until we release this lock. 886 */ 887 spin_lock_irqsave(&bd->bd_intr_lock, flags); 888 889 /* 890 * If board is ready, parse deeper to see if there is anything to do. 891 */ 892 if ((state == BOARD_READY) && (ports > 0)) { 893 /* Loop on each port */ 894 for (i = 0; i < ports; i++) { 895 ch = bd->channels[i]; 896 897 /* Just being careful... */ 898 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 899 continue; 900 901 /* 902 * NOTE: Remember you CANNOT hold any channel 903 * locks when calling the input routine. 904 * 905 * During input processing, its possible we 906 * will call the Linux ld, which might in turn, 907 * do a callback right back into us, resulting 908 * in us trying to grab the channel lock twice! 909 */ 910 dgnc_input(ch); 911 912 /* 913 * Channel lock is grabbed and then released 914 * inside both of these routines, but neither 915 * call anything else that could call back into us. 916 */ 917 neo_copy_data_from_queue_to_uart(ch); 918 dgnc_wakeup_writes(ch); 919 920 /* 921 * Call carrier carrier function, in case something 922 * has changed. 923 */ 924 dgnc_carrier(ch); 925 926 /* 927 * Check to see if we need to turn off a sending break. 928 * The timing check is done inside clear_break() 929 */ 930 if (ch->ch_stop_sending_break) 931 neo_clear_break(ch, 0); 932 } 933 } 934 935 /* Allow interrupt routine to access the interrupt register again */ 936 spin_unlock_irqrestore(&bd->bd_intr_lock, flags); 937 938} 939 940 941/* 942 * dgnc_neo_intr() 943 * 944 * Neo specific interrupt handler. 945 */ 946static irqreturn_t neo_intr(int irq, void *voidbrd) 947{ 948 struct dgnc_board *brd = (struct dgnc_board *) voidbrd; 949 struct channel_t *ch; 950 int port = 0; 951 int type = 0; 952 int current_port; 953 u32 tmp; 954 u32 uart_poll; 955 unsigned long flags; 956 unsigned long flags2; 957 958 if (!brd) { 959 APR(("Received interrupt (%d) with null board associated\n", irq)); 960 return IRQ_NONE; 961 } 962 963 /* 964 * Check to make sure its for us. 965 */ 966 if (brd->magic != DGNC_BOARD_MAGIC) { 967 APR(("Received interrupt (%d) with a board pointer that wasn't ours!\n", irq)); 968 return IRQ_NONE; 969 } 970 971 brd->intr_count++; 972 973 /* Lock out the slow poller from running on this board. */ 974 spin_lock_irqsave(&brd->bd_intr_lock, flags); 975 976 /* 977 * Read in "extended" IRQ information from the 32bit Neo register. 978 * Bits 0-7: What port triggered the interrupt. 979 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. 980 */ 981 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); 982 983 /* 984 * If 0, no interrupts pending. 985 * This can happen if the IRQ is shared among a couple Neo/Classic boards. 986 */ 987 if (!uart_poll) { 988 spin_unlock_irqrestore(&brd->bd_intr_lock, flags); 989 return IRQ_NONE; 990 } 991 992 /* At this point, we have at least SOMETHING to service, dig further... */ 993 994 current_port = 0; 995 996 /* Loop on each port */ 997 while ((uart_poll & 0xff) != 0) { 998 999 tmp = uart_poll; 1000 1001 /* Check current port to see if it has interrupt pending */ 1002 if ((tmp & dgnc_offset_table[current_port]) != 0) { 1003 port = current_port; 1004 type = tmp >> (8 + (port * 3)); 1005 type &= 0x7; 1006 } else { 1007 current_port++; 1008 continue; 1009 } 1010 1011 /* Remove this port + type from uart_poll */ 1012 uart_poll &= ~(dgnc_offset_table[port]); 1013 1014 if (!type) { 1015 /* If no type, just ignore it, and move onto next port */ 1016 continue; 1017 } 1018 1019 /* Switch on type of interrupt we have */ 1020 switch (type) { 1021 1022 case UART_17158_RXRDY_TIMEOUT: 1023 /* 1024 * RXRDY Time-out is cleared by reading data in the 1025 * RX FIFO until it falls below the trigger level. 1026 */ 1027 1028 /* Verify the port is in range. */ 1029 if (port > brd->nasync) 1030 continue; 1031 1032 ch = brd->channels[port]; 1033 neo_copy_data_from_uart_to_queue(ch); 1034 1035 /* Call our tty layer to enforce queue flow control if needed. */ 1036 spin_lock_irqsave(&ch->ch_lock, flags2); 1037 dgnc_check_queue_flow_control(ch); 1038 spin_unlock_irqrestore(&ch->ch_lock, flags2); 1039 1040 continue; 1041 1042 case UART_17158_RX_LINE_STATUS: 1043 /* 1044 * RXRDY and RX LINE Status (logic OR of LSR[4:1]) 1045 */ 1046 neo_parse_lsr(brd, port); 1047 continue; 1048 1049 case UART_17158_TXRDY: 1050 /* 1051 * TXRDY interrupt clears after reading ISR register for the UART channel. 1052 */ 1053 1054 /* 1055 * Yes, this is odd... 1056 * Why would I check EVERY possibility of type of 1057 * interrupt, when we know its TXRDY??? 1058 * Becuz for some reason, even tho we got triggered for TXRDY, 1059 * it seems to be occasionally wrong. Instead of TX, which 1060 * it should be, I was getting things like RXDY too. Weird. 1061 */ 1062 neo_parse_isr(brd, port); 1063 continue; 1064 1065 case UART_17158_MSR: 1066 /* 1067 * MSR or flow control was seen. 1068 */ 1069 neo_parse_isr(brd, port); 1070 continue; 1071 1072 default: 1073 /* 1074 * The UART triggered us with a bogus interrupt type. 1075 * It appears the Exar chip, when REALLY bogged down, will throw 1076 * these once and awhile. 1077 * Its harmless, just ignore it and move on. 1078 */ 1079 continue; 1080 } 1081 } 1082 1083 /* 1084 * Schedule tasklet to more in-depth servicing at a better time. 1085 */ 1086 tasklet_schedule(&brd->helper_tasklet); 1087 1088 spin_unlock_irqrestore(&brd->bd_intr_lock, flags); 1089 1090 return IRQ_HANDLED; 1091} 1092 1093 1094/* 1095 * Neo specific way of turning off the receiver. 1096 * Used as a way to enforce queue flow control when in 1097 * hardware flow control mode. 1098 */ 1099static void neo_disable_receiver(struct channel_t *ch) 1100{ 1101 unsigned char tmp = readb(&ch->ch_neo_uart->ier); 1102 1103 tmp &= ~(UART_IER_RDI); 1104 writeb(tmp, &ch->ch_neo_uart->ier); 1105 neo_pci_posting_flush(ch->ch_bd); 1106} 1107 1108 1109/* 1110 * Neo specific way of turning on the receiver. 1111 * Used as a way to un-enforce queue flow control when in 1112 * hardware flow control mode. 1113 */ 1114static void neo_enable_receiver(struct channel_t *ch) 1115{ 1116 unsigned char tmp = readb(&ch->ch_neo_uart->ier); 1117 1118 tmp |= (UART_IER_RDI); 1119 writeb(tmp, &ch->ch_neo_uart->ier); 1120 neo_pci_posting_flush(ch->ch_bd); 1121} 1122 1123 1124static void neo_copy_data_from_uart_to_queue(struct channel_t *ch) 1125{ 1126 int qleft = 0; 1127 unsigned char linestatus = 0; 1128 unsigned char error_mask = 0; 1129 int n = 0; 1130 int total = 0; 1131 ushort head; 1132 ushort tail; 1133 unsigned long flags; 1134 1135 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1136 return; 1137 1138 spin_lock_irqsave(&ch->ch_lock, flags); 1139 1140 /* cache head and tail of queue */ 1141 head = ch->ch_r_head & RQUEUEMASK; 1142 tail = ch->ch_r_tail & RQUEUEMASK; 1143 1144 /* Get our cached LSR */ 1145 linestatus = ch->ch_cached_lsr; 1146 ch->ch_cached_lsr = 0; 1147 1148 /* Store how much space we have left in the queue */ 1149 qleft = tail - head - 1; 1150 if (qleft < 0) 1151 qleft += RQUEUEMASK + 1; 1152 1153 /* 1154 * If the UART is not in FIFO mode, force the FIFO copy to 1155 * NOT be run, by setting total to 0. 1156 * 1157 * On the other hand, if the UART IS in FIFO mode, then ask 1158 * the UART to give us an approximation of data it has RX'ed. 1159 */ 1160 if (!(ch->ch_flags & CH_FIFO_ENABLED)) 1161 total = 0; 1162 else { 1163 total = readb(&ch->ch_neo_uart->rfifo); 1164 1165 /* 1166 * EXAR chip bug - RX FIFO COUNT - Fudge factor. 1167 * 1168 * This resolves a problem/bug with the Exar chip that sometimes 1169 * returns a bogus value in the rfifo register. 1170 * The count can be any where from 0-3 bytes "off". 1171 * Bizarre, but true. 1172 */ 1173 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID) 1174 total -= 1; 1175 else 1176 total -= 3; 1177 } 1178 1179 1180 /* 1181 * Finally, bound the copy to make sure we don't overflow 1182 * our own queue... 1183 * The byte by byte copy loop below this loop this will 1184 * deal with the queue overflow possibility. 1185 */ 1186 total = min(total, qleft); 1187 1188 while (total > 0) { 1189 1190 /* 1191 * Grab the linestatus register, we need to check 1192 * to see if there are any errors in the FIFO. 1193 */ 1194 linestatus = readb(&ch->ch_neo_uart->lsr); 1195 1196 /* 1197 * Break out if there is a FIFO error somewhere. 1198 * This will allow us to go byte by byte down below, 1199 * finding the exact location of the error. 1200 */ 1201 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) 1202 break; 1203 1204 /* Make sure we don't go over the end of our queue */ 1205 n = min(((uint) total), (RQUEUESIZE - (uint) head)); 1206 1207 /* 1208 * Cut down n even further if needed, this is to fix 1209 * a problem with memcpy_fromio() with the Neo on the 1210 * IBM pSeries platform. 1211 * 15 bytes max appears to be the magic number. 1212 */ 1213 n = min((uint) n, (uint) 12); 1214 1215 /* 1216 * Since we are grabbing the linestatus register, which 1217 * will reset some bits after our read, we need to ensure 1218 * we don't miss our TX FIFO emptys. 1219 */ 1220 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) 1221 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1222 1223 linestatus = 0; 1224 1225 /* Copy data from uart to the queue */ 1226 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); 1227 dgnc_sniff_nowait_nolock(ch, "UART READ", ch->ch_rqueue + head, n); 1228 1229 /* 1230 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed 1231 * that all the data currently in the FIFO is free of 1232 * breaks and parity/frame/orun errors. 1233 */ 1234 memset(ch->ch_equeue + head, 0, n); 1235 1236 /* Add to and flip head if needed */ 1237 head = (head + n) & RQUEUEMASK; 1238 total -= n; 1239 qleft -= n; 1240 ch->ch_rxcount += n; 1241 } 1242 1243 /* 1244 * Create a mask to determine whether we should 1245 * insert the character (if any) into our queue. 1246 */ 1247 if (ch->ch_c_iflag & IGNBRK) 1248 error_mask |= UART_LSR_BI; 1249 1250 /* 1251 * Now cleanup any leftover bytes still in the UART. 1252 * Also deal with any possible queue overflow here as well. 1253 */ 1254 while (1) { 1255 1256 /* 1257 * Its possible we have a linestatus from the loop above 1258 * this, so we "OR" on any extra bits. 1259 */ 1260 linestatus |= readb(&ch->ch_neo_uart->lsr); 1261 1262 /* 1263 * If the chip tells us there is no more data pending to 1264 * be read, we can then leave. 1265 * But before we do, cache the linestatus, just in case. 1266 */ 1267 if (!(linestatus & UART_LSR_DR)) { 1268 ch->ch_cached_lsr = linestatus; 1269 break; 1270 } 1271 1272 /* No need to store this bit */ 1273 linestatus &= ~UART_LSR_DR; 1274 1275 /* 1276 * Since we are grabbing the linestatus register, which 1277 * will reset some bits after our read, we need to ensure 1278 * we don't miss our TX FIFO emptys. 1279 */ 1280 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) { 1281 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR); 1282 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1283 } 1284 1285 /* 1286 * Discard character if we are ignoring the error mask. 1287 */ 1288 if (linestatus & error_mask) { 1289 unsigned char discard; 1290 1291 linestatus = 0; 1292 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); 1293 continue; 1294 } 1295 1296 /* 1297 * If our queue is full, we have no choice but to drop some data. 1298 * The assumption is that HWFLOW or SWFLOW should have stopped 1299 * things way way before we got to this point. 1300 * 1301 * I decided that I wanted to ditch the oldest data first, 1302 * I hope thats okay with everyone? Yes? Good. 1303 */ 1304 while (qleft < 1) { 1305 tail = (tail + 1) & RQUEUEMASK; 1306 ch->ch_r_tail = tail; 1307 ch->ch_err_overrun++; 1308 qleft++; 1309 } 1310 1311 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); 1312 ch->ch_equeue[head] = (unsigned char) linestatus; 1313 dgnc_sniff_nowait_nolock(ch, "UART READ", ch->ch_rqueue + head, 1); 1314 1315 /* Ditch any remaining linestatus value. */ 1316 linestatus = 0; 1317 1318 /* Add to and flip head if needed */ 1319 head = (head + 1) & RQUEUEMASK; 1320 1321 qleft--; 1322 ch->ch_rxcount++; 1323 } 1324 1325 /* 1326 * Write new final heads to channel structure. 1327 */ 1328 ch->ch_r_head = head & RQUEUEMASK; 1329 ch->ch_e_head = head & EQUEUEMASK; 1330 1331 spin_unlock_irqrestore(&ch->ch_lock, flags); 1332} 1333 1334 1335/* 1336 * This function basically goes to sleep for secs, or until 1337 * it gets signalled that the port has fully drained. 1338 */ 1339static int neo_drain(struct tty_struct *tty, uint seconds) 1340{ 1341 unsigned long flags; 1342 struct channel_t *ch; 1343 struct un_t *un; 1344 int rc = 0; 1345 1346 if (!tty || tty->magic != TTY_MAGIC) 1347 return -ENXIO; 1348 1349 un = (struct un_t *) tty->driver_data; 1350 if (!un || un->magic != DGNC_UNIT_MAGIC) 1351 return -ENXIO; 1352 1353 ch = un->un_ch; 1354 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1355 return -ENXIO; 1356 1357 spin_lock_irqsave(&ch->ch_lock, flags); 1358 un->un_flags |= UN_EMPTY; 1359 spin_unlock_irqrestore(&ch->ch_lock, flags); 1360 1361 /* 1362 * Go to sleep waiting for the tty layer to wake me back up when 1363 * the empty flag goes away. 1364 * 1365 * NOTE: TODO: Do something with time passed in. 1366 */ 1367 rc = wait_event_interruptible(un->un_flags_wait, ((un->un_flags & UN_EMPTY) == 0)); 1368 1369 /* If ret is non-zero, user ctrl-c'ed us */ 1370 return rc; 1371} 1372 1373 1374/* 1375 * Flush the WRITE FIFO on the Neo. 1376 * 1377 * NOTE: Channel lock MUST be held before calling this function! 1378 */ 1379static void neo_flush_uart_write(struct channel_t *ch) 1380{ 1381 unsigned char tmp = 0; 1382 int i = 0; 1383 1384 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1385 return; 1386 1387 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1388 neo_pci_posting_flush(ch->ch_bd); 1389 1390 for (i = 0; i < 10; i++) { 1391 1392 /* Check to see if the UART feels it completely flushed the FIFO. */ 1393 tmp = readb(&ch->ch_neo_uart->isr_fcr); 1394 if (tmp & 4) 1395 udelay(10); 1396 else 1397 break; 1398 } 1399 1400 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1401} 1402 1403 1404/* 1405 * Flush the READ FIFO on the Neo. 1406 * 1407 * NOTE: Channel lock MUST be held before calling this function! 1408 */ 1409static void neo_flush_uart_read(struct channel_t *ch) 1410{ 1411 unsigned char tmp = 0; 1412 int i = 0; 1413 1414 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1415 return; 1416 1417 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); 1418 neo_pci_posting_flush(ch->ch_bd); 1419 1420 for (i = 0; i < 10; i++) { 1421 1422 /* Check to see if the UART feels it completely flushed the FIFO. */ 1423 tmp = readb(&ch->ch_neo_uart->isr_fcr); 1424 if (tmp & 2) 1425 udelay(10); 1426 else 1427 break; 1428 } 1429} 1430 1431 1432static void neo_copy_data_from_queue_to_uart(struct channel_t *ch) 1433{ 1434 ushort head; 1435 ushort tail; 1436 int n; 1437 int s; 1438 int qlen; 1439 uint len_written = 0; 1440 unsigned long flags; 1441 1442 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1443 return; 1444 1445 spin_lock_irqsave(&ch->ch_lock, flags); 1446 1447 /* No data to write to the UART */ 1448 if (ch->ch_w_tail == ch->ch_w_head) { 1449 spin_unlock_irqrestore(&ch->ch_lock, flags); 1450 return; 1451 } 1452 1453 /* If port is "stopped", don't send any data to the UART */ 1454 if ((ch->ch_flags & CH_FORCED_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) { 1455 spin_unlock_irqrestore(&ch->ch_lock, flags); 1456 return; 1457 } 1458 1459 /* 1460 * If FIFOs are disabled. Send data directly to txrx register 1461 */ 1462 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { 1463 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr); 1464 1465 /* Cache the LSR bits for later parsing */ 1466 ch->ch_cached_lsr |= lsrbits; 1467 if (ch->ch_cached_lsr & UART_LSR_THRE) { 1468 ch->ch_cached_lsr &= ~(UART_LSR_THRE); 1469 1470 /* 1471 * If RTS Toggle mode is on, turn on RTS now if not already set, 1472 * and make sure we get an event when the data transfer has completed. 1473 */ 1474 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) { 1475 if (!(ch->ch_mostat & UART_MCR_RTS)) { 1476 ch->ch_mostat |= (UART_MCR_RTS); 1477 neo_assert_modem_signals(ch); 1478 } 1479 ch->ch_tun.un_flags |= (UN_EMPTY); 1480 } 1481 /* 1482 * If DTR Toggle mode is on, turn on DTR now if not already set, 1483 * and make sure we get an event when the data transfer has completed. 1484 */ 1485 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) { 1486 if (!(ch->ch_mostat & UART_MCR_DTR)) { 1487 ch->ch_mostat |= (UART_MCR_DTR); 1488 neo_assert_modem_signals(ch); 1489 } 1490 ch->ch_tun.un_flags |= (UN_EMPTY); 1491 } 1492 1493 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx); 1494 ch->ch_w_tail++; 1495 ch->ch_w_tail &= WQUEUEMASK; 1496 ch->ch_txcount++; 1497 } 1498 spin_unlock_irqrestore(&ch->ch_lock, flags); 1499 return; 1500 } 1501 1502 /* 1503 * We have to do it this way, because of the EXAR TXFIFO count bug. 1504 */ 1505 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) { 1506 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) { 1507 spin_unlock_irqrestore(&ch->ch_lock, flags); 1508 return; 1509 } 1510 1511 len_written = 0; 1512 1513 n = readb(&ch->ch_neo_uart->tfifo); 1514 1515 if ((unsigned int) n > ch->ch_t_tlevel) { 1516 spin_unlock_irqrestore(&ch->ch_lock, flags); 1517 return; 1518 } 1519 1520 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; 1521 } else { 1522 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo); 1523 } 1524 1525 /* cache head and tail of queue */ 1526 head = ch->ch_w_head & WQUEUEMASK; 1527 tail = ch->ch_w_tail & WQUEUEMASK; 1528 qlen = (head - tail) & WQUEUEMASK; 1529 1530 /* Find minimum of the FIFO space, versus queue length */ 1531 n = min(n, qlen); 1532 1533 while (n > 0) { 1534 1535 s = ((head >= tail) ? head : WQUEUESIZE) - tail; 1536 s = min(s, n); 1537 1538 if (s <= 0) 1539 break; 1540 1541 /* 1542 * If RTS Toggle mode is on, turn on RTS now if not already set, 1543 * and make sure we get an event when the data transfer has completed. 1544 */ 1545 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) { 1546 if (!(ch->ch_mostat & UART_MCR_RTS)) { 1547 ch->ch_mostat |= (UART_MCR_RTS); 1548 neo_assert_modem_signals(ch); 1549 } 1550 ch->ch_tun.un_flags |= (UN_EMPTY); 1551 } 1552 1553 /* 1554 * If DTR Toggle mode is on, turn on DTR now if not already set, 1555 * and make sure we get an event when the data transfer has completed. 1556 */ 1557 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) { 1558 if (!(ch->ch_mostat & UART_MCR_DTR)) { 1559 ch->ch_mostat |= (UART_MCR_DTR); 1560 neo_assert_modem_signals(ch); 1561 } 1562 ch->ch_tun.un_flags |= (UN_EMPTY); 1563 } 1564 1565 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s); 1566 dgnc_sniff_nowait_nolock(ch, "UART WRITE", ch->ch_wqueue + tail, s); 1567 1568 /* Add and flip queue if needed */ 1569 tail = (tail + s) & WQUEUEMASK; 1570 n -= s; 1571 ch->ch_txcount += s; 1572 len_written += s; 1573 } 1574 1575 /* Update the final tail */ 1576 ch->ch_w_tail = tail & WQUEUEMASK; 1577 1578 if (len_written > 0) { 1579 neo_pci_posting_flush(ch->ch_bd); 1580 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1581 } 1582 1583 spin_unlock_irqrestore(&ch->ch_lock, flags); 1584} 1585 1586 1587static void neo_parse_modem(struct channel_t *ch, unsigned char signals) 1588{ 1589 unsigned char msignals = signals; 1590 1591 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1592 return; 1593 1594 /* 1595 * Do altpin switching. Altpin switches DCD and DSR. 1596 * This prolly breaks DSRPACE, so we should be more clever here. 1597 */ 1598 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) { 1599 unsigned char mswap = msignals; 1600 1601 if (mswap & UART_MSR_DDCD) { 1602 msignals &= ~UART_MSR_DDCD; 1603 msignals |= UART_MSR_DDSR; 1604 } 1605 if (mswap & UART_MSR_DDSR) { 1606 msignals &= ~UART_MSR_DDSR; 1607 msignals |= UART_MSR_DDCD; 1608 } 1609 if (mswap & UART_MSR_DCD) { 1610 msignals &= ~UART_MSR_DCD; 1611 msignals |= UART_MSR_DSR; 1612 } 1613 if (mswap & UART_MSR_DSR) { 1614 msignals &= ~UART_MSR_DSR; 1615 msignals |= UART_MSR_DCD; 1616 } 1617 } 1618 1619 /* Scrub off lower bits. They signify delta's, which I don't care about */ 1620 msignals &= 0xf0; 1621 1622 if (msignals & UART_MSR_DCD) 1623 ch->ch_mistat |= UART_MSR_DCD; 1624 else 1625 ch->ch_mistat &= ~UART_MSR_DCD; 1626 1627 if (msignals & UART_MSR_DSR) 1628 ch->ch_mistat |= UART_MSR_DSR; 1629 else 1630 ch->ch_mistat &= ~UART_MSR_DSR; 1631 1632 if (msignals & UART_MSR_RI) 1633 ch->ch_mistat |= UART_MSR_RI; 1634 else 1635 ch->ch_mistat &= ~UART_MSR_RI; 1636 1637 if (msignals & UART_MSR_CTS) 1638 ch->ch_mistat |= UART_MSR_CTS; 1639 else 1640 ch->ch_mistat &= ~UART_MSR_CTS; 1641} 1642 1643 1644/* Make the UART raise any of the output signals we want up */ 1645static void neo_assert_modem_signals(struct channel_t *ch) 1646{ 1647 unsigned char out; 1648 1649 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1650 return; 1651 1652 out = ch->ch_mostat; 1653 1654 if (ch->ch_flags & CH_LOOPBACK) 1655 out |= UART_MCR_LOOP; 1656 1657 writeb(out, &ch->ch_neo_uart->mcr); 1658 neo_pci_posting_flush(ch->ch_bd); 1659 1660 /* Give time for the UART to actually raise/drop the signals */ 1661 udelay(10); 1662} 1663 1664 1665static void neo_send_start_character(struct channel_t *ch) 1666{ 1667 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1668 return; 1669 1670 if (ch->ch_startc != _POSIX_VDISABLE) { 1671 ch->ch_xon_sends++; 1672 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); 1673 neo_pci_posting_flush(ch->ch_bd); 1674 udelay(10); 1675 } 1676} 1677 1678 1679static void neo_send_stop_character(struct channel_t *ch) 1680{ 1681 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1682 return; 1683 1684 if (ch->ch_stopc != _POSIX_VDISABLE) { 1685 ch->ch_xoff_sends++; 1686 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); 1687 neo_pci_posting_flush(ch->ch_bd); 1688 udelay(10); 1689 } 1690} 1691 1692 1693/* 1694 * neo_uart_init 1695 */ 1696static void neo_uart_init(struct channel_t *ch) 1697{ 1698 1699 writeb(0, &ch->ch_neo_uart->ier); 1700 writeb(0, &ch->ch_neo_uart->efr); 1701 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); 1702 1703 1704 /* Clear out UART and FIFO */ 1705 readb(&ch->ch_neo_uart->txrx); 1706 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); 1707 readb(&ch->ch_neo_uart->lsr); 1708 readb(&ch->ch_neo_uart->msr); 1709 1710 ch->ch_flags |= CH_FIFO_ENABLED; 1711 1712 /* Assert any signals we want up */ 1713 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); 1714 neo_pci_posting_flush(ch->ch_bd); 1715} 1716 1717 1718/* 1719 * Make the UART completely turn off. 1720 */ 1721static void neo_uart_off(struct channel_t *ch) 1722{ 1723 /* Turn off UART enhanced bits */ 1724 writeb(0, &ch->ch_neo_uart->efr); 1725 1726 /* Stop all interrupts from occurring. */ 1727 writeb(0, &ch->ch_neo_uart->ier); 1728 neo_pci_posting_flush(ch->ch_bd); 1729} 1730 1731 1732static uint neo_get_uart_bytes_left(struct channel_t *ch) 1733{ 1734 unsigned char left = 0; 1735 unsigned char lsr = readb(&ch->ch_neo_uart->lsr); 1736 1737 /* We must cache the LSR as some of the bits get reset once read... */ 1738 ch->ch_cached_lsr |= lsr; 1739 1740 /* Determine whether the Transmitter is empty or not */ 1741 if (!(lsr & UART_LSR_TEMT)) { 1742 if (ch->ch_flags & CH_TX_FIFO_EMPTY) 1743 tasklet_schedule(&ch->ch_bd->helper_tasklet); 1744 left = 1; 1745 } else { 1746 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); 1747 left = 0; 1748 } 1749 1750 return left; 1751} 1752 1753 1754/* Channel lock MUST be held by the calling function! */ 1755static void neo_send_break(struct channel_t *ch, int msecs) 1756{ 1757 /* 1758 * If we receive a time of 0, this means turn off the break. 1759 */ 1760 if (msecs == 0) { 1761 if (ch->ch_flags & CH_BREAK_SENDING) { 1762 unsigned char temp = readb(&ch->ch_neo_uart->lcr); 1763 1764 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1765 neo_pci_posting_flush(ch->ch_bd); 1766 ch->ch_flags &= ~(CH_BREAK_SENDING); 1767 ch->ch_stop_sending_break = 0; 1768 } 1769 return; 1770 } 1771 1772 /* 1773 * Set the time we should stop sending the break. 1774 * If we are already sending a break, toss away the existing 1775 * time to stop, and use this new value instead. 1776 */ 1777 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs); 1778 1779 /* Tell the UART to start sending the break */ 1780 if (!(ch->ch_flags & CH_BREAK_SENDING)) { 1781 unsigned char temp = readb(&ch->ch_neo_uart->lcr); 1782 1783 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); 1784 neo_pci_posting_flush(ch->ch_bd); 1785 ch->ch_flags |= (CH_BREAK_SENDING); 1786 } 1787} 1788 1789 1790/* 1791 * neo_send_immediate_char. 1792 * 1793 * Sends a specific character as soon as possible to the UART, 1794 * jumping over any bytes that might be in the write queue. 1795 * 1796 * The channel lock MUST be held by the calling function. 1797 */ 1798static void neo_send_immediate_char(struct channel_t *ch, unsigned char c) 1799{ 1800 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) 1801 return; 1802 1803 writeb(c, &ch->ch_neo_uart->txrx); 1804 neo_pci_posting_flush(ch->ch_bd); 1805} 1806 1807 1808static unsigned int neo_read_eeprom(unsigned char __iomem *base, unsigned int address) 1809{ 1810 unsigned int enable; 1811 unsigned int bits; 1812 unsigned int databit; 1813 unsigned int val; 1814 1815 /* enable chip select */ 1816 writeb(NEO_EECS, base + NEO_EEREG); 1817 /* READ */ 1818 enable = (address | 0x180); 1819 1820 for (bits = 9; bits--; ) { 1821 databit = (enable & (1 << bits)) ? NEO_EEDI : 0; 1822 /* Set read address */ 1823 writeb(databit | NEO_EECS, base + NEO_EEREG); 1824 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG); 1825 } 1826 1827 val = 0; 1828 1829 for (bits = 17; bits--; ) { 1830 /* clock to EEPROM */ 1831 writeb(NEO_EECS, base + NEO_EEREG); 1832 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG); 1833 val <<= 1; 1834 /* read EEPROM */ 1835 if (readb(base + NEO_EEREG) & NEO_EEDO) 1836 val |= 1; 1837 } 1838 1839 /* clock falling edge */ 1840 writeb(NEO_EECS, base + NEO_EEREG); 1841 1842 /* drop chip select */ 1843 writeb(0x00, base + NEO_EEREG); 1844 1845 return val; 1846} 1847 1848 1849static void neo_vpd(struct dgnc_board *brd) 1850{ 1851 unsigned int i = 0; 1852 unsigned int a; 1853 1854 if (!brd || brd->magic != DGNC_BOARD_MAGIC) 1855 return; 1856 1857 if (!brd->re_map_membase) 1858 return; 1859 1860 /* Store the VPD into our buffer */ 1861 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) { 1862 a = neo_read_eeprom(brd->re_map_membase, i); 1863 brd->vpd[i*2] = a & 0xff; 1864 brd->vpd[(i*2)+1] = (a >> 8) & 0xff; 1865 } 1866 1867 if (((brd->vpd[0x08] != 0x82) /* long resource name tag */ 1868 && (brd->vpd[0x10] != 0x82)) /* long resource name tag (PCI-66 files)*/ 1869 || (brd->vpd[0x7F] != 0x78)) { /* small resource end tag */ 1870 1871 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE); 1872 } else { 1873 /* Search for the serial number */ 1874 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++) 1875 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N') 1876 strncpy(brd->serial_num, &(brd->vpd[i + 3]), 9); 1877 } 1878} 1879