1/* 2 * Copyright 2003 Digi International (www.digi.com) 3 * Scott H Kilau <Scott_Kilau at digi dot com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 13 * PURPOSE. See the GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * NOTE: THIS IS A SHARED HEADER. DO NOT CHANGE CODING STYLE!!! 20 * 21 */ 22 23#ifndef __DGNC_NEO_H 24#define __DGNC_NEO_H 25 26#include "dgnc_types.h" 27#include "dgnc_driver.h" 28 29/************************************************************************ 30 * Per channel/port NEO UART structure * 31 ************************************************************************ 32 * Base Structure Entries Usage Meanings to Host * 33 * * 34 * W = read write R = read only * 35 * U = Unused. * 36 ************************************************************************/ 37 38struct neo_uart_struct { 39 u8 txrx; /* WR RHR/THR - Holding Reg */ 40 u8 ier; /* WR IER - Interrupt Enable Reg */ 41 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */ 42 u8 lcr; /* WR LCR - Line Control Reg */ 43 u8 mcr; /* WR MCR - Modem Control Reg */ 44 u8 lsr; /* WR LSR - Line Status Reg */ 45 u8 msr; /* WR MSR - Modem Status Reg */ 46 u8 spr; /* WR SPR - Scratch Pad Reg */ 47 u8 fctr; /* WR FCTR - Feature Control Reg */ 48 u8 efr; /* WR EFR - Enhanced Function Reg */ 49 u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */ 50 u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */ 51 u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */ 52 u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */ 53 u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */ 54 u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */ 55 56 u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */ 57 u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */ 58 u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */ 59 u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */ 60}; 61 62/* Where to read the extended interrupt register (32bits instead of 8bits) */ 63#define UART_17158_POLL_ADDR_OFFSET 0x80 64 65/* These are the current dvid's of the Neo boards */ 66#define UART_XR17C158_DVID 0x20 67#define UART_XR17D158_DVID 0x20 68#define UART_XR17E158_DVID 0x40 69 70#define NEO_EECK 0x10 /* Clock */ 71#define NEO_EECS 0x20 /* Chip Select */ 72#define NEO_EEDI 0x40 /* Data In is an Output Pin */ 73#define NEO_EEDO 0x80 /* Data Out is an Input Pin */ 74#define NEO_EEREG 0x8E /* offset to EEPROM control reg */ 75 76 77#define NEO_VPD_IMAGESIZE 0x40 /* size of image to read from EEPROM in words */ 78#define NEO_VPD_IMAGEBYTES (NEO_VPD_IMAGESIZE * 2) 79 80/* 81 * These are the redefinitions for the FCTR on the XR17C158, since 82 * Exar made them different than their earlier design. (XR16C854) 83 */ 84 85/* These are only applicable when table D is selected */ 86#define UART_17158_FCTR_RTS_NODELAY 0x00 87#define UART_17158_FCTR_RTS_4DELAY 0x01 88#define UART_17158_FCTR_RTS_6DELAY 0x02 89#define UART_17158_FCTR_RTS_8DELAY 0x03 90#define UART_17158_FCTR_RTS_12DELAY 0x12 91#define UART_17158_FCTR_RTS_16DELAY 0x05 92#define UART_17158_FCTR_RTS_20DELAY 0x13 93#define UART_17158_FCTR_RTS_24DELAY 0x06 94#define UART_17158_FCTR_RTS_28DELAY 0x14 95#define UART_17158_FCTR_RTS_32DELAY 0x07 96#define UART_17158_FCTR_RTS_36DELAY 0x16 97#define UART_17158_FCTR_RTS_40DELAY 0x08 98#define UART_17158_FCTR_RTS_44DELAY 0x09 99#define UART_17158_FCTR_RTS_48DELAY 0x10 100#define UART_17158_FCTR_RTS_52DELAY 0x11 101 102#define UART_17158_FCTR_RTS_IRDA 0x10 103#define UART_17158_FCTR_RS485 0x20 104#define UART_17158_FCTR_TRGA 0x00 105#define UART_17158_FCTR_TRGB 0x40 106#define UART_17158_FCTR_TRGC 0x80 107#define UART_17158_FCTR_TRGD 0xC0 108 109/* 17158 trigger table selects.. */ 110#define UART_17158_FCTR_BIT6 0x40 111#define UART_17158_FCTR_BIT7 0x80 112 113/* 17158 TX/RX memmapped buffer offsets */ 114#define UART_17158_RX_FIFOSIZE 64 115#define UART_17158_TX_FIFOSIZE 64 116 117/* 17158 Extended IIR's */ 118#define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ 119#define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */ 120#define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */ 121#define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */ 122 123/* 124 * These are the extended interrupts that get sent 125 * back to us from the UART's 32bit interrupt register 126 */ 127#define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */ 128#define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */ 129#define UART_17158_TXRDY 0x3 /* TX Ready */ 130#define UART_17158_MSR 0x4 /* Modem State Change */ 131#define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */ 132#define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */ 133 134/* 135 * These are the EXTENDED definitions for the 17C158's Interrupt 136 * Enable Register. 137 */ 138#define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */ 139#define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ 140#define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ 141#define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ 142#define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ 143 144#define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ 145#define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ 146 147#define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */ 148#define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */ 149#define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */ 150#define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */ 151 152/* 153 * Our Global Variables 154 */ 155extern struct board_ops dgnc_neo_ops; 156 157#endif 158