1/* 2 * AD5933 AD5934 Impedance Converter, Network Analyzer 3 * 4 * Copyright 2011 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8 9#include <linux/interrupt.h> 10#include <linux/device.h> 11#include <linux/kernel.h> 12#include <linux/sysfs.h> 13#include <linux/i2c.h> 14#include <linux/regulator/consumer.h> 15#include <linux/slab.h> 16#include <linux/types.h> 17#include <linux/err.h> 18#include <linux/delay.h> 19#include <linux/module.h> 20#include <asm/div64.h> 21 22#include <linux/iio/iio.h> 23#include <linux/iio/sysfs.h> 24#include <linux/iio/buffer.h> 25#include <linux/iio/kfifo_buf.h> 26 27#include "ad5933.h" 28 29/* AD5933/AD5934 Registers */ 30#define AD5933_REG_CONTROL_HB 0x80 /* R/W, 2 bytes */ 31#define AD5933_REG_CONTROL_LB 0x81 /* R/W, 2 bytes */ 32#define AD5933_REG_FREQ_START 0x82 /* R/W, 3 bytes */ 33#define AD5933_REG_FREQ_INC 0x85 /* R/W, 3 bytes */ 34#define AD5933_REG_INC_NUM 0x88 /* R/W, 2 bytes, 9 bit */ 35#define AD5933_REG_SETTLING_CYCLES 0x8A /* R/W, 2 bytes */ 36#define AD5933_REG_STATUS 0x8F /* R, 1 byte */ 37#define AD5933_REG_TEMP_DATA 0x92 /* R, 2 bytes*/ 38#define AD5933_REG_REAL_DATA 0x94 /* R, 2 bytes*/ 39#define AD5933_REG_IMAG_DATA 0x96 /* R, 2 bytes*/ 40 41/* AD5933_REG_CONTROL_HB Bits */ 42#define AD5933_CTRL_INIT_START_FREQ (0x1 << 4) 43#define AD5933_CTRL_START_SWEEP (0x2 << 4) 44#define AD5933_CTRL_INC_FREQ (0x3 << 4) 45#define AD5933_CTRL_REPEAT_FREQ (0x4 << 4) 46#define AD5933_CTRL_MEASURE_TEMP (0x9 << 4) 47#define AD5933_CTRL_POWER_DOWN (0xA << 4) 48#define AD5933_CTRL_STANDBY (0xB << 4) 49 50#define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1) 51#define AD5933_CTRL_RANGE_200mVpp (0x1 << 1) 52#define AD5933_CTRL_RANGE_400mVpp (0x2 << 1) 53#define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1) 54#define AD5933_CTRL_RANGE(x) ((x) << 1) 55 56#define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0) 57#define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0) 58 59/* AD5933_REG_CONTROL_LB Bits */ 60#define AD5933_CTRL_RESET (0x1 << 4) 61#define AD5933_CTRL_INT_SYSCLK (0x0 << 3) 62#define AD5933_CTRL_EXT_SYSCLK (0x1 << 3) 63 64/* AD5933_REG_STATUS Bits */ 65#define AD5933_STAT_TEMP_VALID (0x1 << 0) 66#define AD5933_STAT_DATA_VALID (0x1 << 1) 67#define AD5933_STAT_SWEEP_DONE (0x1 << 2) 68 69/* I2C Block Commands */ 70#define AD5933_I2C_BLOCK_WRITE 0xA0 71#define AD5933_I2C_BLOCK_READ 0xA1 72#define AD5933_I2C_ADDR_POINTER 0xB0 73 74/* Device Specs */ 75#define AD5933_INT_OSC_FREQ_Hz 16776000 76#define AD5933_MAX_OUTPUT_FREQ_Hz 100000 77#define AD5933_MAX_RETRIES 100 78 79#define AD5933_OUT_RANGE 1 80#define AD5933_OUT_RANGE_AVAIL 2 81#define AD5933_OUT_SETTLING_CYCLES 3 82#define AD5933_IN_PGA_GAIN 4 83#define AD5933_IN_PGA_GAIN_AVAIL 5 84#define AD5933_FREQ_POINTS 6 85 86#define AD5933_POLL_TIME_ms 10 87#define AD5933_INIT_EXCITATION_TIME_ms 100 88 89struct ad5933_state { 90 struct i2c_client *client; 91 struct regulator *reg; 92 struct ad5933_platform_data *pdata; 93 struct delayed_work work; 94 unsigned long mclk_hz; 95 unsigned char ctrl_hb; 96 unsigned char ctrl_lb; 97 unsigned range_avail[4]; 98 unsigned short vref_mv; 99 unsigned short settling_cycles; 100 unsigned short freq_points; 101 unsigned freq_start; 102 unsigned freq_inc; 103 unsigned state; 104 unsigned poll_time_jiffies; 105}; 106 107static struct ad5933_platform_data ad5933_default_pdata = { 108 .vref_mv = 3300, 109}; 110 111static const struct iio_chan_spec ad5933_channels[] = { 112 { 113 .type = IIO_TEMP, 114 .indexed = 1, 115 .channel = 0, 116 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), 117 .address = AD5933_REG_TEMP_DATA, 118 .scan_index = -1, 119 .scan_type = { 120 .sign = 's', 121 .realbits = 14, 122 .storagebits = 16, 123 }, 124 }, { /* Ring Channels */ 125 .type = IIO_VOLTAGE, 126 .indexed = 1, 127 .channel = 0, 128 .extend_name = "real", 129 .address = AD5933_REG_REAL_DATA, 130 .scan_index = 0, 131 .scan_type = { 132 .sign = 's', 133 .realbits = 16, 134 .storagebits = 16, 135 }, 136 }, { 137 .type = IIO_VOLTAGE, 138 .indexed = 1, 139 .channel = 0, 140 .extend_name = "imag", 141 .address = AD5933_REG_IMAG_DATA, 142 .scan_index = 1, 143 .scan_type = { 144 .sign = 's', 145 .realbits = 16, 146 .storagebits = 16, 147 }, 148 }, 149}; 150 151static int ad5933_i2c_write(struct i2c_client *client, 152 u8 reg, u8 len, u8 *data) 153{ 154 int ret; 155 156 while (len--) { 157 ret = i2c_smbus_write_byte_data(client, reg++, *data++); 158 if (ret < 0) { 159 dev_err(&client->dev, "I2C write error\n"); 160 return ret; 161 } 162 } 163 return 0; 164} 165 166static int ad5933_i2c_read(struct i2c_client *client, 167 u8 reg, u8 len, u8 *data) 168{ 169 int ret; 170 171 while (len--) { 172 ret = i2c_smbus_read_byte_data(client, reg++); 173 if (ret < 0) { 174 dev_err(&client->dev, "I2C read error\n"); 175 return ret; 176 } 177 *data++ = ret; 178 } 179 return 0; 180} 181 182static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd) 183{ 184 unsigned char dat = st->ctrl_hb | cmd; 185 186 return ad5933_i2c_write(st->client, 187 AD5933_REG_CONTROL_HB, 1, &dat); 188} 189 190static int ad5933_reset(struct ad5933_state *st) 191{ 192 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET; 193 194 return ad5933_i2c_write(st->client, 195 AD5933_REG_CONTROL_LB, 1, &dat); 196} 197 198static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event) 199{ 200 unsigned char val, timeout = AD5933_MAX_RETRIES; 201 int ret; 202 203 while (timeout--) { 204 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val); 205 if (ret < 0) 206 return ret; 207 if (val & event) 208 return val; 209 cpu_relax(); 210 mdelay(1); 211 } 212 213 return -EAGAIN; 214} 215 216static int ad5933_set_freq(struct ad5933_state *st, 217 unsigned reg, unsigned long freq) 218{ 219 unsigned long long freqreg; 220 union { 221 __be32 d32; 222 u8 d8[4]; 223 } dat; 224 225 freqreg = (u64) freq * (u64) (1 << 27); 226 do_div(freqreg, st->mclk_hz / 4); 227 228 switch (reg) { 229 case AD5933_REG_FREQ_START: 230 st->freq_start = freq; 231 break; 232 case AD5933_REG_FREQ_INC: 233 st->freq_inc = freq; 234 break; 235 default: 236 return -EINVAL; 237 } 238 239 dat.d32 = cpu_to_be32(freqreg); 240 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]); 241} 242 243static int ad5933_setup(struct ad5933_state *st) 244{ 245 __be16 dat; 246 int ret; 247 248 ret = ad5933_reset(st); 249 if (ret < 0) 250 return ret; 251 252 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000); 253 if (ret < 0) 254 return ret; 255 256 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200); 257 if (ret < 0) 258 return ret; 259 260 st->settling_cycles = 10; 261 dat = cpu_to_be16(st->settling_cycles); 262 263 ret = ad5933_i2c_write(st->client, 264 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat); 265 if (ret < 0) 266 return ret; 267 268 st->freq_points = 100; 269 dat = cpu_to_be16(st->freq_points); 270 271 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat); 272} 273 274static void ad5933_calc_out_ranges(struct ad5933_state *st) 275{ 276 int i; 277 unsigned normalized_3v3[4] = {1980, 198, 383, 970}; 278 279 for (i = 0; i < 4; i++) 280 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300; 281 282} 283 284/* 285 * handles: AD5933_REG_FREQ_START and AD5933_REG_FREQ_INC 286 */ 287 288static ssize_t ad5933_show_frequency(struct device *dev, 289 struct device_attribute *attr, 290 char *buf) 291{ 292 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 293 struct ad5933_state *st = iio_priv(indio_dev); 294 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 295 int ret; 296 unsigned long long freqreg; 297 union { 298 __be32 d32; 299 u8 d8[4]; 300 } dat; 301 302 mutex_lock(&indio_dev->mlock); 303 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]); 304 mutex_unlock(&indio_dev->mlock); 305 if (ret < 0) 306 return ret; 307 308 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF; 309 310 freqreg = (u64) freqreg * (u64) (st->mclk_hz / 4); 311 do_div(freqreg, 1 << 27); 312 313 return sprintf(buf, "%d\n", (int) freqreg); 314} 315 316static ssize_t ad5933_store_frequency(struct device *dev, 317 struct device_attribute *attr, 318 const char *buf, 319 size_t len) 320{ 321 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 322 struct ad5933_state *st = iio_priv(indio_dev); 323 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 324 unsigned long val; 325 int ret; 326 327 ret = kstrtoul(buf, 10, &val); 328 if (ret) 329 return ret; 330 331 if (val > AD5933_MAX_OUTPUT_FREQ_Hz) 332 return -EINVAL; 333 334 mutex_lock(&indio_dev->mlock); 335 ret = ad5933_set_freq(st, this_attr->address, val); 336 mutex_unlock(&indio_dev->mlock); 337 338 return ret ? ret : len; 339} 340 341static IIO_DEVICE_ATTR(out_voltage0_freq_start, S_IRUGO | S_IWUSR, 342 ad5933_show_frequency, 343 ad5933_store_frequency, 344 AD5933_REG_FREQ_START); 345 346static IIO_DEVICE_ATTR(out_voltage0_freq_increment, S_IRUGO | S_IWUSR, 347 ad5933_show_frequency, 348 ad5933_store_frequency, 349 AD5933_REG_FREQ_INC); 350 351static ssize_t ad5933_show(struct device *dev, 352 struct device_attribute *attr, 353 char *buf) 354{ 355 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 356 struct ad5933_state *st = iio_priv(indio_dev); 357 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 358 int ret = 0, len = 0; 359 360 mutex_lock(&indio_dev->mlock); 361 switch ((u32) this_attr->address) { 362 case AD5933_OUT_RANGE: 363 len = sprintf(buf, "%d\n", 364 st->range_avail[(st->ctrl_hb >> 1) & 0x3]); 365 break; 366 case AD5933_OUT_RANGE_AVAIL: 367 len = sprintf(buf, "%d %d %d %d\n", st->range_avail[0], 368 st->range_avail[3], st->range_avail[2], 369 st->range_avail[1]); 370 break; 371 case AD5933_OUT_SETTLING_CYCLES: 372 len = sprintf(buf, "%d\n", st->settling_cycles); 373 break; 374 case AD5933_IN_PGA_GAIN: 375 len = sprintf(buf, "%s\n", 376 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ? 377 "1" : "0.2"); 378 break; 379 case AD5933_IN_PGA_GAIN_AVAIL: 380 len = sprintf(buf, "1 0.2\n"); 381 break; 382 case AD5933_FREQ_POINTS: 383 len = sprintf(buf, "%d\n", st->freq_points); 384 break; 385 default: 386 ret = -EINVAL; 387 } 388 389 mutex_unlock(&indio_dev->mlock); 390 return ret ? ret : len; 391} 392 393static ssize_t ad5933_store(struct device *dev, 394 struct device_attribute *attr, 395 const char *buf, 396 size_t len) 397{ 398 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 399 struct ad5933_state *st = iio_priv(indio_dev); 400 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 401 u16 val; 402 int i, ret = 0; 403 __be16 dat; 404 405 if (this_attr->address != AD5933_IN_PGA_GAIN) { 406 ret = kstrtou16(buf, 10, &val); 407 if (ret) 408 return ret; 409 } 410 411 mutex_lock(&indio_dev->mlock); 412 switch ((u32) this_attr->address) { 413 case AD5933_OUT_RANGE: 414 for (i = 0; i < 4; i++) 415 if (val == st->range_avail[i]) { 416 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3); 417 st->ctrl_hb |= AD5933_CTRL_RANGE(i); 418 ret = ad5933_cmd(st, 0); 419 break; 420 } 421 ret = -EINVAL; 422 break; 423 case AD5933_IN_PGA_GAIN: 424 if (sysfs_streq(buf, "1")) { 425 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1; 426 } else if (sysfs_streq(buf, "0.2")) { 427 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1; 428 } else { 429 ret = -EINVAL; 430 break; 431 } 432 ret = ad5933_cmd(st, 0); 433 break; 434 case AD5933_OUT_SETTLING_CYCLES: 435 val = clamp(val, (u16)0, (u16)0x7FF); 436 st->settling_cycles = val; 437 438 /* 2x, 4x handling, see datasheet */ 439 if (val > 511) 440 val = (val >> 1) | (1 << 9); 441 else if (val > 1022) 442 val = (val >> 2) | (3 << 9); 443 444 dat = cpu_to_be16(val); 445 ret = ad5933_i2c_write(st->client, 446 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat); 447 break; 448 case AD5933_FREQ_POINTS: 449 val = clamp(val, (u16)0, (u16)511); 450 st->freq_points = val; 451 452 dat = cpu_to_be16(val); 453 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, 454 (u8 *)&dat); 455 break; 456 default: 457 ret = -EINVAL; 458 } 459 460 mutex_unlock(&indio_dev->mlock); 461 return ret ? ret : len; 462} 463 464static IIO_DEVICE_ATTR(out_voltage0_scale, S_IRUGO | S_IWUSR, 465 ad5933_show, 466 ad5933_store, 467 AD5933_OUT_RANGE); 468 469static IIO_DEVICE_ATTR(out_voltage0_scale_available, S_IRUGO, 470 ad5933_show, 471 NULL, 472 AD5933_OUT_RANGE_AVAIL); 473 474static IIO_DEVICE_ATTR(in_voltage0_scale, S_IRUGO | S_IWUSR, 475 ad5933_show, 476 ad5933_store, 477 AD5933_IN_PGA_GAIN); 478 479static IIO_DEVICE_ATTR(in_voltage0_scale_available, S_IRUGO, 480 ad5933_show, 481 NULL, 482 AD5933_IN_PGA_GAIN_AVAIL); 483 484static IIO_DEVICE_ATTR(out_voltage0_freq_points, S_IRUGO | S_IWUSR, 485 ad5933_show, 486 ad5933_store, 487 AD5933_FREQ_POINTS); 488 489static IIO_DEVICE_ATTR(out_voltage0_settling_cycles, S_IRUGO | S_IWUSR, 490 ad5933_show, 491 ad5933_store, 492 AD5933_OUT_SETTLING_CYCLES); 493 494/* note: 495 * ideally we would handle the scale attributes via the iio_info 496 * (read|write)_raw methods, however this part is a untypical since we 497 * don't create dedicated sysfs channel attributes for out0 and in0. 498 */ 499static struct attribute *ad5933_attributes[] = { 500 &iio_dev_attr_out_voltage0_scale.dev_attr.attr, 501 &iio_dev_attr_out_voltage0_scale_available.dev_attr.attr, 502 &iio_dev_attr_out_voltage0_freq_start.dev_attr.attr, 503 &iio_dev_attr_out_voltage0_freq_increment.dev_attr.attr, 504 &iio_dev_attr_out_voltage0_freq_points.dev_attr.attr, 505 &iio_dev_attr_out_voltage0_settling_cycles.dev_attr.attr, 506 &iio_dev_attr_in_voltage0_scale.dev_attr.attr, 507 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr, 508 NULL 509}; 510 511static const struct attribute_group ad5933_attribute_group = { 512 .attrs = ad5933_attributes, 513}; 514 515static int ad5933_read_raw(struct iio_dev *indio_dev, 516 struct iio_chan_spec const *chan, 517 int *val, 518 int *val2, 519 long m) 520{ 521 struct ad5933_state *st = iio_priv(indio_dev); 522 __be16 dat; 523 int ret = -EINVAL; 524 525 mutex_lock(&indio_dev->mlock); 526 switch (m) { 527 case IIO_CHAN_INFO_RAW: 528 case IIO_CHAN_INFO_PROCESSED: 529 if (iio_buffer_enabled(indio_dev)) { 530 ret = -EBUSY; 531 goto out; 532 } 533 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP); 534 if (ret < 0) 535 goto out; 536 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID); 537 if (ret < 0) 538 goto out; 539 540 ret = ad5933_i2c_read(st->client, 541 AD5933_REG_TEMP_DATA, 2, 542 (u8 *)&dat); 543 if (ret < 0) 544 goto out; 545 mutex_unlock(&indio_dev->mlock); 546 ret = be16_to_cpu(dat); 547 /* Temp in Milli degrees Celsius */ 548 if (ret < 8192) 549 *val = ret * 1000 / 32; 550 else 551 *val = (ret - 16384) * 1000 / 32; 552 553 return IIO_VAL_INT; 554 } 555 556out: 557 mutex_unlock(&indio_dev->mlock); 558 return ret; 559} 560 561static const struct iio_info ad5933_info = { 562 .read_raw = &ad5933_read_raw, 563 .attrs = &ad5933_attribute_group, 564 .driver_module = THIS_MODULE, 565}; 566 567static int ad5933_ring_preenable(struct iio_dev *indio_dev) 568{ 569 struct ad5933_state *st = iio_priv(indio_dev); 570 int ret; 571 572 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) 573 return -EINVAL; 574 575 ret = ad5933_reset(st); 576 if (ret < 0) 577 return ret; 578 579 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY); 580 if (ret < 0) 581 return ret; 582 583 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ); 584 if (ret < 0) 585 return ret; 586 587 st->state = AD5933_CTRL_INIT_START_FREQ; 588 589 return 0; 590} 591 592static int ad5933_ring_postenable(struct iio_dev *indio_dev) 593{ 594 struct ad5933_state *st = iio_priv(indio_dev); 595 596 /* AD5933_CTRL_INIT_START_FREQ: 597 * High Q complex circuits require a long time to reach steady state. 598 * To facilitate the measurement of such impedances, this mode allows 599 * the user full control of the settling time requirement before 600 * entering start frequency sweep mode where the impedance measurement 601 * takes place. In this mode the impedance is excited with the 602 * programmed start frequency (ad5933_ring_preenable), 603 * but no measurement takes place. 604 */ 605 606 schedule_delayed_work(&st->work, 607 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms)); 608 return 0; 609} 610 611static int ad5933_ring_postdisable(struct iio_dev *indio_dev) 612{ 613 struct ad5933_state *st = iio_priv(indio_dev); 614 615 cancel_delayed_work_sync(&st->work); 616 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN); 617} 618 619static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = { 620 .preenable = &ad5933_ring_preenable, 621 .postenable = &ad5933_ring_postenable, 622 .postdisable = &ad5933_ring_postdisable, 623}; 624 625static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev) 626{ 627 struct iio_buffer *buffer; 628 629 buffer = iio_kfifo_allocate(indio_dev); 630 if (!buffer) 631 return -ENOMEM; 632 633 iio_device_attach_buffer(indio_dev, buffer); 634 635 /* Ring buffer functions - here trigger setup related */ 636 indio_dev->setup_ops = &ad5933_ring_setup_ops; 637 638 indio_dev->modes |= INDIO_BUFFER_HARDWARE; 639 640 return 0; 641} 642 643static void ad5933_work(struct work_struct *work) 644{ 645 struct ad5933_state *st = container_of(work, 646 struct ad5933_state, work.work); 647 struct iio_dev *indio_dev = i2c_get_clientdata(st->client); 648 signed short buf[2]; 649 unsigned char status; 650 651 mutex_lock(&indio_dev->mlock); 652 if (st->state == AD5933_CTRL_INIT_START_FREQ) { 653 /* start sweep */ 654 ad5933_cmd(st, AD5933_CTRL_START_SWEEP); 655 st->state = AD5933_CTRL_START_SWEEP; 656 schedule_delayed_work(&st->work, st->poll_time_jiffies); 657 mutex_unlock(&indio_dev->mlock); 658 return; 659 } 660 661 ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status); 662 663 if (status & AD5933_STAT_DATA_VALID) { 664 int scan_count = bitmap_weight(indio_dev->active_scan_mask, 665 indio_dev->masklength); 666 ad5933_i2c_read(st->client, 667 test_bit(1, indio_dev->active_scan_mask) ? 668 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA, 669 scan_count * 2, (u8 *)buf); 670 671 if (scan_count == 2) { 672 buf[0] = be16_to_cpu(buf[0]); 673 buf[1] = be16_to_cpu(buf[1]); 674 } else { 675 buf[0] = be16_to_cpu(buf[0]); 676 } 677 iio_push_to_buffers(indio_dev, buf); 678 } else { 679 /* no data available - try again later */ 680 schedule_delayed_work(&st->work, st->poll_time_jiffies); 681 mutex_unlock(&indio_dev->mlock); 682 return; 683 } 684 685 if (status & AD5933_STAT_SWEEP_DONE) { 686 /* last sample received - power down do nothing until 687 * the ring enable is toggled */ 688 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN); 689 } else { 690 /* we just received a valid datum, move on to the next */ 691 ad5933_cmd(st, AD5933_CTRL_INC_FREQ); 692 schedule_delayed_work(&st->work, st->poll_time_jiffies); 693 } 694 695 mutex_unlock(&indio_dev->mlock); 696} 697 698static int ad5933_probe(struct i2c_client *client, 699 const struct i2c_device_id *id) 700{ 701 int ret, voltage_uv = 0; 702 struct ad5933_platform_data *pdata = client->dev.platform_data; 703 struct ad5933_state *st; 704 struct iio_dev *indio_dev; 705 706 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st)); 707 if (indio_dev == NULL) 708 return -ENOMEM; 709 710 st = iio_priv(indio_dev); 711 i2c_set_clientdata(client, indio_dev); 712 st->client = client; 713 714 if (!pdata) 715 st->pdata = &ad5933_default_pdata; 716 else 717 st->pdata = pdata; 718 719 st->reg = devm_regulator_get(&client->dev, "vcc"); 720 if (!IS_ERR(st->reg)) { 721 ret = regulator_enable(st->reg); 722 if (ret) 723 return ret; 724 voltage_uv = regulator_get_voltage(st->reg); 725 } 726 727 if (voltage_uv) 728 st->vref_mv = voltage_uv / 1000; 729 else 730 st->vref_mv = st->pdata->vref_mv; 731 732 if (st->pdata->ext_clk_Hz) { 733 st->mclk_hz = st->pdata->ext_clk_Hz; 734 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK; 735 } else { 736 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz; 737 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK; 738 } 739 740 ad5933_calc_out_ranges(st); 741 INIT_DELAYED_WORK(&st->work, ad5933_work); 742 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms); 743 744 indio_dev->dev.parent = &client->dev; 745 indio_dev->info = &ad5933_info; 746 indio_dev->name = id->name; 747 indio_dev->modes = INDIO_DIRECT_MODE; 748 indio_dev->channels = ad5933_channels; 749 indio_dev->num_channels = ARRAY_SIZE(ad5933_channels); 750 751 ret = ad5933_register_ring_funcs_and_init(indio_dev); 752 if (ret) 753 goto error_disable_reg; 754 755 ret = iio_buffer_register(indio_dev, ad5933_channels, 756 ARRAY_SIZE(ad5933_channels)); 757 if (ret) 758 goto error_unreg_ring; 759 760 /* enable both REAL and IMAG channels by default */ 761 iio_scan_mask_set(indio_dev, indio_dev->buffer, 0); 762 iio_scan_mask_set(indio_dev, indio_dev->buffer, 1); 763 764 ret = ad5933_setup(st); 765 if (ret) 766 goto error_uninitialize_ring; 767 768 ret = iio_device_register(indio_dev); 769 if (ret) 770 goto error_uninitialize_ring; 771 772 return 0; 773 774error_uninitialize_ring: 775 iio_buffer_unregister(indio_dev); 776error_unreg_ring: 777 iio_kfifo_free(indio_dev->buffer); 778error_disable_reg: 779 if (!IS_ERR(st->reg)) 780 regulator_disable(st->reg); 781 782 return ret; 783} 784 785static int ad5933_remove(struct i2c_client *client) 786{ 787 struct iio_dev *indio_dev = i2c_get_clientdata(client); 788 struct ad5933_state *st = iio_priv(indio_dev); 789 790 iio_device_unregister(indio_dev); 791 iio_buffer_unregister(indio_dev); 792 iio_kfifo_free(indio_dev->buffer); 793 if (!IS_ERR(st->reg)) 794 regulator_disable(st->reg); 795 796 return 0; 797} 798 799static const struct i2c_device_id ad5933_id[] = { 800 { "ad5933", 0 }, 801 { "ad5934", 0 }, 802 {} 803}; 804 805MODULE_DEVICE_TABLE(i2c, ad5933_id); 806 807static struct i2c_driver ad5933_driver = { 808 .driver = { 809 .name = "ad5933", 810 }, 811 .probe = ad5933_probe, 812 .remove = ad5933_remove, 813 .id_table = ad5933_id, 814}; 815module_i2c_driver(ad5933_driver); 816 817MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); 818MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer"); 819MODULE_LICENSE("GPL v2"); 820