odm.c revision 18b0950e02649674d2cf690465c89ee0becff41f
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21/* include files */ 22 23#include "odm_precomp.h" 24 25static const u16 dB_Invert_Table[8][12] = { 26 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, 27 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, 28 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63}, 29 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251}, 30 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000}, 31 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, 32 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849}, 33 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} 34}; 35 36/* avoid to warn in FreeBSD ==> To DO modify */ 37static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { 38 /* UL DL */ 39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ 40 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ 41 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ 42 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ 43 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ 44 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ 45 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ 46 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ 47 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ 48 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ 49}; 50 51/* Global var */ 52u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { 53 0x7f8001fe, /* 0, +6.0dB */ 54 0x788001e2, /* 1, +5.5dB */ 55 0x71c001c7, /* 2, +5.0dB */ 56 0x6b8001ae, /* 3, +4.5dB */ 57 0x65400195, /* 4, +4.0dB */ 58 0x5fc0017f, /* 5, +3.5dB */ 59 0x5a400169, /* 6, +3.0dB */ 60 0x55400155, /* 7, +2.5dB */ 61 0x50800142, /* 8, +2.0dB */ 62 0x4c000130, /* 9, +1.5dB */ 63 0x47c0011f, /* 10, +1.0dB */ 64 0x43c0010f, /* 11, +0.5dB */ 65 0x40000100, /* 12, +0dB */ 66 0x3c8000f2, /* 13, -0.5dB */ 67 0x390000e4, /* 14, -1.0dB */ 68 0x35c000d7, /* 15, -1.5dB */ 69 0x32c000cb, /* 16, -2.0dB */ 70 0x300000c0, /* 17, -2.5dB */ 71 0x2d4000b5, /* 18, -3.0dB */ 72 0x2ac000ab, /* 19, -3.5dB */ 73 0x288000a2, /* 20, -4.0dB */ 74 0x26000098, /* 21, -4.5dB */ 75 0x24000090, /* 22, -5.0dB */ 76 0x22000088, /* 23, -5.5dB */ 77 0x20000080, /* 24, -6.0dB */ 78 0x1e400079, /* 25, -6.5dB */ 79 0x1c800072, /* 26, -7.0dB */ 80 0x1b00006c, /* 27. -7.5dB */ 81 0x19800066, /* 28, -8.0dB */ 82 0x18000060, /* 29, -8.5dB */ 83 0x16c0005b, /* 30, -9.0dB */ 84 0x15800056, /* 31, -9.5dB */ 85 0x14400051, /* 32, -10.0dB */ 86 0x1300004c, /* 33, -10.5dB */ 87 0x12000048, /* 34, -11.0dB */ 88 0x11000044, /* 35, -11.5dB */ 89 0x10000040, /* 36, -12.0dB */ 90 0x0f00003c,/* 37, -12.5dB */ 91 0x0e400039,/* 38, -13.0dB */ 92 0x0d800036,/* 39, -13.5dB */ 93 0x0cc00033,/* 40, -14.0dB */ 94 0x0c000030,/* 41, -14.5dB */ 95 0x0b40002d,/* 42, -15.0dB */ 96}; 97 98u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { 99 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 100 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 101 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 102 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 103 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 104 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 105 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 106 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 107 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 108 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 109 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 110 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 111 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 112 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 113 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 114 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 115 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 116 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 117 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 118 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 119 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ 120 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ 121 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ 122 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ 123 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ 124 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ 125 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ 126 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ 127 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ 128 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ 129 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ 130 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ 131 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ 132}; 133 134u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { 135 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 136 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 137 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 138 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 139 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 140 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 141 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 142 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 143 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 144 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 145 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 146 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 147 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 148 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 149 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 150 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 151 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 152 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 153 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 154 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 155 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ 156 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ 157 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ 158 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ 159 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ 160 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ 161 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ 162 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ 163 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ 164 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ 165 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ 166 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ 167 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ 168}; 169 170 171#define RxDefaultAnt1 0x65a9 172#define RxDefaultAnt2 0x569a 173 174/* 3 Export Interface */ 175 176/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ 177void ODM_DMInit(struct odm_dm_struct *pDM_Odm) 178{ 179 /* 2012.05.03 Luke: For all IC series */ 180 odm_CommonInfoSelfInit(pDM_Odm); 181 odm_CmnInfoInit_Debug(pDM_Odm); 182 odm_DIGInit(pDM_Odm); 183 odm_RateAdaptiveMaskInit(pDM_Odm); 184 185 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { 186 ; 187 } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { 188 odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ 189 odm_DynamicBBPowerSavingInit(pDM_Odm); 190 odm_DynamicTxPowerInit(pDM_Odm); 191 odm_TXPowerTrackingInit(pDM_Odm); 192 ODM_EdcaTurboInit(pDM_Odm); 193 ODM_RAInfo_Init_all(pDM_Odm); 194 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 195 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 196 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 197 odm_InitHybridAntDiv(pDM_Odm); 198 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV) 199 odm_SwAntDivInit(pDM_Odm); 200 } 201} 202 203/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ 204/* You can not add any dummy function here, be care, you can only use DM structure */ 205/* to perform any new ODM_DM. */ 206void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) 207{ 208 /* 2012.05.03 Luke: For all IC series */ 209 odm_GlobalAdapterCheck(); 210 odm_CmnInfoHook_Debug(pDM_Odm); 211 odm_CmnInfoUpdate_Debug(pDM_Odm); 212 odm_CommonInfoSelfUpdate(pDM_Odm); 213 odm_FalseAlarmCounterStatistics(pDM_Odm); 214 odm_RSSIMonitorCheck(pDM_Odm); 215 216 /* For CE Platform(SPRD or Tablet) */ 217 /* 8723A or 8189ES platform */ 218 /* NeilChen--2012--08--24-- */ 219 /* Fix Leave LPS issue */ 220 if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */ 221 ((pDM_Odm->SupportICType & (ODM_RTL8723A)) || 222 (pDM_Odm->SupportICType & (ODM_RTL8188E) && 223 ((pDM_Odm->SupportInterface == ODM_ITRF_SDIO))))) { 224 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n")); 225 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n")); 226 odm_DIGbyRSSI_LPS(pDM_Odm); 227 } else { 228 odm_DIG(pDM_Odm); 229 } 230 odm_CCKPacketDetectionThresh(pDM_Odm); 231 232 if (*(pDM_Odm->pbPowerSaving)) 233 return; 234 235 odm_RefreshRateAdaptiveMask(pDM_Odm); 236 237 odm_DynamicBBPowerSaving(pDM_Odm); 238 odm_DynamicPrimaryCCA(pDM_Odm); 239 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 240 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 241 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 242 odm_HwAntDiv(pDM_Odm); 243 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV) 244 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK); 245 246 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { 247 ; 248 } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { 249 ODM_TXPowerTrackingCheck(pDM_Odm); 250 odm_EdcaTurboCheck(pDM_Odm); 251 odm_DynamicTxPower(pDM_Odm); 252 } 253 odm_dtc(pDM_Odm); 254} 255 256/* Init /.. Fixed HW value. Only init time. */ 257void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value) 258{ 259 /* This section is used for init value */ 260 switch (CmnInfo) { 261 /* Fixed ODM value. */ 262 case ODM_CMNINFO_ABILITY: 263 pDM_Odm->SupportAbility = (u32)Value; 264 break; 265 case ODM_CMNINFO_PLATFORM: 266 pDM_Odm->SupportPlatform = (u8)Value; 267 break; 268 case ODM_CMNINFO_INTERFACE: 269 pDM_Odm->SupportInterface = (u8)Value; 270 break; 271 case ODM_CMNINFO_MP_TEST_CHIP: 272 pDM_Odm->bIsMPChip = (u8)Value; 273 break; 274 case ODM_CMNINFO_IC_TYPE: 275 pDM_Odm->SupportICType = Value; 276 break; 277 case ODM_CMNINFO_CUT_VER: 278 pDM_Odm->CutVersion = (u8)Value; 279 break; 280 case ODM_CMNINFO_FAB_VER: 281 pDM_Odm->FabVersion = (u8)Value; 282 break; 283 case ODM_CMNINFO_RF_TYPE: 284 pDM_Odm->RFType = (u8)Value; 285 break; 286 case ODM_CMNINFO_RF_ANTENNA_TYPE: 287 pDM_Odm->AntDivType = (u8)Value; 288 break; 289 case ODM_CMNINFO_BOARD_TYPE: 290 pDM_Odm->BoardType = (u8)Value; 291 break; 292 case ODM_CMNINFO_EXT_LNA: 293 pDM_Odm->ExtLNA = (u8)Value; 294 break; 295 case ODM_CMNINFO_EXT_PA: 296 pDM_Odm->ExtPA = (u8)Value; 297 break; 298 case ODM_CMNINFO_EXT_TRSW: 299 pDM_Odm->ExtTRSW = (u8)Value; 300 break; 301 case ODM_CMNINFO_PATCH_ID: 302 pDM_Odm->PatchID = (u8)Value; 303 break; 304 case ODM_CMNINFO_BINHCT_TEST: 305 pDM_Odm->bInHctTest = (bool)Value; 306 break; 307 case ODM_CMNINFO_BWIFI_TEST: 308 pDM_Odm->bWIFITest = (bool)Value; 309 break; 310 case ODM_CMNINFO_SMART_CONCURRENT: 311 pDM_Odm->bDualMacSmartConcurrent = (bool)Value; 312 break; 313 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 314 default: 315 /* do nothing */ 316 break; 317 } 318 319 /* Tx power tracking BB swing table. */ 320 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ 321 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */ 322 pDM_Odm->BbSwingIdxOfdmCurrent = 12; 323 pDM_Odm->BbSwingFlagOfdm = false; 324} 325 326void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue) 327{ 328 /* */ 329 /* Hook call by reference pointer. */ 330 /* */ 331 switch (CmnInfo) { 332 /* Dynamic call by reference pointer. */ 333 case ODM_CMNINFO_MAC_PHY_MODE: 334 pDM_Odm->pMacPhyMode = (u8 *)pValue; 335 break; 336 case ODM_CMNINFO_TX_UNI: 337 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue; 338 break; 339 case ODM_CMNINFO_RX_UNI: 340 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue; 341 break; 342 case ODM_CMNINFO_WM_MODE: 343 pDM_Odm->pWirelessMode = (u8 *)pValue; 344 break; 345 case ODM_CMNINFO_BAND: 346 pDM_Odm->pBandType = (u8 *)pValue; 347 break; 348 case ODM_CMNINFO_SEC_CHNL_OFFSET: 349 pDM_Odm->pSecChOffset = (u8 *)pValue; 350 break; 351 case ODM_CMNINFO_SEC_MODE: 352 pDM_Odm->pSecurity = (u8 *)pValue; 353 break; 354 case ODM_CMNINFO_BW: 355 pDM_Odm->pBandWidth = (u8 *)pValue; 356 break; 357 case ODM_CMNINFO_CHNL: 358 pDM_Odm->pChannel = (u8 *)pValue; 359 break; 360 case ODM_CMNINFO_DMSP_GET_VALUE: 361 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue; 362 break; 363 case ODM_CMNINFO_BUDDY_ADAPTOR: 364 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue; 365 break; 366 case ODM_CMNINFO_DMSP_IS_MASTER: 367 pDM_Odm->pbMasterOfDMSP = (bool *)pValue; 368 break; 369 case ODM_CMNINFO_SCAN: 370 pDM_Odm->pbScanInProcess = (bool *)pValue; 371 break; 372 case ODM_CMNINFO_POWER_SAVING: 373 pDM_Odm->pbPowerSaving = (bool *)pValue; 374 break; 375 case ODM_CMNINFO_ONE_PATH_CCA: 376 pDM_Odm->pOnePathCCA = (u8 *)pValue; 377 break; 378 case ODM_CMNINFO_DRV_STOP: 379 pDM_Odm->pbDriverStopped = (bool *)pValue; 380 break; 381 case ODM_CMNINFO_PNP_IN: 382 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue; 383 break; 384 case ODM_CMNINFO_INIT_ON: 385 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue; 386 break; 387 case ODM_CMNINFO_ANT_TEST: 388 pDM_Odm->pAntennaTest = (u8 *)pValue; 389 break; 390 case ODM_CMNINFO_NET_CLOSED: 391 pDM_Odm->pbNet_closed = (bool *)pValue; 392 break; 393 case ODM_CMNINFO_MP_MODE: 394 pDM_Odm->mp_mode = (u8 *)pValue; 395 break; 396 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 397 default: 398 /* do nothing */ 399 break; 400 } 401} 402 403void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue) 404{ 405 /* Hook call by reference pointer. */ 406 switch (CmnInfo) { 407 /* Dynamic call by reference pointer. */ 408 case ODM_CMNINFO_STA_STATUS: 409 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue; 410 break; 411 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 412 default: 413 /* do nothing */ 414 break; 415 } 416} 417 418/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ 419void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value) 420{ 421 /* */ 422 /* This init variable may be changed in run time. */ 423 /* */ 424 switch (CmnInfo) { 425 case ODM_CMNINFO_ABILITY: 426 pDM_Odm->SupportAbility = (u32)Value; 427 break; 428 case ODM_CMNINFO_RF_TYPE: 429 pDM_Odm->RFType = (u8)Value; 430 break; 431 case ODM_CMNINFO_WIFI_DIRECT: 432 pDM_Odm->bWIFI_Direct = (bool)Value; 433 break; 434 case ODM_CMNINFO_WIFI_DISPLAY: 435 pDM_Odm->bWIFI_Display = (bool)Value; 436 break; 437 case ODM_CMNINFO_LINK: 438 pDM_Odm->bLinked = (bool)Value; 439 break; 440 case ODM_CMNINFO_RSSI_MIN: 441 pDM_Odm->RSSI_Min = (u8)Value; 442 break; 443 case ODM_CMNINFO_DBG_COMP: 444 pDM_Odm->DebugComponents = Value; 445 break; 446 case ODM_CMNINFO_DBG_LEVEL: 447 pDM_Odm->DebugLevel = (u32)Value; 448 break; 449 case ODM_CMNINFO_RA_THRESHOLD_HIGH: 450 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value; 451 break; 452 case ODM_CMNINFO_RA_THRESHOLD_LOW: 453 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value; 454 break; 455 } 456} 457 458void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) 459{ 460 pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT9); 461 pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F); 462 if (pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D)) 463 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; 464 if (pDM_Odm->SupportICType & (ODM_RTL8723A)) 465 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; 466 467 ODM_InitDebugSetting(pDM_Odm); 468} 469 470void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) 471{ 472 u8 EntryCnt = 0; 473 u8 i; 474 struct sta_info *pEntry; 475 476 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { 477 if (*(pDM_Odm->pSecChOffset) == 1) 478 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; 479 else if (*(pDM_Odm->pSecChOffset) == 2) 480 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; 481 } else { 482 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); 483 } 484 485 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 486 pEntry = pDM_Odm->pODM_StaInfo[i]; 487 if (IS_STA_VALID(pEntry)) 488 EntryCnt++; 489 } 490 if (EntryCnt == 1) 491 pDM_Odm->bOneEntryOnly = true; 492 else 493 pDM_Odm->bOneEntryOnly = false; 494} 495 496void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm) 497{ 498 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); 499 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform)); 500 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility)); 501 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface)); 502 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType)); 503 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion)); 504 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n", pDM_Odm->FabVersion)); 505 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n", pDM_Odm->RFType)); 506 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType)); 507 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA)); 508 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA)); 509 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW)); 510 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID)); 511 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest)); 512 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest)); 513 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent)); 514} 515 516void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm) 517{ 518 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); 519 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast))); 520 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast))); 521 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode))); 522 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset))); 523 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity))); 524 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth))); 525 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel))); 526 527 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess))); 528 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving))); 529 530 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) 531 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pOnePathCCA=%d\n", *(pDM_Odm->pOnePathCCA))); 532} 533 534void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm) 535{ 536 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); 537 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct)); 538 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display)); 539 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked)); 540 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min)); 541} 542 543static int getIGIForDiff(int value_IGI) 544{ 545 #define ONERCCA_LOW_TH 0x30 546 #define ONERCCA_LOW_DIFF 8 547 548 if (value_IGI < ONERCCA_LOW_TH) { 549 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) 550 return ONERCCA_LOW_TH; 551 else 552 return value_IGI + ONERCCA_LOW_DIFF; 553 } else { 554 return value_IGI; 555 } 556} 557 558void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) 559{ 560 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 561 562 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 563 ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", 564 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm))); 565 566 if (pDM_DigTable->CurIGValue != CurrentIGI) { 567 if (pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP)) { 568 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 569 if (pDM_Odm->SupportICType != ODM_RTL8188E) 570 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 571 } else if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) { 572 switch (*(pDM_Odm->pOnePathCCA)) { 573 case ODM_CCA_2R: 574 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 575 if (pDM_Odm->SupportICType != ODM_RTL8188E) 576 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 577 break; 578 case ODM_CCA_1R_A: 579 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 580 if (pDM_Odm->SupportICType != ODM_RTL8188E) 581 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI)); 582 break; 583 case ODM_CCA_1R_B: 584 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI)); 585 if (pDM_Odm->SupportICType != ODM_RTL8188E) 586 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 587 break; 588 } 589 } 590 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n", CurrentIGI)); 591 /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */ 592 pDM_DigTable->CurIGValue = CurrentIGI; 593 } 594 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x\n", CurrentIGI)); 595 596/* Add by Neil Chen to enable edcca to MP Platform */ 597} 598 599/* Need LPS mode for CE platform --2012--08--24--- */ 600/* 8723AS/8189ES */ 601void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm) 602{ 603 struct adapter *pAdapter = pDM_Odm->Adapter; 604 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 605 606 u8 RSSI_Lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */ 607 u8 bFwCurrentInPSMode = false; 608 u8 CurrentIGI = pDM_Odm->RSSI_Min; 609 610 if (!(pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8188E))) 611 return; 612 613 CurrentIGI = CurrentIGI + RSSI_OFFSET_DIG; 614 bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode; 615 616 /* Using FW PS mode to make IGI */ 617 if (bFwCurrentInPSMode) { 618 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n")); 619 /* Adjust by FA in LPS MODE */ 620 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS) 621 CurrentIGI = CurrentIGI+2; 622 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) 623 CurrentIGI = CurrentIGI+1; 624 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) 625 CurrentIGI = CurrentIGI-1; 626 } else { 627 CurrentIGI = RSSI_Lower; 628 } 629 630 /* Lower bound checking */ 631 632 /* RSSI Lower bound check */ 633 if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) 634 RSSI_Lower = (pDM_Odm->RSSI_Min-10); 635 else 636 RSSI_Lower = DM_DIG_MIN_NIC; 637 638 /* Upper and Lower Bound checking */ 639 if (CurrentIGI > DM_DIG_MAX_NIC) 640 CurrentIGI = DM_DIG_MAX_NIC; 641 else if (CurrentIGI < RSSI_Lower) 642 CurrentIGI = RSSI_Lower; 643 644 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 645} 646 647void odm_DIGInit(struct odm_dm_struct *pDM_Odm) 648{ 649 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 650 651 pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); 652 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; 653 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; 654 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW; 655 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH; 656 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) { 657 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 658 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 659 } else { 660 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 661 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 662 } 663 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; 664 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; 665 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; 666 pDM_DigTable->PreCCK_CCAThres = 0xFF; 667 pDM_DigTable->CurCCK_CCAThres = 0x83; 668 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; 669 pDM_DigTable->LargeFAHit = 0; 670 pDM_DigTable->Recover_cnt = 0; 671 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; 672 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; 673 pDM_DigTable->bMediaConnect_0 = false; 674 pDM_DigTable->bMediaConnect_1 = false; 675 676 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */ 677 pDM_Odm->bDMInitialGainEnable = true; 678} 679 680void odm_DIG(struct odm_dm_struct *pDM_Odm) 681{ 682 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 683 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 684 u8 DIG_Dynamic_MIN; 685 u8 DIG_MaxOfMin; 686 bool FirstConnect, FirstDisConnect; 687 u8 dm_dig_max, dm_dig_min; 688 u8 CurrentIGI = pDM_DigTable->CurIGValue; 689 690 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); 691 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) { 692 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 693 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); 694 return; 695 } 696 697 if (*(pDM_Odm->pbScanInProcess)) { 698 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n")); 699 return; 700 } 701 702 /* add by Neil Chen to avoid PSD is processing */ 703 if (pDM_Odm->bDMInitialGainEnable == false) { 704 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n")); 705 return; 706 } 707 708 if (pDM_Odm->SupportICType == ODM_RTL8192D) { 709 if (*(pDM_Odm->pMacPhyMode) == ODM_DMSP) { 710 if (*(pDM_Odm->pbMasterOfDMSP)) { 711 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 712 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 713 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 714 } else { 715 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; 716 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1); 717 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1); 718 } 719 } else { 720 if (*(pDM_Odm->pBandType) == ODM_BAND_5G) { 721 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 722 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 723 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 724 } else { 725 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; 726 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1); 727 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1); 728 } 729 } 730 } else { 731 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 732 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 733 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 734 } 735 736 /* 1 Boundary Decision */ 737 if ((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) && 738 ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) { 739 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) { 740 dm_dig_max = DM_DIG_MAX_AP_HP; 741 dm_dig_min = DM_DIG_MIN_AP_HP; 742 } else { 743 dm_dig_max = DM_DIG_MAX_NIC_HP; 744 dm_dig_min = DM_DIG_MIN_NIC_HP; 745 } 746 DIG_MaxOfMin = DM_DIG_MAX_AP_HP; 747 } else { 748 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) { 749 dm_dig_max = DM_DIG_MAX_AP; 750 dm_dig_min = DM_DIG_MIN_AP; 751 DIG_MaxOfMin = dm_dig_max; 752 } else { 753 dm_dig_max = DM_DIG_MAX_NIC; 754 dm_dig_min = DM_DIG_MIN_NIC; 755 DIG_MaxOfMin = DM_DIG_MAX_AP; 756 } 757 } 758 if (pDM_Odm->bLinked) { 759 /* 2 8723A Series, offset need to be 10 */ 760 if (pDM_Odm->SupportICType == (ODM_RTL8723A)) { 761 /* 2 Upper Bound */ 762 if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC) 763 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 764 else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC) 765 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC; 766 else 767 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10; 768 /* 2 If BT is Concurrent, need to set Lower Bound */ 769 DIG_Dynamic_MIN = DM_DIG_MIN_NIC; 770 } else { 771 /* 2 Modify DIG upper bound */ 772 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) 773 pDM_DigTable->rx_gain_range_max = dm_dig_max; 774 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min) 775 pDM_DigTable->rx_gain_range_max = dm_dig_min; 776 else 777 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; 778 /* 2 Modify DIG lower bound */ 779 if (pDM_Odm->bOneEntryOnly) { 780 if (pDM_Odm->RSSI_Min < dm_dig_min) 781 DIG_Dynamic_MIN = dm_dig_min; 782 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) 783 DIG_Dynamic_MIN = DIG_MaxOfMin; 784 else 785 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; 786 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 787 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n", 788 DIG_Dynamic_MIN)); 789 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 790 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n", 791 pDM_Odm->RSSI_Min)); 792 } else if ((pDM_Odm->SupportICType == ODM_RTL8188E) && 793 (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 794 /* 1 Lower Bound for 88E AntDiv */ 795 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { 796 DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max; 797 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 798 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n", 799 pDM_DigTable->AntDiv_RSSI_max)); 800 } 801 } else { 802 DIG_Dynamic_MIN = dm_dig_min; 803 } 804 } 805 } else { 806 pDM_DigTable->rx_gain_range_max = dm_dig_max; 807 DIG_Dynamic_MIN = dm_dig_min; 808 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); 809 } 810 811 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ 812 if (pFalseAlmCnt->Cnt_all > 10000) { 813 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n")); 814 815 if (pDM_DigTable->LargeFAHit != 3) 816 pDM_DigTable->LargeFAHit++; 817 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { 818 pDM_DigTable->ForbiddenIGI = CurrentIGI; 819 pDM_DigTable->LargeFAHit = 1; 820 } 821 822 if (pDM_DigTable->LargeFAHit >= 3) { 823 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max) 824 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; 825 else 826 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 827 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ 828 } 829 830 } else { 831 /* Recovery mechanism for IGI lower bound */ 832 if (pDM_DigTable->Recover_cnt != 0) { 833 pDM_DigTable->Recover_cnt--; 834 } else { 835 if (pDM_DigTable->LargeFAHit < 3) { 836 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */ 837 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 838 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 839 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); 840 } else { 841 pDM_DigTable->ForbiddenIGI--; 842 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 843 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); 844 } 845 } else { 846 pDM_DigTable->LargeFAHit = 0; 847 } 848 } 849 } 850 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 851 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n", 852 pDM_DigTable->LargeFAHit)); 853 854 /* 1 Adjust initial gain by false alarm */ 855 if (pDM_Odm->bLinked) { 856 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); 857 if (FirstConnect) { 858 CurrentIGI = pDM_Odm->RSSI_Min; 859 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); 860 } else { 861 if (pDM_Odm->SupportICType == ODM_RTL8192D) { 862 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D) 863 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 864 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D) 865 CurrentIGI = CurrentIGI + 1; /* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 866 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D) 867 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 868 } else { 869 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) 870 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 871 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) 872 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 873 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) 874 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 875 } 876 } 877 } else { 878 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); 879 if (FirstDisConnect) { 880 CurrentIGI = pDM_DigTable->rx_gain_range_min; 881 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n")); 882 } else { 883 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ 884 if (pFalseAlmCnt->Cnt_all > 10000) 885 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 886 else if (pFalseAlmCnt->Cnt_all > 8000) 887 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 888 else if (pFalseAlmCnt->Cnt_all < 500) 889 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 890 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n")); 891 } 892 } 893 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); 894 /* 1 Check initial gain by upper/lower bound */ 895 if (CurrentIGI > pDM_DigTable->rx_gain_range_max) 896 CurrentIGI = pDM_DigTable->rx_gain_range_max; 897 if (CurrentIGI < pDM_DigTable->rx_gain_range_min) 898 CurrentIGI = pDM_DigTable->rx_gain_range_min; 899 900 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 901 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", 902 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); 903 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); 904 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); 905 906 /* 2 High power RSSI threshold */ 907 908 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 909 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; 910 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; 911} 912 913/* 3============================================================ */ 914/* 3 FASLE ALARM CHECK */ 915/* 3============================================================ */ 916 917void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 918{ 919 u32 ret_value; 920 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 921 922 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) 923 return; 924 925 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { 926 /* hold ofdm counter */ 927 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ 928 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ 929 930 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); 931 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); 932 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); 933 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); 934 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); 935 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); 936 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); 937 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); 938 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); 939 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); 940 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); 941 942 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + 943 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + 944 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; 945 946 if (pDM_Odm->SupportICType == ODM_RTL8188E) { 947 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord); 948 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); 949 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); 950 } 951 952 /* hold cck counter */ 953 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1); 954 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1); 955 956 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); 957 FalseAlmCnt->Cnt_Cck_fail = ret_value; 958 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); 959 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8; 960 961 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); 962 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8); 963 964 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + 965 FalseAlmCnt->Cnt_SB_Search_fail + 966 FalseAlmCnt->Cnt_Parity_Fail + 967 FalseAlmCnt->Cnt_Rate_Illegal + 968 FalseAlmCnt->Cnt_Crc8_fail + 969 FalseAlmCnt->Cnt_Mcs_fail + 970 FalseAlmCnt->Cnt_Cck_fail); 971 972 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; 973 974 if (pDM_Odm->SupportICType >= ODM_RTL8723A) { 975 /* reset false alarm counter registers */ 976 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1); 977 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0); 978 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1); 979 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0); 980 /* update ofdm counter */ 981 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /* update page C counter */ 982 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /* update page D counter */ 983 984 /* reset CCK CCA counter */ 985 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0); 986 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2); 987 /* reset CCK FA counter */ 988 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0); 989 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2); 990 } 991 992 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); 993 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 994 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", 995 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); 996 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 997 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", 998 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); 999 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 1000 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", 1001 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); 1002 } else { /* FOR ODM_IC_11AC_SERIES */ 1003 /* read OFDM FA counter */ 1004 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord); 1005 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord); 1006 FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail; 1007 1008 /* reset OFDM FA coutner */ 1009 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1); 1010 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0); 1011 /* reset CCK FA counter */ 1012 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0); 1013 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1); 1014 } 1015 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); 1016 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); 1017 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); 1018} 1019 1020/* 3============================================================ */ 1021/* 3 CCK Packet Detect Threshold */ 1022/* 3============================================================ */ 1023 1024void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) 1025{ 1026 u8 CurCCK_CCAThres; 1027 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 1028 1029 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) 1030 return; 1031 if (pDM_Odm->ExtLNA) 1032 return; 1033 if (pDM_Odm->bLinked) { 1034 if (pDM_Odm->RSSI_Min > 25) { 1035 CurCCK_CCAThres = 0xcd; 1036 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) { 1037 CurCCK_CCAThres = 0x83; 1038 } else { 1039 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 1040 CurCCK_CCAThres = 0x83; 1041 else 1042 CurCCK_CCAThres = 0x40; 1043 } 1044 } else { 1045 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 1046 CurCCK_CCAThres = 0x83; 1047 else 1048 CurCCK_CCAThres = 0x40; 1049 } 1050 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); 1051} 1052 1053void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres) 1054{ 1055 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 1056 1057 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ 1058 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres); 1059 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; 1060 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; 1061} 1062 1063/* 3============================================================ */ 1064/* 3 BB Power Save */ 1065/* 3============================================================ */ 1066void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm) 1067{ 1068 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 1069 1070 pDM_PSTable->PreCCAState = CCA_MAX; 1071 pDM_PSTable->CurCCAState = CCA_MAX; 1072 pDM_PSTable->PreRFState = RF_MAX; 1073 pDM_PSTable->CurRFState = RF_MAX; 1074 pDM_PSTable->Rssi_val_min = 0; 1075 pDM_PSTable->initialize = 0; 1076} 1077 1078void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm) 1079{ 1080 if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A)) 1081 return; 1082 if (!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE)) 1083 return; 1084 if (!(pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE))) 1085 return; 1086 1087 /* 1 2.Power Saving for 92C */ 1088 if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->RFType == ODM_2T2R)) { 1089 odm_1R_CCA(pDM_Odm); 1090 } else { 1091 /* 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. */ 1092 /* 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. */ 1093 /* 1 3.Power Saving for 88C */ 1094 ODM_RF_Saving(pDM_Odm, false); 1095 } 1096} 1097 1098void odm_1R_CCA(struct odm_dm_struct *pDM_Odm) 1099{ 1100 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 1101 1102 if (pDM_Odm->RSSI_Min != 0xFF) { 1103 if (pDM_PSTable->PreCCAState == CCA_2R) { 1104 if (pDM_Odm->RSSI_Min >= 35) 1105 pDM_PSTable->CurCCAState = CCA_1R; 1106 else 1107 pDM_PSTable->CurCCAState = CCA_2R; 1108 } else { 1109 if (pDM_Odm->RSSI_Min <= 30) 1110 pDM_PSTable->CurCCAState = CCA_2R; 1111 else 1112 pDM_PSTable->CurCCAState = CCA_1R; 1113 } 1114 } else { 1115 pDM_PSTable->CurCCAState = CCA_MAX; 1116 } 1117 1118 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) { 1119 if (pDM_PSTable->CurCCAState == CCA_1R) { 1120 if (pDM_Odm->RFType == ODM_2T2R) 1121 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x13); 1122 else 1123 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x23); 1124 } else { 1125 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x33); 1126 } 1127 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; 1128 } 1129} 1130 1131void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 1132{ 1133 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 1134 u8 Rssi_Up_bound = 30; 1135 u8 Rssi_Low_bound = 25; 1136 1137 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */ 1138 Rssi_Up_bound = 50; 1139 Rssi_Low_bound = 45; 1140 } 1141 if (pDM_PSTable->initialize == 0) { 1142 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14; 1143 pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3; 1144 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24; 1145 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12; 1146 pDM_PSTable->initialize = 1; 1147 } 1148 1149 if (!bForceInNormal) { 1150 if (pDM_Odm->RSSI_Min != 0xFF) { 1151 if (pDM_PSTable->PreRFState == RF_Normal) { 1152 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound) 1153 pDM_PSTable->CurRFState = RF_Save; 1154 else 1155 pDM_PSTable->CurRFState = RF_Normal; 1156 } else { 1157 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound) 1158 pDM_PSTable->CurRFState = RF_Normal; 1159 else 1160 pDM_PSTable->CurRFState = RF_Save; 1161 } 1162 } else { 1163 pDM_PSTable->CurRFState = RF_MAX; 1164 } 1165 } else { 1166 pDM_PSTable->CurRFState = RF_Normal; 1167 } 1168 1169 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { 1170 if (pDM_PSTable->CurRFState == RF_Save) { 1171 /* <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. */ 1172 /* Suggested by SD3 Yu-Nan. 2011.01.20. */ 1173 if (pDM_Odm->SupportICType == ODM_RTL8723A) 1174 ODM_SetBBReg(pDM_Odm, 0x874 , BIT5, 0x1); /* Reg874[5]=1b'1 */ 1175 ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ 1176 ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ 1177 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ 1178 ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ 1179 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ 1180 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ 1181 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ 1182 } else { 1183 ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874); 1184 ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70); 1185 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); 1186 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74); 1187 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); 1188 1189 if (pDM_Odm->SupportICType == ODM_RTL8723A) 1190 ODM_SetBBReg(pDM_Odm, 0x874, BIT5, 0x0); /* Reg874[5]=1b'0 */ 1191 } 1192 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; 1193 } 1194} 1195 1196/* 3============================================================ */ 1197/* 3 RATR MASK */ 1198/* 3============================================================ */ 1199/* 3============================================================ */ 1200/* 3 Rate Adaptive */ 1201/* 3============================================================ */ 1202 1203void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm) 1204{ 1205 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive; 1206 1207 pOdmRA->Type = DM_Type_ByDriver; 1208 if (pOdmRA->Type == DM_Type_ByDriver) 1209 pDM_Odm->bUseRAMask = true; 1210 else 1211 pDM_Odm->bUseRAMask = false; 1212 1213 pOdmRA->RATRState = DM_RATR_STA_INIT; 1214 pOdmRA->HighRSSIThresh = 50; 1215 pOdmRA->LowRSSIThresh = 20; 1216} 1217 1218u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level) 1219{ 1220 struct sta_info *pEntry; 1221 u32 rate_bitmap = 0x0fffffff; 1222 u8 WirelessMode; 1223 1224 pEntry = pDM_Odm->pODM_StaInfo[macid]; 1225 if (!IS_STA_VALID(pEntry)) 1226 return ra_mask; 1227 1228 WirelessMode = pEntry->wireless_mode; 1229 1230 switch (WirelessMode) { 1231 case ODM_WM_B: 1232 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ 1233 rate_bitmap = 0x0000000d; 1234 else 1235 rate_bitmap = 0x0000000f; 1236 break; 1237 case (ODM_WM_A|ODM_WM_G): 1238 if (rssi_level == DM_RATR_STA_HIGH) 1239 rate_bitmap = 0x00000f00; 1240 else 1241 rate_bitmap = 0x00000ff0; 1242 break; 1243 case (ODM_WM_B|ODM_WM_G): 1244 if (rssi_level == DM_RATR_STA_HIGH) 1245 rate_bitmap = 0x00000f00; 1246 else if (rssi_level == DM_RATR_STA_MIDDLE) 1247 rate_bitmap = 0x00000ff0; 1248 else 1249 rate_bitmap = 0x00000ff5; 1250 break; 1251 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1252 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1253 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { 1254 if (rssi_level == DM_RATR_STA_HIGH) { 1255 rate_bitmap = 0x000f0000; 1256 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1257 rate_bitmap = 0x000ff000; 1258 } else { 1259 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1260 rate_bitmap = 0x000ff015; 1261 else 1262 rate_bitmap = 0x000ff005; 1263 } 1264 } else { 1265 if (rssi_level == DM_RATR_STA_HIGH) { 1266 rate_bitmap = 0x0f8f0000; 1267 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1268 rate_bitmap = 0x0f8ff000; 1269 } else { 1270 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1271 rate_bitmap = 0x0f8ff015; 1272 else 1273 rate_bitmap = 0x0f8ff005; 1274 } 1275 } 1276 break; 1277 default: 1278 /* case WIRELESS_11_24N: */ 1279 /* case WIRELESS_11_5N: */ 1280 if (pDM_Odm->RFType == RF_1T2R) 1281 rate_bitmap = 0x000fffff; 1282 else 1283 rate_bitmap = 0x0fffffff; 1284 break; 1285 } 1286 1287 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1288 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", 1289 rssi_level, WirelessMode, rate_bitmap)); 1290 1291 return rate_bitmap; 1292} 1293 1294/*----------------------------------------------------------------------------- 1295 * Function: odm_RefreshRateAdaptiveMask() 1296 * 1297 * Overview: Update rate table mask according to rssi 1298 * 1299 * Input: NONE 1300 * 1301 * Output: NONE 1302 * 1303 * Return: NONE 1304 * 1305 * Revised History: 1306 * When Who Remark 1307 * 05/27/2009 hpfan Create Version 0. 1308 * 1309 *---------------------------------------------------------------------------*/ 1310void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm) 1311{ 1312 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) 1313 return; 1314 /* */ 1315 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1316 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1317 /* HW dynamic mechanism. */ 1318 /* */ 1319 switch (pDM_Odm->SupportPlatform) { 1320 case ODM_MP: 1321 odm_RefreshRateAdaptiveMaskMP(pDM_Odm); 1322 break; 1323 case ODM_CE: 1324 odm_RefreshRateAdaptiveMaskCE(pDM_Odm); 1325 break; 1326 case ODM_AP: 1327 case ODM_ADSL: 1328 odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm); 1329 break; 1330 } 1331} 1332 1333void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm) 1334{ 1335} 1336 1337void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm) 1338{ 1339 u8 i; 1340 struct adapter *pAdapter = pDM_Odm->Adapter; 1341 1342 if (pAdapter->bDriverStopped) { 1343 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); 1344 return; 1345 } 1346 1347 if (!pDM_Odm->bUseRAMask) { 1348 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); 1349 return; 1350 } 1351 1352 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1353 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; 1354 if (IS_STA_VALID(pstat)) { 1355 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) { 1356 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1357 ("RSSI:%d, RSSI_LEVEL:%d\n", 1358 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); 1359 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level); 1360 } 1361 } 1362 } 1363} 1364 1365void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm) 1366{ 1367} 1368 1369/* Return Value: bool */ 1370/* - true: RATRState is changed. */ 1371bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState) 1372{ 1373 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive; 1374 const u8 GoUpGap = 5; 1375 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh; 1376 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; 1377 u8 RATRState; 1378 1379 /* Threshold Adjustment: */ 1380 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ 1381 /* Here GoUpGap is added to solve the boundary's level alternation issue. */ 1382 switch (*pRATRState) { 1383 case DM_RATR_STA_INIT: 1384 case DM_RATR_STA_HIGH: 1385 break; 1386 case DM_RATR_STA_MIDDLE: 1387 HighRSSIThreshForRA += GoUpGap; 1388 break; 1389 case DM_RATR_STA_LOW: 1390 HighRSSIThreshForRA += GoUpGap; 1391 LowRSSIThreshForRA += GoUpGap; 1392 break; 1393 default: 1394 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState)); 1395 break; 1396 } 1397 1398 /* Decide RATRState by RSSI. */ 1399 if (RSSI > HighRSSIThreshForRA) 1400 RATRState = DM_RATR_STA_HIGH; 1401 else if (RSSI > LowRSSIThreshForRA) 1402 RATRState = DM_RATR_STA_MIDDLE; 1403 else 1404 RATRState = DM_RATR_STA_LOW; 1405 1406 if (*pRATRState != RATRState || bForceUpdate) { 1407 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState)); 1408 *pRATRState = RATRState; 1409 return true; 1410 } 1411 return false; 1412} 1413 1414/* 3============================================================ */ 1415/* 3 Dynamic Tx Power */ 1416/* 3============================================================ */ 1417 1418void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm) 1419{ 1420 struct adapter *Adapter = pDM_Odm->Adapter; 1421 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1422 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1423 pdmpriv->bDynamicTxPowerEnable = false; 1424 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; 1425 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; 1426} 1427 1428void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm) 1429{ 1430 /* For AP/ADSL use struct rtl8192cd_priv * */ 1431 /* For CE/NIC use struct adapter * */ 1432 1433 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1434 return; 1435 1436 /* 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */ 1437 if (!pDM_Odm->ExtPA) 1438 return; 1439 1440 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1441 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1442 /* HW dynamic mechanism. */ 1443 switch (pDM_Odm->SupportPlatform) { 1444 case ODM_MP: 1445 case ODM_CE: 1446 odm_DynamicTxPowerNIC(pDM_Odm); 1447 break; 1448 case ODM_AP: 1449 odm_DynamicTxPowerAP(pDM_Odm); 1450 break; 1451 case ODM_ADSL: 1452 break; 1453 } 1454} 1455 1456void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm) 1457{ 1458 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1459 return; 1460 1461 if (pDM_Odm->SupportICType == ODM_RTL8188E) { 1462 /* ??? */ 1463 /* This part need to be redefined. */ 1464 } 1465} 1466 1467void odm_DynamicTxPowerAP(struct odm_dm_struct *pDM_Odm) 1468{ 1469} 1470 1471/* 3============================================================ */ 1472/* 3 RSSI Monitor */ 1473/* 3============================================================ */ 1474 1475void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm) 1476{ 1477 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) 1478 return; 1479 1480 /* */ 1481 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1482 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1483 /* HW dynamic mechanism. */ 1484 /* */ 1485 switch (pDM_Odm->SupportPlatform) { 1486 case ODM_MP: 1487 odm_RSSIMonitorCheckMP(pDM_Odm); 1488 break; 1489 case ODM_CE: 1490 odm_RSSIMonitorCheckCE(pDM_Odm); 1491 break; 1492 case ODM_AP: 1493 odm_RSSIMonitorCheckAP(pDM_Odm); 1494 break; 1495 case ODM_ADSL: 1496 /* odm_DIGAP(pDM_Odm); */ 1497 break; 1498 } 1499 1500} /* odm_RSSIMonitorCheck */ 1501 1502void odm_RSSIMonitorCheckMP(struct odm_dm_struct *pDM_Odm) 1503{ 1504} 1505 1506static void FindMinimumRSSI(struct adapter *pAdapter) 1507{ 1508 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); 1509 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1510 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; 1511 1512 /* 1 1.Determine the minimum RSSI */ 1513 if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) && 1514 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) 1515 pdmpriv->MinUndecoratedPWDBForDM = 0; 1516 if (check_fwstate(pmlmepriv, _FW_LINKED) == true) /* Default port */ 1517 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1518 else /* associated entry pwdb */ 1519 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1520} 1521 1522void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm) 1523{ 1524 struct adapter *Adapter = pDM_Odm->Adapter; 1525 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1526 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1527 int i; 1528 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; 1529 u8 sta_cnt = 0; 1530 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ 1531 struct sta_info *psta; 1532 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 1533 1534 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) 1535 return; 1536 1537 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1538 psta = pDM_Odm->pODM_StaInfo[i]; 1539 if (IS_STA_VALID(psta) && 1540 (psta->state & WIFI_ASOC_STATE) && 1541 !_rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) && 1542 !_rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) { 1543 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) 1544 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1545 1546 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) 1547 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1548 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) 1549 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16)); 1550 } 1551 } 1552 1553 for (i = 0; i < sta_cnt; i++) { 1554 if (PWDB_rssi[i] != (0)) { 1555 if (pHalData->fw_ractrl) { 1556 /* Report every sta's RSSI to FW */ 1557 } else { 1558 ODM_RA_SetRSSI_8188E( 1559 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); 1560 } 1561 } 1562 } 1563 1564 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */ 1565 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; 1566 else 1567 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; 1568 1569 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */ 1570 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; 1571 else 1572 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; 1573 1574 FindMinimumRSSI(Adapter); 1575 ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); 1576} 1577 1578void odm_RSSIMonitorCheckAP(struct odm_dm_struct *pDM_Odm) 1579{ 1580} 1581 1582void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm) 1583{ 1584 ODM_InitializeTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer, 1585 (void *)odm_SwAntDivChkAntSwitchCallback, NULL, "SwAntennaSwitchTimer"); 1586} 1587 1588void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm) 1589{ 1590 ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer); 1591} 1592 1593void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm) 1594{ 1595 ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer); 1596 1597 ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->FastAntTrainingTimer); 1598} 1599 1600/* 3============================================================ */ 1601/* 3 Tx Power Tracking */ 1602/* 3============================================================ */ 1603 1604void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm) 1605{ 1606 odm_TXPowerTrackingThermalMeterInit(pDM_Odm); 1607} 1608 1609void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm) 1610{ 1611 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; 1612 pDM_Odm->RFCalibrateInfo.TXPowercount = 0; 1613 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; 1614 if (*(pDM_Odm->mp_mode) != 1) 1615 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1616 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); 1617 1618 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1619} 1620 1621void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm) 1622{ 1623 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1624 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1625 /* HW dynamic mechanism. */ 1626 switch (pDM_Odm->SupportPlatform) { 1627 case ODM_MP: 1628 odm_TXPowerTrackingCheckMP(pDM_Odm); 1629 break; 1630 case ODM_CE: 1631 odm_TXPowerTrackingCheckCE(pDM_Odm); 1632 break; 1633 case ODM_AP: 1634 odm_TXPowerTrackingCheckAP(pDM_Odm); 1635 break; 1636 case ODM_ADSL: 1637 break; 1638 } 1639} 1640 1641void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 1642{ 1643 struct adapter *Adapter = pDM_Odm->Adapter; 1644 1645 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) 1646 return; 1647 1648 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ 1649 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); 1650 1651 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; 1652 return; 1653 } else { 1654 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); 1655 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; 1656 } 1657} 1658 1659void odm_TXPowerTrackingCheckMP(struct odm_dm_struct *pDM_Odm) 1660{ 1661} 1662 1663void odm_TXPowerTrackingCheckAP(struct odm_dm_struct *pDM_Odm) 1664{ 1665} 1666 1667/* antenna mapping info */ 1668/* 1: right-side antenna */ 1669/* 2/0: left-side antenna */ 1670/* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */ 1671/* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */ 1672/* We select left antenna as default antenna in initial process, modify it as needed */ 1673/* */ 1674 1675/* 3============================================================ */ 1676/* 3 SW Antenna Diversity */ 1677/* 3============================================================ */ 1678void odm_SwAntDivInit(struct odm_dm_struct *pDM_Odm) 1679{ 1680} 1681 1682void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID, struct odm_phy_status_info *pPhyInfo) 1683{ 1684} 1685 1686void odm_SwAntDivChkAntSwitch(struct odm_dm_struct *pDM_Odm, u8 Step) 1687{ 1688} 1689 1690void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm) 1691{ 1692} 1693 1694void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) 1695{ 1696} 1697 1698/* 3============================================================ */ 1699/* 3 SW Antenna Diversity */ 1700/* 3============================================================ */ 1701 1702void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) 1703{ 1704 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1705 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1706 return; 1707 } 1708 1709 if (pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D)) 1710 ; 1711 else if (pDM_Odm->SupportICType == ODM_RTL8188E) 1712 ODM_AntennaDiversityInit_88E(pDM_Odm); 1713} 1714 1715void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate) 1716{ 1717 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; 1718 1719 if (pDM_SWAT_Table->antsel == 1) { 1720 if (isCCKrate) { 1721 pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++; 1722 } else { 1723 pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++; 1724 pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll; 1725 } 1726 } else { 1727 if (isCCKrate) { 1728 pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++; 1729 } else { 1730 pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++; 1731 pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll; 1732 } 1733 } 1734} 1735 1736void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) 1737{ 1738 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1739 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1740 return; 1741 } 1742 1743 if (pDM_Odm->SupportICType == ODM_RTL8188E) 1744 ODM_AntennaDiversity_88E(pDM_Odm); 1745} 1746 1747/* EDCA Turbo */ 1748void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) 1749{ 1750 struct adapter *Adapter = pDM_Odm->Adapter; 1751 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1752 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; 1753 Adapter->recvpriv.bIsAnyNonBEPkts = false; 1754 1755 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM))); 1756 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM))); 1757 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM))); 1758 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM))); 1759} /* ODM_InitEdcaTurbo */ 1760 1761void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm) 1762{ 1763 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1764 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1765 /* HW dynamic mechanism. */ 1766 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n")); 1767 1768 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)) 1769 return; 1770 1771 switch (pDM_Odm->SupportPlatform) { 1772 case ODM_MP: 1773 break; 1774 case ODM_CE: 1775 odm_EdcaTurboCheckCE(pDM_Odm); 1776 break; 1777 case ODM_AP: 1778 case ODM_ADSL: 1779 break; 1780 } 1781 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n")); 1782} /* odm_CheckEdcaTurbo */ 1783 1784void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm) 1785{ 1786 struct adapter *Adapter = pDM_Odm->Adapter; 1787 u32 trafficIndex; 1788 u32 edca_param; 1789 u64 cur_tx_bytes = 0; 1790 u64 cur_rx_bytes = 0; 1791 u8 bbtchange = false; 1792 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1793 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); 1794 struct recv_priv *precvpriv = &(Adapter->recvpriv); 1795 struct registry_priv *pregpriv = &Adapter->registrypriv; 1796 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); 1797 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 1798 1799 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */ 1800 goto dm_CheckEdcaTurbo_EXIT; 1801 1802 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) 1803 goto dm_CheckEdcaTurbo_EXIT; 1804 1805 /* Check if the status needs to be changed. */ 1806 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) { 1807 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; 1808 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; 1809 1810 /* traffic, TX or RX */ 1811 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) || 1812 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { 1813 if (cur_tx_bytes > (cur_rx_bytes << 2)) { 1814 /* Uplink TP is present. */ 1815 trafficIndex = UP_LINK; 1816 } else { 1817 /* Balance TP is present. */ 1818 trafficIndex = DOWN_LINK; 1819 } 1820 } else { 1821 if (cur_rx_bytes > (cur_tx_bytes << 2)) { 1822 /* Downlink TP is present. */ 1823 trafficIndex = DOWN_LINK; 1824 } else { 1825 /* Balance TP is present. */ 1826 trafficIndex = UP_LINK; 1827 } 1828 } 1829 1830 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) { 1831 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) 1832 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; 1833 else 1834 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; 1835 1836 rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); 1837 1838 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; 1839 } 1840 1841 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; 1842 } else { 1843 /* Turn Off EDCA turbo here. */ 1844 /* Restore original EDCA according to the declaration of AP. */ 1845 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { 1846 rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); 1847 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1848 } 1849 } 1850 1851dm_CheckEdcaTurbo_EXIT: 1852 /* Set variables for next time. */ 1853 precvpriv->bIsAnyNonBEPkts = false; 1854 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; 1855 precvpriv->last_rx_bytes = precvpriv->rx_bytes; 1856} 1857 1858/* need to ODM CE Platform */ 1859/* move to here for ANT detection mechanism using */ 1860 1861u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point, u8 initial_gain_psd) 1862{ 1863 u32 psd_report; 1864 1865 /* Set DCO frequency index, offset=(40MHz/SamplePts)*point */ 1866 ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); 1867 1868 /* Start PSD calculation, Reg808[22]=0->1 */ 1869 ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); 1870 /* Need to wait for HW PSD report */ 1871 ODM_StallExecution(30); 1872 ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0); 1873 /* Read PSD report, Reg8B4[15:0] */ 1874 psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF; 1875 1876 psd_report = (u32) (ConvertTo_dB(psd_report))+(u32)(initial_gain_psd-0x1c); 1877 1878 return psd_report; 1879} 1880 1881u32 ConvertTo_dB(u32 Value) 1882{ 1883 u8 i; 1884 u8 j; 1885 u32 dB; 1886 1887 Value = Value & 0xFFFF; 1888 for (i = 0; i < 8; i++) { 1889 if (Value <= dB_Invert_Table[i][11]) 1890 break; 1891 } 1892 1893 if (i >= 8) 1894 return 96; /* maximum 96 dB */ 1895 1896 for (j = 0; j < 12; j++) { 1897 if (Value <= dB_Invert_Table[i][j]) 1898 break; 1899 } 1900 1901 dB = i*12 + j + 1; 1902 1903 return dB; 1904} 1905 1906/* 2011/09/22 MH Add for 92D global spin lock utilization. */ 1907void odm_GlobalAdapterCheck(void) 1908{ 1909} /* odm_GlobalAdapterCheck */ 1910 1911/* Description: */ 1912/* Set Single/Dual Antenna default setting for products that do not do detection in advance. */ 1913/* Added by Joseph, 2012.03.22 */ 1914void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm) 1915{ 1916 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; 1917 1918 pDM_SWAT_Table->ANTA_ON = true; 1919 pDM_SWAT_Table->ANTB_ON = true; 1920} 1921 1922 1923/* 2 8723A ANT DETECT */ 1924 1925static void odm_PHY_SaveAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegisterNum) 1926{ 1927 u32 i; 1928 1929 /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */ 1930 for (i = 0; i < RegisterNum; i++) 1931 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord); 1932} 1933 1934static void odm_PHY_ReloadAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegiesterNum) 1935{ 1936 u32 i; 1937 1938 for (i = 0; i < RegiesterNum; i++) 1939 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]); 1940} 1941 1942/* 2 8723A ANT DETECT */ 1943/* Description: */ 1944/* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */ 1945/* This function is cooperated with BB team Neil. */ 1946bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode) 1947{ 1948 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; 1949 u32 CurrentChannel, RfLoopReg; 1950 u8 n; 1951 u32 Reg88c, Regc08, Reg874, Regc50; 1952 u8 initial_gain = 0x5a; 1953 u32 PSD_report_tmp; 1954 u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0; 1955 bool bResult = true; 1956 u32 AFE_Backup[16]; 1957 u32 AFE_REG_8723A[16] = { 1958 rRx_Wait_CCA, rTx_CCK_RFON, 1959 rTx_CCK_BBON, rTx_OFDM_RFON, 1960 rTx_OFDM_BBON, rTx_To_Rx, 1961 rTx_To_Tx, rRx_CCK, 1962 rRx_OFDM, rRx_Wait_RIFS, 1963 rRx_TO_Rx, rStandby, 1964 rSleep, rPMPD_ANAEN, 1965 rFPGA0_XCD_SwitchControl, rBlue_Tooth}; 1966 1967 if (!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))) 1968 return bResult; 1969 1970 if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) 1971 return bResult; 1972 1973 if (pDM_Odm->SupportICType == ODM_RTL8192C) { 1974 /* Which path in ADC/DAC is turnned on for PSD: both I/Q */ 1975 ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3); 1976 /* Ageraged number: 8 */ 1977 ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1); 1978 /* pts = 128; */ 1979 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0); 1980 } 1981 1982 /* 1 Backup Current RF/BB Settings */ 1983 1984 CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); 1985 RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask); 1986 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); /* change to Antenna A */ 1987 /* Step 1: USE IQK to transmitter single tone */ 1988 1989 ODM_StallExecution(10); 1990 1991 /* Store A Path Register 88c, c08, 874, c50 */ 1992 Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord); 1993 Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord); 1994 Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord); 1995 Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); 1996 1997 /* Store AFE Registers */ 1998 odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); 1999 2000 /* Set PSD 128 pts */ 2001 ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); /* 128 pts */ 2002 2003 /* To SET CH1 to do */ 2004 ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); /* Channel 1 */ 2005 2006 /* AFE all on step */ 2007 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4); 2008 ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4); 2009 ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4); 2010 ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4); 2011 ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4); 2012 ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4); 2013 ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4); 2014 ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4); 2015 ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4); 2016 ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4); 2017 ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4); 2018 ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4); 2019 ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4); 2020 ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4); 2021 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4); 2022 ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4); 2023 2024 /* 3 wire Disable */ 2025 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0); 2026 2027 /* BB IQK Setting */ 2028 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4); 2029 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000); 2030 2031 /* IQK setting tone@ 4.34Mhz */ 2032 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C); 2033 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); 2034 2035 2036 /* Page B init */ 2037 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000); 2038 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); 2039 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); 2040 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); 2041 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008); 2042 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008); 2043 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0); 2044 2045 /* RF loop Setting */ 2046 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008); 2047 2048 /* IQK Single tone start */ 2049 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000); 2050 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 2051 ODM_StallExecution(1000); 2052 PSD_report_tmp = 0x0; 2053 2054 for (n = 0; n < 2; n++) { 2055 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); 2056 if (PSD_report_tmp > AntA_report) 2057 AntA_report = PSD_report_tmp; 2058 } 2059 2060 PSD_report_tmp = 0x0; 2061 2062 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */ 2063 ODM_StallExecution(10); 2064 2065 2066 for (n = 0; n < 2; n++) { 2067 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); 2068 if (PSD_report_tmp > AntB_report) 2069 AntB_report = PSD_report_tmp; 2070 } 2071 2072 /* change to open case */ 2073 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); /* change to Ant A and B all open case */ 2074 ODM_StallExecution(10); 2075 2076 for (n = 0; n < 2; n++) { 2077 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); 2078 if (PSD_report_tmp > AntO_report) 2079 AntO_report = PSD_report_tmp; 2080 } 2081 2082 /* Close IQK Single Tone function */ 2083 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000); 2084 PSD_report_tmp = 0x0; 2085 2086 /* 1 Return to antanna A */ 2087 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); 2088 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c); 2089 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08); 2090 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874); 2091 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40); 2092 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50); 2093 ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel); 2094 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg); 2095 2096 /* Reload AFE Registers */ 2097 odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); 2098 2099 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report)); 2100 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report)); 2101 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d\n", 2416, AntO_report)); 2102 2103 2104 if (pDM_Odm->SupportICType == ODM_RTL8723A) { 2105 /* 2 Test Ant B based on Ant A is ON */ 2106 if (mode == ANTTESTB) { 2107 if (AntA_report >= 100) { 2108 if (AntB_report > (AntA_report+1)) { 2109 pDM_SWAT_Table->ANTB_ON = false; 2110 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n")); 2111 } else { 2112 pDM_SWAT_Table->ANTB_ON = true; 2113 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n")); 2114 } 2115 } else { 2116 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); 2117 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */ 2118 bResult = false; 2119 } 2120 } else if (mode == ANTTESTALL) { 2121 /* 2 Test Ant A and B based on DPDT Open */ 2122 if ((AntO_report >= 100)&(AntO_report < 118)) { 2123 if (AntA_report > (AntO_report+1)) { 2124 pDM_SWAT_Table->ANTA_ON = false; 2125 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF")); 2126 } else { 2127 pDM_SWAT_Table->ANTA_ON = true; 2128 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON")); 2129 } 2130 2131 if (AntB_report > (AntO_report+2)) { 2132 pDM_SWAT_Table->ANTB_ON = false; 2133 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF")); 2134 } else { 2135 pDM_SWAT_Table->ANTB_ON = true; 2136 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON")); 2137 } 2138 } 2139 } 2140 } else if (pDM_Odm->SupportICType == ODM_RTL8192C) { 2141 if (AntA_report >= 100) { 2142 if (AntB_report > (AntA_report+2)) { 2143 pDM_SWAT_Table->ANTA_ON = false; 2144 pDM_SWAT_Table->ANTB_ON = true; 2145 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); 2146 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n")); 2147 } else if (AntA_report > (AntB_report+2)) { 2148 pDM_SWAT_Table->ANTA_ON = true; 2149 pDM_SWAT_Table->ANTB_ON = false; 2150 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); 2151 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n")); 2152 } else { 2153 pDM_SWAT_Table->ANTA_ON = true; 2154 pDM_SWAT_Table->ANTB_ON = true; 2155 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 2156 ("ODM_SingleDualAntennaDetection(): Dual Antenna\n")); 2157 } 2158 } else { 2159 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); 2160 pDM_SWAT_Table->ANTA_ON = true; /* Set Antenna A on as default */ 2161 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */ 2162 bResult = false; 2163 } 2164 } 2165 return bResult; 2166} 2167 2168/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ 2169void odm_dtc(struct odm_dm_struct *pDM_Odm) 2170{ 2171} 2172