odm.c revision 36298867fd33ed8a2641e7d3125b88bb925987b4
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21/* include files */ 22 23#include "odm_precomp.h" 24 25static const u16 dB_Invert_Table[8][12] = { 26 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, 27 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, 28 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63}, 29 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251}, 30 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000}, 31 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, 32 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849}, 33 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} 34}; 35 36/* avoid to warn in FreeBSD ==> To DO modify */ 37static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { 38 /* UL DL */ 39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ 40 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ 41 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ 42 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ 43 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ 44 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ 45 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ 46 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ 47 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ 48 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ 49}; 50 51/* Global var */ 52u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { 53 0x7f8001fe, /* 0, +6.0dB */ 54 0x788001e2, /* 1, +5.5dB */ 55 0x71c001c7, /* 2, +5.0dB */ 56 0x6b8001ae, /* 3, +4.5dB */ 57 0x65400195, /* 4, +4.0dB */ 58 0x5fc0017f, /* 5, +3.5dB */ 59 0x5a400169, /* 6, +3.0dB */ 60 0x55400155, /* 7, +2.5dB */ 61 0x50800142, /* 8, +2.0dB */ 62 0x4c000130, /* 9, +1.5dB */ 63 0x47c0011f, /* 10, +1.0dB */ 64 0x43c0010f, /* 11, +0.5dB */ 65 0x40000100, /* 12, +0dB */ 66 0x3c8000f2, /* 13, -0.5dB */ 67 0x390000e4, /* 14, -1.0dB */ 68 0x35c000d7, /* 15, -1.5dB */ 69 0x32c000cb, /* 16, -2.0dB */ 70 0x300000c0, /* 17, -2.5dB */ 71 0x2d4000b5, /* 18, -3.0dB */ 72 0x2ac000ab, /* 19, -3.5dB */ 73 0x288000a2, /* 20, -4.0dB */ 74 0x26000098, /* 21, -4.5dB */ 75 0x24000090, /* 22, -5.0dB */ 76 0x22000088, /* 23, -5.5dB */ 77 0x20000080, /* 24, -6.0dB */ 78 0x1e400079, /* 25, -6.5dB */ 79 0x1c800072, /* 26, -7.0dB */ 80 0x1b00006c, /* 27. -7.5dB */ 81 0x19800066, /* 28, -8.0dB */ 82 0x18000060, /* 29, -8.5dB */ 83 0x16c0005b, /* 30, -9.0dB */ 84 0x15800056, /* 31, -9.5dB */ 85 0x14400051, /* 32, -10.0dB */ 86 0x1300004c, /* 33, -10.5dB */ 87 0x12000048, /* 34, -11.0dB */ 88 0x11000044, /* 35, -11.5dB */ 89 0x10000040, /* 36, -12.0dB */ 90 0x0f00003c,/* 37, -12.5dB */ 91 0x0e400039,/* 38, -13.0dB */ 92 0x0d800036,/* 39, -13.5dB */ 93 0x0cc00033,/* 40, -14.0dB */ 94 0x0c000030,/* 41, -14.5dB */ 95 0x0b40002d,/* 42, -15.0dB */ 96}; 97 98u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { 99 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 100 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 101 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 102 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 103 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 104 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 105 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 106 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 107 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 108 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 109 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 110 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 111 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 112 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 113 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 114 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 115 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 116 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 117 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 118 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 119 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ 120 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ 121 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ 122 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ 123 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ 124 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ 125 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ 126 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ 127 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ 128 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ 129 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ 130 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ 131 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ 132}; 133 134u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { 135 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 136 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 137 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 138 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 139 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 140 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 141 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 142 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 143 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 144 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 145 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 146 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 147 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 148 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 149 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 150 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 151 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 152 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 153 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 154 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 155 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ 156 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ 157 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ 158 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ 159 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ 160 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ 161 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ 162 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ 163 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ 164 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ 165 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ 166 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ 167 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ 168}; 169 170 171#define RxDefaultAnt1 0x65a9 172#define RxDefaultAnt2 0x569a 173 174/* 3 Export Interface */ 175 176/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ 177void ODM_DMInit(struct odm_dm_struct *pDM_Odm) 178{ 179 /* 2012.05.03 Luke: For all IC series */ 180 odm_CommonInfoSelfInit(pDM_Odm); 181 odm_CmnInfoInit_Debug(pDM_Odm); 182 odm_DIGInit(pDM_Odm); 183 odm_RateAdaptiveMaskInit(pDM_Odm); 184 185 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { 186 ; 187 } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { 188 odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ 189 odm_DynamicBBPowerSavingInit(pDM_Odm); 190 odm_DynamicTxPowerInit(pDM_Odm); 191 odm_TXPowerTrackingInit(pDM_Odm); 192 ODM_EdcaTurboInit(pDM_Odm); 193 ODM_RAInfo_Init_all(pDM_Odm); 194 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 195 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 196 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 197 odm_InitHybridAntDiv(pDM_Odm); 198 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV) 199 odm_SwAntDivInit(pDM_Odm); 200 } 201} 202 203/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ 204/* You can not add any dummy function here, be care, you can only use DM structure */ 205/* to perform any new ODM_DM. */ 206void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) 207{ 208 /* 2012.05.03 Luke: For all IC series */ 209 odm_GlobalAdapterCheck(); 210 odm_CmnInfoHook_Debug(pDM_Odm); 211 odm_CmnInfoUpdate_Debug(pDM_Odm); 212 odm_CommonInfoSelfUpdate(pDM_Odm); 213 odm_FalseAlarmCounterStatistics(pDM_Odm); 214 odm_RSSIMonitorCheck(pDM_Odm); 215 216 /* For CE Platform(SPRD or Tablet) */ 217 /* 8723A or 8189ES platform */ 218 /* NeilChen--2012--08--24-- */ 219 /* Fix Leave LPS issue */ 220 if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */ 221 ((pDM_Odm->SupportICType & (ODM_RTL8723A)) || 222 (pDM_Odm->SupportICType & (ODM_RTL8188E) && 223 ((pDM_Odm->SupportInterface == ODM_ITRF_SDIO))))) { 224 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n")); 225 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n")); 226 odm_DIGbyRSSI_LPS(pDM_Odm); 227 } else { 228 odm_DIG(pDM_Odm); 229 } 230 odm_CCKPacketDetectionThresh(pDM_Odm); 231 232 if (*(pDM_Odm->pbPowerSaving)) 233 return; 234 235 odm_RefreshRateAdaptiveMask(pDM_Odm); 236 237 odm_DynamicBBPowerSaving(pDM_Odm); 238 odm_DynamicPrimaryCCA(pDM_Odm); 239 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 240 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 241 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 242 odm_HwAntDiv(pDM_Odm); 243 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV) 244 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK); 245 246 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { 247 ; 248 } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { 249 ODM_TXPowerTrackingCheck(pDM_Odm); 250 odm_EdcaTurboCheck(pDM_Odm); 251 odm_DynamicTxPower(pDM_Odm); 252 } 253 odm_dtc(pDM_Odm); 254} 255 256/* Init /.. Fixed HW value. Only init time. */ 257void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value) 258{ 259 /* This section is used for init value */ 260 switch (CmnInfo) { 261 /* Fixed ODM value. */ 262 case ODM_CMNINFO_ABILITY: 263 pDM_Odm->SupportAbility = (u32)Value; 264 break; 265 case ODM_CMNINFO_PLATFORM: 266 pDM_Odm->SupportPlatform = (u8)Value; 267 break; 268 case ODM_CMNINFO_INTERFACE: 269 pDM_Odm->SupportInterface = (u8)Value; 270 break; 271 case ODM_CMNINFO_MP_TEST_CHIP: 272 pDM_Odm->bIsMPChip = (u8)Value; 273 break; 274 case ODM_CMNINFO_IC_TYPE: 275 pDM_Odm->SupportICType = Value; 276 break; 277 case ODM_CMNINFO_CUT_VER: 278 pDM_Odm->CutVersion = (u8)Value; 279 break; 280 case ODM_CMNINFO_FAB_VER: 281 pDM_Odm->FabVersion = (u8)Value; 282 break; 283 case ODM_CMNINFO_RF_TYPE: 284 pDM_Odm->RFType = (u8)Value; 285 break; 286 case ODM_CMNINFO_RF_ANTENNA_TYPE: 287 pDM_Odm->AntDivType = (u8)Value; 288 break; 289 case ODM_CMNINFO_BOARD_TYPE: 290 pDM_Odm->BoardType = (u8)Value; 291 break; 292 case ODM_CMNINFO_EXT_LNA: 293 pDM_Odm->ExtLNA = (u8)Value; 294 break; 295 case ODM_CMNINFO_EXT_PA: 296 pDM_Odm->ExtPA = (u8)Value; 297 break; 298 case ODM_CMNINFO_EXT_TRSW: 299 pDM_Odm->ExtTRSW = (u8)Value; 300 break; 301 case ODM_CMNINFO_PATCH_ID: 302 pDM_Odm->PatchID = (u8)Value; 303 break; 304 case ODM_CMNINFO_BINHCT_TEST: 305 pDM_Odm->bInHctTest = (bool)Value; 306 break; 307 case ODM_CMNINFO_BWIFI_TEST: 308 pDM_Odm->bWIFITest = (bool)Value; 309 break; 310 case ODM_CMNINFO_SMART_CONCURRENT: 311 pDM_Odm->bDualMacSmartConcurrent = (bool)Value; 312 break; 313 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 314 default: 315 /* do nothing */ 316 break; 317 } 318 319 /* Tx power tracking BB swing table. */ 320 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ 321 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */ 322 pDM_Odm->BbSwingIdxOfdmCurrent = 12; 323 pDM_Odm->BbSwingFlagOfdm = false; 324} 325 326void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue) 327{ 328 /* */ 329 /* Hook call by reference pointer. */ 330 /* */ 331 switch (CmnInfo) { 332 /* Dynamic call by reference pointer. */ 333 case ODM_CMNINFO_MAC_PHY_MODE: 334 pDM_Odm->pMacPhyMode = (u8 *)pValue; 335 break; 336 case ODM_CMNINFO_TX_UNI: 337 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue; 338 break; 339 case ODM_CMNINFO_RX_UNI: 340 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue; 341 break; 342 case ODM_CMNINFO_WM_MODE: 343 pDM_Odm->pWirelessMode = (u8 *)pValue; 344 break; 345 case ODM_CMNINFO_BAND: 346 pDM_Odm->pBandType = (u8 *)pValue; 347 break; 348 case ODM_CMNINFO_SEC_CHNL_OFFSET: 349 pDM_Odm->pSecChOffset = (u8 *)pValue; 350 break; 351 case ODM_CMNINFO_SEC_MODE: 352 pDM_Odm->pSecurity = (u8 *)pValue; 353 break; 354 case ODM_CMNINFO_BW: 355 pDM_Odm->pBandWidth = (u8 *)pValue; 356 break; 357 case ODM_CMNINFO_CHNL: 358 pDM_Odm->pChannel = (u8 *)pValue; 359 break; 360 case ODM_CMNINFO_DMSP_GET_VALUE: 361 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue; 362 break; 363 case ODM_CMNINFO_BUDDY_ADAPTOR: 364 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue; 365 break; 366 case ODM_CMNINFO_DMSP_IS_MASTER: 367 pDM_Odm->pbMasterOfDMSP = (bool *)pValue; 368 break; 369 case ODM_CMNINFO_SCAN: 370 pDM_Odm->pbScanInProcess = (bool *)pValue; 371 break; 372 case ODM_CMNINFO_POWER_SAVING: 373 pDM_Odm->pbPowerSaving = (bool *)pValue; 374 break; 375 case ODM_CMNINFO_ONE_PATH_CCA: 376 pDM_Odm->pOnePathCCA = (u8 *)pValue; 377 break; 378 case ODM_CMNINFO_DRV_STOP: 379 pDM_Odm->pbDriverStopped = (bool *)pValue; 380 break; 381 case ODM_CMNINFO_PNP_IN: 382 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue; 383 break; 384 case ODM_CMNINFO_INIT_ON: 385 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue; 386 break; 387 case ODM_CMNINFO_ANT_TEST: 388 pDM_Odm->pAntennaTest = (u8 *)pValue; 389 break; 390 case ODM_CMNINFO_NET_CLOSED: 391 pDM_Odm->pbNet_closed = (bool *)pValue; 392 break; 393 case ODM_CMNINFO_MP_MODE: 394 pDM_Odm->mp_mode = (u8 *)pValue; 395 break; 396 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 397 default: 398 /* do nothing */ 399 break; 400 } 401} 402 403void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue) 404{ 405 /* Hook call by reference pointer. */ 406 switch (CmnInfo) { 407 /* Dynamic call by reference pointer. */ 408 case ODM_CMNINFO_STA_STATUS: 409 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue; 410 break; 411 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 412 default: 413 /* do nothing */ 414 break; 415 } 416} 417 418/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ 419void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value) 420{ 421 /* */ 422 /* This init variable may be changed in run time. */ 423 /* */ 424 switch (CmnInfo) { 425 case ODM_CMNINFO_ABILITY: 426 pDM_Odm->SupportAbility = (u32)Value; 427 break; 428 case ODM_CMNINFO_RF_TYPE: 429 pDM_Odm->RFType = (u8)Value; 430 break; 431 case ODM_CMNINFO_WIFI_DIRECT: 432 pDM_Odm->bWIFI_Direct = (bool)Value; 433 break; 434 case ODM_CMNINFO_WIFI_DISPLAY: 435 pDM_Odm->bWIFI_Display = (bool)Value; 436 break; 437 case ODM_CMNINFO_LINK: 438 pDM_Odm->bLinked = (bool)Value; 439 break; 440 case ODM_CMNINFO_RSSI_MIN: 441 pDM_Odm->RSSI_Min = (u8)Value; 442 break; 443 case ODM_CMNINFO_DBG_COMP: 444 pDM_Odm->DebugComponents = Value; 445 break; 446 case ODM_CMNINFO_DBG_LEVEL: 447 pDM_Odm->DebugLevel = (u32)Value; 448 break; 449 case ODM_CMNINFO_RA_THRESHOLD_HIGH: 450 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value; 451 break; 452 case ODM_CMNINFO_RA_THRESHOLD_LOW: 453 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value; 454 break; 455 } 456} 457 458void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) 459{ 460 struct adapter *adapter = pDM_Odm->Adapter; 461 462 pDM_Odm->bCckHighPower = (bool) PHY_QueryBBReg(adapter, 0x824, BIT9); 463 pDM_Odm->RFPathRxEnable = (u8) PHY_QueryBBReg(adapter, 0xc04, 0x0F); 464 if (pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D)) 465 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; 466 if (pDM_Odm->SupportICType & (ODM_RTL8723A)) 467 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; 468 469 ODM_InitDebugSetting(pDM_Odm); 470} 471 472void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) 473{ 474 u8 EntryCnt = 0; 475 u8 i; 476 struct sta_info *pEntry; 477 478 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { 479 if (*(pDM_Odm->pSecChOffset) == 1) 480 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; 481 else if (*(pDM_Odm->pSecChOffset) == 2) 482 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; 483 } else { 484 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); 485 } 486 487 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 488 pEntry = pDM_Odm->pODM_StaInfo[i]; 489 if (IS_STA_VALID(pEntry)) 490 EntryCnt++; 491 } 492 if (EntryCnt == 1) 493 pDM_Odm->bOneEntryOnly = true; 494 else 495 pDM_Odm->bOneEntryOnly = false; 496} 497 498void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm) 499{ 500 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); 501 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform)); 502 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility)); 503 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface)); 504 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType)); 505 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion)); 506 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n", pDM_Odm->FabVersion)); 507 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n", pDM_Odm->RFType)); 508 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType)); 509 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA)); 510 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA)); 511 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW)); 512 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID)); 513 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest)); 514 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest)); 515 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent)); 516} 517 518void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm) 519{ 520 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); 521 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast))); 522 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast))); 523 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode))); 524 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset))); 525 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity))); 526 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth))); 527 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel))); 528 529 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess))); 530 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving))); 531 532 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) 533 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pOnePathCCA=%d\n", *(pDM_Odm->pOnePathCCA))); 534} 535 536void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm) 537{ 538 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); 539 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct)); 540 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display)); 541 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked)); 542 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min)); 543} 544 545static int getIGIForDiff(int value_IGI) 546{ 547 #define ONERCCA_LOW_TH 0x30 548 #define ONERCCA_LOW_DIFF 8 549 550 if (value_IGI < ONERCCA_LOW_TH) { 551 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) 552 return ONERCCA_LOW_TH; 553 else 554 return value_IGI + ONERCCA_LOW_DIFF; 555 } else { 556 return value_IGI; 557 } 558} 559 560void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) 561{ 562 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 563 struct adapter *adapter = pDM_Odm->Adapter; 564 565 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 566 ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", 567 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm))); 568 569 if (pDM_DigTable->CurIGValue != CurrentIGI) { 570 if (pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP)) { 571 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 572 if (pDM_Odm->SupportICType != ODM_RTL8188E) 573 PHY_SetBBReg(adapter, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 574 } else if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) { 575 switch (*(pDM_Odm->pOnePathCCA)) { 576 case ODM_CCA_2R: 577 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 578 if (pDM_Odm->SupportICType != ODM_RTL8188E) 579 PHY_SetBBReg(adapter, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 580 break; 581 case ODM_CCA_1R_A: 582 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 583 if (pDM_Odm->SupportICType != ODM_RTL8188E) 584 PHY_SetBBReg(adapter, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI)); 585 break; 586 case ODM_CCA_1R_B: 587 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI)); 588 if (pDM_Odm->SupportICType != ODM_RTL8188E) 589 PHY_SetBBReg(adapter, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 590 break; 591 } 592 } 593 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n", CurrentIGI)); 594 /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */ 595 pDM_DigTable->CurIGValue = CurrentIGI; 596 } 597 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x\n", CurrentIGI)); 598 599/* Add by Neil Chen to enable edcca to MP Platform */ 600} 601 602/* Need LPS mode for CE platform --2012--08--24--- */ 603/* 8723AS/8189ES */ 604void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm) 605{ 606 struct adapter *pAdapter = pDM_Odm->Adapter; 607 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 608 609 u8 RSSI_Lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */ 610 u8 bFwCurrentInPSMode = false; 611 u8 CurrentIGI = pDM_Odm->RSSI_Min; 612 613 if (!(pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8188E))) 614 return; 615 616 CurrentIGI = CurrentIGI + RSSI_OFFSET_DIG; 617 bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode; 618 619 /* Using FW PS mode to make IGI */ 620 if (bFwCurrentInPSMode) { 621 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n")); 622 /* Adjust by FA in LPS MODE */ 623 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS) 624 CurrentIGI = CurrentIGI+2; 625 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) 626 CurrentIGI = CurrentIGI+1; 627 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) 628 CurrentIGI = CurrentIGI-1; 629 } else { 630 CurrentIGI = RSSI_Lower; 631 } 632 633 /* Lower bound checking */ 634 635 /* RSSI Lower bound check */ 636 if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) 637 RSSI_Lower = (pDM_Odm->RSSI_Min-10); 638 else 639 RSSI_Lower = DM_DIG_MIN_NIC; 640 641 /* Upper and Lower Bound checking */ 642 if (CurrentIGI > DM_DIG_MAX_NIC) 643 CurrentIGI = DM_DIG_MAX_NIC; 644 else if (CurrentIGI < RSSI_Lower) 645 CurrentIGI = RSSI_Lower; 646 647 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 648} 649 650void odm_DIGInit(struct odm_dm_struct *pDM_Odm) 651{ 652 struct adapter *adapter = pDM_Odm->Adapter; 653 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 654 655 pDM_DigTable->CurIGValue = (u8) PHY_QueryBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); 656 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; 657 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; 658 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW; 659 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH; 660 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) { 661 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 662 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 663 } else { 664 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 665 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 666 } 667 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; 668 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; 669 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; 670 pDM_DigTable->PreCCK_CCAThres = 0xFF; 671 pDM_DigTable->CurCCK_CCAThres = 0x83; 672 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; 673 pDM_DigTable->LargeFAHit = 0; 674 pDM_DigTable->Recover_cnt = 0; 675 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; 676 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; 677 pDM_DigTable->bMediaConnect_0 = false; 678 pDM_DigTable->bMediaConnect_1 = false; 679 680 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */ 681 pDM_Odm->bDMInitialGainEnable = true; 682} 683 684void odm_DIG(struct odm_dm_struct *pDM_Odm) 685{ 686 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 687 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 688 u8 DIG_Dynamic_MIN; 689 u8 DIG_MaxOfMin; 690 bool FirstConnect, FirstDisConnect; 691 u8 dm_dig_max, dm_dig_min; 692 u8 CurrentIGI = pDM_DigTable->CurIGValue; 693 694 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); 695 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) { 696 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 697 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); 698 return; 699 } 700 701 if (*(pDM_Odm->pbScanInProcess)) { 702 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n")); 703 return; 704 } 705 706 /* add by Neil Chen to avoid PSD is processing */ 707 if (pDM_Odm->bDMInitialGainEnable == false) { 708 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n")); 709 return; 710 } 711 712 if (pDM_Odm->SupportICType == ODM_RTL8192D) { 713 if (*(pDM_Odm->pMacPhyMode) == ODM_DMSP) { 714 if (*(pDM_Odm->pbMasterOfDMSP)) { 715 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 716 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 717 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 718 } else { 719 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; 720 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1); 721 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1); 722 } 723 } else { 724 if (*(pDM_Odm->pBandType) == ODM_BAND_5G) { 725 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 726 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 727 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 728 } else { 729 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; 730 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1); 731 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1); 732 } 733 } 734 } else { 735 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 736 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 737 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 738 } 739 740 /* 1 Boundary Decision */ 741 if ((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) && 742 ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) { 743 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) { 744 dm_dig_max = DM_DIG_MAX_AP_HP; 745 dm_dig_min = DM_DIG_MIN_AP_HP; 746 } else { 747 dm_dig_max = DM_DIG_MAX_NIC_HP; 748 dm_dig_min = DM_DIG_MIN_NIC_HP; 749 } 750 DIG_MaxOfMin = DM_DIG_MAX_AP_HP; 751 } else { 752 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) { 753 dm_dig_max = DM_DIG_MAX_AP; 754 dm_dig_min = DM_DIG_MIN_AP; 755 DIG_MaxOfMin = dm_dig_max; 756 } else { 757 dm_dig_max = DM_DIG_MAX_NIC; 758 dm_dig_min = DM_DIG_MIN_NIC; 759 DIG_MaxOfMin = DM_DIG_MAX_AP; 760 } 761 } 762 if (pDM_Odm->bLinked) { 763 /* 2 8723A Series, offset need to be 10 */ 764 if (pDM_Odm->SupportICType == (ODM_RTL8723A)) { 765 /* 2 Upper Bound */ 766 if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC) 767 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 768 else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC) 769 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC; 770 else 771 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10; 772 /* 2 If BT is Concurrent, need to set Lower Bound */ 773 DIG_Dynamic_MIN = DM_DIG_MIN_NIC; 774 } else { 775 /* 2 Modify DIG upper bound */ 776 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) 777 pDM_DigTable->rx_gain_range_max = dm_dig_max; 778 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min) 779 pDM_DigTable->rx_gain_range_max = dm_dig_min; 780 else 781 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; 782 /* 2 Modify DIG lower bound */ 783 if (pDM_Odm->bOneEntryOnly) { 784 if (pDM_Odm->RSSI_Min < dm_dig_min) 785 DIG_Dynamic_MIN = dm_dig_min; 786 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) 787 DIG_Dynamic_MIN = DIG_MaxOfMin; 788 else 789 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; 790 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 791 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n", 792 DIG_Dynamic_MIN)); 793 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 794 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n", 795 pDM_Odm->RSSI_Min)); 796 } else if ((pDM_Odm->SupportICType == ODM_RTL8188E) && 797 (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 798 /* 1 Lower Bound for 88E AntDiv */ 799 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { 800 DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max; 801 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 802 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n", 803 pDM_DigTable->AntDiv_RSSI_max)); 804 } 805 } else { 806 DIG_Dynamic_MIN = dm_dig_min; 807 } 808 } 809 } else { 810 pDM_DigTable->rx_gain_range_max = dm_dig_max; 811 DIG_Dynamic_MIN = dm_dig_min; 812 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); 813 } 814 815 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ 816 if (pFalseAlmCnt->Cnt_all > 10000) { 817 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n")); 818 819 if (pDM_DigTable->LargeFAHit != 3) 820 pDM_DigTable->LargeFAHit++; 821 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { 822 pDM_DigTable->ForbiddenIGI = CurrentIGI; 823 pDM_DigTable->LargeFAHit = 1; 824 } 825 826 if (pDM_DigTable->LargeFAHit >= 3) { 827 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max) 828 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; 829 else 830 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 831 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ 832 } 833 834 } else { 835 /* Recovery mechanism for IGI lower bound */ 836 if (pDM_DigTable->Recover_cnt != 0) { 837 pDM_DigTable->Recover_cnt--; 838 } else { 839 if (pDM_DigTable->LargeFAHit < 3) { 840 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */ 841 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 842 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 843 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); 844 } else { 845 pDM_DigTable->ForbiddenIGI--; 846 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 847 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); 848 } 849 } else { 850 pDM_DigTable->LargeFAHit = 0; 851 } 852 } 853 } 854 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 855 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n", 856 pDM_DigTable->LargeFAHit)); 857 858 /* 1 Adjust initial gain by false alarm */ 859 if (pDM_Odm->bLinked) { 860 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); 861 if (FirstConnect) { 862 CurrentIGI = pDM_Odm->RSSI_Min; 863 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); 864 } else { 865 if (pDM_Odm->SupportICType == ODM_RTL8192D) { 866 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D) 867 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 868 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D) 869 CurrentIGI = CurrentIGI + 1; /* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 870 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D) 871 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 872 } else { 873 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) 874 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 875 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) 876 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 877 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) 878 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 879 } 880 } 881 } else { 882 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); 883 if (FirstDisConnect) { 884 CurrentIGI = pDM_DigTable->rx_gain_range_min; 885 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n")); 886 } else { 887 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ 888 if (pFalseAlmCnt->Cnt_all > 10000) 889 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 890 else if (pFalseAlmCnt->Cnt_all > 8000) 891 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 892 else if (pFalseAlmCnt->Cnt_all < 500) 893 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 894 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n")); 895 } 896 } 897 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); 898 /* 1 Check initial gain by upper/lower bound */ 899 if (CurrentIGI > pDM_DigTable->rx_gain_range_max) 900 CurrentIGI = pDM_DigTable->rx_gain_range_max; 901 if (CurrentIGI < pDM_DigTable->rx_gain_range_min) 902 CurrentIGI = pDM_DigTable->rx_gain_range_min; 903 904 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 905 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", 906 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); 907 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); 908 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); 909 910 /* 2 High power RSSI threshold */ 911 912 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 913 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; 914 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; 915} 916 917/* 3============================================================ */ 918/* 3 FASLE ALARM CHECK */ 919/* 3============================================================ */ 920 921void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 922{ 923 struct adapter *adapter = pDM_Odm->Adapter; 924 u32 ret_value; 925 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 926 927 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) 928 return; 929 930 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { 931 /* hold ofdm counter */ 932 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ 933 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ 934 935 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); 936 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); 937 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); 938 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); 939 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); 940 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); 941 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); 942 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); 943 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); 944 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); 945 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); 946 947 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + 948 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + 949 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; 950 951 if (pDM_Odm->SupportICType == ODM_RTL8188E) { 952 ret_value = PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); 953 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); 954 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); 955 } 956 957 /* hold cck counter */ 958 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); 959 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); 960 961 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); 962 FalseAlmCnt->Cnt_Cck_fail = ret_value; 963 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); 964 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8; 965 966 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); 967 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8); 968 969 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + 970 FalseAlmCnt->Cnt_SB_Search_fail + 971 FalseAlmCnt->Cnt_Parity_Fail + 972 FalseAlmCnt->Cnt_Rate_Illegal + 973 FalseAlmCnt->Cnt_Crc8_fail + 974 FalseAlmCnt->Cnt_Mcs_fail + 975 FalseAlmCnt->Cnt_Cck_fail); 976 977 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; 978 979 if (pDM_Odm->SupportICType >= ODM_RTL8723A) { 980 /* reset false alarm counter registers */ 981 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1); 982 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0); 983 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1); 984 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0); 985 /* update ofdm counter */ 986 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /* update page C counter */ 987 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /* update page D counter */ 988 989 /* reset CCK CCA counter */ 990 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0); 991 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2); 992 /* reset CCK FA counter */ 993 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0); 994 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2); 995 } 996 997 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); 998 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 999 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", 1000 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); 1001 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 1002 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", 1003 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); 1004 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 1005 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", 1006 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); 1007 } else { /* FOR ODM_IC_11AC_SERIES */ 1008 /* read OFDM FA counter */ 1009 FalseAlmCnt->Cnt_Ofdm_fail = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_11AC, bMaskLWord); 1010 FalseAlmCnt->Cnt_Cck_fail = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_11AC, bMaskLWord); 1011 FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail; 1012 1013 /* reset OFDM FA coutner */ 1014 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1); 1015 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0); 1016 /* reset CCK FA counter */ 1017 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11AC, BIT15, 0); 1018 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11AC, BIT15, 1); 1019 } 1020 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); 1021 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); 1022 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); 1023} 1024 1025/* 3============================================================ */ 1026/* 3 CCK Packet Detect Threshold */ 1027/* 3============================================================ */ 1028 1029void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) 1030{ 1031 u8 CurCCK_CCAThres; 1032 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 1033 1034 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) 1035 return; 1036 if (pDM_Odm->ExtLNA) 1037 return; 1038 if (pDM_Odm->bLinked) { 1039 if (pDM_Odm->RSSI_Min > 25) { 1040 CurCCK_CCAThres = 0xcd; 1041 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) { 1042 CurCCK_CCAThres = 0x83; 1043 } else { 1044 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 1045 CurCCK_CCAThres = 0x83; 1046 else 1047 CurCCK_CCAThres = 0x40; 1048 } 1049 } else { 1050 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 1051 CurCCK_CCAThres = 0x83; 1052 else 1053 CurCCK_CCAThres = 0x40; 1054 } 1055 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); 1056} 1057 1058void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres) 1059{ 1060 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 1061 1062 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ 1063 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres); 1064 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; 1065 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; 1066} 1067 1068/* 3============================================================ */ 1069/* 3 BB Power Save */ 1070/* 3============================================================ */ 1071void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm) 1072{ 1073 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 1074 1075 pDM_PSTable->PreCCAState = CCA_MAX; 1076 pDM_PSTable->CurCCAState = CCA_MAX; 1077 pDM_PSTable->PreRFState = RF_MAX; 1078 pDM_PSTable->CurRFState = RF_MAX; 1079 pDM_PSTable->Rssi_val_min = 0; 1080 pDM_PSTable->initialize = 0; 1081} 1082 1083void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm) 1084{ 1085 if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A)) 1086 return; 1087 if (!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE)) 1088 return; 1089 if (!(pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE))) 1090 return; 1091 1092 /* 1 2.Power Saving for 92C */ 1093 if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->RFType == ODM_2T2R)) { 1094 odm_1R_CCA(pDM_Odm); 1095 } else { 1096 /* 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. */ 1097 /* 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. */ 1098 /* 1 3.Power Saving for 88C */ 1099 ODM_RF_Saving(pDM_Odm, false); 1100 } 1101} 1102 1103void odm_1R_CCA(struct odm_dm_struct *pDM_Odm) 1104{ 1105 struct adapter *adapter = pDM_Odm->Adapter; 1106 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 1107 1108 if (pDM_Odm->RSSI_Min != 0xFF) { 1109 if (pDM_PSTable->PreCCAState == CCA_2R) { 1110 if (pDM_Odm->RSSI_Min >= 35) 1111 pDM_PSTable->CurCCAState = CCA_1R; 1112 else 1113 pDM_PSTable->CurCCAState = CCA_2R; 1114 } else { 1115 if (pDM_Odm->RSSI_Min <= 30) 1116 pDM_PSTable->CurCCAState = CCA_2R; 1117 else 1118 pDM_PSTable->CurCCAState = CCA_1R; 1119 } 1120 } else { 1121 pDM_PSTable->CurCCAState = CCA_MAX; 1122 } 1123 1124 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) { 1125 if (pDM_PSTable->CurCCAState == CCA_1R) { 1126 if (pDM_Odm->RFType == ODM_2T2R) 1127 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x13); 1128 else 1129 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x23); 1130 } else { 1131 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x33); 1132 } 1133 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; 1134 } 1135} 1136 1137void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 1138{ 1139 struct adapter *adapter = pDM_Odm->Adapter; 1140 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 1141 u8 Rssi_Up_bound = 30; 1142 u8 Rssi_Low_bound = 25; 1143 1144 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */ 1145 Rssi_Up_bound = 50; 1146 Rssi_Low_bound = 45; 1147 } 1148 if (pDM_PSTable->initialize == 0) { 1149 pDM_PSTable->Reg874 = (PHY_QueryBBReg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14; 1150 pDM_PSTable->RegC70 = (PHY_QueryBBReg(adapter, 0xc70, bMaskDWord)&BIT3)>>3; 1151 pDM_PSTable->Reg85C = (PHY_QueryBBReg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; 1152 pDM_PSTable->RegA74 = (PHY_QueryBBReg(adapter, 0xa74, bMaskDWord)&0xF000)>>12; 1153 pDM_PSTable->initialize = 1; 1154 } 1155 1156 if (!bForceInNormal) { 1157 if (pDM_Odm->RSSI_Min != 0xFF) { 1158 if (pDM_PSTable->PreRFState == RF_Normal) { 1159 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound) 1160 pDM_PSTable->CurRFState = RF_Save; 1161 else 1162 pDM_PSTable->CurRFState = RF_Normal; 1163 } else { 1164 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound) 1165 pDM_PSTable->CurRFState = RF_Normal; 1166 else 1167 pDM_PSTable->CurRFState = RF_Save; 1168 } 1169 } else { 1170 pDM_PSTable->CurRFState = RF_MAX; 1171 } 1172 } else { 1173 pDM_PSTable->CurRFState = RF_Normal; 1174 } 1175 1176 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { 1177 if (pDM_PSTable->CurRFState == RF_Save) { 1178 /* <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. */ 1179 /* Suggested by SD3 Yu-Nan. 2011.01.20. */ 1180 if (pDM_Odm->SupportICType == ODM_RTL8723A) 1181 PHY_SetBBReg(adapter, 0x874 , BIT5, 0x1); /* Reg874[5]=1b'1 */ 1182 PHY_SetBBReg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ 1183 PHY_SetBBReg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ 1184 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ 1185 PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ 1186 PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ 1187 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ 1188 PHY_SetBBReg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ 1189 } else { 1190 PHY_SetBBReg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); 1191 PHY_SetBBReg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); 1192 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); 1193 PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); 1194 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); 1195 1196 if (pDM_Odm->SupportICType == ODM_RTL8723A) 1197 PHY_SetBBReg(adapter, 0x874, BIT5, 0x0); /* Reg874[5]=1b'0 */ 1198 } 1199 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; 1200 } 1201} 1202 1203/* 3============================================================ */ 1204/* 3 RATR MASK */ 1205/* 3============================================================ */ 1206/* 3============================================================ */ 1207/* 3 Rate Adaptive */ 1208/* 3============================================================ */ 1209 1210void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm) 1211{ 1212 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive; 1213 1214 pOdmRA->Type = DM_Type_ByDriver; 1215 if (pOdmRA->Type == DM_Type_ByDriver) 1216 pDM_Odm->bUseRAMask = true; 1217 else 1218 pDM_Odm->bUseRAMask = false; 1219 1220 pOdmRA->RATRState = DM_RATR_STA_INIT; 1221 pOdmRA->HighRSSIThresh = 50; 1222 pOdmRA->LowRSSIThresh = 20; 1223} 1224 1225u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level) 1226{ 1227 struct sta_info *pEntry; 1228 u32 rate_bitmap = 0x0fffffff; 1229 u8 WirelessMode; 1230 1231 pEntry = pDM_Odm->pODM_StaInfo[macid]; 1232 if (!IS_STA_VALID(pEntry)) 1233 return ra_mask; 1234 1235 WirelessMode = pEntry->wireless_mode; 1236 1237 switch (WirelessMode) { 1238 case ODM_WM_B: 1239 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ 1240 rate_bitmap = 0x0000000d; 1241 else 1242 rate_bitmap = 0x0000000f; 1243 break; 1244 case (ODM_WM_A|ODM_WM_G): 1245 if (rssi_level == DM_RATR_STA_HIGH) 1246 rate_bitmap = 0x00000f00; 1247 else 1248 rate_bitmap = 0x00000ff0; 1249 break; 1250 case (ODM_WM_B|ODM_WM_G): 1251 if (rssi_level == DM_RATR_STA_HIGH) 1252 rate_bitmap = 0x00000f00; 1253 else if (rssi_level == DM_RATR_STA_MIDDLE) 1254 rate_bitmap = 0x00000ff0; 1255 else 1256 rate_bitmap = 0x00000ff5; 1257 break; 1258 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1259 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1260 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { 1261 if (rssi_level == DM_RATR_STA_HIGH) { 1262 rate_bitmap = 0x000f0000; 1263 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1264 rate_bitmap = 0x000ff000; 1265 } else { 1266 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1267 rate_bitmap = 0x000ff015; 1268 else 1269 rate_bitmap = 0x000ff005; 1270 } 1271 } else { 1272 if (rssi_level == DM_RATR_STA_HIGH) { 1273 rate_bitmap = 0x0f8f0000; 1274 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1275 rate_bitmap = 0x0f8ff000; 1276 } else { 1277 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1278 rate_bitmap = 0x0f8ff015; 1279 else 1280 rate_bitmap = 0x0f8ff005; 1281 } 1282 } 1283 break; 1284 default: 1285 /* case WIRELESS_11_24N: */ 1286 /* case WIRELESS_11_5N: */ 1287 if (pDM_Odm->RFType == RF_1T2R) 1288 rate_bitmap = 0x000fffff; 1289 else 1290 rate_bitmap = 0x0fffffff; 1291 break; 1292 } 1293 1294 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1295 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", 1296 rssi_level, WirelessMode, rate_bitmap)); 1297 1298 return rate_bitmap; 1299} 1300 1301/*----------------------------------------------------------------------------- 1302 * Function: odm_RefreshRateAdaptiveMask() 1303 * 1304 * Overview: Update rate table mask according to rssi 1305 * 1306 * Input: NONE 1307 * 1308 * Output: NONE 1309 * 1310 * Return: NONE 1311 * 1312 * Revised History: 1313 * When Who Remark 1314 * 05/27/2009 hpfan Create Version 0. 1315 * 1316 *---------------------------------------------------------------------------*/ 1317void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm) 1318{ 1319 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) 1320 return; 1321 /* */ 1322 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1323 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1324 /* HW dynamic mechanism. */ 1325 /* */ 1326 switch (pDM_Odm->SupportPlatform) { 1327 case ODM_MP: 1328 odm_RefreshRateAdaptiveMaskMP(pDM_Odm); 1329 break; 1330 case ODM_CE: 1331 odm_RefreshRateAdaptiveMaskCE(pDM_Odm); 1332 break; 1333 case ODM_AP: 1334 case ODM_ADSL: 1335 odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm); 1336 break; 1337 } 1338} 1339 1340void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm) 1341{ 1342} 1343 1344void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm) 1345{ 1346 u8 i; 1347 struct adapter *pAdapter = pDM_Odm->Adapter; 1348 1349 if (pAdapter->bDriverStopped) { 1350 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); 1351 return; 1352 } 1353 1354 if (!pDM_Odm->bUseRAMask) { 1355 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); 1356 return; 1357 } 1358 1359 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1360 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; 1361 if (IS_STA_VALID(pstat)) { 1362 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) { 1363 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1364 ("RSSI:%d, RSSI_LEVEL:%d\n", 1365 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); 1366 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level); 1367 } 1368 } 1369 } 1370} 1371 1372void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm) 1373{ 1374} 1375 1376/* Return Value: bool */ 1377/* - true: RATRState is changed. */ 1378bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState) 1379{ 1380 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive; 1381 const u8 GoUpGap = 5; 1382 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh; 1383 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; 1384 u8 RATRState; 1385 1386 /* Threshold Adjustment: */ 1387 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ 1388 /* Here GoUpGap is added to solve the boundary's level alternation issue. */ 1389 switch (*pRATRState) { 1390 case DM_RATR_STA_INIT: 1391 case DM_RATR_STA_HIGH: 1392 break; 1393 case DM_RATR_STA_MIDDLE: 1394 HighRSSIThreshForRA += GoUpGap; 1395 break; 1396 case DM_RATR_STA_LOW: 1397 HighRSSIThreshForRA += GoUpGap; 1398 LowRSSIThreshForRA += GoUpGap; 1399 break; 1400 default: 1401 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState)); 1402 break; 1403 } 1404 1405 /* Decide RATRState by RSSI. */ 1406 if (RSSI > HighRSSIThreshForRA) 1407 RATRState = DM_RATR_STA_HIGH; 1408 else if (RSSI > LowRSSIThreshForRA) 1409 RATRState = DM_RATR_STA_MIDDLE; 1410 else 1411 RATRState = DM_RATR_STA_LOW; 1412 1413 if (*pRATRState != RATRState || bForceUpdate) { 1414 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState)); 1415 *pRATRState = RATRState; 1416 return true; 1417 } 1418 return false; 1419} 1420 1421/* 3============================================================ */ 1422/* 3 Dynamic Tx Power */ 1423/* 3============================================================ */ 1424 1425void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm) 1426{ 1427 struct adapter *Adapter = pDM_Odm->Adapter; 1428 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1429 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1430 pdmpriv->bDynamicTxPowerEnable = false; 1431 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; 1432 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; 1433} 1434 1435void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm) 1436{ 1437 /* For AP/ADSL use struct rtl8192cd_priv * */ 1438 /* For CE/NIC use struct adapter * */ 1439 1440 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1441 return; 1442 1443 /* 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */ 1444 if (!pDM_Odm->ExtPA) 1445 return; 1446 1447 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1448 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1449 /* HW dynamic mechanism. */ 1450 switch (pDM_Odm->SupportPlatform) { 1451 case ODM_MP: 1452 case ODM_CE: 1453 odm_DynamicTxPowerNIC(pDM_Odm); 1454 break; 1455 case ODM_AP: 1456 odm_DynamicTxPowerAP(pDM_Odm); 1457 break; 1458 case ODM_ADSL: 1459 break; 1460 } 1461} 1462 1463void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm) 1464{ 1465 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1466 return; 1467 1468 if (pDM_Odm->SupportICType == ODM_RTL8188E) { 1469 /* ??? */ 1470 /* This part need to be redefined. */ 1471 } 1472} 1473 1474void odm_DynamicTxPowerAP(struct odm_dm_struct *pDM_Odm) 1475{ 1476} 1477 1478/* 3============================================================ */ 1479/* 3 RSSI Monitor */ 1480/* 3============================================================ */ 1481 1482void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm) 1483{ 1484 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) 1485 return; 1486 1487 /* */ 1488 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1489 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1490 /* HW dynamic mechanism. */ 1491 /* */ 1492 switch (pDM_Odm->SupportPlatform) { 1493 case ODM_MP: 1494 odm_RSSIMonitorCheckMP(pDM_Odm); 1495 break; 1496 case ODM_CE: 1497 odm_RSSIMonitorCheckCE(pDM_Odm); 1498 break; 1499 case ODM_AP: 1500 odm_RSSIMonitorCheckAP(pDM_Odm); 1501 break; 1502 case ODM_ADSL: 1503 /* odm_DIGAP(pDM_Odm); */ 1504 break; 1505 } 1506 1507} /* odm_RSSIMonitorCheck */ 1508 1509void odm_RSSIMonitorCheckMP(struct odm_dm_struct *pDM_Odm) 1510{ 1511} 1512 1513static void FindMinimumRSSI(struct adapter *pAdapter) 1514{ 1515 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); 1516 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1517 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; 1518 1519 /* 1 1.Determine the minimum RSSI */ 1520 if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) && 1521 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) 1522 pdmpriv->MinUndecoratedPWDBForDM = 0; 1523 if (check_fwstate(pmlmepriv, _FW_LINKED) == true) /* Default port */ 1524 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1525 else /* associated entry pwdb */ 1526 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1527} 1528 1529void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm) 1530{ 1531 struct adapter *Adapter = pDM_Odm->Adapter; 1532 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1533 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1534 int i; 1535 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; 1536 u8 sta_cnt = 0; 1537 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ 1538 struct sta_info *psta; 1539 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 1540 1541 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) 1542 return; 1543 1544 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1545 psta = pDM_Odm->pODM_StaInfo[i]; 1546 if (IS_STA_VALID(psta) && 1547 (psta->state & WIFI_ASOC_STATE) && 1548 !_rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) && 1549 !_rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) { 1550 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) 1551 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1552 1553 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) 1554 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1555 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) 1556 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16)); 1557 } 1558 } 1559 1560 for (i = 0; i < sta_cnt; i++) { 1561 if (PWDB_rssi[i] != (0)) { 1562 if (pHalData->fw_ractrl) { 1563 /* Report every sta's RSSI to FW */ 1564 } else { 1565 ODM_RA_SetRSSI_8188E( 1566 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); 1567 } 1568 } 1569 } 1570 1571 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */ 1572 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; 1573 else 1574 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; 1575 1576 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */ 1577 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; 1578 else 1579 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; 1580 1581 FindMinimumRSSI(Adapter); 1582 ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); 1583} 1584 1585void odm_RSSIMonitorCheckAP(struct odm_dm_struct *pDM_Odm) 1586{ 1587} 1588 1589void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm) 1590{ 1591 ODM_InitializeTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer, 1592 (void *)odm_SwAntDivChkAntSwitchCallback, NULL, "SwAntennaSwitchTimer"); 1593} 1594 1595void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm) 1596{ 1597 ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer); 1598} 1599 1600/* 3============================================================ */ 1601/* 3 Tx Power Tracking */ 1602/* 3============================================================ */ 1603 1604void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm) 1605{ 1606 odm_TXPowerTrackingThermalMeterInit(pDM_Odm); 1607} 1608 1609void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm) 1610{ 1611 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; 1612 pDM_Odm->RFCalibrateInfo.TXPowercount = 0; 1613 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; 1614 if (*(pDM_Odm->mp_mode) != 1) 1615 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1616 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); 1617 1618 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1619} 1620 1621void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm) 1622{ 1623 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1624 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1625 /* HW dynamic mechanism. */ 1626 switch (pDM_Odm->SupportPlatform) { 1627 case ODM_MP: 1628 odm_TXPowerTrackingCheckMP(pDM_Odm); 1629 break; 1630 case ODM_CE: 1631 odm_TXPowerTrackingCheckCE(pDM_Odm); 1632 break; 1633 case ODM_AP: 1634 odm_TXPowerTrackingCheckAP(pDM_Odm); 1635 break; 1636 case ODM_ADSL: 1637 break; 1638 } 1639} 1640 1641void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 1642{ 1643 struct adapter *Adapter = pDM_Odm->Adapter; 1644 1645 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) 1646 return; 1647 1648 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ 1649 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); 1650 1651 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; 1652 return; 1653 } else { 1654 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); 1655 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; 1656 } 1657} 1658 1659void odm_TXPowerTrackingCheckMP(struct odm_dm_struct *pDM_Odm) 1660{ 1661} 1662 1663void odm_TXPowerTrackingCheckAP(struct odm_dm_struct *pDM_Odm) 1664{ 1665} 1666 1667/* antenna mapping info */ 1668/* 1: right-side antenna */ 1669/* 2/0: left-side antenna */ 1670/* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */ 1671/* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */ 1672/* We select left antenna as default antenna in initial process, modify it as needed */ 1673/* */ 1674 1675/* 3============================================================ */ 1676/* 3 SW Antenna Diversity */ 1677/* 3============================================================ */ 1678void odm_SwAntDivInit(struct odm_dm_struct *pDM_Odm) 1679{ 1680} 1681 1682void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID, struct odm_phy_status_info *pPhyInfo) 1683{ 1684} 1685 1686void odm_SwAntDivChkAntSwitch(struct odm_dm_struct *pDM_Odm, u8 Step) 1687{ 1688} 1689 1690void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm) 1691{ 1692} 1693 1694void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) 1695{ 1696} 1697 1698/* 3============================================================ */ 1699/* 3 SW Antenna Diversity */ 1700/* 3============================================================ */ 1701 1702void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) 1703{ 1704 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1705 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1706 return; 1707 } 1708 1709 if (pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D)) 1710 ; 1711 else if (pDM_Odm->SupportICType == ODM_RTL8188E) 1712 ODM_AntennaDiversityInit_88E(pDM_Odm); 1713} 1714 1715void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate) 1716{ 1717 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; 1718 1719 if (pDM_SWAT_Table->antsel == 1) { 1720 if (isCCKrate) { 1721 pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++; 1722 } else { 1723 pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++; 1724 pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll; 1725 } 1726 } else { 1727 if (isCCKrate) { 1728 pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++; 1729 } else { 1730 pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++; 1731 pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll; 1732 } 1733 } 1734} 1735 1736void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) 1737{ 1738 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1739 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1740 return; 1741 } 1742 1743 if (pDM_Odm->SupportICType == ODM_RTL8188E) 1744 ODM_AntennaDiversity_88E(pDM_Odm); 1745} 1746 1747/* EDCA Turbo */ 1748void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) 1749{ 1750 struct adapter *Adapter = pDM_Odm->Adapter; 1751 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1752 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; 1753 Adapter->recvpriv.bIsAnyNonBEPkts = false; 1754 1755 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM))); 1756 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM))); 1757 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM))); 1758 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM))); 1759} /* ODM_InitEdcaTurbo */ 1760 1761void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm) 1762{ 1763 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1764 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1765 /* HW dynamic mechanism. */ 1766 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n")); 1767 1768 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)) 1769 return; 1770 1771 switch (pDM_Odm->SupportPlatform) { 1772 case ODM_MP: 1773 break; 1774 case ODM_CE: 1775 odm_EdcaTurboCheckCE(pDM_Odm); 1776 break; 1777 case ODM_AP: 1778 case ODM_ADSL: 1779 break; 1780 } 1781 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n")); 1782} /* odm_CheckEdcaTurbo */ 1783 1784void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm) 1785{ 1786 struct adapter *Adapter = pDM_Odm->Adapter; 1787 u32 trafficIndex; 1788 u32 edca_param; 1789 u64 cur_tx_bytes = 0; 1790 u64 cur_rx_bytes = 0; 1791 u8 bbtchange = false; 1792 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1793 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); 1794 struct recv_priv *precvpriv = &(Adapter->recvpriv); 1795 struct registry_priv *pregpriv = &Adapter->registrypriv; 1796 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); 1797 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 1798 1799 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */ 1800 goto dm_CheckEdcaTurbo_EXIT; 1801 1802 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) 1803 goto dm_CheckEdcaTurbo_EXIT; 1804 1805 /* Check if the status needs to be changed. */ 1806 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) { 1807 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; 1808 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; 1809 1810 /* traffic, TX or RX */ 1811 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) || 1812 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { 1813 if (cur_tx_bytes > (cur_rx_bytes << 2)) { 1814 /* Uplink TP is present. */ 1815 trafficIndex = UP_LINK; 1816 } else { 1817 /* Balance TP is present. */ 1818 trafficIndex = DOWN_LINK; 1819 } 1820 } else { 1821 if (cur_rx_bytes > (cur_tx_bytes << 2)) { 1822 /* Downlink TP is present. */ 1823 trafficIndex = DOWN_LINK; 1824 } else { 1825 /* Balance TP is present. */ 1826 trafficIndex = UP_LINK; 1827 } 1828 } 1829 1830 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) { 1831 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) 1832 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; 1833 else 1834 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; 1835 1836 rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); 1837 1838 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; 1839 } 1840 1841 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; 1842 } else { 1843 /* Turn Off EDCA turbo here. */ 1844 /* Restore original EDCA according to the declaration of AP. */ 1845 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { 1846 rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); 1847 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1848 } 1849 } 1850 1851dm_CheckEdcaTurbo_EXIT: 1852 /* Set variables for next time. */ 1853 precvpriv->bIsAnyNonBEPkts = false; 1854 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; 1855 precvpriv->last_rx_bytes = precvpriv->rx_bytes; 1856} 1857 1858/* need to ODM CE Platform */ 1859/* move to here for ANT detection mechanism using */ 1860 1861u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point, u8 initial_gain_psd) 1862{ 1863 struct adapter *adapter = pDM_Odm->Adapter; 1864 u32 psd_report; 1865 1866 /* Set DCO frequency index, offset=(40MHz/SamplePts)*point */ 1867 PHY_SetBBReg(adapter, 0x808, 0x3FF, point); 1868 1869 /* Start PSD calculation, Reg808[22]=0->1 */ 1870 PHY_SetBBReg(adapter, 0x808, BIT22, 1); 1871 /* Need to wait for HW PSD report */ 1872 udelay(30); 1873 PHY_SetBBReg(adapter, 0x808, BIT22, 0); 1874 /* Read PSD report, Reg8B4[15:0] */ 1875 psd_report = PHY_QueryBBReg(adapter, 0x8B4, bMaskDWord) & 0x0000FFFF; 1876 1877 psd_report = (u32) (ConvertTo_dB(psd_report))+(u32)(initial_gain_psd-0x1c); 1878 1879 return psd_report; 1880} 1881 1882u32 ConvertTo_dB(u32 Value) 1883{ 1884 u8 i; 1885 u8 j; 1886 u32 dB; 1887 1888 Value = Value & 0xFFFF; 1889 for (i = 0; i < 8; i++) { 1890 if (Value <= dB_Invert_Table[i][11]) 1891 break; 1892 } 1893 1894 if (i >= 8) 1895 return 96; /* maximum 96 dB */ 1896 1897 for (j = 0; j < 12; j++) { 1898 if (Value <= dB_Invert_Table[i][j]) 1899 break; 1900 } 1901 1902 dB = i*12 + j + 1; 1903 1904 return dB; 1905} 1906 1907/* 2011/09/22 MH Add for 92D global spin lock utilization. */ 1908void odm_GlobalAdapterCheck(void) 1909{ 1910} /* odm_GlobalAdapterCheck */ 1911 1912/* Description: */ 1913/* Set Single/Dual Antenna default setting for products that do not do detection in advance. */ 1914/* Added by Joseph, 2012.03.22 */ 1915void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm) 1916{ 1917 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; 1918 1919 pDM_SWAT_Table->ANTA_ON = true; 1920 pDM_SWAT_Table->ANTB_ON = true; 1921} 1922 1923 1924/* 2 8723A ANT DETECT */ 1925 1926static void odm_PHY_SaveAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegisterNum) 1927{ 1928 struct adapter *adapter = pDM_Odm->Adapter; 1929 u32 i; 1930 1931 /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */ 1932 for (i = 0; i < RegisterNum; i++) 1933 AFEBackup[i] = PHY_QueryBBReg(adapter, AFEReg[i], bMaskDWord); 1934} 1935 1936static void odm_PHY_ReloadAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegiesterNum) 1937{ 1938 struct adapter *adapter = pDM_Odm->Adapter; 1939 u32 i; 1940 1941 for (i = 0; i < RegiesterNum; i++) 1942 PHY_SetBBReg(adapter, AFEReg[i], bMaskDWord, AFEBackup[i]); 1943} 1944 1945/* 2 8723A ANT DETECT */ 1946/* Description: */ 1947/* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */ 1948/* This function is cooperated with BB team Neil. */ 1949bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode) 1950{ 1951 struct adapter *adapter = pDM_Odm->Adapter; 1952 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; 1953 u32 CurrentChannel, RfLoopReg; 1954 u8 n; 1955 u32 Reg88c, Regc08, Reg874, Regc50; 1956 u8 initial_gain = 0x5a; 1957 u32 PSD_report_tmp; 1958 u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0; 1959 bool bResult = true; 1960 u32 AFE_Backup[16]; 1961 u32 AFE_REG_8723A[16] = { 1962 rRx_Wait_CCA, rTx_CCK_RFON, 1963 rTx_CCK_BBON, rTx_OFDM_RFON, 1964 rTx_OFDM_BBON, rTx_To_Rx, 1965 rTx_To_Tx, rRx_CCK, 1966 rRx_OFDM, rRx_Wait_RIFS, 1967 rRx_TO_Rx, rStandby, 1968 rSleep, rPMPD_ANAEN, 1969 rFPGA0_XCD_SwitchControl, rBlue_Tooth}; 1970 1971 if (!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))) 1972 return bResult; 1973 1974 if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) 1975 return bResult; 1976 1977 if (pDM_Odm->SupportICType == ODM_RTL8192C) { 1978 /* Which path in ADC/DAC is turnned on for PSD: both I/Q */ 1979 PHY_SetBBReg(adapter, 0x808, BIT10|BIT11, 0x3); 1980 /* Ageraged number: 8 */ 1981 PHY_SetBBReg(adapter, 0x808, BIT12|BIT13, 0x1); 1982 /* pts = 128; */ 1983 PHY_SetBBReg(adapter, 0x808, BIT14|BIT15, 0x0); 1984 } 1985 1986 /* 1 Backup Current RF/BB Settings */ 1987 1988 CurrentChannel = PHY_QueryRFReg(adapter, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); 1989 RfLoopReg = PHY_QueryRFReg(adapter, RF_PATH_A, 0x00, bRFRegOffsetMask); 1990 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); /* change to Antenna A */ 1991 /* Step 1: USE IQK to transmitter single tone */ 1992 1993 udelay(10); 1994 1995 /* Store A Path Register 88c, c08, 874, c50 */ 1996 Reg88c = PHY_QueryBBReg(adapter, rFPGA0_AnalogParameter4, bMaskDWord); 1997 Regc08 = PHY_QueryBBReg(adapter, rOFDM0_TRMuxPar, bMaskDWord); 1998 Reg874 = PHY_QueryBBReg(adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord); 1999 Regc50 = PHY_QueryBBReg(adapter, rOFDM0_XAAGCCore1, bMaskDWord); 2000 2001 /* Store AFE Registers */ 2002 odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); 2003 2004 /* Set PSD 128 pts */ 2005 PHY_SetBBReg(adapter, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); /* 128 pts */ 2006 2007 /* To SET CH1 to do */ 2008 PHY_SetRFReg(adapter, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); /* Channel 1 */ 2009 2010 /* AFE all on step */ 2011 PHY_SetBBReg(adapter, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4); 2012 PHY_SetBBReg(adapter, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4); 2013 PHY_SetBBReg(adapter, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4); 2014 PHY_SetBBReg(adapter, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4); 2015 PHY_SetBBReg(adapter, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4); 2016 PHY_SetBBReg(adapter, rTx_To_Rx, bMaskDWord, 0x6FDB25A4); 2017 PHY_SetBBReg(adapter, rTx_To_Tx, bMaskDWord, 0x6FDB25A4); 2018 PHY_SetBBReg(adapter, rRx_CCK, bMaskDWord, 0x6FDB25A4); 2019 PHY_SetBBReg(adapter, rRx_OFDM, bMaskDWord, 0x6FDB25A4); 2020 PHY_SetBBReg(adapter, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4); 2021 PHY_SetBBReg(adapter, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4); 2022 PHY_SetBBReg(adapter, rStandby, bMaskDWord, 0x6FDB25A4); 2023 PHY_SetBBReg(adapter, rSleep, bMaskDWord, 0x6FDB25A4); 2024 PHY_SetBBReg(adapter, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4); 2025 PHY_SetBBReg(adapter, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4); 2026 PHY_SetBBReg(adapter, rBlue_Tooth, bMaskDWord, 0x6FDB25A4); 2027 2028 /* 3 wire Disable */ 2029 PHY_SetBBReg(adapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0); 2030 2031 /* BB IQK Setting */ 2032 PHY_SetBBReg(adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4); 2033 PHY_SetBBReg(adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000); 2034 2035 /* IQK setting tone@ 4.34Mhz */ 2036 PHY_SetBBReg(adapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C); 2037 PHY_SetBBReg(adapter, rTx_IQK, bMaskDWord, 0x01007c00); 2038 2039 2040 /* Page B init */ 2041 PHY_SetBBReg(adapter, rConfig_AntA, bMaskDWord, 0x00080000); 2042 PHY_SetBBReg(adapter, rConfig_AntA, bMaskDWord, 0x0f600000); 2043 PHY_SetBBReg(adapter, rRx_IQK, bMaskDWord, 0x01004800); 2044 PHY_SetBBReg(adapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); 2045 PHY_SetBBReg(adapter, rTx_IQK_PI_A, bMaskDWord, 0x82150008); 2046 PHY_SetBBReg(adapter, rRx_IQK_PI_A, bMaskDWord, 0x28150008); 2047 PHY_SetBBReg(adapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0); 2048 2049 /* RF loop Setting */ 2050 PHY_SetRFReg(adapter, RF_PATH_A, 0x0, 0xFFFFF, 0x50008); 2051 2052 /* IQK Single tone start */ 2053 PHY_SetBBReg(adapter, rFPGA0_IQK, bMaskDWord, 0x80800000); 2054 PHY_SetBBReg(adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 2055 udelay(1000); 2056 PSD_report_tmp = 0x0; 2057 2058 for (n = 0; n < 2; n++) { 2059 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); 2060 if (PSD_report_tmp > AntA_report) 2061 AntA_report = PSD_report_tmp; 2062 } 2063 2064 PSD_report_tmp = 0x0; 2065 2066 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */ 2067 udelay(10); 2068 2069 2070 for (n = 0; n < 2; n++) { 2071 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); 2072 if (PSD_report_tmp > AntB_report) 2073 AntB_report = PSD_report_tmp; 2074 } 2075 2076 /* change to open case */ 2077 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0); /* change to Ant A and B all open case */ 2078 udelay(10); 2079 2080 for (n = 0; n < 2; n++) { 2081 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); 2082 if (PSD_report_tmp > AntO_report) 2083 AntO_report = PSD_report_tmp; 2084 } 2085 2086 /* Close IQK Single Tone function */ 2087 PHY_SetBBReg(adapter, rFPGA0_IQK, bMaskDWord, 0x00000000); 2088 PSD_report_tmp = 0x0; 2089 2090 /* 1 Return to antanna A */ 2091 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); 2092 PHY_SetBBReg(adapter, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c); 2093 PHY_SetBBReg(adapter, rOFDM0_TRMuxPar, bMaskDWord, Regc08); 2094 PHY_SetBBReg(adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874); 2095 PHY_SetBBReg(adapter, rOFDM0_XAAGCCore1, 0x7F, 0x40); 2096 PHY_SetBBReg(adapter, rOFDM0_XAAGCCore1, bMaskDWord, Regc50); 2097 PHY_SetRFReg(adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel); 2098 PHY_SetRFReg(adapter, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg); 2099 2100 /* Reload AFE Registers */ 2101 odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); 2102 2103 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report)); 2104 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report)); 2105 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d\n", 2416, AntO_report)); 2106 2107 2108 if (pDM_Odm->SupportICType == ODM_RTL8723A) { 2109 /* 2 Test Ant B based on Ant A is ON */ 2110 if (mode == ANTTESTB) { 2111 if (AntA_report >= 100) { 2112 if (AntB_report > (AntA_report+1)) { 2113 pDM_SWAT_Table->ANTB_ON = false; 2114 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n")); 2115 } else { 2116 pDM_SWAT_Table->ANTB_ON = true; 2117 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n")); 2118 } 2119 } else { 2120 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); 2121 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */ 2122 bResult = false; 2123 } 2124 } else if (mode == ANTTESTALL) { 2125 /* 2 Test Ant A and B based on DPDT Open */ 2126 if ((AntO_report >= 100)&(AntO_report < 118)) { 2127 if (AntA_report > (AntO_report+1)) { 2128 pDM_SWAT_Table->ANTA_ON = false; 2129 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF")); 2130 } else { 2131 pDM_SWAT_Table->ANTA_ON = true; 2132 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON")); 2133 } 2134 2135 if (AntB_report > (AntO_report+2)) { 2136 pDM_SWAT_Table->ANTB_ON = false; 2137 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF")); 2138 } else { 2139 pDM_SWAT_Table->ANTB_ON = true; 2140 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON")); 2141 } 2142 } 2143 } 2144 } else if (pDM_Odm->SupportICType == ODM_RTL8192C) { 2145 if (AntA_report >= 100) { 2146 if (AntB_report > (AntA_report+2)) { 2147 pDM_SWAT_Table->ANTA_ON = false; 2148 pDM_SWAT_Table->ANTB_ON = true; 2149 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); 2150 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n")); 2151 } else if (AntA_report > (AntB_report+2)) { 2152 pDM_SWAT_Table->ANTA_ON = true; 2153 pDM_SWAT_Table->ANTB_ON = false; 2154 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); 2155 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n")); 2156 } else { 2157 pDM_SWAT_Table->ANTA_ON = true; 2158 pDM_SWAT_Table->ANTB_ON = true; 2159 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 2160 ("ODM_SingleDualAntennaDetection(): Dual Antenna\n")); 2161 } 2162 } else { 2163 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); 2164 pDM_SWAT_Table->ANTA_ON = true; /* Set Antenna A on as default */ 2165 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */ 2166 bResult = false; 2167 } 2168 } 2169 return bResult; 2170} 2171 2172/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ 2173void odm_dtc(struct odm_dm_struct *pDM_Odm) 2174{ 2175} 2176