odm.c revision 368c75b98bdfdfad54e7f165016819ef344e3587
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21/* include files */ 22 23#include "odm_precomp.h" 24#include "phy.h" 25 26u32 GlobalDebugLevel; 27static const u16 dB_Invert_Table[8][12] = { 28 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, 29 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, 30 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63}, 31 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251}, 32 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000}, 33 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, 34 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849}, 35 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} 36}; 37 38/* avoid to warn in FreeBSD ==> To DO modify */ 39static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { 40 /* UL DL */ 41 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ 42 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ 43 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ 44 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ 45 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ 46 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ 47 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ 48 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ 49 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ 50 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ 51}; 52 53/* Global var */ 54u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { 55 0x7f8001fe, /* 0, +6.0dB */ 56 0x788001e2, /* 1, +5.5dB */ 57 0x71c001c7, /* 2, +5.0dB */ 58 0x6b8001ae, /* 3, +4.5dB */ 59 0x65400195, /* 4, +4.0dB */ 60 0x5fc0017f, /* 5, +3.5dB */ 61 0x5a400169, /* 6, +3.0dB */ 62 0x55400155, /* 7, +2.5dB */ 63 0x50800142, /* 8, +2.0dB */ 64 0x4c000130, /* 9, +1.5dB */ 65 0x47c0011f, /* 10, +1.0dB */ 66 0x43c0010f, /* 11, +0.5dB */ 67 0x40000100, /* 12, +0dB */ 68 0x3c8000f2, /* 13, -0.5dB */ 69 0x390000e4, /* 14, -1.0dB */ 70 0x35c000d7, /* 15, -1.5dB */ 71 0x32c000cb, /* 16, -2.0dB */ 72 0x300000c0, /* 17, -2.5dB */ 73 0x2d4000b5, /* 18, -3.0dB */ 74 0x2ac000ab, /* 19, -3.5dB */ 75 0x288000a2, /* 20, -4.0dB */ 76 0x26000098, /* 21, -4.5dB */ 77 0x24000090, /* 22, -5.0dB */ 78 0x22000088, /* 23, -5.5dB */ 79 0x20000080, /* 24, -6.0dB */ 80 0x1e400079, /* 25, -6.5dB */ 81 0x1c800072, /* 26, -7.0dB */ 82 0x1b00006c, /* 27. -7.5dB */ 83 0x19800066, /* 28, -8.0dB */ 84 0x18000060, /* 29, -8.5dB */ 85 0x16c0005b, /* 30, -9.0dB */ 86 0x15800056, /* 31, -9.5dB */ 87 0x14400051, /* 32, -10.0dB */ 88 0x1300004c, /* 33, -10.5dB */ 89 0x12000048, /* 34, -11.0dB */ 90 0x11000044, /* 35, -11.5dB */ 91 0x10000040, /* 36, -12.0dB */ 92 0x0f00003c,/* 37, -12.5dB */ 93 0x0e400039,/* 38, -13.0dB */ 94 0x0d800036,/* 39, -13.5dB */ 95 0x0cc00033,/* 40, -14.0dB */ 96 0x0c000030,/* 41, -14.5dB */ 97 0x0b40002d,/* 42, -15.0dB */ 98}; 99 100u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { 101 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 102 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 103 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 104 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 105 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 106 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 107 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 108 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 109 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 110 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 111 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 112 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 113 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 114 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 115 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 116 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 117 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 118 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 119 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 120 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 121 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ 122 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ 123 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ 124 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ 125 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ 126 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ 127 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ 128 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ 129 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ 130 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ 131 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ 132 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ 133 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ 134}; 135 136u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { 137 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 138 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 139 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 140 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 141 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 142 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 143 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 144 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 145 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 146 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 147 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 148 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 149 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 150 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 151 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 152 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 153 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 154 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 155 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 156 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 157 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ 158 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ 159 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ 160 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ 161 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ 162 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ 163 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ 164 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ 165 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ 166 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ 167 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ 168 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ 169 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ 170}; 171 172 173#define RxDefaultAnt1 0x65a9 174#define RxDefaultAnt2 0x569a 175 176void ODM_InitDebugSetting(struct odm_dm_struct *pDM_Odm) 177{ 178 pDM_Odm->DebugLevel = ODM_DBG_TRACE; 179 180 pDM_Odm->DebugComponents = 0; 181} 182 183/* 3 Export Interface */ 184 185/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ 186void ODM_DMInit(struct odm_dm_struct *pDM_Odm) 187{ 188 /* 2012.05.03 Luke: For all IC series */ 189 odm_CommonInfoSelfInit(pDM_Odm); 190 odm_CmnInfoInit_Debug(pDM_Odm); 191 odm_DIGInit(pDM_Odm); 192 odm_RateAdaptiveMaskInit(pDM_Odm); 193 194 odm_DynamicTxPowerInit(pDM_Odm); 195 odm_TXPowerTrackingInit(pDM_Odm); 196 ODM_EdcaTurboInit(pDM_Odm); 197 ODM_RAInfo_Init_all(pDM_Odm); 198 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 199 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 200 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 201 odm_InitHybridAntDiv(pDM_Odm); 202} 203 204/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ 205/* You can not add any dummy function here, be care, you can only use DM structure */ 206/* to perform any new ODM_DM. */ 207void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) 208{ 209 /* 2012.05.03 Luke: For all IC series */ 210 odm_CmnInfoHook_Debug(pDM_Odm); 211 odm_CmnInfoUpdate_Debug(pDM_Odm); 212 odm_CommonInfoSelfUpdate(pDM_Odm); 213 odm_FalseAlarmCounterStatistics(pDM_Odm); 214 odm_RSSIMonitorCheck(pDM_Odm); 215 216 /* Fix Leave LPS issue */ 217 odm_DIG(pDM_Odm); 218 odm_CCKPacketDetectionThresh(pDM_Odm); 219 220 if (*(pDM_Odm->pbPowerSaving)) 221 return; 222 223 odm_RefreshRateAdaptiveMask(pDM_Odm); 224 225 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 226 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 227 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 228 odm_HwAntDiv(pDM_Odm); 229 230 ODM_TXPowerTrackingCheck(pDM_Odm); 231 odm_EdcaTurboCheck(pDM_Odm); 232} 233 234/* Init /.. Fixed HW value. Only init time. */ 235void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value) 236{ 237 /* This section is used for init value */ 238 switch (CmnInfo) { 239 /* Fixed ODM value. */ 240 case ODM_CMNINFO_ABILITY: 241 pDM_Odm->SupportAbility = (u32)Value; 242 break; 243 case ODM_CMNINFO_PLATFORM: 244 pDM_Odm->SupportPlatform = (u8)Value; 245 break; 246 case ODM_CMNINFO_INTERFACE: 247 pDM_Odm->SupportInterface = (u8)Value; 248 break; 249 case ODM_CMNINFO_MP_TEST_CHIP: 250 pDM_Odm->bIsMPChip = (u8)Value; 251 break; 252 case ODM_CMNINFO_IC_TYPE: 253 pDM_Odm->SupportICType = Value; 254 break; 255 case ODM_CMNINFO_CUT_VER: 256 pDM_Odm->CutVersion = (u8)Value; 257 break; 258 case ODM_CMNINFO_FAB_VER: 259 pDM_Odm->FabVersion = (u8)Value; 260 break; 261 case ODM_CMNINFO_RF_TYPE: 262 pDM_Odm->RFType = (u8)Value; 263 break; 264 case ODM_CMNINFO_RF_ANTENNA_TYPE: 265 pDM_Odm->AntDivType = (u8)Value; 266 break; 267 case ODM_CMNINFO_BOARD_TYPE: 268 pDM_Odm->BoardType = (u8)Value; 269 break; 270 case ODM_CMNINFO_EXT_LNA: 271 pDM_Odm->ExtLNA = (u8)Value; 272 break; 273 case ODM_CMNINFO_EXT_PA: 274 pDM_Odm->ExtPA = (u8)Value; 275 break; 276 case ODM_CMNINFO_EXT_TRSW: 277 pDM_Odm->ExtTRSW = (u8)Value; 278 break; 279 case ODM_CMNINFO_PATCH_ID: 280 pDM_Odm->PatchID = (u8)Value; 281 break; 282 case ODM_CMNINFO_BINHCT_TEST: 283 pDM_Odm->bInHctTest = (bool)Value; 284 break; 285 case ODM_CMNINFO_BWIFI_TEST: 286 pDM_Odm->bWIFITest = (bool)Value; 287 break; 288 case ODM_CMNINFO_SMART_CONCURRENT: 289 pDM_Odm->bDualMacSmartConcurrent = (bool)Value; 290 break; 291 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 292 default: 293 /* do nothing */ 294 break; 295 } 296 297 /* Tx power tracking BB swing table. */ 298 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ 299 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */ 300 pDM_Odm->BbSwingIdxOfdmCurrent = 12; 301 pDM_Odm->BbSwingFlagOfdm = false; 302} 303 304void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue) 305{ 306 /* */ 307 /* Hook call by reference pointer. */ 308 /* */ 309 switch (CmnInfo) { 310 /* Dynamic call by reference pointer. */ 311 case ODM_CMNINFO_MAC_PHY_MODE: 312 pDM_Odm->pMacPhyMode = (u8 *)pValue; 313 break; 314 case ODM_CMNINFO_TX_UNI: 315 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue; 316 break; 317 case ODM_CMNINFO_RX_UNI: 318 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue; 319 break; 320 case ODM_CMNINFO_WM_MODE: 321 pDM_Odm->pWirelessMode = (u8 *)pValue; 322 break; 323 case ODM_CMNINFO_BAND: 324 pDM_Odm->pBandType = (u8 *)pValue; 325 break; 326 case ODM_CMNINFO_SEC_CHNL_OFFSET: 327 pDM_Odm->pSecChOffset = (u8 *)pValue; 328 break; 329 case ODM_CMNINFO_SEC_MODE: 330 pDM_Odm->pSecurity = (u8 *)pValue; 331 break; 332 case ODM_CMNINFO_BW: 333 pDM_Odm->pBandWidth = (u8 *)pValue; 334 break; 335 case ODM_CMNINFO_CHNL: 336 pDM_Odm->pChannel = (u8 *)pValue; 337 break; 338 case ODM_CMNINFO_DMSP_GET_VALUE: 339 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue; 340 break; 341 case ODM_CMNINFO_BUDDY_ADAPTOR: 342 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue; 343 break; 344 case ODM_CMNINFO_DMSP_IS_MASTER: 345 pDM_Odm->pbMasterOfDMSP = (bool *)pValue; 346 break; 347 case ODM_CMNINFO_SCAN: 348 pDM_Odm->pbScanInProcess = (bool *)pValue; 349 break; 350 case ODM_CMNINFO_POWER_SAVING: 351 pDM_Odm->pbPowerSaving = (bool *)pValue; 352 break; 353 case ODM_CMNINFO_ONE_PATH_CCA: 354 pDM_Odm->pOnePathCCA = (u8 *)pValue; 355 break; 356 case ODM_CMNINFO_DRV_STOP: 357 pDM_Odm->pbDriverStopped = (bool *)pValue; 358 break; 359 case ODM_CMNINFO_PNP_IN: 360 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue; 361 break; 362 case ODM_CMNINFO_INIT_ON: 363 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue; 364 break; 365 case ODM_CMNINFO_ANT_TEST: 366 pDM_Odm->pAntennaTest = (u8 *)pValue; 367 break; 368 case ODM_CMNINFO_NET_CLOSED: 369 pDM_Odm->pbNet_closed = (bool *)pValue; 370 break; 371 case ODM_CMNINFO_MP_MODE: 372 pDM_Odm->mp_mode = (u8 *)pValue; 373 break; 374 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 375 default: 376 /* do nothing */ 377 break; 378 } 379} 380 381void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue) 382{ 383 /* Hook call by reference pointer. */ 384 switch (CmnInfo) { 385 /* Dynamic call by reference pointer. */ 386 case ODM_CMNINFO_STA_STATUS: 387 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue; 388 break; 389 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 390 default: 391 /* do nothing */ 392 break; 393 } 394} 395 396/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ 397void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value) 398{ 399 /* */ 400 /* This init variable may be changed in run time. */ 401 /* */ 402 switch (CmnInfo) { 403 case ODM_CMNINFO_ABILITY: 404 pDM_Odm->SupportAbility = (u32)Value; 405 break; 406 case ODM_CMNINFO_RF_TYPE: 407 pDM_Odm->RFType = (u8)Value; 408 break; 409 case ODM_CMNINFO_WIFI_DIRECT: 410 pDM_Odm->bWIFI_Direct = (bool)Value; 411 break; 412 case ODM_CMNINFO_WIFI_DISPLAY: 413 pDM_Odm->bWIFI_Display = (bool)Value; 414 break; 415 case ODM_CMNINFO_LINK: 416 pDM_Odm->bLinked = (bool)Value; 417 break; 418 case ODM_CMNINFO_RSSI_MIN: 419 pDM_Odm->RSSI_Min = (u8)Value; 420 break; 421 case ODM_CMNINFO_DBG_COMP: 422 pDM_Odm->DebugComponents = Value; 423 break; 424 case ODM_CMNINFO_DBG_LEVEL: 425 pDM_Odm->DebugLevel = (u32)Value; 426 break; 427 case ODM_CMNINFO_RA_THRESHOLD_HIGH: 428 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value; 429 break; 430 case ODM_CMNINFO_RA_THRESHOLD_LOW: 431 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value; 432 break; 433 } 434} 435 436void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) 437{ 438 struct adapter *adapter = pDM_Odm->Adapter; 439 440 pDM_Odm->bCckHighPower = (bool) phy_query_bb_reg(adapter, 0x824, BIT9); 441 pDM_Odm->RFPathRxEnable = (u8) phy_query_bb_reg(adapter, 0xc04, 0x0F); 442 443 ODM_InitDebugSetting(pDM_Odm); 444} 445 446void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) 447{ 448 u8 EntryCnt = 0; 449 u8 i; 450 struct sta_info *pEntry; 451 452 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { 453 if (*(pDM_Odm->pSecChOffset) == 1) 454 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; 455 else if (*(pDM_Odm->pSecChOffset) == 2) 456 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; 457 } else { 458 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); 459 } 460 461 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 462 pEntry = pDM_Odm->pODM_StaInfo[i]; 463 if (IS_STA_VALID(pEntry)) 464 EntryCnt++; 465 } 466 if (EntryCnt == 1) 467 pDM_Odm->bOneEntryOnly = true; 468 else 469 pDM_Odm->bOneEntryOnly = false; 470} 471 472void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm) 473{ 474 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); 475 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform)); 476 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility)); 477 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface)); 478 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType)); 479 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion)); 480 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n", pDM_Odm->FabVersion)); 481 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n", pDM_Odm->RFType)); 482 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType)); 483 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA)); 484 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA)); 485 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW)); 486 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID)); 487 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest)); 488 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest)); 489 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent)); 490} 491 492void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm) 493{ 494 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); 495 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast))); 496 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast))); 497 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode))); 498 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset))); 499 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity))); 500 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth))); 501 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel))); 502 503 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess))); 504 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving))); 505} 506 507void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm) 508{ 509 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); 510 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct)); 511 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display)); 512 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked)); 513 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min)); 514} 515 516void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) 517{ 518 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 519 struct adapter *adapter = pDM_Odm->Adapter; 520 521 if (pDM_DigTable->CurIGValue != CurrentIGI) { 522 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI); 523 pDM_DigTable->CurIGValue = CurrentIGI; 524 } 525} 526 527void odm_DIGInit(struct odm_dm_struct *pDM_Odm) 528{ 529 struct adapter *adapter = pDM_Odm->Adapter; 530 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 531 532 pDM_DigTable->CurIGValue = (u8) phy_query_bb_reg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N); 533 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; 534 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; 535 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW; 536 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH; 537 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) { 538 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 539 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 540 } else { 541 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 542 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 543 } 544 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; 545 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; 546 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; 547 pDM_DigTable->PreCCK_CCAThres = 0xFF; 548 pDM_DigTable->CurCCK_CCAThres = 0x83; 549 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; 550 pDM_DigTable->LargeFAHit = 0; 551 pDM_DigTable->Recover_cnt = 0; 552 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; 553 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; 554 pDM_DigTable->bMediaConnect_0 = false; 555 pDM_DigTable->bMediaConnect_1 = false; 556 557 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */ 558 pDM_Odm->bDMInitialGainEnable = true; 559} 560 561void odm_DIG(struct odm_dm_struct *pDM_Odm) 562{ 563 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 564 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 565 u8 DIG_Dynamic_MIN; 566 u8 DIG_MaxOfMin; 567 bool FirstConnect, FirstDisConnect; 568 u8 dm_dig_max, dm_dig_min; 569 u8 CurrentIGI = pDM_DigTable->CurIGValue; 570 571 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); 572 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) { 573 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 574 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); 575 return; 576 } 577 578 if (*(pDM_Odm->pbScanInProcess)) { 579 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n")); 580 return; 581 } 582 583 /* add by Neil Chen to avoid PSD is processing */ 584 if (pDM_Odm->bDMInitialGainEnable == false) { 585 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n")); 586 return; 587 } 588 589 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 590 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 591 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 592 593 /* 1 Boundary Decision */ 594 dm_dig_max = DM_DIG_MAX_NIC; 595 dm_dig_min = DM_DIG_MIN_NIC; 596 DIG_MaxOfMin = DM_DIG_MAX_AP; 597 598 if (pDM_Odm->bLinked) { 599 /* 2 Modify DIG upper bound */ 600 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) 601 pDM_DigTable->rx_gain_range_max = dm_dig_max; 602 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min) 603 pDM_DigTable->rx_gain_range_max = dm_dig_min; 604 else 605 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; 606 /* 2 Modify DIG lower bound */ 607 if (pDM_Odm->bOneEntryOnly) { 608 if (pDM_Odm->RSSI_Min < dm_dig_min) 609 DIG_Dynamic_MIN = dm_dig_min; 610 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) 611 DIG_Dynamic_MIN = DIG_MaxOfMin; 612 else 613 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; 614 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 615 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n", 616 DIG_Dynamic_MIN)); 617 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 618 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n", 619 pDM_Odm->RSSI_Min)); 620 } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) { 621 /* 1 Lower Bound for 88E AntDiv */ 622 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { 623 DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max; 624 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 625 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n", 626 pDM_DigTable->AntDiv_RSSI_max)); 627 } 628 } else { 629 DIG_Dynamic_MIN = dm_dig_min; 630 } 631 } else { 632 pDM_DigTable->rx_gain_range_max = dm_dig_max; 633 DIG_Dynamic_MIN = dm_dig_min; 634 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); 635 } 636 637 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ 638 if (pFalseAlmCnt->Cnt_all > 10000) { 639 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n")); 640 641 if (pDM_DigTable->LargeFAHit != 3) 642 pDM_DigTable->LargeFAHit++; 643 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { 644 pDM_DigTable->ForbiddenIGI = CurrentIGI; 645 pDM_DigTable->LargeFAHit = 1; 646 } 647 648 if (pDM_DigTable->LargeFAHit >= 3) { 649 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max) 650 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; 651 else 652 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 653 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ 654 } 655 656 } else { 657 /* Recovery mechanism for IGI lower bound */ 658 if (pDM_DigTable->Recover_cnt != 0) { 659 pDM_DigTable->Recover_cnt--; 660 } else { 661 if (pDM_DigTable->LargeFAHit < 3) { 662 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */ 663 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 664 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 665 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); 666 } else { 667 pDM_DigTable->ForbiddenIGI--; 668 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 669 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); 670 } 671 } else { 672 pDM_DigTable->LargeFAHit = 0; 673 } 674 } 675 } 676 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 677 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n", 678 pDM_DigTable->LargeFAHit)); 679 680 /* 1 Adjust initial gain by false alarm */ 681 if (pDM_Odm->bLinked) { 682 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); 683 if (FirstConnect) { 684 CurrentIGI = pDM_Odm->RSSI_Min; 685 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); 686 } else { 687 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) 688 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 689 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) 690 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 691 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) 692 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 693 } 694 } else { 695 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); 696 if (FirstDisConnect) { 697 CurrentIGI = pDM_DigTable->rx_gain_range_min; 698 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n")); 699 } else { 700 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ 701 if (pFalseAlmCnt->Cnt_all > 10000) 702 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 703 else if (pFalseAlmCnt->Cnt_all > 8000) 704 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 705 else if (pFalseAlmCnt->Cnt_all < 500) 706 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 707 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n")); 708 } 709 } 710 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); 711 /* 1 Check initial gain by upper/lower bound */ 712 if (CurrentIGI > pDM_DigTable->rx_gain_range_max) 713 CurrentIGI = pDM_DigTable->rx_gain_range_max; 714 if (CurrentIGI < pDM_DigTable->rx_gain_range_min) 715 CurrentIGI = pDM_DigTable->rx_gain_range_min; 716 717 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 718 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", 719 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); 720 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); 721 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); 722 723 /* 2 High power RSSI threshold */ 724 725 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 726 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; 727 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; 728} 729 730/* 3============================================================ */ 731/* 3 FASLE ALARM CHECK */ 732/* 3============================================================ */ 733 734void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 735{ 736 struct adapter *adapter = pDM_Odm->Adapter; 737 u32 ret_value; 738 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 739 740 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) 741 return; 742 743 /* hold ofdm counter */ 744 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ 745 phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ 746 747 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); 748 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); 749 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); 750 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); 751 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); 752 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); 753 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); 754 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); 755 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); 756 ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); 757 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); 758 759 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + 760 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + 761 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; 762 763 ret_value = phy_query_bb_reg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); 764 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); 765 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); 766 767 /* hold cck counter */ 768 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); 769 phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); 770 771 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); 772 FalseAlmCnt->Cnt_Cck_fail = ret_value; 773 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); 774 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8; 775 776 ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); 777 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8); 778 779 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + 780 FalseAlmCnt->Cnt_SB_Search_fail + 781 FalseAlmCnt->Cnt_Parity_Fail + 782 FalseAlmCnt->Cnt_Rate_Illegal + 783 FalseAlmCnt->Cnt_Crc8_fail + 784 FalseAlmCnt->Cnt_Mcs_fail + 785 FalseAlmCnt->Cnt_Cck_fail); 786 787 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; 788 789 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); 790 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 791 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", 792 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); 793 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 794 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", 795 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); 796 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 797 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", 798 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); 799 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); 800 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); 801 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); 802} 803 804/* 3============================================================ */ 805/* 3 CCK Packet Detect Threshold */ 806/* 3============================================================ */ 807 808void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) 809{ 810 u8 CurCCK_CCAThres; 811 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 812 813 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) 814 return; 815 if (pDM_Odm->ExtLNA) 816 return; 817 if (pDM_Odm->bLinked) { 818 if (pDM_Odm->RSSI_Min > 25) { 819 CurCCK_CCAThres = 0xcd; 820 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) { 821 CurCCK_CCAThres = 0x83; 822 } else { 823 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 824 CurCCK_CCAThres = 0x83; 825 else 826 CurCCK_CCAThres = 0x40; 827 } 828 } else { 829 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 830 CurCCK_CCAThres = 0x83; 831 else 832 CurCCK_CCAThres = 0x40; 833 } 834 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); 835} 836 837void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres) 838{ 839 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 840 struct adapter *adapt = pDM_Odm->Adapter; 841 842 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ 843 usb_write8(adapt, ODM_REG_CCK_CCA_11N, CurCCK_CCAThres); 844 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; 845 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; 846} 847 848void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 849{ 850 struct adapter *adapter = pDM_Odm->Adapter; 851 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 852 u8 Rssi_Up_bound = 30; 853 u8 Rssi_Low_bound = 25; 854 855 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */ 856 Rssi_Up_bound = 50; 857 Rssi_Low_bound = 45; 858 } 859 if (pDM_PSTable->initialize == 0) { 860 pDM_PSTable->Reg874 = (phy_query_bb_reg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14; 861 pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord)&BIT3)>>3; 862 pDM_PSTable->Reg85C = (phy_query_bb_reg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; 863 pDM_PSTable->RegA74 = (phy_query_bb_reg(adapter, 0xa74, bMaskDWord)&0xF000)>>12; 864 pDM_PSTable->initialize = 1; 865 } 866 867 if (!bForceInNormal) { 868 if (pDM_Odm->RSSI_Min != 0xFF) { 869 if (pDM_PSTable->PreRFState == RF_Normal) { 870 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound) 871 pDM_PSTable->CurRFState = RF_Save; 872 else 873 pDM_PSTable->CurRFState = RF_Normal; 874 } else { 875 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound) 876 pDM_PSTable->CurRFState = RF_Normal; 877 else 878 pDM_PSTable->CurRFState = RF_Save; 879 } 880 } else { 881 pDM_PSTable->CurRFState = RF_MAX; 882 } 883 } else { 884 pDM_PSTable->CurRFState = RF_Normal; 885 } 886 887 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { 888 if (pDM_PSTable->CurRFState == RF_Save) { 889 phy_set_bb_reg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ 890 phy_set_bb_reg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ 891 phy_set_bb_reg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ 892 phy_set_bb_reg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ 893 phy_set_bb_reg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ 894 phy_set_bb_reg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ 895 phy_set_bb_reg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ 896 } else { 897 phy_set_bb_reg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); 898 phy_set_bb_reg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); 899 phy_set_bb_reg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); 900 phy_set_bb_reg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); 901 phy_set_bb_reg(adapter, 0x818, BIT28, 0x0); 902 } 903 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; 904 } 905} 906 907/* 3============================================================ */ 908/* 3 RATR MASK */ 909/* 3============================================================ */ 910/* 3============================================================ */ 911/* 3 Rate Adaptive */ 912/* 3============================================================ */ 913 914void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm) 915{ 916 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive; 917 918 pOdmRA->Type = DM_Type_ByDriver; 919 if (pOdmRA->Type == DM_Type_ByDriver) 920 pDM_Odm->bUseRAMask = true; 921 else 922 pDM_Odm->bUseRAMask = false; 923 924 pOdmRA->RATRState = DM_RATR_STA_INIT; 925 pOdmRA->HighRSSIThresh = 50; 926 pOdmRA->LowRSSIThresh = 20; 927} 928 929u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level) 930{ 931 struct sta_info *pEntry; 932 u32 rate_bitmap = 0x0fffffff; 933 u8 WirelessMode; 934 935 pEntry = pDM_Odm->pODM_StaInfo[macid]; 936 if (!IS_STA_VALID(pEntry)) 937 return ra_mask; 938 939 WirelessMode = pEntry->wireless_mode; 940 941 switch (WirelessMode) { 942 case ODM_WM_B: 943 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ 944 rate_bitmap = 0x0000000d; 945 else 946 rate_bitmap = 0x0000000f; 947 break; 948 case (ODM_WM_A|ODM_WM_G): 949 if (rssi_level == DM_RATR_STA_HIGH) 950 rate_bitmap = 0x00000f00; 951 else 952 rate_bitmap = 0x00000ff0; 953 break; 954 case (ODM_WM_B|ODM_WM_G): 955 if (rssi_level == DM_RATR_STA_HIGH) 956 rate_bitmap = 0x00000f00; 957 else if (rssi_level == DM_RATR_STA_MIDDLE) 958 rate_bitmap = 0x00000ff0; 959 else 960 rate_bitmap = 0x00000ff5; 961 break; 962 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 963 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 964 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { 965 if (rssi_level == DM_RATR_STA_HIGH) { 966 rate_bitmap = 0x000f0000; 967 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 968 rate_bitmap = 0x000ff000; 969 } else { 970 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 971 rate_bitmap = 0x000ff015; 972 else 973 rate_bitmap = 0x000ff005; 974 } 975 } else { 976 if (rssi_level == DM_RATR_STA_HIGH) { 977 rate_bitmap = 0x0f8f0000; 978 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 979 rate_bitmap = 0x0f8ff000; 980 } else { 981 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 982 rate_bitmap = 0x0f8ff015; 983 else 984 rate_bitmap = 0x0f8ff005; 985 } 986 } 987 break; 988 default: 989 /* case WIRELESS_11_24N: */ 990 /* case WIRELESS_11_5N: */ 991 if (pDM_Odm->RFType == RF_1T2R) 992 rate_bitmap = 0x000fffff; 993 else 994 rate_bitmap = 0x0fffffff; 995 break; 996 } 997 998 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 999 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", 1000 rssi_level, WirelessMode, rate_bitmap)); 1001 1002 return rate_bitmap; 1003} 1004 1005/*----------------------------------------------------------------------------- 1006 * Function: odm_RefreshRateAdaptiveMask() 1007 * 1008 * Overview: Update rate table mask according to rssi 1009 * 1010 * Input: NONE 1011 * 1012 * Output: NONE 1013 * 1014 * Return: NONE 1015 * 1016 * Revised History: 1017 * When Who Remark 1018 * 05/27/2009 hpfan Create Version 0. 1019 * 1020 *---------------------------------------------------------------------------*/ 1021void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm) 1022{ 1023 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) 1024 return; 1025 /* */ 1026 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1027 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1028 /* HW dynamic mechanism. */ 1029 /* */ 1030 odm_RefreshRateAdaptiveMaskCE(pDM_Odm); 1031} 1032 1033void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm) 1034{ 1035 u8 i; 1036 struct adapter *pAdapter = pDM_Odm->Adapter; 1037 1038 if (pAdapter->bDriverStopped) { 1039 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); 1040 return; 1041 } 1042 1043 if (!pDM_Odm->bUseRAMask) { 1044 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); 1045 return; 1046 } 1047 1048 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1049 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; 1050 if (IS_STA_VALID(pstat)) { 1051 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) { 1052 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1053 ("RSSI:%d, RSSI_LEVEL:%d\n", 1054 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); 1055 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level); 1056 } 1057 } 1058 } 1059} 1060 1061/* Return Value: bool */ 1062/* - true: RATRState is changed. */ 1063bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState) 1064{ 1065 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive; 1066 const u8 GoUpGap = 5; 1067 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh; 1068 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; 1069 u8 RATRState; 1070 1071 /* Threshold Adjustment: */ 1072 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ 1073 /* Here GoUpGap is added to solve the boundary's level alternation issue. */ 1074 switch (*pRATRState) { 1075 case DM_RATR_STA_INIT: 1076 case DM_RATR_STA_HIGH: 1077 break; 1078 case DM_RATR_STA_MIDDLE: 1079 HighRSSIThreshForRA += GoUpGap; 1080 break; 1081 case DM_RATR_STA_LOW: 1082 HighRSSIThreshForRA += GoUpGap; 1083 LowRSSIThreshForRA += GoUpGap; 1084 break; 1085 default: 1086 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState)); 1087 break; 1088 } 1089 1090 /* Decide RATRState by RSSI. */ 1091 if (RSSI > HighRSSIThreshForRA) 1092 RATRState = DM_RATR_STA_HIGH; 1093 else if (RSSI > LowRSSIThreshForRA) 1094 RATRState = DM_RATR_STA_MIDDLE; 1095 else 1096 RATRState = DM_RATR_STA_LOW; 1097 1098 if (*pRATRState != RATRState || bForceUpdate) { 1099 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState)); 1100 *pRATRState = RATRState; 1101 return true; 1102 } 1103 return false; 1104} 1105 1106/* 3============================================================ */ 1107/* 3 Dynamic Tx Power */ 1108/* 3============================================================ */ 1109 1110void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm) 1111{ 1112 struct adapter *Adapter = pDM_Odm->Adapter; 1113 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1114 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1115 pdmpriv->bDynamicTxPowerEnable = false; 1116 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; 1117 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; 1118} 1119 1120/* 3============================================================ */ 1121/* 3 RSSI Monitor */ 1122/* 3============================================================ */ 1123 1124void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm) 1125{ 1126 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) 1127 return; 1128 1129 /* */ 1130 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1131 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1132 /* HW dynamic mechanism. */ 1133 /* */ 1134 odm_RSSIMonitorCheckCE(pDM_Odm); 1135} /* odm_RSSIMonitorCheck */ 1136 1137static void FindMinimumRSSI(struct adapter *pAdapter) 1138{ 1139 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); 1140 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1141 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; 1142 1143 /* 1 1.Determine the minimum RSSI */ 1144 if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) && 1145 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) 1146 pdmpriv->MinUndecoratedPWDBForDM = 0; 1147 if (check_fwstate(pmlmepriv, _FW_LINKED) == true) /* Default port */ 1148 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1149 else /* associated entry pwdb */ 1150 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1151} 1152 1153void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm) 1154{ 1155 struct adapter *Adapter = pDM_Odm->Adapter; 1156 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1157 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1158 int i; 1159 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; 1160 u8 sta_cnt = 0; 1161 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ 1162 struct sta_info *psta; 1163 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 1164 1165 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) 1166 return; 1167 1168 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1169 psta = pDM_Odm->pODM_StaInfo[i]; 1170 if (IS_STA_VALID(psta) && 1171 (psta->state & WIFI_ASOC_STATE) && 1172 memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) && 1173 memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) { 1174 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) 1175 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1176 1177 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) 1178 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1179 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) 1180 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16)); 1181 } 1182 } 1183 1184 for (i = 0; i < sta_cnt; i++) { 1185 if (PWDB_rssi[i] != (0)) { 1186 if (pHalData->fw_ractrl) { 1187 /* Report every sta's RSSI to FW */ 1188 } else { 1189 ODM_RA_SetRSSI_8188E( 1190 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); 1191 } 1192 } 1193 } 1194 1195 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */ 1196 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; 1197 else 1198 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; 1199 1200 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */ 1201 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; 1202 else 1203 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; 1204 1205 FindMinimumRSSI(Adapter); 1206 ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); 1207} 1208 1209/* 3============================================================ */ 1210/* 3 Tx Power Tracking */ 1211/* 3============================================================ */ 1212 1213void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm) 1214{ 1215 odm_TXPowerTrackingThermalMeterInit(pDM_Odm); 1216} 1217 1218void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm) 1219{ 1220 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; 1221 pDM_Odm->RFCalibrateInfo.TXPowercount = 0; 1222 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; 1223 if (*(pDM_Odm->mp_mode) != 1) 1224 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1225 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); 1226 1227 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1228} 1229 1230void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm) 1231{ 1232 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1233 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1234 /* HW dynamic mechanism. */ 1235 odm_TXPowerTrackingCheckCE(pDM_Odm); 1236} 1237 1238void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 1239{ 1240 struct adapter *Adapter = pDM_Odm->Adapter; 1241 1242 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) 1243 return; 1244 1245 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ 1246 phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); 1247 1248 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; 1249 return; 1250 } else { 1251 rtl88eu_dm_txpower_tracking_callback_thermalmeter(Adapter); 1252 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; 1253 } 1254} 1255 1256/* 3============================================================ */ 1257/* 3 SW Antenna Diversity */ 1258/* 3============================================================ */ 1259 1260void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) 1261{ 1262 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1263 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1264 return; 1265 } 1266 1267 rtl88eu_dm_antenna_div_init(pDM_Odm); 1268} 1269 1270void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) 1271{ 1272 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1273 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1274 return; 1275 } 1276 1277 rtl88eu_dm_antenna_diversity(pDM_Odm); 1278} 1279 1280/* EDCA Turbo */ 1281void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) 1282{ 1283 struct adapter *Adapter = pDM_Odm->Adapter; 1284 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1285 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; 1286 Adapter->recvpriv.bIsAnyNonBEPkts = false; 1287 1288 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VO_PARAM))); 1289 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_VI_PARAM))); 1290 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BE_PARAM))); 1291 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", usb_read32(Adapter, ODM_EDCA_BK_PARAM))); 1292} /* ODM_InitEdcaTurbo */ 1293 1294void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm) 1295{ 1296 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1297 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1298 /* HW dynamic mechanism. */ 1299 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n")); 1300 1301 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)) 1302 return; 1303 1304 odm_EdcaTurboCheckCE(pDM_Odm); 1305 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n")); 1306} /* odm_CheckEdcaTurbo */ 1307 1308void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm) 1309{ 1310 struct adapter *Adapter = pDM_Odm->Adapter; 1311 u32 trafficIndex; 1312 u32 edca_param; 1313 u64 cur_tx_bytes = 0; 1314 u64 cur_rx_bytes = 0; 1315 u8 bbtchange = false; 1316 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1317 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); 1318 struct recv_priv *precvpriv = &(Adapter->recvpriv); 1319 struct registry_priv *pregpriv = &Adapter->registrypriv; 1320 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); 1321 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 1322 1323 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */ 1324 goto dm_CheckEdcaTurbo_EXIT; 1325 1326 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) 1327 goto dm_CheckEdcaTurbo_EXIT; 1328 1329 /* Check if the status needs to be changed. */ 1330 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) { 1331 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; 1332 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; 1333 1334 /* traffic, TX or RX */ 1335 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) || 1336 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { 1337 if (cur_tx_bytes > (cur_rx_bytes << 2)) { 1338 /* Uplink TP is present. */ 1339 trafficIndex = UP_LINK; 1340 } else { 1341 /* Balance TP is present. */ 1342 trafficIndex = DOWN_LINK; 1343 } 1344 } else { 1345 if (cur_rx_bytes > (cur_tx_bytes << 2)) { 1346 /* Downlink TP is present. */ 1347 trafficIndex = DOWN_LINK; 1348 } else { 1349 /* Balance TP is present. */ 1350 trafficIndex = UP_LINK; 1351 } 1352 } 1353 1354 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) { 1355 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) 1356 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; 1357 else 1358 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; 1359 1360 usb_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); 1361 1362 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; 1363 } 1364 1365 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; 1366 } else { 1367 /* Turn Off EDCA turbo here. */ 1368 /* Restore original EDCA according to the declaration of AP. */ 1369 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { 1370 usb_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); 1371 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1372 } 1373 } 1374 1375dm_CheckEdcaTurbo_EXIT: 1376 /* Set variables for next time. */ 1377 precvpriv->bIsAnyNonBEPkts = false; 1378 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; 1379 precvpriv->last_rx_bytes = precvpriv->rx_bytes; 1380} 1381