odm.c revision 86ff64405ec14d7c01edd5fdb40cc338872728c0
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21/* include files */ 22 23#include "odm_precomp.h" 24 25static const u16 dB_Invert_Table[8][12] = { 26 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, 27 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, 28 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63}, 29 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251}, 30 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000}, 31 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, 32 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849}, 33 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} 34}; 35 36/* avoid to warn in FreeBSD ==> To DO modify */ 37static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { 38 /* UL DL */ 39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ 40 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ 41 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ 42 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ 43 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ 44 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ 45 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ 46 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ 47 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ 48 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ 49}; 50 51/* Global var */ 52u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { 53 0x7f8001fe, /* 0, +6.0dB */ 54 0x788001e2, /* 1, +5.5dB */ 55 0x71c001c7, /* 2, +5.0dB */ 56 0x6b8001ae, /* 3, +4.5dB */ 57 0x65400195, /* 4, +4.0dB */ 58 0x5fc0017f, /* 5, +3.5dB */ 59 0x5a400169, /* 6, +3.0dB */ 60 0x55400155, /* 7, +2.5dB */ 61 0x50800142, /* 8, +2.0dB */ 62 0x4c000130, /* 9, +1.5dB */ 63 0x47c0011f, /* 10, +1.0dB */ 64 0x43c0010f, /* 11, +0.5dB */ 65 0x40000100, /* 12, +0dB */ 66 0x3c8000f2, /* 13, -0.5dB */ 67 0x390000e4, /* 14, -1.0dB */ 68 0x35c000d7, /* 15, -1.5dB */ 69 0x32c000cb, /* 16, -2.0dB */ 70 0x300000c0, /* 17, -2.5dB */ 71 0x2d4000b5, /* 18, -3.0dB */ 72 0x2ac000ab, /* 19, -3.5dB */ 73 0x288000a2, /* 20, -4.0dB */ 74 0x26000098, /* 21, -4.5dB */ 75 0x24000090, /* 22, -5.0dB */ 76 0x22000088, /* 23, -5.5dB */ 77 0x20000080, /* 24, -6.0dB */ 78 0x1e400079, /* 25, -6.5dB */ 79 0x1c800072, /* 26, -7.0dB */ 80 0x1b00006c, /* 27. -7.5dB */ 81 0x19800066, /* 28, -8.0dB */ 82 0x18000060, /* 29, -8.5dB */ 83 0x16c0005b, /* 30, -9.0dB */ 84 0x15800056, /* 31, -9.5dB */ 85 0x14400051, /* 32, -10.0dB */ 86 0x1300004c, /* 33, -10.5dB */ 87 0x12000048, /* 34, -11.0dB */ 88 0x11000044, /* 35, -11.5dB */ 89 0x10000040, /* 36, -12.0dB */ 90 0x0f00003c,/* 37, -12.5dB */ 91 0x0e400039,/* 38, -13.0dB */ 92 0x0d800036,/* 39, -13.5dB */ 93 0x0cc00033,/* 40, -14.0dB */ 94 0x0c000030,/* 41, -14.5dB */ 95 0x0b40002d,/* 42, -15.0dB */ 96}; 97 98u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { 99 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 100 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 101 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 102 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 103 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 104 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 105 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 106 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 107 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 108 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 109 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 110 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 111 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 112 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 113 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 114 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 115 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 116 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 117 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 118 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 119 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ 120 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ 121 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ 122 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ 123 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ 124 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ 125 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ 126 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ 127 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ 128 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ 129 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ 130 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ 131 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ 132}; 133 134u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { 135 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 136 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 137 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 138 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 139 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 140 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 141 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 142 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 143 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 144 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 145 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 146 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 147 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 148 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 149 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 150 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 151 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 152 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 153 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 154 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 155 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ 156 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ 157 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ 158 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ 159 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ 160 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ 161 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ 162 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ 163 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ 164 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ 165 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ 166 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ 167 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ 168}; 169 170 171#define RxDefaultAnt1 0x65a9 172#define RxDefaultAnt2 0x569a 173 174/* 3 Export Interface */ 175 176/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ 177void ODM_DMInit(struct odm_dm_struct *pDM_Odm) 178{ 179 /* 2012.05.03 Luke: For all IC series */ 180 odm_CommonInfoSelfInit(pDM_Odm); 181 odm_CmnInfoInit_Debug(pDM_Odm); 182 odm_DIGInit(pDM_Odm); 183 odm_RateAdaptiveMaskInit(pDM_Odm); 184 185 odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ 186 odm_DynamicTxPowerInit(pDM_Odm); 187 odm_TXPowerTrackingInit(pDM_Odm); 188 ODM_EdcaTurboInit(pDM_Odm); 189 ODM_RAInfo_Init_all(pDM_Odm); 190 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 191 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 192 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 193 odm_InitHybridAntDiv(pDM_Odm); 194} 195 196/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ 197/* You can not add any dummy function here, be care, you can only use DM structure */ 198/* to perform any new ODM_DM. */ 199void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) 200{ 201 /* 2012.05.03 Luke: For all IC series */ 202 odm_CmnInfoHook_Debug(pDM_Odm); 203 odm_CmnInfoUpdate_Debug(pDM_Odm); 204 odm_CommonInfoSelfUpdate(pDM_Odm); 205 odm_FalseAlarmCounterStatistics(pDM_Odm); 206 odm_RSSIMonitorCheck(pDM_Odm); 207 208 /* Fix Leave LPS issue */ 209 odm_DIG(pDM_Odm); 210 odm_CCKPacketDetectionThresh(pDM_Odm); 211 212 if (*(pDM_Odm->pbPowerSaving)) 213 return; 214 215 odm_RefreshRateAdaptiveMask(pDM_Odm); 216 217 odm_DynamicPrimaryCCA(pDM_Odm); 218 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 219 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 220 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 221 odm_HwAntDiv(pDM_Odm); 222 223 ODM_TXPowerTrackingCheck(pDM_Odm); 224 odm_EdcaTurboCheck(pDM_Odm); 225 odm_DynamicTxPower(pDM_Odm); 226} 227 228/* Init /.. Fixed HW value. Only init time. */ 229void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value) 230{ 231 /* This section is used for init value */ 232 switch (CmnInfo) { 233 /* Fixed ODM value. */ 234 case ODM_CMNINFO_ABILITY: 235 pDM_Odm->SupportAbility = (u32)Value; 236 break; 237 case ODM_CMNINFO_PLATFORM: 238 pDM_Odm->SupportPlatform = (u8)Value; 239 break; 240 case ODM_CMNINFO_INTERFACE: 241 pDM_Odm->SupportInterface = (u8)Value; 242 break; 243 case ODM_CMNINFO_MP_TEST_CHIP: 244 pDM_Odm->bIsMPChip = (u8)Value; 245 break; 246 case ODM_CMNINFO_IC_TYPE: 247 pDM_Odm->SupportICType = Value; 248 break; 249 case ODM_CMNINFO_CUT_VER: 250 pDM_Odm->CutVersion = (u8)Value; 251 break; 252 case ODM_CMNINFO_FAB_VER: 253 pDM_Odm->FabVersion = (u8)Value; 254 break; 255 case ODM_CMNINFO_RF_TYPE: 256 pDM_Odm->RFType = (u8)Value; 257 break; 258 case ODM_CMNINFO_RF_ANTENNA_TYPE: 259 pDM_Odm->AntDivType = (u8)Value; 260 break; 261 case ODM_CMNINFO_BOARD_TYPE: 262 pDM_Odm->BoardType = (u8)Value; 263 break; 264 case ODM_CMNINFO_EXT_LNA: 265 pDM_Odm->ExtLNA = (u8)Value; 266 break; 267 case ODM_CMNINFO_EXT_PA: 268 pDM_Odm->ExtPA = (u8)Value; 269 break; 270 case ODM_CMNINFO_EXT_TRSW: 271 pDM_Odm->ExtTRSW = (u8)Value; 272 break; 273 case ODM_CMNINFO_PATCH_ID: 274 pDM_Odm->PatchID = (u8)Value; 275 break; 276 case ODM_CMNINFO_BINHCT_TEST: 277 pDM_Odm->bInHctTest = (bool)Value; 278 break; 279 case ODM_CMNINFO_BWIFI_TEST: 280 pDM_Odm->bWIFITest = (bool)Value; 281 break; 282 case ODM_CMNINFO_SMART_CONCURRENT: 283 pDM_Odm->bDualMacSmartConcurrent = (bool)Value; 284 break; 285 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 286 default: 287 /* do nothing */ 288 break; 289 } 290 291 /* Tx power tracking BB swing table. */ 292 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ 293 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */ 294 pDM_Odm->BbSwingIdxOfdmCurrent = 12; 295 pDM_Odm->BbSwingFlagOfdm = false; 296} 297 298void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue) 299{ 300 /* */ 301 /* Hook call by reference pointer. */ 302 /* */ 303 switch (CmnInfo) { 304 /* Dynamic call by reference pointer. */ 305 case ODM_CMNINFO_MAC_PHY_MODE: 306 pDM_Odm->pMacPhyMode = (u8 *)pValue; 307 break; 308 case ODM_CMNINFO_TX_UNI: 309 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue; 310 break; 311 case ODM_CMNINFO_RX_UNI: 312 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue; 313 break; 314 case ODM_CMNINFO_WM_MODE: 315 pDM_Odm->pWirelessMode = (u8 *)pValue; 316 break; 317 case ODM_CMNINFO_BAND: 318 pDM_Odm->pBandType = (u8 *)pValue; 319 break; 320 case ODM_CMNINFO_SEC_CHNL_OFFSET: 321 pDM_Odm->pSecChOffset = (u8 *)pValue; 322 break; 323 case ODM_CMNINFO_SEC_MODE: 324 pDM_Odm->pSecurity = (u8 *)pValue; 325 break; 326 case ODM_CMNINFO_BW: 327 pDM_Odm->pBandWidth = (u8 *)pValue; 328 break; 329 case ODM_CMNINFO_CHNL: 330 pDM_Odm->pChannel = (u8 *)pValue; 331 break; 332 case ODM_CMNINFO_DMSP_GET_VALUE: 333 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue; 334 break; 335 case ODM_CMNINFO_BUDDY_ADAPTOR: 336 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue; 337 break; 338 case ODM_CMNINFO_DMSP_IS_MASTER: 339 pDM_Odm->pbMasterOfDMSP = (bool *)pValue; 340 break; 341 case ODM_CMNINFO_SCAN: 342 pDM_Odm->pbScanInProcess = (bool *)pValue; 343 break; 344 case ODM_CMNINFO_POWER_SAVING: 345 pDM_Odm->pbPowerSaving = (bool *)pValue; 346 break; 347 case ODM_CMNINFO_ONE_PATH_CCA: 348 pDM_Odm->pOnePathCCA = (u8 *)pValue; 349 break; 350 case ODM_CMNINFO_DRV_STOP: 351 pDM_Odm->pbDriverStopped = (bool *)pValue; 352 break; 353 case ODM_CMNINFO_PNP_IN: 354 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue; 355 break; 356 case ODM_CMNINFO_INIT_ON: 357 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue; 358 break; 359 case ODM_CMNINFO_ANT_TEST: 360 pDM_Odm->pAntennaTest = (u8 *)pValue; 361 break; 362 case ODM_CMNINFO_NET_CLOSED: 363 pDM_Odm->pbNet_closed = (bool *)pValue; 364 break; 365 case ODM_CMNINFO_MP_MODE: 366 pDM_Odm->mp_mode = (u8 *)pValue; 367 break; 368 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 369 default: 370 /* do nothing */ 371 break; 372 } 373} 374 375void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue) 376{ 377 /* Hook call by reference pointer. */ 378 switch (CmnInfo) { 379 /* Dynamic call by reference pointer. */ 380 case ODM_CMNINFO_STA_STATUS: 381 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue; 382 break; 383 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 384 default: 385 /* do nothing */ 386 break; 387 } 388} 389 390/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ 391void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value) 392{ 393 /* */ 394 /* This init variable may be changed in run time. */ 395 /* */ 396 switch (CmnInfo) { 397 case ODM_CMNINFO_ABILITY: 398 pDM_Odm->SupportAbility = (u32)Value; 399 break; 400 case ODM_CMNINFO_RF_TYPE: 401 pDM_Odm->RFType = (u8)Value; 402 break; 403 case ODM_CMNINFO_WIFI_DIRECT: 404 pDM_Odm->bWIFI_Direct = (bool)Value; 405 break; 406 case ODM_CMNINFO_WIFI_DISPLAY: 407 pDM_Odm->bWIFI_Display = (bool)Value; 408 break; 409 case ODM_CMNINFO_LINK: 410 pDM_Odm->bLinked = (bool)Value; 411 break; 412 case ODM_CMNINFO_RSSI_MIN: 413 pDM_Odm->RSSI_Min = (u8)Value; 414 break; 415 case ODM_CMNINFO_DBG_COMP: 416 pDM_Odm->DebugComponents = Value; 417 break; 418 case ODM_CMNINFO_DBG_LEVEL: 419 pDM_Odm->DebugLevel = (u32)Value; 420 break; 421 case ODM_CMNINFO_RA_THRESHOLD_HIGH: 422 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value; 423 break; 424 case ODM_CMNINFO_RA_THRESHOLD_LOW: 425 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value; 426 break; 427 } 428} 429 430void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) 431{ 432 struct adapter *adapter = pDM_Odm->Adapter; 433 434 pDM_Odm->bCckHighPower = (bool) PHY_QueryBBReg(adapter, 0x824, BIT9); 435 pDM_Odm->RFPathRxEnable = (u8) PHY_QueryBBReg(adapter, 0xc04, 0x0F); 436 437 ODM_InitDebugSetting(pDM_Odm); 438} 439 440void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) 441{ 442 u8 EntryCnt = 0; 443 u8 i; 444 struct sta_info *pEntry; 445 446 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { 447 if (*(pDM_Odm->pSecChOffset) == 1) 448 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; 449 else if (*(pDM_Odm->pSecChOffset) == 2) 450 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; 451 } else { 452 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); 453 } 454 455 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 456 pEntry = pDM_Odm->pODM_StaInfo[i]; 457 if (IS_STA_VALID(pEntry)) 458 EntryCnt++; 459 } 460 if (EntryCnt == 1) 461 pDM_Odm->bOneEntryOnly = true; 462 else 463 pDM_Odm->bOneEntryOnly = false; 464} 465 466void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm) 467{ 468 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); 469 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform)); 470 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility)); 471 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface)); 472 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType)); 473 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion)); 474 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n", pDM_Odm->FabVersion)); 475 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n", pDM_Odm->RFType)); 476 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType)); 477 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA)); 478 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA)); 479 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW)); 480 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID)); 481 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest)); 482 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest)); 483 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent)); 484} 485 486void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm) 487{ 488 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); 489 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast))); 490 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast))); 491 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode))); 492 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset))); 493 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity))); 494 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth))); 495 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel))); 496 497 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess))); 498 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving))); 499} 500 501void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm) 502{ 503 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); 504 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct)); 505 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display)); 506 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked)); 507 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min)); 508} 509 510void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) 511{ 512 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 513 struct adapter *adapter = pDM_Odm->Adapter; 514 515 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 516 ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", 517 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm))); 518 519 if (pDM_DigTable->CurIGValue != CurrentIGI) { 520 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 521 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n", CurrentIGI)); 522 /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */ 523 pDM_DigTable->CurIGValue = CurrentIGI; 524 } 525 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x\n", CurrentIGI)); 526 527/* Add by Neil Chen to enable edcca to MP Platform */ 528} 529 530void odm_DIGInit(struct odm_dm_struct *pDM_Odm) 531{ 532 struct adapter *adapter = pDM_Odm->Adapter; 533 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 534 535 pDM_DigTable->CurIGValue = (u8) PHY_QueryBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); 536 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; 537 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; 538 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW; 539 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH; 540 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) { 541 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 542 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 543 } else { 544 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 545 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 546 } 547 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; 548 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; 549 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; 550 pDM_DigTable->PreCCK_CCAThres = 0xFF; 551 pDM_DigTable->CurCCK_CCAThres = 0x83; 552 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; 553 pDM_DigTable->LargeFAHit = 0; 554 pDM_DigTable->Recover_cnt = 0; 555 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; 556 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; 557 pDM_DigTable->bMediaConnect_0 = false; 558 pDM_DigTable->bMediaConnect_1 = false; 559 560 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */ 561 pDM_Odm->bDMInitialGainEnable = true; 562} 563 564void odm_DIG(struct odm_dm_struct *pDM_Odm) 565{ 566 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 567 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 568 u8 DIG_Dynamic_MIN; 569 u8 DIG_MaxOfMin; 570 bool FirstConnect, FirstDisConnect; 571 u8 dm_dig_max, dm_dig_min; 572 u8 CurrentIGI = pDM_DigTable->CurIGValue; 573 574 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); 575 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) { 576 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 577 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); 578 return; 579 } 580 581 if (*(pDM_Odm->pbScanInProcess)) { 582 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n")); 583 return; 584 } 585 586 /* add by Neil Chen to avoid PSD is processing */ 587 if (pDM_Odm->bDMInitialGainEnable == false) { 588 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n")); 589 return; 590 } 591 592 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 593 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 594 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 595 596 /* 1 Boundary Decision */ 597 dm_dig_max = DM_DIG_MAX_NIC; 598 dm_dig_min = DM_DIG_MIN_NIC; 599 DIG_MaxOfMin = DM_DIG_MAX_AP; 600 601 if (pDM_Odm->bLinked) { 602 /* 2 Modify DIG upper bound */ 603 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) 604 pDM_DigTable->rx_gain_range_max = dm_dig_max; 605 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min) 606 pDM_DigTable->rx_gain_range_max = dm_dig_min; 607 else 608 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; 609 /* 2 Modify DIG lower bound */ 610 if (pDM_Odm->bOneEntryOnly) { 611 if (pDM_Odm->RSSI_Min < dm_dig_min) 612 DIG_Dynamic_MIN = dm_dig_min; 613 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) 614 DIG_Dynamic_MIN = DIG_MaxOfMin; 615 else 616 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; 617 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 618 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n", 619 DIG_Dynamic_MIN)); 620 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 621 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n", 622 pDM_Odm->RSSI_Min)); 623 } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) { 624 /* 1 Lower Bound for 88E AntDiv */ 625 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { 626 DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max; 627 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 628 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n", 629 pDM_DigTable->AntDiv_RSSI_max)); 630 } 631 } else { 632 DIG_Dynamic_MIN = dm_dig_min; 633 } 634 } else { 635 pDM_DigTable->rx_gain_range_max = dm_dig_max; 636 DIG_Dynamic_MIN = dm_dig_min; 637 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); 638 } 639 640 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ 641 if (pFalseAlmCnt->Cnt_all > 10000) { 642 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n")); 643 644 if (pDM_DigTable->LargeFAHit != 3) 645 pDM_DigTable->LargeFAHit++; 646 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { 647 pDM_DigTable->ForbiddenIGI = CurrentIGI; 648 pDM_DigTable->LargeFAHit = 1; 649 } 650 651 if (pDM_DigTable->LargeFAHit >= 3) { 652 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max) 653 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; 654 else 655 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 656 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ 657 } 658 659 } else { 660 /* Recovery mechanism for IGI lower bound */ 661 if (pDM_DigTable->Recover_cnt != 0) { 662 pDM_DigTable->Recover_cnt--; 663 } else { 664 if (pDM_DigTable->LargeFAHit < 3) { 665 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */ 666 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 667 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 668 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); 669 } else { 670 pDM_DigTable->ForbiddenIGI--; 671 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 672 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); 673 } 674 } else { 675 pDM_DigTable->LargeFAHit = 0; 676 } 677 } 678 } 679 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 680 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n", 681 pDM_DigTable->LargeFAHit)); 682 683 /* 1 Adjust initial gain by false alarm */ 684 if (pDM_Odm->bLinked) { 685 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); 686 if (FirstConnect) { 687 CurrentIGI = pDM_Odm->RSSI_Min; 688 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); 689 } else { 690 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) 691 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 692 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) 693 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 694 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) 695 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 696 } 697 } else { 698 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); 699 if (FirstDisConnect) { 700 CurrentIGI = pDM_DigTable->rx_gain_range_min; 701 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n")); 702 } else { 703 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ 704 if (pFalseAlmCnt->Cnt_all > 10000) 705 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 706 else if (pFalseAlmCnt->Cnt_all > 8000) 707 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 708 else if (pFalseAlmCnt->Cnt_all < 500) 709 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 710 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n")); 711 } 712 } 713 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); 714 /* 1 Check initial gain by upper/lower bound */ 715 if (CurrentIGI > pDM_DigTable->rx_gain_range_max) 716 CurrentIGI = pDM_DigTable->rx_gain_range_max; 717 if (CurrentIGI < pDM_DigTable->rx_gain_range_min) 718 CurrentIGI = pDM_DigTable->rx_gain_range_min; 719 720 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 721 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", 722 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); 723 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); 724 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); 725 726 /* 2 High power RSSI threshold */ 727 728 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 729 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; 730 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; 731} 732 733/* 3============================================================ */ 734/* 3 FASLE ALARM CHECK */ 735/* 3============================================================ */ 736 737void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 738{ 739 struct adapter *adapter = pDM_Odm->Adapter; 740 u32 ret_value; 741 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 742 743 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) 744 return; 745 746 /* hold ofdm counter */ 747 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ 748 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ 749 750 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); 751 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); 752 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); 753 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); 754 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); 755 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); 756 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); 757 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); 758 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); 759 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); 760 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); 761 762 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + 763 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + 764 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; 765 766 ret_value = PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); 767 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); 768 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); 769 770 /* hold cck counter */ 771 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); 772 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); 773 774 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); 775 FalseAlmCnt->Cnt_Cck_fail = ret_value; 776 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); 777 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8; 778 779 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); 780 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8); 781 782 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + 783 FalseAlmCnt->Cnt_SB_Search_fail + 784 FalseAlmCnt->Cnt_Parity_Fail + 785 FalseAlmCnt->Cnt_Rate_Illegal + 786 FalseAlmCnt->Cnt_Crc8_fail + 787 FalseAlmCnt->Cnt_Mcs_fail + 788 FalseAlmCnt->Cnt_Cck_fail); 789 790 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; 791 792 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); 793 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 794 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", 795 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); 796 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 797 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", 798 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); 799 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 800 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", 801 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); 802 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); 803 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); 804 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); 805} 806 807/* 3============================================================ */ 808/* 3 CCK Packet Detect Threshold */ 809/* 3============================================================ */ 810 811void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) 812{ 813 u8 CurCCK_CCAThres; 814 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 815 816 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) 817 return; 818 if (pDM_Odm->ExtLNA) 819 return; 820 if (pDM_Odm->bLinked) { 821 if (pDM_Odm->RSSI_Min > 25) { 822 CurCCK_CCAThres = 0xcd; 823 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) { 824 CurCCK_CCAThres = 0x83; 825 } else { 826 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 827 CurCCK_CCAThres = 0x83; 828 else 829 CurCCK_CCAThres = 0x40; 830 } 831 } else { 832 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 833 CurCCK_CCAThres = 0x83; 834 else 835 CurCCK_CCAThres = 0x40; 836 } 837 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); 838} 839 840void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres) 841{ 842 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 843 struct adapter *adapt = pDM_Odm->Adapter; 844 845 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ 846 rtw_write8(adapt, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres); 847 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; 848 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; 849} 850 851/* 3============================================================ */ 852/* 3 BB Power Save */ 853/* 3============================================================ */ 854void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm) 855{ 856 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 857 858 pDM_PSTable->PreCCAState = CCA_MAX; 859 pDM_PSTable->CurCCAState = CCA_MAX; 860 pDM_PSTable->PreRFState = RF_MAX; 861 pDM_PSTable->CurRFState = RF_MAX; 862 pDM_PSTable->Rssi_val_min = 0; 863 pDM_PSTable->initialize = 0; 864} 865 866void odm_1R_CCA(struct odm_dm_struct *pDM_Odm) 867{ 868 struct adapter *adapter = pDM_Odm->Adapter; 869 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 870 871 if (pDM_Odm->RSSI_Min != 0xFF) { 872 if (pDM_PSTable->PreCCAState == CCA_2R) { 873 if (pDM_Odm->RSSI_Min >= 35) 874 pDM_PSTable->CurCCAState = CCA_1R; 875 else 876 pDM_PSTable->CurCCAState = CCA_2R; 877 } else { 878 if (pDM_Odm->RSSI_Min <= 30) 879 pDM_PSTable->CurCCAState = CCA_2R; 880 else 881 pDM_PSTable->CurCCAState = CCA_1R; 882 } 883 } else { 884 pDM_PSTable->CurCCAState = CCA_MAX; 885 } 886 887 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) { 888 if (pDM_PSTable->CurCCAState == CCA_1R) { 889 if (pDM_Odm->RFType == ODM_2T2R) 890 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x13); 891 else 892 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x23); 893 } else { 894 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x33); 895 } 896 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; 897 } 898} 899 900void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 901{ 902 struct adapter *adapter = pDM_Odm->Adapter; 903 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 904 u8 Rssi_Up_bound = 30; 905 u8 Rssi_Low_bound = 25; 906 907 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */ 908 Rssi_Up_bound = 50; 909 Rssi_Low_bound = 45; 910 } 911 if (pDM_PSTable->initialize == 0) { 912 pDM_PSTable->Reg874 = (PHY_QueryBBReg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14; 913 pDM_PSTable->RegC70 = (PHY_QueryBBReg(adapter, 0xc70, bMaskDWord)&BIT3)>>3; 914 pDM_PSTable->Reg85C = (PHY_QueryBBReg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; 915 pDM_PSTable->RegA74 = (PHY_QueryBBReg(adapter, 0xa74, bMaskDWord)&0xF000)>>12; 916 pDM_PSTable->initialize = 1; 917 } 918 919 if (!bForceInNormal) { 920 if (pDM_Odm->RSSI_Min != 0xFF) { 921 if (pDM_PSTable->PreRFState == RF_Normal) { 922 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound) 923 pDM_PSTable->CurRFState = RF_Save; 924 else 925 pDM_PSTable->CurRFState = RF_Normal; 926 } else { 927 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound) 928 pDM_PSTable->CurRFState = RF_Normal; 929 else 930 pDM_PSTable->CurRFState = RF_Save; 931 } 932 } else { 933 pDM_PSTable->CurRFState = RF_MAX; 934 } 935 } else { 936 pDM_PSTable->CurRFState = RF_Normal; 937 } 938 939 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { 940 if (pDM_PSTable->CurRFState == RF_Save) { 941 PHY_SetBBReg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ 942 PHY_SetBBReg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ 943 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ 944 PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ 945 PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ 946 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ 947 PHY_SetBBReg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ 948 } else { 949 PHY_SetBBReg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); 950 PHY_SetBBReg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); 951 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); 952 PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); 953 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); 954 } 955 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; 956 } 957} 958 959/* 3============================================================ */ 960/* 3 RATR MASK */ 961/* 3============================================================ */ 962/* 3============================================================ */ 963/* 3 Rate Adaptive */ 964/* 3============================================================ */ 965 966void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm) 967{ 968 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive; 969 970 pOdmRA->Type = DM_Type_ByDriver; 971 if (pOdmRA->Type == DM_Type_ByDriver) 972 pDM_Odm->bUseRAMask = true; 973 else 974 pDM_Odm->bUseRAMask = false; 975 976 pOdmRA->RATRState = DM_RATR_STA_INIT; 977 pOdmRA->HighRSSIThresh = 50; 978 pOdmRA->LowRSSIThresh = 20; 979} 980 981u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level) 982{ 983 struct sta_info *pEntry; 984 u32 rate_bitmap = 0x0fffffff; 985 u8 WirelessMode; 986 987 pEntry = pDM_Odm->pODM_StaInfo[macid]; 988 if (!IS_STA_VALID(pEntry)) 989 return ra_mask; 990 991 WirelessMode = pEntry->wireless_mode; 992 993 switch (WirelessMode) { 994 case ODM_WM_B: 995 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ 996 rate_bitmap = 0x0000000d; 997 else 998 rate_bitmap = 0x0000000f; 999 break; 1000 case (ODM_WM_A|ODM_WM_G): 1001 if (rssi_level == DM_RATR_STA_HIGH) 1002 rate_bitmap = 0x00000f00; 1003 else 1004 rate_bitmap = 0x00000ff0; 1005 break; 1006 case (ODM_WM_B|ODM_WM_G): 1007 if (rssi_level == DM_RATR_STA_HIGH) 1008 rate_bitmap = 0x00000f00; 1009 else if (rssi_level == DM_RATR_STA_MIDDLE) 1010 rate_bitmap = 0x00000ff0; 1011 else 1012 rate_bitmap = 0x00000ff5; 1013 break; 1014 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1015 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1016 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { 1017 if (rssi_level == DM_RATR_STA_HIGH) { 1018 rate_bitmap = 0x000f0000; 1019 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1020 rate_bitmap = 0x000ff000; 1021 } else { 1022 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1023 rate_bitmap = 0x000ff015; 1024 else 1025 rate_bitmap = 0x000ff005; 1026 } 1027 } else { 1028 if (rssi_level == DM_RATR_STA_HIGH) { 1029 rate_bitmap = 0x0f8f0000; 1030 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1031 rate_bitmap = 0x0f8ff000; 1032 } else { 1033 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1034 rate_bitmap = 0x0f8ff015; 1035 else 1036 rate_bitmap = 0x0f8ff005; 1037 } 1038 } 1039 break; 1040 default: 1041 /* case WIRELESS_11_24N: */ 1042 /* case WIRELESS_11_5N: */ 1043 if (pDM_Odm->RFType == RF_1T2R) 1044 rate_bitmap = 0x000fffff; 1045 else 1046 rate_bitmap = 0x0fffffff; 1047 break; 1048 } 1049 1050 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1051 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", 1052 rssi_level, WirelessMode, rate_bitmap)); 1053 1054 return rate_bitmap; 1055} 1056 1057/*----------------------------------------------------------------------------- 1058 * Function: odm_RefreshRateAdaptiveMask() 1059 * 1060 * Overview: Update rate table mask according to rssi 1061 * 1062 * Input: NONE 1063 * 1064 * Output: NONE 1065 * 1066 * Return: NONE 1067 * 1068 * Revised History: 1069 * When Who Remark 1070 * 05/27/2009 hpfan Create Version 0. 1071 * 1072 *---------------------------------------------------------------------------*/ 1073void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm) 1074{ 1075 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) 1076 return; 1077 /* */ 1078 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1079 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1080 /* HW dynamic mechanism. */ 1081 /* */ 1082 odm_RefreshRateAdaptiveMaskCE(pDM_Odm); 1083} 1084 1085void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm) 1086{ 1087} 1088 1089void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm) 1090{ 1091 u8 i; 1092 struct adapter *pAdapter = pDM_Odm->Adapter; 1093 1094 if (pAdapter->bDriverStopped) { 1095 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); 1096 return; 1097 } 1098 1099 if (!pDM_Odm->bUseRAMask) { 1100 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); 1101 return; 1102 } 1103 1104 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1105 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; 1106 if (IS_STA_VALID(pstat)) { 1107 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) { 1108 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1109 ("RSSI:%d, RSSI_LEVEL:%d\n", 1110 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); 1111 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level); 1112 } 1113 } 1114 } 1115} 1116 1117void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm) 1118{ 1119} 1120 1121/* Return Value: bool */ 1122/* - true: RATRState is changed. */ 1123bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState) 1124{ 1125 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive; 1126 const u8 GoUpGap = 5; 1127 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh; 1128 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; 1129 u8 RATRState; 1130 1131 /* Threshold Adjustment: */ 1132 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ 1133 /* Here GoUpGap is added to solve the boundary's level alternation issue. */ 1134 switch (*pRATRState) { 1135 case DM_RATR_STA_INIT: 1136 case DM_RATR_STA_HIGH: 1137 break; 1138 case DM_RATR_STA_MIDDLE: 1139 HighRSSIThreshForRA += GoUpGap; 1140 break; 1141 case DM_RATR_STA_LOW: 1142 HighRSSIThreshForRA += GoUpGap; 1143 LowRSSIThreshForRA += GoUpGap; 1144 break; 1145 default: 1146 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState)); 1147 break; 1148 } 1149 1150 /* Decide RATRState by RSSI. */ 1151 if (RSSI > HighRSSIThreshForRA) 1152 RATRState = DM_RATR_STA_HIGH; 1153 else if (RSSI > LowRSSIThreshForRA) 1154 RATRState = DM_RATR_STA_MIDDLE; 1155 else 1156 RATRState = DM_RATR_STA_LOW; 1157 1158 if (*pRATRState != RATRState || bForceUpdate) { 1159 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState)); 1160 *pRATRState = RATRState; 1161 return true; 1162 } 1163 return false; 1164} 1165 1166/* 3============================================================ */ 1167/* 3 Dynamic Tx Power */ 1168/* 3============================================================ */ 1169 1170void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm) 1171{ 1172 struct adapter *Adapter = pDM_Odm->Adapter; 1173 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1174 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1175 pdmpriv->bDynamicTxPowerEnable = false; 1176 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; 1177 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; 1178} 1179 1180void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm) 1181{ 1182 /* For AP/ADSL use struct rtl8192cd_priv * */ 1183 /* For CE/NIC use struct adapter * */ 1184 1185 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1186 return; 1187 1188 /* 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */ 1189 if (!pDM_Odm->ExtPA) 1190 return; 1191 1192 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1193 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1194 /* HW dynamic mechanism. */ 1195 odm_DynamicTxPowerNIC(pDM_Odm); 1196} 1197 1198void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm) 1199{ 1200} 1201 1202/* 3============================================================ */ 1203/* 3 RSSI Monitor */ 1204/* 3============================================================ */ 1205 1206void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm) 1207{ 1208 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) 1209 return; 1210 1211 /* */ 1212 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1213 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1214 /* HW dynamic mechanism. */ 1215 /* */ 1216 odm_RSSIMonitorCheckCE(pDM_Odm); 1217} /* odm_RSSIMonitorCheck */ 1218 1219static void FindMinimumRSSI(struct adapter *pAdapter) 1220{ 1221 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); 1222 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1223 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; 1224 1225 /* 1 1.Determine the minimum RSSI */ 1226 if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) && 1227 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) 1228 pdmpriv->MinUndecoratedPWDBForDM = 0; 1229 if (check_fwstate(pmlmepriv, _FW_LINKED) == true) /* Default port */ 1230 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1231 else /* associated entry pwdb */ 1232 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1233} 1234 1235void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm) 1236{ 1237 struct adapter *Adapter = pDM_Odm->Adapter; 1238 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1239 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1240 int i; 1241 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; 1242 u8 sta_cnt = 0; 1243 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ 1244 struct sta_info *psta; 1245 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 1246 1247 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) 1248 return; 1249 1250 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1251 psta = pDM_Odm->pODM_StaInfo[i]; 1252 if (IS_STA_VALID(psta) && 1253 (psta->state & WIFI_ASOC_STATE) && 1254 memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) && 1255 memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) { 1256 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) 1257 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1258 1259 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) 1260 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1261 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) 1262 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16)); 1263 } 1264 } 1265 1266 for (i = 0; i < sta_cnt; i++) { 1267 if (PWDB_rssi[i] != (0)) { 1268 if (pHalData->fw_ractrl) { 1269 /* Report every sta's RSSI to FW */ 1270 } else { 1271 ODM_RA_SetRSSI_8188E( 1272 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); 1273 } 1274 } 1275 } 1276 1277 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */ 1278 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; 1279 else 1280 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; 1281 1282 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */ 1283 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; 1284 else 1285 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; 1286 1287 FindMinimumRSSI(Adapter); 1288 ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); 1289} 1290 1291/* 3============================================================ */ 1292/* 3 Tx Power Tracking */ 1293/* 3============================================================ */ 1294 1295void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm) 1296{ 1297 odm_TXPowerTrackingThermalMeterInit(pDM_Odm); 1298} 1299 1300void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm) 1301{ 1302 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; 1303 pDM_Odm->RFCalibrateInfo.TXPowercount = 0; 1304 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; 1305 if (*(pDM_Odm->mp_mode) != 1) 1306 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1307 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); 1308 1309 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1310} 1311 1312void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm) 1313{ 1314 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1315 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1316 /* HW dynamic mechanism. */ 1317 odm_TXPowerTrackingCheckCE(pDM_Odm); 1318} 1319 1320void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 1321{ 1322 struct adapter *Adapter = pDM_Odm->Adapter; 1323 1324 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) 1325 return; 1326 1327 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ 1328 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); 1329 1330 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; 1331 return; 1332 } else { 1333 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); 1334 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; 1335 } 1336} 1337 1338/* antenna mapping info */ 1339/* 1: right-side antenna */ 1340/* 2/0: left-side antenna */ 1341/* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */ 1342/* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */ 1343/* We select left antenna as default antenna in initial process, modify it as needed */ 1344/* */ 1345 1346/* 3============================================================ */ 1347/* 3 SW Antenna Diversity */ 1348/* 3============================================================ */ 1349 1350void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) 1351{ 1352} 1353 1354/* 3============================================================ */ 1355/* 3 SW Antenna Diversity */ 1356/* 3============================================================ */ 1357 1358void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) 1359{ 1360 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1361 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1362 return; 1363 } 1364 1365 ODM_AntennaDiversityInit_88E(pDM_Odm); 1366} 1367 1368void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) 1369{ 1370 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1371 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1372 return; 1373 } 1374 1375 ODM_AntennaDiversity_88E(pDM_Odm); 1376} 1377 1378/* EDCA Turbo */ 1379void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) 1380{ 1381 struct adapter *Adapter = pDM_Odm->Adapter; 1382 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1383 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; 1384 Adapter->recvpriv.bIsAnyNonBEPkts = false; 1385 1386 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_VO_PARAM))); 1387 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_VI_PARAM))); 1388 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_BE_PARAM))); 1389 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_BK_PARAM))); 1390} /* ODM_InitEdcaTurbo */ 1391 1392void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm) 1393{ 1394 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1395 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1396 /* HW dynamic mechanism. */ 1397 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n")); 1398 1399 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)) 1400 return; 1401 1402 odm_EdcaTurboCheckCE(pDM_Odm); 1403 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n")); 1404} /* odm_CheckEdcaTurbo */ 1405 1406void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm) 1407{ 1408 struct adapter *Adapter = pDM_Odm->Adapter; 1409 u32 trafficIndex; 1410 u32 edca_param; 1411 u64 cur_tx_bytes = 0; 1412 u64 cur_rx_bytes = 0; 1413 u8 bbtchange = false; 1414 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1415 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); 1416 struct recv_priv *precvpriv = &(Adapter->recvpriv); 1417 struct registry_priv *pregpriv = &Adapter->registrypriv; 1418 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); 1419 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 1420 1421 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */ 1422 goto dm_CheckEdcaTurbo_EXIT; 1423 1424 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) 1425 goto dm_CheckEdcaTurbo_EXIT; 1426 1427 /* Check if the status needs to be changed. */ 1428 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) { 1429 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; 1430 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; 1431 1432 /* traffic, TX or RX */ 1433 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) || 1434 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { 1435 if (cur_tx_bytes > (cur_rx_bytes << 2)) { 1436 /* Uplink TP is present. */ 1437 trafficIndex = UP_LINK; 1438 } else { 1439 /* Balance TP is present. */ 1440 trafficIndex = DOWN_LINK; 1441 } 1442 } else { 1443 if (cur_rx_bytes > (cur_tx_bytes << 2)) { 1444 /* Downlink TP is present. */ 1445 trafficIndex = DOWN_LINK; 1446 } else { 1447 /* Balance TP is present. */ 1448 trafficIndex = UP_LINK; 1449 } 1450 } 1451 1452 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) { 1453 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) 1454 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; 1455 else 1456 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; 1457 1458 rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); 1459 1460 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; 1461 } 1462 1463 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; 1464 } else { 1465 /* Turn Off EDCA turbo here. */ 1466 /* Restore original EDCA according to the declaration of AP. */ 1467 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { 1468 rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); 1469 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1470 } 1471 } 1472 1473dm_CheckEdcaTurbo_EXIT: 1474 /* Set variables for next time. */ 1475 precvpriv->bIsAnyNonBEPkts = false; 1476 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; 1477 precvpriv->last_rx_bytes = precvpriv->rx_bytes; 1478} 1479 1480u32 ConvertTo_dB(u32 Value) 1481{ 1482 u8 i; 1483 u8 j; 1484 u32 dB; 1485 1486 Value = Value & 0xFFFF; 1487 for (i = 0; i < 8; i++) { 1488 if (Value <= dB_Invert_Table[i][11]) 1489 break; 1490 } 1491 1492 if (i >= 8) 1493 return 96; /* maximum 96 dB */ 1494 1495 for (j = 0; j < 12; j++) { 1496 if (Value <= dB_Invert_Table[i][j]) 1497 break; 1498 } 1499 1500 dB = i*12 + j + 1; 1501 1502 return dB; 1503} 1504