odm.c revision e02a0089f90859a6c435ad088454415bd19574ed
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21/* include files */ 22 23#include "odm_precomp.h" 24 25static const u16 dB_Invert_Table[8][12] = { 26 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, 27 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, 28 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63}, 29 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251}, 30 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000}, 31 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, 32 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849}, 33 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} 34}; 35 36/* avoid to warn in FreeBSD ==> To DO modify */ 37static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { 38 /* UL DL */ 39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ 40 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ 41 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ 42 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ 43 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ 44 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ 45 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ 46 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ 47 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ 48 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ 49}; 50 51/* Global var */ 52u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { 53 0x7f8001fe, /* 0, +6.0dB */ 54 0x788001e2, /* 1, +5.5dB */ 55 0x71c001c7, /* 2, +5.0dB */ 56 0x6b8001ae, /* 3, +4.5dB */ 57 0x65400195, /* 4, +4.0dB */ 58 0x5fc0017f, /* 5, +3.5dB */ 59 0x5a400169, /* 6, +3.0dB */ 60 0x55400155, /* 7, +2.5dB */ 61 0x50800142, /* 8, +2.0dB */ 62 0x4c000130, /* 9, +1.5dB */ 63 0x47c0011f, /* 10, +1.0dB */ 64 0x43c0010f, /* 11, +0.5dB */ 65 0x40000100, /* 12, +0dB */ 66 0x3c8000f2, /* 13, -0.5dB */ 67 0x390000e4, /* 14, -1.0dB */ 68 0x35c000d7, /* 15, -1.5dB */ 69 0x32c000cb, /* 16, -2.0dB */ 70 0x300000c0, /* 17, -2.5dB */ 71 0x2d4000b5, /* 18, -3.0dB */ 72 0x2ac000ab, /* 19, -3.5dB */ 73 0x288000a2, /* 20, -4.0dB */ 74 0x26000098, /* 21, -4.5dB */ 75 0x24000090, /* 22, -5.0dB */ 76 0x22000088, /* 23, -5.5dB */ 77 0x20000080, /* 24, -6.0dB */ 78 0x1e400079, /* 25, -6.5dB */ 79 0x1c800072, /* 26, -7.0dB */ 80 0x1b00006c, /* 27. -7.5dB */ 81 0x19800066, /* 28, -8.0dB */ 82 0x18000060, /* 29, -8.5dB */ 83 0x16c0005b, /* 30, -9.0dB */ 84 0x15800056, /* 31, -9.5dB */ 85 0x14400051, /* 32, -10.0dB */ 86 0x1300004c, /* 33, -10.5dB */ 87 0x12000048, /* 34, -11.0dB */ 88 0x11000044, /* 35, -11.5dB */ 89 0x10000040, /* 36, -12.0dB */ 90 0x0f00003c,/* 37, -12.5dB */ 91 0x0e400039,/* 38, -13.0dB */ 92 0x0d800036,/* 39, -13.5dB */ 93 0x0cc00033,/* 40, -14.0dB */ 94 0x0c000030,/* 41, -14.5dB */ 95 0x0b40002d,/* 42, -15.0dB */ 96}; 97 98u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { 99 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 100 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 101 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 102 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 103 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 104 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 105 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 106 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 107 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 108 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 109 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 110 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 111 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 112 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 113 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 114 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 115 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 116 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 117 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 118 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 119 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ 120 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ 121 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ 122 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ 123 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ 124 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ 125 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ 126 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ 127 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ 128 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ 129 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ 130 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ 131 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ 132}; 133 134u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { 135 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 136 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 137 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 138 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 139 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 140 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 141 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 142 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 143 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 144 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 145 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 146 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 147 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 148 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 149 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 150 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 151 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 152 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 153 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 154 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 155 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ 156 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ 157 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ 158 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ 159 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ 160 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ 161 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ 162 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ 163 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ 164 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ 165 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ 166 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ 167 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ 168}; 169 170 171#define RxDefaultAnt1 0x65a9 172#define RxDefaultAnt2 0x569a 173 174/* 3 Export Interface */ 175 176/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ 177void ODM_DMInit(struct odm_dm_struct *pDM_Odm) 178{ 179 /* 2012.05.03 Luke: For all IC series */ 180 odm_CommonInfoSelfInit(pDM_Odm); 181 odm_CmnInfoInit_Debug(pDM_Odm); 182 odm_DIGInit(pDM_Odm); 183 odm_RateAdaptiveMaskInit(pDM_Odm); 184 185 odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ 186 odm_DynamicBBPowerSavingInit(pDM_Odm); 187 odm_DynamicTxPowerInit(pDM_Odm); 188 odm_TXPowerTrackingInit(pDM_Odm); 189 ODM_EdcaTurboInit(pDM_Odm); 190 ODM_RAInfo_Init_all(pDM_Odm); 191 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 192 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 193 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 194 odm_InitHybridAntDiv(pDM_Odm); 195} 196 197/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ 198/* You can not add any dummy function here, be care, you can only use DM structure */ 199/* to perform any new ODM_DM. */ 200void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) 201{ 202 /* 2012.05.03 Luke: For all IC series */ 203 odm_CmnInfoHook_Debug(pDM_Odm); 204 odm_CmnInfoUpdate_Debug(pDM_Odm); 205 odm_CommonInfoSelfUpdate(pDM_Odm); 206 odm_FalseAlarmCounterStatistics(pDM_Odm); 207 odm_RSSIMonitorCheck(pDM_Odm); 208 209 /* For CE Platform(SPRD or Tablet) */ 210 /* 8723A or 8189ES platform */ 211 /* NeilChen--2012--08--24-- */ 212 /* Fix Leave LPS issue */ 213 if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */ 214 (pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) { 215 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n")); 216 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n")); 217 odm_DIGbyRSSI_LPS(pDM_Odm); 218 } else { 219 odm_DIG(pDM_Odm); 220 } 221 odm_CCKPacketDetectionThresh(pDM_Odm); 222 223 if (*(pDM_Odm->pbPowerSaving)) 224 return; 225 226 odm_RefreshRateAdaptiveMask(pDM_Odm); 227 228 odm_DynamicBBPowerSaving(pDM_Odm); 229 odm_DynamicPrimaryCCA(pDM_Odm); 230 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 231 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 232 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 233 odm_HwAntDiv(pDM_Odm); 234 235 ODM_TXPowerTrackingCheck(pDM_Odm); 236 odm_EdcaTurboCheck(pDM_Odm); 237 odm_DynamicTxPower(pDM_Odm); 238} 239 240/* Init /.. Fixed HW value. Only init time. */ 241void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value) 242{ 243 /* This section is used for init value */ 244 switch (CmnInfo) { 245 /* Fixed ODM value. */ 246 case ODM_CMNINFO_ABILITY: 247 pDM_Odm->SupportAbility = (u32)Value; 248 break; 249 case ODM_CMNINFO_PLATFORM: 250 pDM_Odm->SupportPlatform = (u8)Value; 251 break; 252 case ODM_CMNINFO_INTERFACE: 253 pDM_Odm->SupportInterface = (u8)Value; 254 break; 255 case ODM_CMNINFO_MP_TEST_CHIP: 256 pDM_Odm->bIsMPChip = (u8)Value; 257 break; 258 case ODM_CMNINFO_IC_TYPE: 259 pDM_Odm->SupportICType = Value; 260 break; 261 case ODM_CMNINFO_CUT_VER: 262 pDM_Odm->CutVersion = (u8)Value; 263 break; 264 case ODM_CMNINFO_FAB_VER: 265 pDM_Odm->FabVersion = (u8)Value; 266 break; 267 case ODM_CMNINFO_RF_TYPE: 268 pDM_Odm->RFType = (u8)Value; 269 break; 270 case ODM_CMNINFO_RF_ANTENNA_TYPE: 271 pDM_Odm->AntDivType = (u8)Value; 272 break; 273 case ODM_CMNINFO_BOARD_TYPE: 274 pDM_Odm->BoardType = (u8)Value; 275 break; 276 case ODM_CMNINFO_EXT_LNA: 277 pDM_Odm->ExtLNA = (u8)Value; 278 break; 279 case ODM_CMNINFO_EXT_PA: 280 pDM_Odm->ExtPA = (u8)Value; 281 break; 282 case ODM_CMNINFO_EXT_TRSW: 283 pDM_Odm->ExtTRSW = (u8)Value; 284 break; 285 case ODM_CMNINFO_PATCH_ID: 286 pDM_Odm->PatchID = (u8)Value; 287 break; 288 case ODM_CMNINFO_BINHCT_TEST: 289 pDM_Odm->bInHctTest = (bool)Value; 290 break; 291 case ODM_CMNINFO_BWIFI_TEST: 292 pDM_Odm->bWIFITest = (bool)Value; 293 break; 294 case ODM_CMNINFO_SMART_CONCURRENT: 295 pDM_Odm->bDualMacSmartConcurrent = (bool)Value; 296 break; 297 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 298 default: 299 /* do nothing */ 300 break; 301 } 302 303 /* Tx power tracking BB swing table. */ 304 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ 305 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */ 306 pDM_Odm->BbSwingIdxOfdmCurrent = 12; 307 pDM_Odm->BbSwingFlagOfdm = false; 308} 309 310void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue) 311{ 312 /* */ 313 /* Hook call by reference pointer. */ 314 /* */ 315 switch (CmnInfo) { 316 /* Dynamic call by reference pointer. */ 317 case ODM_CMNINFO_MAC_PHY_MODE: 318 pDM_Odm->pMacPhyMode = (u8 *)pValue; 319 break; 320 case ODM_CMNINFO_TX_UNI: 321 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue; 322 break; 323 case ODM_CMNINFO_RX_UNI: 324 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue; 325 break; 326 case ODM_CMNINFO_WM_MODE: 327 pDM_Odm->pWirelessMode = (u8 *)pValue; 328 break; 329 case ODM_CMNINFO_BAND: 330 pDM_Odm->pBandType = (u8 *)pValue; 331 break; 332 case ODM_CMNINFO_SEC_CHNL_OFFSET: 333 pDM_Odm->pSecChOffset = (u8 *)pValue; 334 break; 335 case ODM_CMNINFO_SEC_MODE: 336 pDM_Odm->pSecurity = (u8 *)pValue; 337 break; 338 case ODM_CMNINFO_BW: 339 pDM_Odm->pBandWidth = (u8 *)pValue; 340 break; 341 case ODM_CMNINFO_CHNL: 342 pDM_Odm->pChannel = (u8 *)pValue; 343 break; 344 case ODM_CMNINFO_DMSP_GET_VALUE: 345 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue; 346 break; 347 case ODM_CMNINFO_BUDDY_ADAPTOR: 348 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue; 349 break; 350 case ODM_CMNINFO_DMSP_IS_MASTER: 351 pDM_Odm->pbMasterOfDMSP = (bool *)pValue; 352 break; 353 case ODM_CMNINFO_SCAN: 354 pDM_Odm->pbScanInProcess = (bool *)pValue; 355 break; 356 case ODM_CMNINFO_POWER_SAVING: 357 pDM_Odm->pbPowerSaving = (bool *)pValue; 358 break; 359 case ODM_CMNINFO_ONE_PATH_CCA: 360 pDM_Odm->pOnePathCCA = (u8 *)pValue; 361 break; 362 case ODM_CMNINFO_DRV_STOP: 363 pDM_Odm->pbDriverStopped = (bool *)pValue; 364 break; 365 case ODM_CMNINFO_PNP_IN: 366 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue; 367 break; 368 case ODM_CMNINFO_INIT_ON: 369 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue; 370 break; 371 case ODM_CMNINFO_ANT_TEST: 372 pDM_Odm->pAntennaTest = (u8 *)pValue; 373 break; 374 case ODM_CMNINFO_NET_CLOSED: 375 pDM_Odm->pbNet_closed = (bool *)pValue; 376 break; 377 case ODM_CMNINFO_MP_MODE: 378 pDM_Odm->mp_mode = (u8 *)pValue; 379 break; 380 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 381 default: 382 /* do nothing */ 383 break; 384 } 385} 386 387void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue) 388{ 389 /* Hook call by reference pointer. */ 390 switch (CmnInfo) { 391 /* Dynamic call by reference pointer. */ 392 case ODM_CMNINFO_STA_STATUS: 393 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue; 394 break; 395 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 396 default: 397 /* do nothing */ 398 break; 399 } 400} 401 402/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ 403void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value) 404{ 405 /* */ 406 /* This init variable may be changed in run time. */ 407 /* */ 408 switch (CmnInfo) { 409 case ODM_CMNINFO_ABILITY: 410 pDM_Odm->SupportAbility = (u32)Value; 411 break; 412 case ODM_CMNINFO_RF_TYPE: 413 pDM_Odm->RFType = (u8)Value; 414 break; 415 case ODM_CMNINFO_WIFI_DIRECT: 416 pDM_Odm->bWIFI_Direct = (bool)Value; 417 break; 418 case ODM_CMNINFO_WIFI_DISPLAY: 419 pDM_Odm->bWIFI_Display = (bool)Value; 420 break; 421 case ODM_CMNINFO_LINK: 422 pDM_Odm->bLinked = (bool)Value; 423 break; 424 case ODM_CMNINFO_RSSI_MIN: 425 pDM_Odm->RSSI_Min = (u8)Value; 426 break; 427 case ODM_CMNINFO_DBG_COMP: 428 pDM_Odm->DebugComponents = Value; 429 break; 430 case ODM_CMNINFO_DBG_LEVEL: 431 pDM_Odm->DebugLevel = (u32)Value; 432 break; 433 case ODM_CMNINFO_RA_THRESHOLD_HIGH: 434 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value; 435 break; 436 case ODM_CMNINFO_RA_THRESHOLD_LOW: 437 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value; 438 break; 439 } 440} 441 442void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) 443{ 444 struct adapter *adapter = pDM_Odm->Adapter; 445 446 pDM_Odm->bCckHighPower = (bool) PHY_QueryBBReg(adapter, 0x824, BIT9); 447 pDM_Odm->RFPathRxEnable = (u8) PHY_QueryBBReg(adapter, 0xc04, 0x0F); 448 449 ODM_InitDebugSetting(pDM_Odm); 450} 451 452void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) 453{ 454 u8 EntryCnt = 0; 455 u8 i; 456 struct sta_info *pEntry; 457 458 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { 459 if (*(pDM_Odm->pSecChOffset) == 1) 460 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; 461 else if (*(pDM_Odm->pSecChOffset) == 2) 462 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; 463 } else { 464 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); 465 } 466 467 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 468 pEntry = pDM_Odm->pODM_StaInfo[i]; 469 if (IS_STA_VALID(pEntry)) 470 EntryCnt++; 471 } 472 if (EntryCnt == 1) 473 pDM_Odm->bOneEntryOnly = true; 474 else 475 pDM_Odm->bOneEntryOnly = false; 476} 477 478void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm) 479{ 480 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); 481 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform)); 482 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility)); 483 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface)); 484 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType)); 485 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion)); 486 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n", pDM_Odm->FabVersion)); 487 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n", pDM_Odm->RFType)); 488 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType)); 489 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA)); 490 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA)); 491 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW)); 492 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID)); 493 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest)); 494 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest)); 495 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent)); 496} 497 498void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm) 499{ 500 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); 501 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast))); 502 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast))); 503 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode))); 504 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset))); 505 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity))); 506 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth))); 507 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel))); 508 509 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess))); 510 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving))); 511} 512 513void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm) 514{ 515 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); 516 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct)); 517 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display)); 518 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked)); 519 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min)); 520} 521 522void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) 523{ 524 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 525 struct adapter *adapter = pDM_Odm->Adapter; 526 527 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 528 ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", 529 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm))); 530 531 if (pDM_DigTable->CurIGValue != CurrentIGI) { 532 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 533 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n", CurrentIGI)); 534 /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */ 535 pDM_DigTable->CurIGValue = CurrentIGI; 536 } 537 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x\n", CurrentIGI)); 538 539/* Add by Neil Chen to enable edcca to MP Platform */ 540} 541 542/* Need LPS mode for CE platform --2012--08--24--- */ 543/* 8723AS/8189ES */ 544void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm) 545{ 546 struct adapter *pAdapter = pDM_Odm->Adapter; 547 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 548 549 u8 RSSI_Lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */ 550 u8 bFwCurrentInPSMode = false; 551 u8 CurrentIGI = pDM_Odm->RSSI_Min; 552 553 CurrentIGI = CurrentIGI + RSSI_OFFSET_DIG; 554 bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode; 555 556 /* Using FW PS mode to make IGI */ 557 if (bFwCurrentInPSMode) { 558 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n")); 559 /* Adjust by FA in LPS MODE */ 560 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS) 561 CurrentIGI = CurrentIGI+2; 562 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) 563 CurrentIGI = CurrentIGI+1; 564 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) 565 CurrentIGI = CurrentIGI-1; 566 } else { 567 CurrentIGI = RSSI_Lower; 568 } 569 570 /* Lower bound checking */ 571 572 /* RSSI Lower bound check */ 573 if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) 574 RSSI_Lower = (pDM_Odm->RSSI_Min-10); 575 else 576 RSSI_Lower = DM_DIG_MIN_NIC; 577 578 /* Upper and Lower Bound checking */ 579 if (CurrentIGI > DM_DIG_MAX_NIC) 580 CurrentIGI = DM_DIG_MAX_NIC; 581 else if (CurrentIGI < RSSI_Lower) 582 CurrentIGI = RSSI_Lower; 583 584 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 585} 586 587void odm_DIGInit(struct odm_dm_struct *pDM_Odm) 588{ 589 struct adapter *adapter = pDM_Odm->Adapter; 590 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 591 592 pDM_DigTable->CurIGValue = (u8) PHY_QueryBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); 593 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; 594 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; 595 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW; 596 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH; 597 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) { 598 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 599 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 600 } else { 601 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 602 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 603 } 604 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; 605 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; 606 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; 607 pDM_DigTable->PreCCK_CCAThres = 0xFF; 608 pDM_DigTable->CurCCK_CCAThres = 0x83; 609 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; 610 pDM_DigTable->LargeFAHit = 0; 611 pDM_DigTable->Recover_cnt = 0; 612 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; 613 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; 614 pDM_DigTable->bMediaConnect_0 = false; 615 pDM_DigTable->bMediaConnect_1 = false; 616 617 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */ 618 pDM_Odm->bDMInitialGainEnable = true; 619} 620 621void odm_DIG(struct odm_dm_struct *pDM_Odm) 622{ 623 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 624 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 625 u8 DIG_Dynamic_MIN; 626 u8 DIG_MaxOfMin; 627 bool FirstConnect, FirstDisConnect; 628 u8 dm_dig_max, dm_dig_min; 629 u8 CurrentIGI = pDM_DigTable->CurIGValue; 630 631 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); 632 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) { 633 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 634 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); 635 return; 636 } 637 638 if (*(pDM_Odm->pbScanInProcess)) { 639 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n")); 640 return; 641 } 642 643 /* add by Neil Chen to avoid PSD is processing */ 644 if (pDM_Odm->bDMInitialGainEnable == false) { 645 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n")); 646 return; 647 } 648 649 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 650 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 651 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 652 653 /* 1 Boundary Decision */ 654 dm_dig_max = DM_DIG_MAX_NIC; 655 dm_dig_min = DM_DIG_MIN_NIC; 656 DIG_MaxOfMin = DM_DIG_MAX_AP; 657 658 if (pDM_Odm->bLinked) { 659 /* 2 Modify DIG upper bound */ 660 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) 661 pDM_DigTable->rx_gain_range_max = dm_dig_max; 662 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min) 663 pDM_DigTable->rx_gain_range_max = dm_dig_min; 664 else 665 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; 666 /* 2 Modify DIG lower bound */ 667 if (pDM_Odm->bOneEntryOnly) { 668 if (pDM_Odm->RSSI_Min < dm_dig_min) 669 DIG_Dynamic_MIN = dm_dig_min; 670 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) 671 DIG_Dynamic_MIN = DIG_MaxOfMin; 672 else 673 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; 674 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 675 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n", 676 DIG_Dynamic_MIN)); 677 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 678 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n", 679 pDM_Odm->RSSI_Min)); 680 } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) { 681 /* 1 Lower Bound for 88E AntDiv */ 682 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { 683 DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max; 684 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 685 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n", 686 pDM_DigTable->AntDiv_RSSI_max)); 687 } 688 } else { 689 DIG_Dynamic_MIN = dm_dig_min; 690 } 691 } else { 692 pDM_DigTable->rx_gain_range_max = dm_dig_max; 693 DIG_Dynamic_MIN = dm_dig_min; 694 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); 695 } 696 697 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ 698 if (pFalseAlmCnt->Cnt_all > 10000) { 699 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n")); 700 701 if (pDM_DigTable->LargeFAHit != 3) 702 pDM_DigTable->LargeFAHit++; 703 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { 704 pDM_DigTable->ForbiddenIGI = CurrentIGI; 705 pDM_DigTable->LargeFAHit = 1; 706 } 707 708 if (pDM_DigTable->LargeFAHit >= 3) { 709 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max) 710 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; 711 else 712 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 713 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ 714 } 715 716 } else { 717 /* Recovery mechanism for IGI lower bound */ 718 if (pDM_DigTable->Recover_cnt != 0) { 719 pDM_DigTable->Recover_cnt--; 720 } else { 721 if (pDM_DigTable->LargeFAHit < 3) { 722 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */ 723 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 724 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 725 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); 726 } else { 727 pDM_DigTable->ForbiddenIGI--; 728 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 729 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); 730 } 731 } else { 732 pDM_DigTable->LargeFAHit = 0; 733 } 734 } 735 } 736 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 737 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n", 738 pDM_DigTable->LargeFAHit)); 739 740 /* 1 Adjust initial gain by false alarm */ 741 if (pDM_Odm->bLinked) { 742 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); 743 if (FirstConnect) { 744 CurrentIGI = pDM_Odm->RSSI_Min; 745 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); 746 } else { 747 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) 748 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 749 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) 750 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 751 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) 752 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 753 } 754 } else { 755 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); 756 if (FirstDisConnect) { 757 CurrentIGI = pDM_DigTable->rx_gain_range_min; 758 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n")); 759 } else { 760 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ 761 if (pFalseAlmCnt->Cnt_all > 10000) 762 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 763 else if (pFalseAlmCnt->Cnt_all > 8000) 764 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 765 else if (pFalseAlmCnt->Cnt_all < 500) 766 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 767 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n")); 768 } 769 } 770 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); 771 /* 1 Check initial gain by upper/lower bound */ 772 if (CurrentIGI > pDM_DigTable->rx_gain_range_max) 773 CurrentIGI = pDM_DigTable->rx_gain_range_max; 774 if (CurrentIGI < pDM_DigTable->rx_gain_range_min) 775 CurrentIGI = pDM_DigTable->rx_gain_range_min; 776 777 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 778 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", 779 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); 780 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); 781 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); 782 783 /* 2 High power RSSI threshold */ 784 785 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 786 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; 787 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; 788} 789 790/* 3============================================================ */ 791/* 3 FASLE ALARM CHECK */ 792/* 3============================================================ */ 793 794void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 795{ 796 struct adapter *adapter = pDM_Odm->Adapter; 797 u32 ret_value; 798 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 799 800 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) 801 return; 802 803 /* hold ofdm counter */ 804 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ 805 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ 806 807 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); 808 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); 809 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); 810 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); 811 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); 812 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); 813 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); 814 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); 815 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); 816 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); 817 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); 818 819 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + 820 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + 821 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; 822 823 ret_value = PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); 824 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); 825 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); 826 827 /* hold cck counter */ 828 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); 829 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); 830 831 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); 832 FalseAlmCnt->Cnt_Cck_fail = ret_value; 833 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); 834 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8; 835 836 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); 837 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8); 838 839 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + 840 FalseAlmCnt->Cnt_SB_Search_fail + 841 FalseAlmCnt->Cnt_Parity_Fail + 842 FalseAlmCnt->Cnt_Rate_Illegal + 843 FalseAlmCnt->Cnt_Crc8_fail + 844 FalseAlmCnt->Cnt_Mcs_fail + 845 FalseAlmCnt->Cnt_Cck_fail); 846 847 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; 848 849 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); 850 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 851 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", 852 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); 853 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 854 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", 855 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); 856 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 857 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", 858 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); 859 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); 860 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); 861 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); 862} 863 864/* 3============================================================ */ 865/* 3 CCK Packet Detect Threshold */ 866/* 3============================================================ */ 867 868void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) 869{ 870 u8 CurCCK_CCAThres; 871 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 872 873 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) 874 return; 875 if (pDM_Odm->ExtLNA) 876 return; 877 if (pDM_Odm->bLinked) { 878 if (pDM_Odm->RSSI_Min > 25) { 879 CurCCK_CCAThres = 0xcd; 880 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) { 881 CurCCK_CCAThres = 0x83; 882 } else { 883 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 884 CurCCK_CCAThres = 0x83; 885 else 886 CurCCK_CCAThres = 0x40; 887 } 888 } else { 889 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 890 CurCCK_CCAThres = 0x83; 891 else 892 CurCCK_CCAThres = 0x40; 893 } 894 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); 895} 896 897void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres) 898{ 899 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 900 901 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ 902 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres); 903 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; 904 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; 905} 906 907/* 3============================================================ */ 908/* 3 BB Power Save */ 909/* 3============================================================ */ 910void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm) 911{ 912 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 913 914 pDM_PSTable->PreCCAState = CCA_MAX; 915 pDM_PSTable->CurCCAState = CCA_MAX; 916 pDM_PSTable->PreRFState = RF_MAX; 917 pDM_PSTable->CurRFState = RF_MAX; 918 pDM_PSTable->Rssi_val_min = 0; 919 pDM_PSTable->initialize = 0; 920} 921 922void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm) 923{ 924} 925 926void odm_1R_CCA(struct odm_dm_struct *pDM_Odm) 927{ 928 struct adapter *adapter = pDM_Odm->Adapter; 929 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 930 931 if (pDM_Odm->RSSI_Min != 0xFF) { 932 if (pDM_PSTable->PreCCAState == CCA_2R) { 933 if (pDM_Odm->RSSI_Min >= 35) 934 pDM_PSTable->CurCCAState = CCA_1R; 935 else 936 pDM_PSTable->CurCCAState = CCA_2R; 937 } else { 938 if (pDM_Odm->RSSI_Min <= 30) 939 pDM_PSTable->CurCCAState = CCA_2R; 940 else 941 pDM_PSTable->CurCCAState = CCA_1R; 942 } 943 } else { 944 pDM_PSTable->CurCCAState = CCA_MAX; 945 } 946 947 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) { 948 if (pDM_PSTable->CurCCAState == CCA_1R) { 949 if (pDM_Odm->RFType == ODM_2T2R) 950 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x13); 951 else 952 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x23); 953 } else { 954 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x33); 955 } 956 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; 957 } 958} 959 960void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 961{ 962 struct adapter *adapter = pDM_Odm->Adapter; 963 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 964 u8 Rssi_Up_bound = 30; 965 u8 Rssi_Low_bound = 25; 966 967 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */ 968 Rssi_Up_bound = 50; 969 Rssi_Low_bound = 45; 970 } 971 if (pDM_PSTable->initialize == 0) { 972 pDM_PSTable->Reg874 = (PHY_QueryBBReg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14; 973 pDM_PSTable->RegC70 = (PHY_QueryBBReg(adapter, 0xc70, bMaskDWord)&BIT3)>>3; 974 pDM_PSTable->Reg85C = (PHY_QueryBBReg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; 975 pDM_PSTable->RegA74 = (PHY_QueryBBReg(adapter, 0xa74, bMaskDWord)&0xF000)>>12; 976 pDM_PSTable->initialize = 1; 977 } 978 979 if (!bForceInNormal) { 980 if (pDM_Odm->RSSI_Min != 0xFF) { 981 if (pDM_PSTable->PreRFState == RF_Normal) { 982 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound) 983 pDM_PSTable->CurRFState = RF_Save; 984 else 985 pDM_PSTable->CurRFState = RF_Normal; 986 } else { 987 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound) 988 pDM_PSTable->CurRFState = RF_Normal; 989 else 990 pDM_PSTable->CurRFState = RF_Save; 991 } 992 } else { 993 pDM_PSTable->CurRFState = RF_MAX; 994 } 995 } else { 996 pDM_PSTable->CurRFState = RF_Normal; 997 } 998 999 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { 1000 if (pDM_PSTable->CurRFState == RF_Save) { 1001 PHY_SetBBReg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ 1002 PHY_SetBBReg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ 1003 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ 1004 PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ 1005 PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ 1006 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ 1007 PHY_SetBBReg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ 1008 } else { 1009 PHY_SetBBReg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); 1010 PHY_SetBBReg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); 1011 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); 1012 PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); 1013 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); 1014 } 1015 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; 1016 } 1017} 1018 1019/* 3============================================================ */ 1020/* 3 RATR MASK */ 1021/* 3============================================================ */ 1022/* 3============================================================ */ 1023/* 3 Rate Adaptive */ 1024/* 3============================================================ */ 1025 1026void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm) 1027{ 1028 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive; 1029 1030 pOdmRA->Type = DM_Type_ByDriver; 1031 if (pOdmRA->Type == DM_Type_ByDriver) 1032 pDM_Odm->bUseRAMask = true; 1033 else 1034 pDM_Odm->bUseRAMask = false; 1035 1036 pOdmRA->RATRState = DM_RATR_STA_INIT; 1037 pOdmRA->HighRSSIThresh = 50; 1038 pOdmRA->LowRSSIThresh = 20; 1039} 1040 1041u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level) 1042{ 1043 struct sta_info *pEntry; 1044 u32 rate_bitmap = 0x0fffffff; 1045 u8 WirelessMode; 1046 1047 pEntry = pDM_Odm->pODM_StaInfo[macid]; 1048 if (!IS_STA_VALID(pEntry)) 1049 return ra_mask; 1050 1051 WirelessMode = pEntry->wireless_mode; 1052 1053 switch (WirelessMode) { 1054 case ODM_WM_B: 1055 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ 1056 rate_bitmap = 0x0000000d; 1057 else 1058 rate_bitmap = 0x0000000f; 1059 break; 1060 case (ODM_WM_A|ODM_WM_G): 1061 if (rssi_level == DM_RATR_STA_HIGH) 1062 rate_bitmap = 0x00000f00; 1063 else 1064 rate_bitmap = 0x00000ff0; 1065 break; 1066 case (ODM_WM_B|ODM_WM_G): 1067 if (rssi_level == DM_RATR_STA_HIGH) 1068 rate_bitmap = 0x00000f00; 1069 else if (rssi_level == DM_RATR_STA_MIDDLE) 1070 rate_bitmap = 0x00000ff0; 1071 else 1072 rate_bitmap = 0x00000ff5; 1073 break; 1074 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1075 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1076 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { 1077 if (rssi_level == DM_RATR_STA_HIGH) { 1078 rate_bitmap = 0x000f0000; 1079 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1080 rate_bitmap = 0x000ff000; 1081 } else { 1082 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1083 rate_bitmap = 0x000ff015; 1084 else 1085 rate_bitmap = 0x000ff005; 1086 } 1087 } else { 1088 if (rssi_level == DM_RATR_STA_HIGH) { 1089 rate_bitmap = 0x0f8f0000; 1090 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1091 rate_bitmap = 0x0f8ff000; 1092 } else { 1093 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1094 rate_bitmap = 0x0f8ff015; 1095 else 1096 rate_bitmap = 0x0f8ff005; 1097 } 1098 } 1099 break; 1100 default: 1101 /* case WIRELESS_11_24N: */ 1102 /* case WIRELESS_11_5N: */ 1103 if (pDM_Odm->RFType == RF_1T2R) 1104 rate_bitmap = 0x000fffff; 1105 else 1106 rate_bitmap = 0x0fffffff; 1107 break; 1108 } 1109 1110 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1111 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", 1112 rssi_level, WirelessMode, rate_bitmap)); 1113 1114 return rate_bitmap; 1115} 1116 1117/*----------------------------------------------------------------------------- 1118 * Function: odm_RefreshRateAdaptiveMask() 1119 * 1120 * Overview: Update rate table mask according to rssi 1121 * 1122 * Input: NONE 1123 * 1124 * Output: NONE 1125 * 1126 * Return: NONE 1127 * 1128 * Revised History: 1129 * When Who Remark 1130 * 05/27/2009 hpfan Create Version 0. 1131 * 1132 *---------------------------------------------------------------------------*/ 1133void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm) 1134{ 1135 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) 1136 return; 1137 /* */ 1138 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1139 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1140 /* HW dynamic mechanism. */ 1141 /* */ 1142 odm_RefreshRateAdaptiveMaskCE(pDM_Odm); 1143} 1144 1145void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm) 1146{ 1147} 1148 1149void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm) 1150{ 1151 u8 i; 1152 struct adapter *pAdapter = pDM_Odm->Adapter; 1153 1154 if (pAdapter->bDriverStopped) { 1155 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); 1156 return; 1157 } 1158 1159 if (!pDM_Odm->bUseRAMask) { 1160 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); 1161 return; 1162 } 1163 1164 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1165 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; 1166 if (IS_STA_VALID(pstat)) { 1167 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) { 1168 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1169 ("RSSI:%d, RSSI_LEVEL:%d\n", 1170 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); 1171 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level); 1172 } 1173 } 1174 } 1175} 1176 1177void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm) 1178{ 1179} 1180 1181/* Return Value: bool */ 1182/* - true: RATRState is changed. */ 1183bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState) 1184{ 1185 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive; 1186 const u8 GoUpGap = 5; 1187 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh; 1188 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; 1189 u8 RATRState; 1190 1191 /* Threshold Adjustment: */ 1192 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ 1193 /* Here GoUpGap is added to solve the boundary's level alternation issue. */ 1194 switch (*pRATRState) { 1195 case DM_RATR_STA_INIT: 1196 case DM_RATR_STA_HIGH: 1197 break; 1198 case DM_RATR_STA_MIDDLE: 1199 HighRSSIThreshForRA += GoUpGap; 1200 break; 1201 case DM_RATR_STA_LOW: 1202 HighRSSIThreshForRA += GoUpGap; 1203 LowRSSIThreshForRA += GoUpGap; 1204 break; 1205 default: 1206 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState)); 1207 break; 1208 } 1209 1210 /* Decide RATRState by RSSI. */ 1211 if (RSSI > HighRSSIThreshForRA) 1212 RATRState = DM_RATR_STA_HIGH; 1213 else if (RSSI > LowRSSIThreshForRA) 1214 RATRState = DM_RATR_STA_MIDDLE; 1215 else 1216 RATRState = DM_RATR_STA_LOW; 1217 1218 if (*pRATRState != RATRState || bForceUpdate) { 1219 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState)); 1220 *pRATRState = RATRState; 1221 return true; 1222 } 1223 return false; 1224} 1225 1226/* 3============================================================ */ 1227/* 3 Dynamic Tx Power */ 1228/* 3============================================================ */ 1229 1230void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm) 1231{ 1232 struct adapter *Adapter = pDM_Odm->Adapter; 1233 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1234 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1235 pdmpriv->bDynamicTxPowerEnable = false; 1236 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; 1237 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; 1238} 1239 1240void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm) 1241{ 1242 /* For AP/ADSL use struct rtl8192cd_priv * */ 1243 /* For CE/NIC use struct adapter * */ 1244 1245 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1246 return; 1247 1248 /* 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */ 1249 if (!pDM_Odm->ExtPA) 1250 return; 1251 1252 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1253 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1254 /* HW dynamic mechanism. */ 1255 odm_DynamicTxPowerNIC(pDM_Odm); 1256} 1257 1258void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm) 1259{ 1260} 1261 1262/* 3============================================================ */ 1263/* 3 RSSI Monitor */ 1264/* 3============================================================ */ 1265 1266void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm) 1267{ 1268 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) 1269 return; 1270 1271 /* */ 1272 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1273 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1274 /* HW dynamic mechanism. */ 1275 /* */ 1276 odm_RSSIMonitorCheckCE(pDM_Odm); 1277} /* odm_RSSIMonitorCheck */ 1278 1279static void FindMinimumRSSI(struct adapter *pAdapter) 1280{ 1281 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); 1282 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1283 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; 1284 1285 /* 1 1.Determine the minimum RSSI */ 1286 if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) && 1287 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) 1288 pdmpriv->MinUndecoratedPWDBForDM = 0; 1289 if (check_fwstate(pmlmepriv, _FW_LINKED) == true) /* Default port */ 1290 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1291 else /* associated entry pwdb */ 1292 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1293} 1294 1295void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm) 1296{ 1297 struct adapter *Adapter = pDM_Odm->Adapter; 1298 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1299 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1300 int i; 1301 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; 1302 u8 sta_cnt = 0; 1303 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ 1304 struct sta_info *psta; 1305 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 1306 1307 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) 1308 return; 1309 1310 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1311 psta = pDM_Odm->pODM_StaInfo[i]; 1312 if (IS_STA_VALID(psta) && 1313 (psta->state & WIFI_ASOC_STATE) && 1314 !_rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) && 1315 !_rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) { 1316 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) 1317 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1318 1319 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) 1320 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1321 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) 1322 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16)); 1323 } 1324 } 1325 1326 for (i = 0; i < sta_cnt; i++) { 1327 if (PWDB_rssi[i] != (0)) { 1328 if (pHalData->fw_ractrl) { 1329 /* Report every sta's RSSI to FW */ 1330 } else { 1331 ODM_RA_SetRSSI_8188E( 1332 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); 1333 } 1334 } 1335 } 1336 1337 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */ 1338 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; 1339 else 1340 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; 1341 1342 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */ 1343 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; 1344 else 1345 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; 1346 1347 FindMinimumRSSI(Adapter); 1348 ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); 1349} 1350 1351/* 3============================================================ */ 1352/* 3 Tx Power Tracking */ 1353/* 3============================================================ */ 1354 1355void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm) 1356{ 1357 odm_TXPowerTrackingThermalMeterInit(pDM_Odm); 1358} 1359 1360void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm) 1361{ 1362 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; 1363 pDM_Odm->RFCalibrateInfo.TXPowercount = 0; 1364 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; 1365 if (*(pDM_Odm->mp_mode) != 1) 1366 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1367 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); 1368 1369 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1370} 1371 1372void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm) 1373{ 1374 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1375 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1376 /* HW dynamic mechanism. */ 1377 odm_TXPowerTrackingCheckCE(pDM_Odm); 1378} 1379 1380void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 1381{ 1382 struct adapter *Adapter = pDM_Odm->Adapter; 1383 1384 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) 1385 return; 1386 1387 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ 1388 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); 1389 1390 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; 1391 return; 1392 } else { 1393 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); 1394 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; 1395 } 1396} 1397 1398/* antenna mapping info */ 1399/* 1: right-side antenna */ 1400/* 2/0: left-side antenna */ 1401/* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */ 1402/* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */ 1403/* We select left antenna as default antenna in initial process, modify it as needed */ 1404/* */ 1405 1406/* 3============================================================ */ 1407/* 3 SW Antenna Diversity */ 1408/* 3============================================================ */ 1409 1410void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) 1411{ 1412} 1413 1414/* 3============================================================ */ 1415/* 3 SW Antenna Diversity */ 1416/* 3============================================================ */ 1417 1418void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) 1419{ 1420 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1421 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1422 return; 1423 } 1424 1425 ODM_AntennaDiversityInit_88E(pDM_Odm); 1426} 1427 1428void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) 1429{ 1430 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1431 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1432 return; 1433 } 1434 1435 ODM_AntennaDiversity_88E(pDM_Odm); 1436} 1437 1438/* EDCA Turbo */ 1439void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) 1440{ 1441 struct adapter *Adapter = pDM_Odm->Adapter; 1442 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1443 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; 1444 Adapter->recvpriv.bIsAnyNonBEPkts = false; 1445 1446 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM))); 1447 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM))); 1448 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM))); 1449 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM))); 1450} /* ODM_InitEdcaTurbo */ 1451 1452void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm) 1453{ 1454 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1455 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1456 /* HW dynamic mechanism. */ 1457 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n")); 1458 1459 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)) 1460 return; 1461 1462 odm_EdcaTurboCheckCE(pDM_Odm); 1463 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n")); 1464} /* odm_CheckEdcaTurbo */ 1465 1466void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm) 1467{ 1468 struct adapter *Adapter = pDM_Odm->Adapter; 1469 u32 trafficIndex; 1470 u32 edca_param; 1471 u64 cur_tx_bytes = 0; 1472 u64 cur_rx_bytes = 0; 1473 u8 bbtchange = false; 1474 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1475 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); 1476 struct recv_priv *precvpriv = &(Adapter->recvpriv); 1477 struct registry_priv *pregpriv = &Adapter->registrypriv; 1478 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); 1479 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 1480 1481 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */ 1482 goto dm_CheckEdcaTurbo_EXIT; 1483 1484 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) 1485 goto dm_CheckEdcaTurbo_EXIT; 1486 1487 /* Check if the status needs to be changed. */ 1488 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) { 1489 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; 1490 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; 1491 1492 /* traffic, TX or RX */ 1493 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) || 1494 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { 1495 if (cur_tx_bytes > (cur_rx_bytes << 2)) { 1496 /* Uplink TP is present. */ 1497 trafficIndex = UP_LINK; 1498 } else { 1499 /* Balance TP is present. */ 1500 trafficIndex = DOWN_LINK; 1501 } 1502 } else { 1503 if (cur_rx_bytes > (cur_tx_bytes << 2)) { 1504 /* Downlink TP is present. */ 1505 trafficIndex = DOWN_LINK; 1506 } else { 1507 /* Balance TP is present. */ 1508 trafficIndex = UP_LINK; 1509 } 1510 } 1511 1512 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) { 1513 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) 1514 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; 1515 else 1516 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; 1517 1518 rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); 1519 1520 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; 1521 } 1522 1523 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; 1524 } else { 1525 /* Turn Off EDCA turbo here. */ 1526 /* Restore original EDCA according to the declaration of AP. */ 1527 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { 1528 rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); 1529 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1530 } 1531 } 1532 1533dm_CheckEdcaTurbo_EXIT: 1534 /* Set variables for next time. */ 1535 precvpriv->bIsAnyNonBEPkts = false; 1536 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; 1537 precvpriv->last_rx_bytes = precvpriv->rx_bytes; 1538} 1539 1540u32 ConvertTo_dB(u32 Value) 1541{ 1542 u8 i; 1543 u8 j; 1544 u32 dB; 1545 1546 Value = Value & 0xFFFF; 1547 for (i = 0; i < 8; i++) { 1548 if (Value <= dB_Invert_Table[i][11]) 1549 break; 1550 } 1551 1552 if (i >= 8) 1553 return 96; /* maximum 96 dB */ 1554 1555 for (j = 0; j < 12; j++) { 1556 if (Value <= dB_Invert_Table[i][j]) 1557 break; 1558 } 1559 1560 dB = i*12 + j + 1; 1561 1562 return dB; 1563} 1564