odm.c revision e690895a16e884a7885bc7f4378e68825ecafef3
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21/* include files */ 22 23#include "odm_precomp.h" 24 25static const u16 dB_Invert_Table[8][12] = { 26 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, 27 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, 28 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63}, 29 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251}, 30 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000}, 31 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, 32 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849}, 33 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} 34}; 35 36/* avoid to warn in FreeBSD ==> To DO modify */ 37static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { 38 /* UL DL */ 39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ 40 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ 41 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ 42 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ 43 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ 44 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ 45 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ 46 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ 47 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ 48 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ 49}; 50 51/* Global var */ 52u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { 53 0x7f8001fe, /* 0, +6.0dB */ 54 0x788001e2, /* 1, +5.5dB */ 55 0x71c001c7, /* 2, +5.0dB */ 56 0x6b8001ae, /* 3, +4.5dB */ 57 0x65400195, /* 4, +4.0dB */ 58 0x5fc0017f, /* 5, +3.5dB */ 59 0x5a400169, /* 6, +3.0dB */ 60 0x55400155, /* 7, +2.5dB */ 61 0x50800142, /* 8, +2.0dB */ 62 0x4c000130, /* 9, +1.5dB */ 63 0x47c0011f, /* 10, +1.0dB */ 64 0x43c0010f, /* 11, +0.5dB */ 65 0x40000100, /* 12, +0dB */ 66 0x3c8000f2, /* 13, -0.5dB */ 67 0x390000e4, /* 14, -1.0dB */ 68 0x35c000d7, /* 15, -1.5dB */ 69 0x32c000cb, /* 16, -2.0dB */ 70 0x300000c0, /* 17, -2.5dB */ 71 0x2d4000b5, /* 18, -3.0dB */ 72 0x2ac000ab, /* 19, -3.5dB */ 73 0x288000a2, /* 20, -4.0dB */ 74 0x26000098, /* 21, -4.5dB */ 75 0x24000090, /* 22, -5.0dB */ 76 0x22000088, /* 23, -5.5dB */ 77 0x20000080, /* 24, -6.0dB */ 78 0x1e400079, /* 25, -6.5dB */ 79 0x1c800072, /* 26, -7.0dB */ 80 0x1b00006c, /* 27. -7.5dB */ 81 0x19800066, /* 28, -8.0dB */ 82 0x18000060, /* 29, -8.5dB */ 83 0x16c0005b, /* 30, -9.0dB */ 84 0x15800056, /* 31, -9.5dB */ 85 0x14400051, /* 32, -10.0dB */ 86 0x1300004c, /* 33, -10.5dB */ 87 0x12000048, /* 34, -11.0dB */ 88 0x11000044, /* 35, -11.5dB */ 89 0x10000040, /* 36, -12.0dB */ 90 0x0f00003c,/* 37, -12.5dB */ 91 0x0e400039,/* 38, -13.0dB */ 92 0x0d800036,/* 39, -13.5dB */ 93 0x0cc00033,/* 40, -14.0dB */ 94 0x0c000030,/* 41, -14.5dB */ 95 0x0b40002d,/* 42, -15.0dB */ 96}; 97 98u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { 99 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 100 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 101 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 102 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 103 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 104 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 105 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 106 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 107 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 108 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 109 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 110 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 111 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 112 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 113 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 114 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 115 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 116 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 117 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 118 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 119 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ 120 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ 121 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ 122 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ 123 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ 124 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ 125 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ 126 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ 127 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ 128 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ 129 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ 130 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ 131 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ 132}; 133 134u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { 135 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 136 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 137 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 138 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 139 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 140 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 141 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 142 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 143 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 144 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 145 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 146 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 147 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 148 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 149 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 150 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 151 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 152 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 153 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 154 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 155 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ 156 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ 157 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ 158 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ 159 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ 160 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ 161 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ 162 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ 163 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ 164 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ 165 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ 166 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ 167 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ 168}; 169 170 171#define RxDefaultAnt1 0x65a9 172#define RxDefaultAnt2 0x569a 173 174/* 3 Export Interface */ 175 176/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ 177void ODM_DMInit(struct odm_dm_struct *pDM_Odm) 178{ 179 /* 2012.05.03 Luke: For all IC series */ 180 odm_CommonInfoSelfInit(pDM_Odm); 181 odm_CmnInfoInit_Debug(pDM_Odm); 182 odm_DIGInit(pDM_Odm); 183 odm_RateAdaptiveMaskInit(pDM_Odm); 184 185 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { 186 ; 187 } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { 188 odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ 189 odm_DynamicBBPowerSavingInit(pDM_Odm); 190 odm_DynamicTxPowerInit(pDM_Odm); 191 odm_TXPowerTrackingInit(pDM_Odm); 192 ODM_EdcaTurboInit(pDM_Odm); 193 ODM_RAInfo_Init_all(pDM_Odm); 194 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 195 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 196 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 197 odm_InitHybridAntDiv(pDM_Odm); 198 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV) 199 odm_SwAntDivInit(pDM_Odm); 200 } 201} 202 203/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ 204/* You can not add any dummy function here, be care, you can only use DM structure */ 205/* to perform any new ODM_DM. */ 206void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) 207{ 208 /* 2012.05.03 Luke: For all IC series */ 209 odm_GlobalAdapterCheck(); 210 odm_CmnInfoHook_Debug(pDM_Odm); 211 odm_CmnInfoUpdate_Debug(pDM_Odm); 212 odm_CommonInfoSelfUpdate(pDM_Odm); 213 odm_FalseAlarmCounterStatistics(pDM_Odm); 214 odm_RSSIMonitorCheck(pDM_Odm); 215 216 /* For CE Platform(SPRD or Tablet) */ 217 /* 8723A or 8189ES platform */ 218 /* NeilChen--2012--08--24-- */ 219 /* Fix Leave LPS issue */ 220 if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */ 221 ((pDM_Odm->SupportICType & (ODM_RTL8723A)) || 222 (pDM_Odm->SupportICType & (ODM_RTL8188E) && 223 ((pDM_Odm->SupportInterface == ODM_ITRF_SDIO))))) { 224 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n")); 225 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n")); 226 odm_DIGbyRSSI_LPS(pDM_Odm); 227 } else { 228 odm_DIG(pDM_Odm); 229 } 230 odm_CCKPacketDetectionThresh(pDM_Odm); 231 232 if (*(pDM_Odm->pbPowerSaving)) 233 return; 234 235 odm_RefreshRateAdaptiveMask(pDM_Odm); 236 237 odm_DynamicBBPowerSaving(pDM_Odm); 238 odm_DynamicPrimaryCCA(pDM_Odm); 239 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 240 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 241 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 242 odm_HwAntDiv(pDM_Odm); 243 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV) 244 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK); 245 246 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { 247 ; 248 } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { 249 ODM_TXPowerTrackingCheck(pDM_Odm); 250 odm_EdcaTurboCheck(pDM_Odm); 251 odm_DynamicTxPower(pDM_Odm); 252 } 253 odm_dtc(pDM_Odm); 254} 255 256/* Init /.. Fixed HW value. Only init time. */ 257void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value) 258{ 259 /* This section is used for init value */ 260 switch (CmnInfo) { 261 /* Fixed ODM value. */ 262 case ODM_CMNINFO_ABILITY: 263 pDM_Odm->SupportAbility = (u32)Value; 264 break; 265 case ODM_CMNINFO_PLATFORM: 266 pDM_Odm->SupportPlatform = (u8)Value; 267 break; 268 case ODM_CMNINFO_INTERFACE: 269 pDM_Odm->SupportInterface = (u8)Value; 270 break; 271 case ODM_CMNINFO_MP_TEST_CHIP: 272 pDM_Odm->bIsMPChip = (u8)Value; 273 break; 274 case ODM_CMNINFO_IC_TYPE: 275 pDM_Odm->SupportICType = Value; 276 break; 277 case ODM_CMNINFO_CUT_VER: 278 pDM_Odm->CutVersion = (u8)Value; 279 break; 280 case ODM_CMNINFO_FAB_VER: 281 pDM_Odm->FabVersion = (u8)Value; 282 break; 283 case ODM_CMNINFO_RF_TYPE: 284 pDM_Odm->RFType = (u8)Value; 285 break; 286 case ODM_CMNINFO_RF_ANTENNA_TYPE: 287 pDM_Odm->AntDivType = (u8)Value; 288 break; 289 case ODM_CMNINFO_BOARD_TYPE: 290 pDM_Odm->BoardType = (u8)Value; 291 break; 292 case ODM_CMNINFO_EXT_LNA: 293 pDM_Odm->ExtLNA = (u8)Value; 294 break; 295 case ODM_CMNINFO_EXT_PA: 296 pDM_Odm->ExtPA = (u8)Value; 297 break; 298 case ODM_CMNINFO_EXT_TRSW: 299 pDM_Odm->ExtTRSW = (u8)Value; 300 break; 301 case ODM_CMNINFO_PATCH_ID: 302 pDM_Odm->PatchID = (u8)Value; 303 break; 304 case ODM_CMNINFO_BINHCT_TEST: 305 pDM_Odm->bInHctTest = (bool)Value; 306 break; 307 case ODM_CMNINFO_BWIFI_TEST: 308 pDM_Odm->bWIFITest = (bool)Value; 309 break; 310 case ODM_CMNINFO_SMART_CONCURRENT: 311 pDM_Odm->bDualMacSmartConcurrent = (bool)Value; 312 break; 313 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 314 default: 315 /* do nothing */ 316 break; 317 } 318 319 /* Tx power tracking BB swing table. */ 320 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ 321 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */ 322 pDM_Odm->BbSwingIdxOfdmCurrent = 12; 323 pDM_Odm->BbSwingFlagOfdm = false; 324} 325 326void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue) 327{ 328 /* */ 329 /* Hook call by reference pointer. */ 330 /* */ 331 switch (CmnInfo) { 332 /* Dynamic call by reference pointer. */ 333 case ODM_CMNINFO_MAC_PHY_MODE: 334 pDM_Odm->pMacPhyMode = (u8 *)pValue; 335 break; 336 case ODM_CMNINFO_TX_UNI: 337 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue; 338 break; 339 case ODM_CMNINFO_RX_UNI: 340 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue; 341 break; 342 case ODM_CMNINFO_WM_MODE: 343 pDM_Odm->pWirelessMode = (u8 *)pValue; 344 break; 345 case ODM_CMNINFO_BAND: 346 pDM_Odm->pBandType = (u8 *)pValue; 347 break; 348 case ODM_CMNINFO_SEC_CHNL_OFFSET: 349 pDM_Odm->pSecChOffset = (u8 *)pValue; 350 break; 351 case ODM_CMNINFO_SEC_MODE: 352 pDM_Odm->pSecurity = (u8 *)pValue; 353 break; 354 case ODM_CMNINFO_BW: 355 pDM_Odm->pBandWidth = (u8 *)pValue; 356 break; 357 case ODM_CMNINFO_CHNL: 358 pDM_Odm->pChannel = (u8 *)pValue; 359 break; 360 case ODM_CMNINFO_DMSP_GET_VALUE: 361 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue; 362 break; 363 case ODM_CMNINFO_BUDDY_ADAPTOR: 364 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue; 365 break; 366 case ODM_CMNINFO_DMSP_IS_MASTER: 367 pDM_Odm->pbMasterOfDMSP = (bool *)pValue; 368 break; 369 case ODM_CMNINFO_SCAN: 370 pDM_Odm->pbScanInProcess = (bool *)pValue; 371 break; 372 case ODM_CMNINFO_POWER_SAVING: 373 pDM_Odm->pbPowerSaving = (bool *)pValue; 374 break; 375 case ODM_CMNINFO_ONE_PATH_CCA: 376 pDM_Odm->pOnePathCCA = (u8 *)pValue; 377 break; 378 case ODM_CMNINFO_DRV_STOP: 379 pDM_Odm->pbDriverStopped = (bool *)pValue; 380 break; 381 case ODM_CMNINFO_PNP_IN: 382 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue; 383 break; 384 case ODM_CMNINFO_INIT_ON: 385 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue; 386 break; 387 case ODM_CMNINFO_ANT_TEST: 388 pDM_Odm->pAntennaTest = (u8 *)pValue; 389 break; 390 case ODM_CMNINFO_NET_CLOSED: 391 pDM_Odm->pbNet_closed = (bool *)pValue; 392 break; 393 case ODM_CMNINFO_MP_MODE: 394 pDM_Odm->mp_mode = (u8 *)pValue; 395 break; 396 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 397 default: 398 /* do nothing */ 399 break; 400 } 401} 402 403void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue) 404{ 405 /* Hook call by reference pointer. */ 406 switch (CmnInfo) { 407 /* Dynamic call by reference pointer. */ 408 case ODM_CMNINFO_STA_STATUS: 409 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue; 410 break; 411 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 412 default: 413 /* do nothing */ 414 break; 415 } 416} 417 418/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ 419void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value) 420{ 421 /* */ 422 /* This init variable may be changed in run time. */ 423 /* */ 424 switch (CmnInfo) { 425 case ODM_CMNINFO_ABILITY: 426 pDM_Odm->SupportAbility = (u32)Value; 427 break; 428 case ODM_CMNINFO_RF_TYPE: 429 pDM_Odm->RFType = (u8)Value; 430 break; 431 case ODM_CMNINFO_WIFI_DIRECT: 432 pDM_Odm->bWIFI_Direct = (bool)Value; 433 break; 434 case ODM_CMNINFO_WIFI_DISPLAY: 435 pDM_Odm->bWIFI_Display = (bool)Value; 436 break; 437 case ODM_CMNINFO_LINK: 438 pDM_Odm->bLinked = (bool)Value; 439 break; 440 case ODM_CMNINFO_RSSI_MIN: 441 pDM_Odm->RSSI_Min = (u8)Value; 442 break; 443 case ODM_CMNINFO_DBG_COMP: 444 pDM_Odm->DebugComponents = Value; 445 break; 446 case ODM_CMNINFO_DBG_LEVEL: 447 pDM_Odm->DebugLevel = (u32)Value; 448 break; 449 case ODM_CMNINFO_RA_THRESHOLD_HIGH: 450 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value; 451 break; 452 case ODM_CMNINFO_RA_THRESHOLD_LOW: 453 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value; 454 break; 455 } 456} 457 458void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) 459{ 460 pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT9); 461 pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F); 462 if (pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D)) 463 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; 464 if (pDM_Odm->SupportICType & (ODM_RTL8723A)) 465 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV; 466 467 ODM_InitDebugSetting(pDM_Odm); 468} 469 470void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) 471{ 472 u8 EntryCnt = 0; 473 u8 i; 474 struct sta_info *pEntry; 475 476 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { 477 if (*(pDM_Odm->pSecChOffset) == 1) 478 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; 479 else if (*(pDM_Odm->pSecChOffset) == 2) 480 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; 481 } else { 482 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); 483 } 484 485 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 486 pEntry = pDM_Odm->pODM_StaInfo[i]; 487 if (IS_STA_VALID(pEntry)) 488 EntryCnt++; 489 } 490 if (EntryCnt == 1) 491 pDM_Odm->bOneEntryOnly = true; 492 else 493 pDM_Odm->bOneEntryOnly = false; 494} 495 496void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm) 497{ 498 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); 499 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform)); 500 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility)); 501 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface)); 502 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType)); 503 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion)); 504 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n", pDM_Odm->FabVersion)); 505 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n", pDM_Odm->RFType)); 506 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType)); 507 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA)); 508 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA)); 509 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW)); 510 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID)); 511 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest)); 512 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest)); 513 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent)); 514} 515 516void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm) 517{ 518 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); 519 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast))); 520 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast))); 521 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode))); 522 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset))); 523 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity))); 524 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth))); 525 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel))); 526 527 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess))); 528 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving))); 529 530 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) 531 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pOnePathCCA=%d\n", *(pDM_Odm->pOnePathCCA))); 532} 533 534void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm) 535{ 536 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); 537 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct)); 538 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display)); 539 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked)); 540 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min)); 541} 542 543static int getIGIForDiff(int value_IGI) 544{ 545 #define ONERCCA_LOW_TH 0x30 546 #define ONERCCA_LOW_DIFF 8 547 548 if (value_IGI < ONERCCA_LOW_TH) { 549 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) 550 return ONERCCA_LOW_TH; 551 else 552 return value_IGI + ONERCCA_LOW_DIFF; 553 } else { 554 return value_IGI; 555 } 556} 557 558void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) 559{ 560 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 561 struct adapter *adapter = pDM_Odm->Adapter; 562 563 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 564 ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", 565 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm))); 566 567 if (pDM_DigTable->CurIGValue != CurrentIGI) { 568 if (pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP)) { 569 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 570 if (pDM_Odm->SupportICType != ODM_RTL8188E) 571 PHY_SetBBReg(adapter, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 572 } else if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) { 573 switch (*(pDM_Odm->pOnePathCCA)) { 574 case ODM_CCA_2R: 575 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 576 if (pDM_Odm->SupportICType != ODM_RTL8188E) 577 PHY_SetBBReg(adapter, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 578 break; 579 case ODM_CCA_1R_A: 580 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 581 if (pDM_Odm->SupportICType != ODM_RTL8188E) 582 PHY_SetBBReg(adapter, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI)); 583 break; 584 case ODM_CCA_1R_B: 585 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), getIGIForDiff(CurrentIGI)); 586 if (pDM_Odm->SupportICType != ODM_RTL8188E) 587 PHY_SetBBReg(adapter, ODM_REG(IGI_B, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 588 break; 589 } 590 } 591 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n", CurrentIGI)); 592 /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */ 593 pDM_DigTable->CurIGValue = CurrentIGI; 594 } 595 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x\n", CurrentIGI)); 596 597/* Add by Neil Chen to enable edcca to MP Platform */ 598} 599 600/* Need LPS mode for CE platform --2012--08--24--- */ 601/* 8723AS/8189ES */ 602void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm) 603{ 604 struct adapter *pAdapter = pDM_Odm->Adapter; 605 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 606 607 u8 RSSI_Lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */ 608 u8 bFwCurrentInPSMode = false; 609 u8 CurrentIGI = pDM_Odm->RSSI_Min; 610 611 if (!(pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8188E))) 612 return; 613 614 CurrentIGI = CurrentIGI + RSSI_OFFSET_DIG; 615 bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode; 616 617 /* Using FW PS mode to make IGI */ 618 if (bFwCurrentInPSMode) { 619 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n")); 620 /* Adjust by FA in LPS MODE */ 621 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS) 622 CurrentIGI = CurrentIGI+2; 623 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) 624 CurrentIGI = CurrentIGI+1; 625 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) 626 CurrentIGI = CurrentIGI-1; 627 } else { 628 CurrentIGI = RSSI_Lower; 629 } 630 631 /* Lower bound checking */ 632 633 /* RSSI Lower bound check */ 634 if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) 635 RSSI_Lower = (pDM_Odm->RSSI_Min-10); 636 else 637 RSSI_Lower = DM_DIG_MIN_NIC; 638 639 /* Upper and Lower Bound checking */ 640 if (CurrentIGI > DM_DIG_MAX_NIC) 641 CurrentIGI = DM_DIG_MAX_NIC; 642 else if (CurrentIGI < RSSI_Lower) 643 CurrentIGI = RSSI_Lower; 644 645 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 646} 647 648void odm_DIGInit(struct odm_dm_struct *pDM_Odm) 649{ 650 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 651 652 pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); 653 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; 654 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; 655 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW; 656 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH; 657 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) { 658 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 659 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 660 } else { 661 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 662 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 663 } 664 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; 665 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; 666 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; 667 pDM_DigTable->PreCCK_CCAThres = 0xFF; 668 pDM_DigTable->CurCCK_CCAThres = 0x83; 669 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; 670 pDM_DigTable->LargeFAHit = 0; 671 pDM_DigTable->Recover_cnt = 0; 672 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; 673 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; 674 pDM_DigTable->bMediaConnect_0 = false; 675 pDM_DigTable->bMediaConnect_1 = false; 676 677 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */ 678 pDM_Odm->bDMInitialGainEnable = true; 679} 680 681void odm_DIG(struct odm_dm_struct *pDM_Odm) 682{ 683 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 684 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 685 u8 DIG_Dynamic_MIN; 686 u8 DIG_MaxOfMin; 687 bool FirstConnect, FirstDisConnect; 688 u8 dm_dig_max, dm_dig_min; 689 u8 CurrentIGI = pDM_DigTable->CurIGValue; 690 691 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); 692 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) { 693 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 694 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); 695 return; 696 } 697 698 if (*(pDM_Odm->pbScanInProcess)) { 699 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n")); 700 return; 701 } 702 703 /* add by Neil Chen to avoid PSD is processing */ 704 if (pDM_Odm->bDMInitialGainEnable == false) { 705 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n")); 706 return; 707 } 708 709 if (pDM_Odm->SupportICType == ODM_RTL8192D) { 710 if (*(pDM_Odm->pMacPhyMode) == ODM_DMSP) { 711 if (*(pDM_Odm->pbMasterOfDMSP)) { 712 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 713 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 714 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 715 } else { 716 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; 717 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1); 718 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1); 719 } 720 } else { 721 if (*(pDM_Odm->pBandType) == ODM_BAND_5G) { 722 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 723 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 724 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 725 } else { 726 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; 727 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_1); 728 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1); 729 } 730 } 731 } else { 732 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 733 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 734 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 735 } 736 737 /* 1 Boundary Decision */ 738 if ((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) && 739 ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) { 740 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) { 741 dm_dig_max = DM_DIG_MAX_AP_HP; 742 dm_dig_min = DM_DIG_MIN_AP_HP; 743 } else { 744 dm_dig_max = DM_DIG_MAX_NIC_HP; 745 dm_dig_min = DM_DIG_MIN_NIC_HP; 746 } 747 DIG_MaxOfMin = DM_DIG_MAX_AP_HP; 748 } else { 749 if (pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) { 750 dm_dig_max = DM_DIG_MAX_AP; 751 dm_dig_min = DM_DIG_MIN_AP; 752 DIG_MaxOfMin = dm_dig_max; 753 } else { 754 dm_dig_max = DM_DIG_MAX_NIC; 755 dm_dig_min = DM_DIG_MIN_NIC; 756 DIG_MaxOfMin = DM_DIG_MAX_AP; 757 } 758 } 759 if (pDM_Odm->bLinked) { 760 /* 2 8723A Series, offset need to be 10 */ 761 if (pDM_Odm->SupportICType == (ODM_RTL8723A)) { 762 /* 2 Upper Bound */ 763 if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC) 764 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 765 else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC) 766 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC; 767 else 768 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10; 769 /* 2 If BT is Concurrent, need to set Lower Bound */ 770 DIG_Dynamic_MIN = DM_DIG_MIN_NIC; 771 } else { 772 /* 2 Modify DIG upper bound */ 773 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) 774 pDM_DigTable->rx_gain_range_max = dm_dig_max; 775 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min) 776 pDM_DigTable->rx_gain_range_max = dm_dig_min; 777 else 778 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; 779 /* 2 Modify DIG lower bound */ 780 if (pDM_Odm->bOneEntryOnly) { 781 if (pDM_Odm->RSSI_Min < dm_dig_min) 782 DIG_Dynamic_MIN = dm_dig_min; 783 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) 784 DIG_Dynamic_MIN = DIG_MaxOfMin; 785 else 786 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; 787 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 788 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n", 789 DIG_Dynamic_MIN)); 790 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 791 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n", 792 pDM_Odm->RSSI_Min)); 793 } else if ((pDM_Odm->SupportICType == ODM_RTL8188E) && 794 (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 795 /* 1 Lower Bound for 88E AntDiv */ 796 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { 797 DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max; 798 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 799 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n", 800 pDM_DigTable->AntDiv_RSSI_max)); 801 } 802 } else { 803 DIG_Dynamic_MIN = dm_dig_min; 804 } 805 } 806 } else { 807 pDM_DigTable->rx_gain_range_max = dm_dig_max; 808 DIG_Dynamic_MIN = dm_dig_min; 809 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); 810 } 811 812 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ 813 if (pFalseAlmCnt->Cnt_all > 10000) { 814 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n")); 815 816 if (pDM_DigTable->LargeFAHit != 3) 817 pDM_DigTable->LargeFAHit++; 818 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { 819 pDM_DigTable->ForbiddenIGI = CurrentIGI; 820 pDM_DigTable->LargeFAHit = 1; 821 } 822 823 if (pDM_DigTable->LargeFAHit >= 3) { 824 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max) 825 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; 826 else 827 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 828 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ 829 } 830 831 } else { 832 /* Recovery mechanism for IGI lower bound */ 833 if (pDM_DigTable->Recover_cnt != 0) { 834 pDM_DigTable->Recover_cnt--; 835 } else { 836 if (pDM_DigTable->LargeFAHit < 3) { 837 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */ 838 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 839 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 840 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); 841 } else { 842 pDM_DigTable->ForbiddenIGI--; 843 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 844 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); 845 } 846 } else { 847 pDM_DigTable->LargeFAHit = 0; 848 } 849 } 850 } 851 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 852 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n", 853 pDM_DigTable->LargeFAHit)); 854 855 /* 1 Adjust initial gain by false alarm */ 856 if (pDM_Odm->bLinked) { 857 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); 858 if (FirstConnect) { 859 CurrentIGI = pDM_Odm->RSSI_Min; 860 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); 861 } else { 862 if (pDM_Odm->SupportICType == ODM_RTL8192D) { 863 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D) 864 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 865 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D) 866 CurrentIGI = CurrentIGI + 1; /* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 867 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D) 868 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 869 } else { 870 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) 871 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 872 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) 873 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 874 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) 875 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 876 } 877 } 878 } else { 879 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); 880 if (FirstDisConnect) { 881 CurrentIGI = pDM_DigTable->rx_gain_range_min; 882 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n")); 883 } else { 884 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ 885 if (pFalseAlmCnt->Cnt_all > 10000) 886 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 887 else if (pFalseAlmCnt->Cnt_all > 8000) 888 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 889 else if (pFalseAlmCnt->Cnt_all < 500) 890 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 891 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n")); 892 } 893 } 894 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); 895 /* 1 Check initial gain by upper/lower bound */ 896 if (CurrentIGI > pDM_DigTable->rx_gain_range_max) 897 CurrentIGI = pDM_DigTable->rx_gain_range_max; 898 if (CurrentIGI < pDM_DigTable->rx_gain_range_min) 899 CurrentIGI = pDM_DigTable->rx_gain_range_min; 900 901 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 902 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", 903 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); 904 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); 905 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); 906 907 /* 2 High power RSSI threshold */ 908 909 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 910 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; 911 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; 912} 913 914/* 3============================================================ */ 915/* 3 FASLE ALARM CHECK */ 916/* 3============================================================ */ 917 918void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 919{ 920 struct adapter *adapter = pDM_Odm->Adapter; 921 u32 ret_value; 922 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 923 924 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) 925 return; 926 927 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { 928 /* hold ofdm counter */ 929 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ 930 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ 931 932 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); 933 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); 934 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); 935 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); 936 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); 937 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); 938 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); 939 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); 940 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); 941 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); 942 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); 943 944 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + 945 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + 946 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; 947 948 if (pDM_Odm->SupportICType == ODM_RTL8188E) { 949 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord); 950 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); 951 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); 952 } 953 954 /* hold cck counter */ 955 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); 956 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); 957 958 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); 959 FalseAlmCnt->Cnt_Cck_fail = ret_value; 960 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); 961 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8; 962 963 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); 964 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8); 965 966 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + 967 FalseAlmCnt->Cnt_SB_Search_fail + 968 FalseAlmCnt->Cnt_Parity_Fail + 969 FalseAlmCnt->Cnt_Rate_Illegal + 970 FalseAlmCnt->Cnt_Crc8_fail + 971 FalseAlmCnt->Cnt_Mcs_fail + 972 FalseAlmCnt->Cnt_Cck_fail); 973 974 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; 975 976 if (pDM_Odm->SupportICType >= ODM_RTL8723A) { 977 /* reset false alarm counter registers */ 978 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1); 979 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0); 980 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1); 981 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0); 982 /* update ofdm counter */ 983 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /* update page C counter */ 984 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /* update page D counter */ 985 986 /* reset CCK CCA counter */ 987 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0); 988 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2); 989 /* reset CCK FA counter */ 990 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0); 991 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2); 992 } 993 994 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); 995 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 996 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", 997 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); 998 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 999 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", 1000 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); 1001 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 1002 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", 1003 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); 1004 } else { /* FOR ODM_IC_11AC_SERIES */ 1005 /* read OFDM FA counter */ 1006 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord); 1007 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord); 1008 FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail; 1009 1010 /* reset OFDM FA coutner */ 1011 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1); 1012 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0); 1013 /* reset CCK FA counter */ 1014 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11AC, BIT15, 0); 1015 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11AC, BIT15, 1); 1016 } 1017 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); 1018 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); 1019 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); 1020} 1021 1022/* 3============================================================ */ 1023/* 3 CCK Packet Detect Threshold */ 1024/* 3============================================================ */ 1025 1026void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) 1027{ 1028 u8 CurCCK_CCAThres; 1029 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 1030 1031 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) 1032 return; 1033 if (pDM_Odm->ExtLNA) 1034 return; 1035 if (pDM_Odm->bLinked) { 1036 if (pDM_Odm->RSSI_Min > 25) { 1037 CurCCK_CCAThres = 0xcd; 1038 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) { 1039 CurCCK_CCAThres = 0x83; 1040 } else { 1041 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 1042 CurCCK_CCAThres = 0x83; 1043 else 1044 CurCCK_CCAThres = 0x40; 1045 } 1046 } else { 1047 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 1048 CurCCK_CCAThres = 0x83; 1049 else 1050 CurCCK_CCAThres = 0x40; 1051 } 1052 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); 1053} 1054 1055void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres) 1056{ 1057 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 1058 1059 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ 1060 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres); 1061 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; 1062 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; 1063} 1064 1065/* 3============================================================ */ 1066/* 3 BB Power Save */ 1067/* 3============================================================ */ 1068void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm) 1069{ 1070 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 1071 1072 pDM_PSTable->PreCCAState = CCA_MAX; 1073 pDM_PSTable->CurCCAState = CCA_MAX; 1074 pDM_PSTable->PreRFState = RF_MAX; 1075 pDM_PSTable->CurRFState = RF_MAX; 1076 pDM_PSTable->Rssi_val_min = 0; 1077 pDM_PSTable->initialize = 0; 1078} 1079 1080void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm) 1081{ 1082 if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A)) 1083 return; 1084 if (!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE)) 1085 return; 1086 if (!(pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE))) 1087 return; 1088 1089 /* 1 2.Power Saving for 92C */ 1090 if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->RFType == ODM_2T2R)) { 1091 odm_1R_CCA(pDM_Odm); 1092 } else { 1093 /* 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. */ 1094 /* 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. */ 1095 /* 1 3.Power Saving for 88C */ 1096 ODM_RF_Saving(pDM_Odm, false); 1097 } 1098} 1099 1100void odm_1R_CCA(struct odm_dm_struct *pDM_Odm) 1101{ 1102 struct adapter *adapter = pDM_Odm->Adapter; 1103 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 1104 1105 if (pDM_Odm->RSSI_Min != 0xFF) { 1106 if (pDM_PSTable->PreCCAState == CCA_2R) { 1107 if (pDM_Odm->RSSI_Min >= 35) 1108 pDM_PSTable->CurCCAState = CCA_1R; 1109 else 1110 pDM_PSTable->CurCCAState = CCA_2R; 1111 } else { 1112 if (pDM_Odm->RSSI_Min <= 30) 1113 pDM_PSTable->CurCCAState = CCA_2R; 1114 else 1115 pDM_PSTable->CurCCAState = CCA_1R; 1116 } 1117 } else { 1118 pDM_PSTable->CurCCAState = CCA_MAX; 1119 } 1120 1121 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) { 1122 if (pDM_PSTable->CurCCAState == CCA_1R) { 1123 if (pDM_Odm->RFType == ODM_2T2R) 1124 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x13); 1125 else 1126 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x23); 1127 } else { 1128 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x33); 1129 } 1130 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; 1131 } 1132} 1133 1134void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 1135{ 1136 struct adapter *adapter = pDM_Odm->Adapter; 1137 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 1138 u8 Rssi_Up_bound = 30; 1139 u8 Rssi_Low_bound = 25; 1140 1141 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */ 1142 Rssi_Up_bound = 50; 1143 Rssi_Low_bound = 45; 1144 } 1145 if (pDM_PSTable->initialize == 0) { 1146 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14; 1147 pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3; 1148 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24; 1149 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12; 1150 pDM_PSTable->initialize = 1; 1151 } 1152 1153 if (!bForceInNormal) { 1154 if (pDM_Odm->RSSI_Min != 0xFF) { 1155 if (pDM_PSTable->PreRFState == RF_Normal) { 1156 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound) 1157 pDM_PSTable->CurRFState = RF_Save; 1158 else 1159 pDM_PSTable->CurRFState = RF_Normal; 1160 } else { 1161 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound) 1162 pDM_PSTable->CurRFState = RF_Normal; 1163 else 1164 pDM_PSTable->CurRFState = RF_Save; 1165 } 1166 } else { 1167 pDM_PSTable->CurRFState = RF_MAX; 1168 } 1169 } else { 1170 pDM_PSTable->CurRFState = RF_Normal; 1171 } 1172 1173 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { 1174 if (pDM_PSTable->CurRFState == RF_Save) { 1175 /* <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. */ 1176 /* Suggested by SD3 Yu-Nan. 2011.01.20. */ 1177 if (pDM_Odm->SupportICType == ODM_RTL8723A) 1178 PHY_SetBBReg(adapter, 0x874 , BIT5, 0x1); /* Reg874[5]=1b'1 */ 1179 PHY_SetBBReg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ 1180 PHY_SetBBReg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ 1181 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ 1182 PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ 1183 PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ 1184 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ 1185 PHY_SetBBReg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ 1186 } else { 1187 PHY_SetBBReg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); 1188 PHY_SetBBReg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); 1189 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); 1190 PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); 1191 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); 1192 1193 if (pDM_Odm->SupportICType == ODM_RTL8723A) 1194 PHY_SetBBReg(adapter, 0x874, BIT5, 0x0); /* Reg874[5]=1b'0 */ 1195 } 1196 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; 1197 } 1198} 1199 1200/* 3============================================================ */ 1201/* 3 RATR MASK */ 1202/* 3============================================================ */ 1203/* 3============================================================ */ 1204/* 3 Rate Adaptive */ 1205/* 3============================================================ */ 1206 1207void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm) 1208{ 1209 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive; 1210 1211 pOdmRA->Type = DM_Type_ByDriver; 1212 if (pOdmRA->Type == DM_Type_ByDriver) 1213 pDM_Odm->bUseRAMask = true; 1214 else 1215 pDM_Odm->bUseRAMask = false; 1216 1217 pOdmRA->RATRState = DM_RATR_STA_INIT; 1218 pOdmRA->HighRSSIThresh = 50; 1219 pOdmRA->LowRSSIThresh = 20; 1220} 1221 1222u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level) 1223{ 1224 struct sta_info *pEntry; 1225 u32 rate_bitmap = 0x0fffffff; 1226 u8 WirelessMode; 1227 1228 pEntry = pDM_Odm->pODM_StaInfo[macid]; 1229 if (!IS_STA_VALID(pEntry)) 1230 return ra_mask; 1231 1232 WirelessMode = pEntry->wireless_mode; 1233 1234 switch (WirelessMode) { 1235 case ODM_WM_B: 1236 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ 1237 rate_bitmap = 0x0000000d; 1238 else 1239 rate_bitmap = 0x0000000f; 1240 break; 1241 case (ODM_WM_A|ODM_WM_G): 1242 if (rssi_level == DM_RATR_STA_HIGH) 1243 rate_bitmap = 0x00000f00; 1244 else 1245 rate_bitmap = 0x00000ff0; 1246 break; 1247 case (ODM_WM_B|ODM_WM_G): 1248 if (rssi_level == DM_RATR_STA_HIGH) 1249 rate_bitmap = 0x00000f00; 1250 else if (rssi_level == DM_RATR_STA_MIDDLE) 1251 rate_bitmap = 0x00000ff0; 1252 else 1253 rate_bitmap = 0x00000ff5; 1254 break; 1255 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1256 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1257 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { 1258 if (rssi_level == DM_RATR_STA_HIGH) { 1259 rate_bitmap = 0x000f0000; 1260 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1261 rate_bitmap = 0x000ff000; 1262 } else { 1263 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1264 rate_bitmap = 0x000ff015; 1265 else 1266 rate_bitmap = 0x000ff005; 1267 } 1268 } else { 1269 if (rssi_level == DM_RATR_STA_HIGH) { 1270 rate_bitmap = 0x0f8f0000; 1271 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1272 rate_bitmap = 0x0f8ff000; 1273 } else { 1274 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1275 rate_bitmap = 0x0f8ff015; 1276 else 1277 rate_bitmap = 0x0f8ff005; 1278 } 1279 } 1280 break; 1281 default: 1282 /* case WIRELESS_11_24N: */ 1283 /* case WIRELESS_11_5N: */ 1284 if (pDM_Odm->RFType == RF_1T2R) 1285 rate_bitmap = 0x000fffff; 1286 else 1287 rate_bitmap = 0x0fffffff; 1288 break; 1289 } 1290 1291 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1292 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", 1293 rssi_level, WirelessMode, rate_bitmap)); 1294 1295 return rate_bitmap; 1296} 1297 1298/*----------------------------------------------------------------------------- 1299 * Function: odm_RefreshRateAdaptiveMask() 1300 * 1301 * Overview: Update rate table mask according to rssi 1302 * 1303 * Input: NONE 1304 * 1305 * Output: NONE 1306 * 1307 * Return: NONE 1308 * 1309 * Revised History: 1310 * When Who Remark 1311 * 05/27/2009 hpfan Create Version 0. 1312 * 1313 *---------------------------------------------------------------------------*/ 1314void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm) 1315{ 1316 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) 1317 return; 1318 /* */ 1319 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1320 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1321 /* HW dynamic mechanism. */ 1322 /* */ 1323 switch (pDM_Odm->SupportPlatform) { 1324 case ODM_MP: 1325 odm_RefreshRateAdaptiveMaskMP(pDM_Odm); 1326 break; 1327 case ODM_CE: 1328 odm_RefreshRateAdaptiveMaskCE(pDM_Odm); 1329 break; 1330 case ODM_AP: 1331 case ODM_ADSL: 1332 odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm); 1333 break; 1334 } 1335} 1336 1337void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm) 1338{ 1339} 1340 1341void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm) 1342{ 1343 u8 i; 1344 struct adapter *pAdapter = pDM_Odm->Adapter; 1345 1346 if (pAdapter->bDriverStopped) { 1347 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); 1348 return; 1349 } 1350 1351 if (!pDM_Odm->bUseRAMask) { 1352 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); 1353 return; 1354 } 1355 1356 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1357 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; 1358 if (IS_STA_VALID(pstat)) { 1359 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) { 1360 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1361 ("RSSI:%d, RSSI_LEVEL:%d\n", 1362 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); 1363 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level); 1364 } 1365 } 1366 } 1367} 1368 1369void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm) 1370{ 1371} 1372 1373/* Return Value: bool */ 1374/* - true: RATRState is changed. */ 1375bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState) 1376{ 1377 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive; 1378 const u8 GoUpGap = 5; 1379 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh; 1380 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; 1381 u8 RATRState; 1382 1383 /* Threshold Adjustment: */ 1384 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ 1385 /* Here GoUpGap is added to solve the boundary's level alternation issue. */ 1386 switch (*pRATRState) { 1387 case DM_RATR_STA_INIT: 1388 case DM_RATR_STA_HIGH: 1389 break; 1390 case DM_RATR_STA_MIDDLE: 1391 HighRSSIThreshForRA += GoUpGap; 1392 break; 1393 case DM_RATR_STA_LOW: 1394 HighRSSIThreshForRA += GoUpGap; 1395 LowRSSIThreshForRA += GoUpGap; 1396 break; 1397 default: 1398 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState)); 1399 break; 1400 } 1401 1402 /* Decide RATRState by RSSI. */ 1403 if (RSSI > HighRSSIThreshForRA) 1404 RATRState = DM_RATR_STA_HIGH; 1405 else if (RSSI > LowRSSIThreshForRA) 1406 RATRState = DM_RATR_STA_MIDDLE; 1407 else 1408 RATRState = DM_RATR_STA_LOW; 1409 1410 if (*pRATRState != RATRState || bForceUpdate) { 1411 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState)); 1412 *pRATRState = RATRState; 1413 return true; 1414 } 1415 return false; 1416} 1417 1418/* 3============================================================ */ 1419/* 3 Dynamic Tx Power */ 1420/* 3============================================================ */ 1421 1422void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm) 1423{ 1424 struct adapter *Adapter = pDM_Odm->Adapter; 1425 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1426 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1427 pdmpriv->bDynamicTxPowerEnable = false; 1428 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; 1429 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; 1430} 1431 1432void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm) 1433{ 1434 /* For AP/ADSL use struct rtl8192cd_priv * */ 1435 /* For CE/NIC use struct adapter * */ 1436 1437 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1438 return; 1439 1440 /* 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */ 1441 if (!pDM_Odm->ExtPA) 1442 return; 1443 1444 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1445 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1446 /* HW dynamic mechanism. */ 1447 switch (pDM_Odm->SupportPlatform) { 1448 case ODM_MP: 1449 case ODM_CE: 1450 odm_DynamicTxPowerNIC(pDM_Odm); 1451 break; 1452 case ODM_AP: 1453 odm_DynamicTxPowerAP(pDM_Odm); 1454 break; 1455 case ODM_ADSL: 1456 break; 1457 } 1458} 1459 1460void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm) 1461{ 1462 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1463 return; 1464 1465 if (pDM_Odm->SupportICType == ODM_RTL8188E) { 1466 /* ??? */ 1467 /* This part need to be redefined. */ 1468 } 1469} 1470 1471void odm_DynamicTxPowerAP(struct odm_dm_struct *pDM_Odm) 1472{ 1473} 1474 1475/* 3============================================================ */ 1476/* 3 RSSI Monitor */ 1477/* 3============================================================ */ 1478 1479void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm) 1480{ 1481 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) 1482 return; 1483 1484 /* */ 1485 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1486 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1487 /* HW dynamic mechanism. */ 1488 /* */ 1489 switch (pDM_Odm->SupportPlatform) { 1490 case ODM_MP: 1491 odm_RSSIMonitorCheckMP(pDM_Odm); 1492 break; 1493 case ODM_CE: 1494 odm_RSSIMonitorCheckCE(pDM_Odm); 1495 break; 1496 case ODM_AP: 1497 odm_RSSIMonitorCheckAP(pDM_Odm); 1498 break; 1499 case ODM_ADSL: 1500 /* odm_DIGAP(pDM_Odm); */ 1501 break; 1502 } 1503 1504} /* odm_RSSIMonitorCheck */ 1505 1506void odm_RSSIMonitorCheckMP(struct odm_dm_struct *pDM_Odm) 1507{ 1508} 1509 1510static void FindMinimumRSSI(struct adapter *pAdapter) 1511{ 1512 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); 1513 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1514 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; 1515 1516 /* 1 1.Determine the minimum RSSI */ 1517 if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) && 1518 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) 1519 pdmpriv->MinUndecoratedPWDBForDM = 0; 1520 if (check_fwstate(pmlmepriv, _FW_LINKED) == true) /* Default port */ 1521 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1522 else /* associated entry pwdb */ 1523 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1524} 1525 1526void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm) 1527{ 1528 struct adapter *Adapter = pDM_Odm->Adapter; 1529 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1530 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1531 int i; 1532 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; 1533 u8 sta_cnt = 0; 1534 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ 1535 struct sta_info *psta; 1536 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 1537 1538 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) 1539 return; 1540 1541 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1542 psta = pDM_Odm->pODM_StaInfo[i]; 1543 if (IS_STA_VALID(psta) && 1544 (psta->state & WIFI_ASOC_STATE) && 1545 !_rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) && 1546 !_rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) { 1547 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) 1548 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1549 1550 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) 1551 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1552 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) 1553 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16)); 1554 } 1555 } 1556 1557 for (i = 0; i < sta_cnt; i++) { 1558 if (PWDB_rssi[i] != (0)) { 1559 if (pHalData->fw_ractrl) { 1560 /* Report every sta's RSSI to FW */ 1561 } else { 1562 ODM_RA_SetRSSI_8188E( 1563 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); 1564 } 1565 } 1566 } 1567 1568 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */ 1569 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; 1570 else 1571 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; 1572 1573 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */ 1574 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; 1575 else 1576 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; 1577 1578 FindMinimumRSSI(Adapter); 1579 ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); 1580} 1581 1582void odm_RSSIMonitorCheckAP(struct odm_dm_struct *pDM_Odm) 1583{ 1584} 1585 1586void ODM_InitAllTimers(struct odm_dm_struct *pDM_Odm) 1587{ 1588 ODM_InitializeTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer, 1589 (void *)odm_SwAntDivChkAntSwitchCallback, NULL, "SwAntennaSwitchTimer"); 1590} 1591 1592void ODM_CancelAllTimers(struct odm_dm_struct *pDM_Odm) 1593{ 1594 ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer); 1595} 1596 1597void ODM_ReleaseAllTimers(struct odm_dm_struct *pDM_Odm) 1598{ 1599 ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer); 1600 1601 ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->FastAntTrainingTimer); 1602} 1603 1604/* 3============================================================ */ 1605/* 3 Tx Power Tracking */ 1606/* 3============================================================ */ 1607 1608void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm) 1609{ 1610 odm_TXPowerTrackingThermalMeterInit(pDM_Odm); 1611} 1612 1613void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm) 1614{ 1615 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; 1616 pDM_Odm->RFCalibrateInfo.TXPowercount = 0; 1617 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; 1618 if (*(pDM_Odm->mp_mode) != 1) 1619 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1620 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); 1621 1622 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1623} 1624 1625void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm) 1626{ 1627 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1628 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1629 /* HW dynamic mechanism. */ 1630 switch (pDM_Odm->SupportPlatform) { 1631 case ODM_MP: 1632 odm_TXPowerTrackingCheckMP(pDM_Odm); 1633 break; 1634 case ODM_CE: 1635 odm_TXPowerTrackingCheckCE(pDM_Odm); 1636 break; 1637 case ODM_AP: 1638 odm_TXPowerTrackingCheckAP(pDM_Odm); 1639 break; 1640 case ODM_ADSL: 1641 break; 1642 } 1643} 1644 1645void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 1646{ 1647 struct adapter *Adapter = pDM_Odm->Adapter; 1648 1649 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) 1650 return; 1651 1652 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ 1653 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); 1654 1655 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; 1656 return; 1657 } else { 1658 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); 1659 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; 1660 } 1661} 1662 1663void odm_TXPowerTrackingCheckMP(struct odm_dm_struct *pDM_Odm) 1664{ 1665} 1666 1667void odm_TXPowerTrackingCheckAP(struct odm_dm_struct *pDM_Odm) 1668{ 1669} 1670 1671/* antenna mapping info */ 1672/* 1: right-side antenna */ 1673/* 2/0: left-side antenna */ 1674/* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */ 1675/* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */ 1676/* We select left antenna as default antenna in initial process, modify it as needed */ 1677/* */ 1678 1679/* 3============================================================ */ 1680/* 3 SW Antenna Diversity */ 1681/* 3============================================================ */ 1682void odm_SwAntDivInit(struct odm_dm_struct *pDM_Odm) 1683{ 1684} 1685 1686void ODM_SwAntDivChkPerPktRssi(struct odm_dm_struct *pDM_Odm, u8 StationID, struct odm_phy_status_info *pPhyInfo) 1687{ 1688} 1689 1690void odm_SwAntDivChkAntSwitch(struct odm_dm_struct *pDM_Odm, u8 Step) 1691{ 1692} 1693 1694void ODM_SwAntDivRestAfterLink(struct odm_dm_struct *pDM_Odm) 1695{ 1696} 1697 1698void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) 1699{ 1700} 1701 1702/* 3============================================================ */ 1703/* 3 SW Antenna Diversity */ 1704/* 3============================================================ */ 1705 1706void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) 1707{ 1708 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1709 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1710 return; 1711 } 1712 1713 if (pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D)) 1714 ; 1715 else if (pDM_Odm->SupportICType == ODM_RTL8188E) 1716 ODM_AntennaDiversityInit_88E(pDM_Odm); 1717} 1718 1719void ODM_AntselStatistics_88C(struct odm_dm_struct *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate) 1720{ 1721 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; 1722 1723 if (pDM_SWAT_Table->antsel == 1) { 1724 if (isCCKrate) { 1725 pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++; 1726 } else { 1727 pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++; 1728 pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll; 1729 } 1730 } else { 1731 if (isCCKrate) { 1732 pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++; 1733 } else { 1734 pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++; 1735 pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll; 1736 } 1737 } 1738} 1739 1740void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) 1741{ 1742 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1743 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1744 return; 1745 } 1746 1747 if (pDM_Odm->SupportICType == ODM_RTL8188E) 1748 ODM_AntennaDiversity_88E(pDM_Odm); 1749} 1750 1751/* EDCA Turbo */ 1752void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) 1753{ 1754 struct adapter *Adapter = pDM_Odm->Adapter; 1755 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1756 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; 1757 Adapter->recvpriv.bIsAnyNonBEPkts = false; 1758 1759 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM))); 1760 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM))); 1761 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM))); 1762 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM))); 1763} /* ODM_InitEdcaTurbo */ 1764 1765void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm) 1766{ 1767 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1768 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1769 /* HW dynamic mechanism. */ 1770 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n")); 1771 1772 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)) 1773 return; 1774 1775 switch (pDM_Odm->SupportPlatform) { 1776 case ODM_MP: 1777 break; 1778 case ODM_CE: 1779 odm_EdcaTurboCheckCE(pDM_Odm); 1780 break; 1781 case ODM_AP: 1782 case ODM_ADSL: 1783 break; 1784 } 1785 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n")); 1786} /* odm_CheckEdcaTurbo */ 1787 1788void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm) 1789{ 1790 struct adapter *Adapter = pDM_Odm->Adapter; 1791 u32 trafficIndex; 1792 u32 edca_param; 1793 u64 cur_tx_bytes = 0; 1794 u64 cur_rx_bytes = 0; 1795 u8 bbtchange = false; 1796 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1797 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); 1798 struct recv_priv *precvpriv = &(Adapter->recvpriv); 1799 struct registry_priv *pregpriv = &Adapter->registrypriv; 1800 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); 1801 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 1802 1803 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */ 1804 goto dm_CheckEdcaTurbo_EXIT; 1805 1806 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) 1807 goto dm_CheckEdcaTurbo_EXIT; 1808 1809 /* Check if the status needs to be changed. */ 1810 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) { 1811 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; 1812 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; 1813 1814 /* traffic, TX or RX */ 1815 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) || 1816 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { 1817 if (cur_tx_bytes > (cur_rx_bytes << 2)) { 1818 /* Uplink TP is present. */ 1819 trafficIndex = UP_LINK; 1820 } else { 1821 /* Balance TP is present. */ 1822 trafficIndex = DOWN_LINK; 1823 } 1824 } else { 1825 if (cur_rx_bytes > (cur_tx_bytes << 2)) { 1826 /* Downlink TP is present. */ 1827 trafficIndex = DOWN_LINK; 1828 } else { 1829 /* Balance TP is present. */ 1830 trafficIndex = UP_LINK; 1831 } 1832 } 1833 1834 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) { 1835 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) 1836 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; 1837 else 1838 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; 1839 1840 rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); 1841 1842 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; 1843 } 1844 1845 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; 1846 } else { 1847 /* Turn Off EDCA turbo here. */ 1848 /* Restore original EDCA according to the declaration of AP. */ 1849 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { 1850 rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); 1851 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1852 } 1853 } 1854 1855dm_CheckEdcaTurbo_EXIT: 1856 /* Set variables for next time. */ 1857 precvpriv->bIsAnyNonBEPkts = false; 1858 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; 1859 precvpriv->last_rx_bytes = precvpriv->rx_bytes; 1860} 1861 1862/* need to ODM CE Platform */ 1863/* move to here for ANT detection mechanism using */ 1864 1865u32 GetPSDData(struct odm_dm_struct *pDM_Odm, unsigned int point, u8 initial_gain_psd) 1866{ 1867 struct adapter *adapter = pDM_Odm->Adapter; 1868 u32 psd_report; 1869 1870 /* Set DCO frequency index, offset=(40MHz/SamplePts)*point */ 1871 PHY_SetBBReg(adapter, 0x808, 0x3FF, point); 1872 1873 /* Start PSD calculation, Reg808[22]=0->1 */ 1874 PHY_SetBBReg(adapter, 0x808, BIT22, 1); 1875 /* Need to wait for HW PSD report */ 1876 udelay(30); 1877 PHY_SetBBReg(adapter, 0x808, BIT22, 0); 1878 /* Read PSD report, Reg8B4[15:0] */ 1879 psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF; 1880 1881 psd_report = (u32) (ConvertTo_dB(psd_report))+(u32)(initial_gain_psd-0x1c); 1882 1883 return psd_report; 1884} 1885 1886u32 ConvertTo_dB(u32 Value) 1887{ 1888 u8 i; 1889 u8 j; 1890 u32 dB; 1891 1892 Value = Value & 0xFFFF; 1893 for (i = 0; i < 8; i++) { 1894 if (Value <= dB_Invert_Table[i][11]) 1895 break; 1896 } 1897 1898 if (i >= 8) 1899 return 96; /* maximum 96 dB */ 1900 1901 for (j = 0; j < 12; j++) { 1902 if (Value <= dB_Invert_Table[i][j]) 1903 break; 1904 } 1905 1906 dB = i*12 + j + 1; 1907 1908 return dB; 1909} 1910 1911/* 2011/09/22 MH Add for 92D global spin lock utilization. */ 1912void odm_GlobalAdapterCheck(void) 1913{ 1914} /* odm_GlobalAdapterCheck */ 1915 1916/* Description: */ 1917/* Set Single/Dual Antenna default setting for products that do not do detection in advance. */ 1918/* Added by Joseph, 2012.03.22 */ 1919void ODM_SingleDualAntennaDefaultSetting(struct odm_dm_struct *pDM_Odm) 1920{ 1921 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; 1922 1923 pDM_SWAT_Table->ANTA_ON = true; 1924 pDM_SWAT_Table->ANTB_ON = true; 1925} 1926 1927 1928/* 2 8723A ANT DETECT */ 1929 1930static void odm_PHY_SaveAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegisterNum) 1931{ 1932 struct adapter *adapter = pDM_Odm->Adapter; 1933 u32 i; 1934 1935 /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */ 1936 for (i = 0; i < RegisterNum; i++) 1937 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord); 1938} 1939 1940static void odm_PHY_ReloadAFERegisters(struct odm_dm_struct *pDM_Odm, u32 *AFEReg, u32 *AFEBackup, u32 RegiesterNum) 1941{ 1942 struct adapter *adapter = pDM_Odm->Adapter; 1943 u32 i; 1944 1945 for (i = 0; i < RegiesterNum; i++) 1946 PHY_SetBBReg(adapter, AFEReg[i], bMaskDWord, AFEBackup[i]); 1947} 1948 1949/* 2 8723A ANT DETECT */ 1950/* Description: */ 1951/* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */ 1952/* This function is cooperated with BB team Neil. */ 1953bool ODM_SingleDualAntennaDetection(struct odm_dm_struct *pDM_Odm, u8 mode) 1954{ 1955 struct adapter *adapter = pDM_Odm->Adapter; 1956 struct sw_ant_switch *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; 1957 u32 CurrentChannel, RfLoopReg; 1958 u8 n; 1959 u32 Reg88c, Regc08, Reg874, Regc50; 1960 u8 initial_gain = 0x5a; 1961 u32 PSD_report_tmp; 1962 u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0; 1963 bool bResult = true; 1964 u32 AFE_Backup[16]; 1965 u32 AFE_REG_8723A[16] = { 1966 rRx_Wait_CCA, rTx_CCK_RFON, 1967 rTx_CCK_BBON, rTx_OFDM_RFON, 1968 rTx_OFDM_BBON, rTx_To_Rx, 1969 rTx_To_Tx, rRx_CCK, 1970 rRx_OFDM, rRx_Wait_RIFS, 1971 rRx_TO_Rx, rStandby, 1972 rSleep, rPMPD_ANAEN, 1973 rFPGA0_XCD_SwitchControl, rBlue_Tooth}; 1974 1975 if (!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))) 1976 return bResult; 1977 1978 if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV)) 1979 return bResult; 1980 1981 if (pDM_Odm->SupportICType == ODM_RTL8192C) { 1982 /* Which path in ADC/DAC is turnned on for PSD: both I/Q */ 1983 PHY_SetBBReg(adapter, 0x808, BIT10|BIT11, 0x3); 1984 /* Ageraged number: 8 */ 1985 PHY_SetBBReg(adapter, 0x808, BIT12|BIT13, 0x1); 1986 /* pts = 128; */ 1987 PHY_SetBBReg(adapter, 0x808, BIT14|BIT15, 0x0); 1988 } 1989 1990 /* 1 Backup Current RF/BB Settings */ 1991 1992 CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); 1993 RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask); 1994 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); /* change to Antenna A */ 1995 /* Step 1: USE IQK to transmitter single tone */ 1996 1997 udelay(10); 1998 1999 /* Store A Path Register 88c, c08, 874, c50 */ 2000 Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord); 2001 Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord); 2002 Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord); 2003 Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); 2004 2005 /* Store AFE Registers */ 2006 odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); 2007 2008 /* Set PSD 128 pts */ 2009 PHY_SetBBReg(adapter, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); /* 128 pts */ 2010 2011 /* To SET CH1 to do */ 2012 ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); /* Channel 1 */ 2013 2014 /* AFE all on step */ 2015 PHY_SetBBReg(adapter, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4); 2016 PHY_SetBBReg(adapter, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4); 2017 PHY_SetBBReg(adapter, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4); 2018 PHY_SetBBReg(adapter, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4); 2019 PHY_SetBBReg(adapter, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4); 2020 PHY_SetBBReg(adapter, rTx_To_Rx, bMaskDWord, 0x6FDB25A4); 2021 PHY_SetBBReg(adapter, rTx_To_Tx, bMaskDWord, 0x6FDB25A4); 2022 PHY_SetBBReg(adapter, rRx_CCK, bMaskDWord, 0x6FDB25A4); 2023 PHY_SetBBReg(adapter, rRx_OFDM, bMaskDWord, 0x6FDB25A4); 2024 PHY_SetBBReg(adapter, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4); 2025 PHY_SetBBReg(adapter, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4); 2026 PHY_SetBBReg(adapter, rStandby, bMaskDWord, 0x6FDB25A4); 2027 PHY_SetBBReg(adapter, rSleep, bMaskDWord, 0x6FDB25A4); 2028 PHY_SetBBReg(adapter, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4); 2029 PHY_SetBBReg(adapter, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4); 2030 PHY_SetBBReg(adapter, rBlue_Tooth, bMaskDWord, 0x6FDB25A4); 2031 2032 /* 3 wire Disable */ 2033 PHY_SetBBReg(adapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0); 2034 2035 /* BB IQK Setting */ 2036 PHY_SetBBReg(adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4); 2037 PHY_SetBBReg(adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000); 2038 2039 /* IQK setting tone@ 4.34Mhz */ 2040 PHY_SetBBReg(adapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C); 2041 PHY_SetBBReg(adapter, rTx_IQK, bMaskDWord, 0x01007c00); 2042 2043 2044 /* Page B init */ 2045 PHY_SetBBReg(adapter, rConfig_AntA, bMaskDWord, 0x00080000); 2046 PHY_SetBBReg(adapter, rConfig_AntA, bMaskDWord, 0x0f600000); 2047 PHY_SetBBReg(adapter, rRx_IQK, bMaskDWord, 0x01004800); 2048 PHY_SetBBReg(adapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); 2049 PHY_SetBBReg(adapter, rTx_IQK_PI_A, bMaskDWord, 0x82150008); 2050 PHY_SetBBReg(adapter, rRx_IQK_PI_A, bMaskDWord, 0x28150008); 2051 PHY_SetBBReg(adapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0); 2052 2053 /* RF loop Setting */ 2054 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008); 2055 2056 /* IQK Single tone start */ 2057 PHY_SetBBReg(adapter, rFPGA0_IQK, bMaskDWord, 0x80800000); 2058 PHY_SetBBReg(adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 2059 udelay(1000); 2060 PSD_report_tmp = 0x0; 2061 2062 for (n = 0; n < 2; n++) { 2063 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); 2064 if (PSD_report_tmp > AntA_report) 2065 AntA_report = PSD_report_tmp; 2066 } 2067 2068 PSD_report_tmp = 0x0; 2069 2070 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */ 2071 udelay(10); 2072 2073 2074 for (n = 0; n < 2; n++) { 2075 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); 2076 if (PSD_report_tmp > AntB_report) 2077 AntB_report = PSD_report_tmp; 2078 } 2079 2080 /* change to open case */ 2081 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0); /* change to Ant A and B all open case */ 2082 udelay(10); 2083 2084 for (n = 0; n < 2; n++) { 2085 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); 2086 if (PSD_report_tmp > AntO_report) 2087 AntO_report = PSD_report_tmp; 2088 } 2089 2090 /* Close IQK Single Tone function */ 2091 PHY_SetBBReg(adapter, rFPGA0_IQK, bMaskDWord, 0x00000000); 2092 PSD_report_tmp = 0x0; 2093 2094 /* 1 Return to antanna A */ 2095 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); 2096 PHY_SetBBReg(adapter, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c); 2097 PHY_SetBBReg(adapter, rOFDM0_TRMuxPar, bMaskDWord, Regc08); 2098 PHY_SetBBReg(adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874); 2099 PHY_SetBBReg(adapter, rOFDM0_XAAGCCore1, 0x7F, 0x40); 2100 PHY_SetBBReg(adapter, rOFDM0_XAAGCCore1, bMaskDWord, Regc50); 2101 ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel); 2102 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg); 2103 2104 /* Reload AFE Registers */ 2105 odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16); 2106 2107 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report)); 2108 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report)); 2109 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d\n", 2416, AntO_report)); 2110 2111 2112 if (pDM_Odm->SupportICType == ODM_RTL8723A) { 2113 /* 2 Test Ant B based on Ant A is ON */ 2114 if (mode == ANTTESTB) { 2115 if (AntA_report >= 100) { 2116 if (AntB_report > (AntA_report+1)) { 2117 pDM_SWAT_Table->ANTB_ON = false; 2118 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n")); 2119 } else { 2120 pDM_SWAT_Table->ANTB_ON = true; 2121 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n")); 2122 } 2123 } else { 2124 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); 2125 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */ 2126 bResult = false; 2127 } 2128 } else if (mode == ANTTESTALL) { 2129 /* 2 Test Ant A and B based on DPDT Open */ 2130 if ((AntO_report >= 100)&(AntO_report < 118)) { 2131 if (AntA_report > (AntO_report+1)) { 2132 pDM_SWAT_Table->ANTA_ON = false; 2133 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF")); 2134 } else { 2135 pDM_SWAT_Table->ANTA_ON = true; 2136 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON")); 2137 } 2138 2139 if (AntB_report > (AntO_report+2)) { 2140 pDM_SWAT_Table->ANTB_ON = false; 2141 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF")); 2142 } else { 2143 pDM_SWAT_Table->ANTB_ON = true; 2144 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON")); 2145 } 2146 } 2147 } 2148 } else if (pDM_Odm->SupportICType == ODM_RTL8192C) { 2149 if (AntA_report >= 100) { 2150 if (AntB_report > (AntA_report+2)) { 2151 pDM_SWAT_Table->ANTA_ON = false; 2152 pDM_SWAT_Table->ANTB_ON = true; 2153 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); 2154 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n")); 2155 } else if (AntA_report > (AntB_report+2)) { 2156 pDM_SWAT_Table->ANTA_ON = true; 2157 pDM_SWAT_Table->ANTB_ON = false; 2158 PHY_SetBBReg(adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A); 2159 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n")); 2160 } else { 2161 pDM_SWAT_Table->ANTA_ON = true; 2162 pDM_SWAT_Table->ANTB_ON = true; 2163 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 2164 ("ODM_SingleDualAntennaDetection(): Dual Antenna\n")); 2165 } 2166 } else { 2167 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); 2168 pDM_SWAT_Table->ANTA_ON = true; /* Set Antenna A on as default */ 2169 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */ 2170 bResult = false; 2171 } 2172 } 2173 return bResult; 2174} 2175 2176/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ 2177void odm_dtc(struct odm_dm_struct *pDM_Odm) 2178{ 2179} 2180