odm.c revision e76484d00c5147d2959e673faa858e7ace4567dd
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21/* include files */ 22 23#include "odm_precomp.h" 24 25static const u16 dB_Invert_Table[8][12] = { 26 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, 27 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, 28 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63}, 29 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251}, 30 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000}, 31 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, 32 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849}, 33 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} 34}; 35 36/* avoid to warn in FreeBSD ==> To DO modify */ 37static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { 38 /* UL DL */ 39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ 40 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ 41 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ 42 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ 43 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ 44 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ 45 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ 46 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ 47 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ 48 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ 49}; 50 51/* Global var */ 52u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { 53 0x7f8001fe, /* 0, +6.0dB */ 54 0x788001e2, /* 1, +5.5dB */ 55 0x71c001c7, /* 2, +5.0dB */ 56 0x6b8001ae, /* 3, +4.5dB */ 57 0x65400195, /* 4, +4.0dB */ 58 0x5fc0017f, /* 5, +3.5dB */ 59 0x5a400169, /* 6, +3.0dB */ 60 0x55400155, /* 7, +2.5dB */ 61 0x50800142, /* 8, +2.0dB */ 62 0x4c000130, /* 9, +1.5dB */ 63 0x47c0011f, /* 10, +1.0dB */ 64 0x43c0010f, /* 11, +0.5dB */ 65 0x40000100, /* 12, +0dB */ 66 0x3c8000f2, /* 13, -0.5dB */ 67 0x390000e4, /* 14, -1.0dB */ 68 0x35c000d7, /* 15, -1.5dB */ 69 0x32c000cb, /* 16, -2.0dB */ 70 0x300000c0, /* 17, -2.5dB */ 71 0x2d4000b5, /* 18, -3.0dB */ 72 0x2ac000ab, /* 19, -3.5dB */ 73 0x288000a2, /* 20, -4.0dB */ 74 0x26000098, /* 21, -4.5dB */ 75 0x24000090, /* 22, -5.0dB */ 76 0x22000088, /* 23, -5.5dB */ 77 0x20000080, /* 24, -6.0dB */ 78 0x1e400079, /* 25, -6.5dB */ 79 0x1c800072, /* 26, -7.0dB */ 80 0x1b00006c, /* 27. -7.5dB */ 81 0x19800066, /* 28, -8.0dB */ 82 0x18000060, /* 29, -8.5dB */ 83 0x16c0005b, /* 30, -9.0dB */ 84 0x15800056, /* 31, -9.5dB */ 85 0x14400051, /* 32, -10.0dB */ 86 0x1300004c, /* 33, -10.5dB */ 87 0x12000048, /* 34, -11.0dB */ 88 0x11000044, /* 35, -11.5dB */ 89 0x10000040, /* 36, -12.0dB */ 90 0x0f00003c,/* 37, -12.5dB */ 91 0x0e400039,/* 38, -13.0dB */ 92 0x0d800036,/* 39, -13.5dB */ 93 0x0cc00033,/* 40, -14.0dB */ 94 0x0c000030,/* 41, -14.5dB */ 95 0x0b40002d,/* 42, -15.0dB */ 96}; 97 98u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { 99 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 100 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 101 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 102 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 103 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 104 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 105 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 106 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 107 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 108 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 109 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 110 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 111 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 112 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 113 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 114 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 115 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 116 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 117 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 118 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 119 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ 120 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ 121 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ 122 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ 123 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ 124 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ 125 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ 126 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ 127 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ 128 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ 129 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ 130 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ 131 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ 132}; 133 134u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { 135 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 136 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 137 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 138 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 139 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 140 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 141 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 142 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 143 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 144 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 145 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 146 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 147 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 148 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 149 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 150 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 151 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 152 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 153 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 154 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 155 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ 156 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ 157 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ 158 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ 159 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ 160 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ 161 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ 162 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ 163 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ 164 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ 165 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ 166 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ 167 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ 168}; 169 170 171#define RxDefaultAnt1 0x65a9 172#define RxDefaultAnt2 0x569a 173 174/* 3 Export Interface */ 175 176/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ 177void ODM_DMInit(struct odm_dm_struct *pDM_Odm) 178{ 179 /* 2012.05.03 Luke: For all IC series */ 180 odm_CommonInfoSelfInit(pDM_Odm); 181 odm_CmnInfoInit_Debug(pDM_Odm); 182 odm_DIGInit(pDM_Odm); 183 odm_RateAdaptiveMaskInit(pDM_Odm); 184 185 odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ 186 odm_DynamicTxPowerInit(pDM_Odm); 187 odm_TXPowerTrackingInit(pDM_Odm); 188 ODM_EdcaTurboInit(pDM_Odm); 189 ODM_RAInfo_Init_all(pDM_Odm); 190 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 191 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 192 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 193 odm_InitHybridAntDiv(pDM_Odm); 194} 195 196/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ 197/* You can not add any dummy function here, be care, you can only use DM structure */ 198/* to perform any new ODM_DM. */ 199void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) 200{ 201 /* 2012.05.03 Luke: For all IC series */ 202 odm_CmnInfoHook_Debug(pDM_Odm); 203 odm_CmnInfoUpdate_Debug(pDM_Odm); 204 odm_CommonInfoSelfUpdate(pDM_Odm); 205 odm_FalseAlarmCounterStatistics(pDM_Odm); 206 odm_RSSIMonitorCheck(pDM_Odm); 207 208 /* Fix Leave LPS issue */ 209 odm_DIG(pDM_Odm); 210 odm_CCKPacketDetectionThresh(pDM_Odm); 211 212 if (*(pDM_Odm->pbPowerSaving)) 213 return; 214 215 odm_RefreshRateAdaptiveMask(pDM_Odm); 216 217 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 218 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 219 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 220 odm_HwAntDiv(pDM_Odm); 221 222 ODM_TXPowerTrackingCheck(pDM_Odm); 223 odm_EdcaTurboCheck(pDM_Odm); 224 odm_DynamicTxPower(pDM_Odm); 225} 226 227/* Init /.. Fixed HW value. Only init time. */ 228void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value) 229{ 230 /* This section is used for init value */ 231 switch (CmnInfo) { 232 /* Fixed ODM value. */ 233 case ODM_CMNINFO_ABILITY: 234 pDM_Odm->SupportAbility = (u32)Value; 235 break; 236 case ODM_CMNINFO_PLATFORM: 237 pDM_Odm->SupportPlatform = (u8)Value; 238 break; 239 case ODM_CMNINFO_INTERFACE: 240 pDM_Odm->SupportInterface = (u8)Value; 241 break; 242 case ODM_CMNINFO_MP_TEST_CHIP: 243 pDM_Odm->bIsMPChip = (u8)Value; 244 break; 245 case ODM_CMNINFO_IC_TYPE: 246 pDM_Odm->SupportICType = Value; 247 break; 248 case ODM_CMNINFO_CUT_VER: 249 pDM_Odm->CutVersion = (u8)Value; 250 break; 251 case ODM_CMNINFO_FAB_VER: 252 pDM_Odm->FabVersion = (u8)Value; 253 break; 254 case ODM_CMNINFO_RF_TYPE: 255 pDM_Odm->RFType = (u8)Value; 256 break; 257 case ODM_CMNINFO_RF_ANTENNA_TYPE: 258 pDM_Odm->AntDivType = (u8)Value; 259 break; 260 case ODM_CMNINFO_BOARD_TYPE: 261 pDM_Odm->BoardType = (u8)Value; 262 break; 263 case ODM_CMNINFO_EXT_LNA: 264 pDM_Odm->ExtLNA = (u8)Value; 265 break; 266 case ODM_CMNINFO_EXT_PA: 267 pDM_Odm->ExtPA = (u8)Value; 268 break; 269 case ODM_CMNINFO_EXT_TRSW: 270 pDM_Odm->ExtTRSW = (u8)Value; 271 break; 272 case ODM_CMNINFO_PATCH_ID: 273 pDM_Odm->PatchID = (u8)Value; 274 break; 275 case ODM_CMNINFO_BINHCT_TEST: 276 pDM_Odm->bInHctTest = (bool)Value; 277 break; 278 case ODM_CMNINFO_BWIFI_TEST: 279 pDM_Odm->bWIFITest = (bool)Value; 280 break; 281 case ODM_CMNINFO_SMART_CONCURRENT: 282 pDM_Odm->bDualMacSmartConcurrent = (bool)Value; 283 break; 284 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 285 default: 286 /* do nothing */ 287 break; 288 } 289 290 /* Tx power tracking BB swing table. */ 291 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ 292 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */ 293 pDM_Odm->BbSwingIdxOfdmCurrent = 12; 294 pDM_Odm->BbSwingFlagOfdm = false; 295} 296 297void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue) 298{ 299 /* */ 300 /* Hook call by reference pointer. */ 301 /* */ 302 switch (CmnInfo) { 303 /* Dynamic call by reference pointer. */ 304 case ODM_CMNINFO_MAC_PHY_MODE: 305 pDM_Odm->pMacPhyMode = (u8 *)pValue; 306 break; 307 case ODM_CMNINFO_TX_UNI: 308 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue; 309 break; 310 case ODM_CMNINFO_RX_UNI: 311 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue; 312 break; 313 case ODM_CMNINFO_WM_MODE: 314 pDM_Odm->pWirelessMode = (u8 *)pValue; 315 break; 316 case ODM_CMNINFO_BAND: 317 pDM_Odm->pBandType = (u8 *)pValue; 318 break; 319 case ODM_CMNINFO_SEC_CHNL_OFFSET: 320 pDM_Odm->pSecChOffset = (u8 *)pValue; 321 break; 322 case ODM_CMNINFO_SEC_MODE: 323 pDM_Odm->pSecurity = (u8 *)pValue; 324 break; 325 case ODM_CMNINFO_BW: 326 pDM_Odm->pBandWidth = (u8 *)pValue; 327 break; 328 case ODM_CMNINFO_CHNL: 329 pDM_Odm->pChannel = (u8 *)pValue; 330 break; 331 case ODM_CMNINFO_DMSP_GET_VALUE: 332 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue; 333 break; 334 case ODM_CMNINFO_BUDDY_ADAPTOR: 335 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue; 336 break; 337 case ODM_CMNINFO_DMSP_IS_MASTER: 338 pDM_Odm->pbMasterOfDMSP = (bool *)pValue; 339 break; 340 case ODM_CMNINFO_SCAN: 341 pDM_Odm->pbScanInProcess = (bool *)pValue; 342 break; 343 case ODM_CMNINFO_POWER_SAVING: 344 pDM_Odm->pbPowerSaving = (bool *)pValue; 345 break; 346 case ODM_CMNINFO_ONE_PATH_CCA: 347 pDM_Odm->pOnePathCCA = (u8 *)pValue; 348 break; 349 case ODM_CMNINFO_DRV_STOP: 350 pDM_Odm->pbDriverStopped = (bool *)pValue; 351 break; 352 case ODM_CMNINFO_PNP_IN: 353 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue; 354 break; 355 case ODM_CMNINFO_INIT_ON: 356 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue; 357 break; 358 case ODM_CMNINFO_ANT_TEST: 359 pDM_Odm->pAntennaTest = (u8 *)pValue; 360 break; 361 case ODM_CMNINFO_NET_CLOSED: 362 pDM_Odm->pbNet_closed = (bool *)pValue; 363 break; 364 case ODM_CMNINFO_MP_MODE: 365 pDM_Odm->mp_mode = (u8 *)pValue; 366 break; 367 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 368 default: 369 /* do nothing */ 370 break; 371 } 372} 373 374void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue) 375{ 376 /* Hook call by reference pointer. */ 377 switch (CmnInfo) { 378 /* Dynamic call by reference pointer. */ 379 case ODM_CMNINFO_STA_STATUS: 380 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue; 381 break; 382 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 383 default: 384 /* do nothing */ 385 break; 386 } 387} 388 389/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ 390void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value) 391{ 392 /* */ 393 /* This init variable may be changed in run time. */ 394 /* */ 395 switch (CmnInfo) { 396 case ODM_CMNINFO_ABILITY: 397 pDM_Odm->SupportAbility = (u32)Value; 398 break; 399 case ODM_CMNINFO_RF_TYPE: 400 pDM_Odm->RFType = (u8)Value; 401 break; 402 case ODM_CMNINFO_WIFI_DIRECT: 403 pDM_Odm->bWIFI_Direct = (bool)Value; 404 break; 405 case ODM_CMNINFO_WIFI_DISPLAY: 406 pDM_Odm->bWIFI_Display = (bool)Value; 407 break; 408 case ODM_CMNINFO_LINK: 409 pDM_Odm->bLinked = (bool)Value; 410 break; 411 case ODM_CMNINFO_RSSI_MIN: 412 pDM_Odm->RSSI_Min = (u8)Value; 413 break; 414 case ODM_CMNINFO_DBG_COMP: 415 pDM_Odm->DebugComponents = Value; 416 break; 417 case ODM_CMNINFO_DBG_LEVEL: 418 pDM_Odm->DebugLevel = (u32)Value; 419 break; 420 case ODM_CMNINFO_RA_THRESHOLD_HIGH: 421 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value; 422 break; 423 case ODM_CMNINFO_RA_THRESHOLD_LOW: 424 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value; 425 break; 426 } 427} 428 429void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) 430{ 431 struct adapter *adapter = pDM_Odm->Adapter; 432 433 pDM_Odm->bCckHighPower = (bool) PHY_QueryBBReg(adapter, 0x824, BIT9); 434 pDM_Odm->RFPathRxEnable = (u8) PHY_QueryBBReg(adapter, 0xc04, 0x0F); 435 436 ODM_InitDebugSetting(pDM_Odm); 437} 438 439void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) 440{ 441 u8 EntryCnt = 0; 442 u8 i; 443 struct sta_info *pEntry; 444 445 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { 446 if (*(pDM_Odm->pSecChOffset) == 1) 447 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; 448 else if (*(pDM_Odm->pSecChOffset) == 2) 449 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; 450 } else { 451 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); 452 } 453 454 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 455 pEntry = pDM_Odm->pODM_StaInfo[i]; 456 if (IS_STA_VALID(pEntry)) 457 EntryCnt++; 458 } 459 if (EntryCnt == 1) 460 pDM_Odm->bOneEntryOnly = true; 461 else 462 pDM_Odm->bOneEntryOnly = false; 463} 464 465void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm) 466{ 467 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); 468 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform)); 469 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility)); 470 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface)); 471 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType)); 472 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion)); 473 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n", pDM_Odm->FabVersion)); 474 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n", pDM_Odm->RFType)); 475 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType)); 476 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA)); 477 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA)); 478 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW)); 479 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID)); 480 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest)); 481 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest)); 482 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent)); 483} 484 485void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm) 486{ 487 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); 488 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast))); 489 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast))); 490 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode))); 491 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset))); 492 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity))); 493 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth))); 494 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel))); 495 496 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess))); 497 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving))); 498} 499 500void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm) 501{ 502 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); 503 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct)); 504 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display)); 505 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked)); 506 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min)); 507} 508 509void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) 510{ 511 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 512 struct adapter *adapter = pDM_Odm->Adapter; 513 514 if (pDM_DigTable->CurIGValue != CurrentIGI) { 515 PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N, CurrentIGI); 516 pDM_DigTable->CurIGValue = CurrentIGI; 517 } 518} 519 520void odm_DIGInit(struct odm_dm_struct *pDM_Odm) 521{ 522 struct adapter *adapter = pDM_Odm->Adapter; 523 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 524 525 pDM_DigTable->CurIGValue = (u8) PHY_QueryBBReg(adapter, ODM_REG_IGI_A_11N, ODM_BIT_IGI_11N); 526 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; 527 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; 528 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW; 529 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH; 530 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) { 531 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 532 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 533 } else { 534 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 535 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 536 } 537 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; 538 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; 539 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; 540 pDM_DigTable->PreCCK_CCAThres = 0xFF; 541 pDM_DigTable->CurCCK_CCAThres = 0x83; 542 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; 543 pDM_DigTable->LargeFAHit = 0; 544 pDM_DigTable->Recover_cnt = 0; 545 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; 546 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; 547 pDM_DigTable->bMediaConnect_0 = false; 548 pDM_DigTable->bMediaConnect_1 = false; 549 550 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */ 551 pDM_Odm->bDMInitialGainEnable = true; 552} 553 554void odm_DIG(struct odm_dm_struct *pDM_Odm) 555{ 556 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 557 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 558 u8 DIG_Dynamic_MIN; 559 u8 DIG_MaxOfMin; 560 bool FirstConnect, FirstDisConnect; 561 u8 dm_dig_max, dm_dig_min; 562 u8 CurrentIGI = pDM_DigTable->CurIGValue; 563 564 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); 565 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) { 566 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 567 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); 568 return; 569 } 570 571 if (*(pDM_Odm->pbScanInProcess)) { 572 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n")); 573 return; 574 } 575 576 /* add by Neil Chen to avoid PSD is processing */ 577 if (pDM_Odm->bDMInitialGainEnable == false) { 578 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n")); 579 return; 580 } 581 582 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 583 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 584 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 585 586 /* 1 Boundary Decision */ 587 dm_dig_max = DM_DIG_MAX_NIC; 588 dm_dig_min = DM_DIG_MIN_NIC; 589 DIG_MaxOfMin = DM_DIG_MAX_AP; 590 591 if (pDM_Odm->bLinked) { 592 /* 2 Modify DIG upper bound */ 593 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) 594 pDM_DigTable->rx_gain_range_max = dm_dig_max; 595 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min) 596 pDM_DigTable->rx_gain_range_max = dm_dig_min; 597 else 598 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; 599 /* 2 Modify DIG lower bound */ 600 if (pDM_Odm->bOneEntryOnly) { 601 if (pDM_Odm->RSSI_Min < dm_dig_min) 602 DIG_Dynamic_MIN = dm_dig_min; 603 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) 604 DIG_Dynamic_MIN = DIG_MaxOfMin; 605 else 606 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; 607 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 608 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n", 609 DIG_Dynamic_MIN)); 610 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 611 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n", 612 pDM_Odm->RSSI_Min)); 613 } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) { 614 /* 1 Lower Bound for 88E AntDiv */ 615 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { 616 DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max; 617 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 618 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n", 619 pDM_DigTable->AntDiv_RSSI_max)); 620 } 621 } else { 622 DIG_Dynamic_MIN = dm_dig_min; 623 } 624 } else { 625 pDM_DigTable->rx_gain_range_max = dm_dig_max; 626 DIG_Dynamic_MIN = dm_dig_min; 627 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); 628 } 629 630 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ 631 if (pFalseAlmCnt->Cnt_all > 10000) { 632 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n")); 633 634 if (pDM_DigTable->LargeFAHit != 3) 635 pDM_DigTable->LargeFAHit++; 636 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { 637 pDM_DigTable->ForbiddenIGI = CurrentIGI; 638 pDM_DigTable->LargeFAHit = 1; 639 } 640 641 if (pDM_DigTable->LargeFAHit >= 3) { 642 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max) 643 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; 644 else 645 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 646 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ 647 } 648 649 } else { 650 /* Recovery mechanism for IGI lower bound */ 651 if (pDM_DigTable->Recover_cnt != 0) { 652 pDM_DigTable->Recover_cnt--; 653 } else { 654 if (pDM_DigTable->LargeFAHit < 3) { 655 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */ 656 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 657 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 658 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); 659 } else { 660 pDM_DigTable->ForbiddenIGI--; 661 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 662 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); 663 } 664 } else { 665 pDM_DigTable->LargeFAHit = 0; 666 } 667 } 668 } 669 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 670 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n", 671 pDM_DigTable->LargeFAHit)); 672 673 /* 1 Adjust initial gain by false alarm */ 674 if (pDM_Odm->bLinked) { 675 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); 676 if (FirstConnect) { 677 CurrentIGI = pDM_Odm->RSSI_Min; 678 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); 679 } else { 680 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) 681 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 682 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) 683 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 684 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) 685 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 686 } 687 } else { 688 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); 689 if (FirstDisConnect) { 690 CurrentIGI = pDM_DigTable->rx_gain_range_min; 691 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n")); 692 } else { 693 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ 694 if (pFalseAlmCnt->Cnt_all > 10000) 695 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 696 else if (pFalseAlmCnt->Cnt_all > 8000) 697 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 698 else if (pFalseAlmCnt->Cnt_all < 500) 699 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 700 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n")); 701 } 702 } 703 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); 704 /* 1 Check initial gain by upper/lower bound */ 705 if (CurrentIGI > pDM_DigTable->rx_gain_range_max) 706 CurrentIGI = pDM_DigTable->rx_gain_range_max; 707 if (CurrentIGI < pDM_DigTable->rx_gain_range_min) 708 CurrentIGI = pDM_DigTable->rx_gain_range_min; 709 710 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 711 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", 712 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); 713 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); 714 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); 715 716 /* 2 High power RSSI threshold */ 717 718 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 719 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; 720 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; 721} 722 723/* 3============================================================ */ 724/* 3 FASLE ALARM CHECK */ 725/* 3============================================================ */ 726 727void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 728{ 729 struct adapter *adapter = pDM_Odm->Adapter; 730 u32 ret_value; 731 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 732 733 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) 734 return; 735 736 /* hold ofdm counter */ 737 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ 738 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ 739 740 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); 741 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); 742 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); 743 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); 744 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); 745 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); 746 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); 747 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); 748 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); 749 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); 750 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); 751 752 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + 753 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + 754 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; 755 756 ret_value = PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); 757 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); 758 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); 759 760 /* hold cck counter */ 761 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); 762 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); 763 764 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); 765 FalseAlmCnt->Cnt_Cck_fail = ret_value; 766 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); 767 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8; 768 769 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); 770 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8); 771 772 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + 773 FalseAlmCnt->Cnt_SB_Search_fail + 774 FalseAlmCnt->Cnt_Parity_Fail + 775 FalseAlmCnt->Cnt_Rate_Illegal + 776 FalseAlmCnt->Cnt_Crc8_fail + 777 FalseAlmCnt->Cnt_Mcs_fail + 778 FalseAlmCnt->Cnt_Cck_fail); 779 780 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; 781 782 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); 783 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 784 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", 785 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); 786 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 787 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", 788 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); 789 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 790 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", 791 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); 792 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); 793 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); 794 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); 795} 796 797/* 3============================================================ */ 798/* 3 CCK Packet Detect Threshold */ 799/* 3============================================================ */ 800 801void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) 802{ 803 u8 CurCCK_CCAThres; 804 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 805 806 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) 807 return; 808 if (pDM_Odm->ExtLNA) 809 return; 810 if (pDM_Odm->bLinked) { 811 if (pDM_Odm->RSSI_Min > 25) { 812 CurCCK_CCAThres = 0xcd; 813 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) { 814 CurCCK_CCAThres = 0x83; 815 } else { 816 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 817 CurCCK_CCAThres = 0x83; 818 else 819 CurCCK_CCAThres = 0x40; 820 } 821 } else { 822 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 823 CurCCK_CCAThres = 0x83; 824 else 825 CurCCK_CCAThres = 0x40; 826 } 827 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); 828} 829 830void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres) 831{ 832 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 833 struct adapter *adapt = pDM_Odm->Adapter; 834 835 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ 836 usb_write8(adapt, ODM_REG_CCK_CCA_11N, CurCCK_CCAThres); 837 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; 838 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; 839} 840 841void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 842{ 843 struct adapter *adapter = pDM_Odm->Adapter; 844 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 845 u8 Rssi_Up_bound = 30; 846 u8 Rssi_Low_bound = 25; 847 848 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */ 849 Rssi_Up_bound = 50; 850 Rssi_Low_bound = 45; 851 } 852 if (pDM_PSTable->initialize == 0) { 853 pDM_PSTable->Reg874 = (PHY_QueryBBReg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14; 854 pDM_PSTable->RegC70 = (PHY_QueryBBReg(adapter, 0xc70, bMaskDWord)&BIT3)>>3; 855 pDM_PSTable->Reg85C = (PHY_QueryBBReg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; 856 pDM_PSTable->RegA74 = (PHY_QueryBBReg(adapter, 0xa74, bMaskDWord)&0xF000)>>12; 857 pDM_PSTable->initialize = 1; 858 } 859 860 if (!bForceInNormal) { 861 if (pDM_Odm->RSSI_Min != 0xFF) { 862 if (pDM_PSTable->PreRFState == RF_Normal) { 863 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound) 864 pDM_PSTable->CurRFState = RF_Save; 865 else 866 pDM_PSTable->CurRFState = RF_Normal; 867 } else { 868 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound) 869 pDM_PSTable->CurRFState = RF_Normal; 870 else 871 pDM_PSTable->CurRFState = RF_Save; 872 } 873 } else { 874 pDM_PSTable->CurRFState = RF_MAX; 875 } 876 } else { 877 pDM_PSTable->CurRFState = RF_Normal; 878 } 879 880 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { 881 if (pDM_PSTable->CurRFState == RF_Save) { 882 PHY_SetBBReg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ 883 PHY_SetBBReg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ 884 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ 885 PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ 886 PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ 887 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ 888 PHY_SetBBReg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ 889 } else { 890 PHY_SetBBReg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); 891 PHY_SetBBReg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); 892 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); 893 PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); 894 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); 895 } 896 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; 897 } 898} 899 900/* 3============================================================ */ 901/* 3 RATR MASK */ 902/* 3============================================================ */ 903/* 3============================================================ */ 904/* 3 Rate Adaptive */ 905/* 3============================================================ */ 906 907void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm) 908{ 909 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive; 910 911 pOdmRA->Type = DM_Type_ByDriver; 912 if (pOdmRA->Type == DM_Type_ByDriver) 913 pDM_Odm->bUseRAMask = true; 914 else 915 pDM_Odm->bUseRAMask = false; 916 917 pOdmRA->RATRState = DM_RATR_STA_INIT; 918 pOdmRA->HighRSSIThresh = 50; 919 pOdmRA->LowRSSIThresh = 20; 920} 921 922u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level) 923{ 924 struct sta_info *pEntry; 925 u32 rate_bitmap = 0x0fffffff; 926 u8 WirelessMode; 927 928 pEntry = pDM_Odm->pODM_StaInfo[macid]; 929 if (!IS_STA_VALID(pEntry)) 930 return ra_mask; 931 932 WirelessMode = pEntry->wireless_mode; 933 934 switch (WirelessMode) { 935 case ODM_WM_B: 936 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ 937 rate_bitmap = 0x0000000d; 938 else 939 rate_bitmap = 0x0000000f; 940 break; 941 case (ODM_WM_A|ODM_WM_G): 942 if (rssi_level == DM_RATR_STA_HIGH) 943 rate_bitmap = 0x00000f00; 944 else 945 rate_bitmap = 0x00000ff0; 946 break; 947 case (ODM_WM_B|ODM_WM_G): 948 if (rssi_level == DM_RATR_STA_HIGH) 949 rate_bitmap = 0x00000f00; 950 else if (rssi_level == DM_RATR_STA_MIDDLE) 951 rate_bitmap = 0x00000ff0; 952 else 953 rate_bitmap = 0x00000ff5; 954 break; 955 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 956 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 957 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { 958 if (rssi_level == DM_RATR_STA_HIGH) { 959 rate_bitmap = 0x000f0000; 960 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 961 rate_bitmap = 0x000ff000; 962 } else { 963 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 964 rate_bitmap = 0x000ff015; 965 else 966 rate_bitmap = 0x000ff005; 967 } 968 } else { 969 if (rssi_level == DM_RATR_STA_HIGH) { 970 rate_bitmap = 0x0f8f0000; 971 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 972 rate_bitmap = 0x0f8ff000; 973 } else { 974 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 975 rate_bitmap = 0x0f8ff015; 976 else 977 rate_bitmap = 0x0f8ff005; 978 } 979 } 980 break; 981 default: 982 /* case WIRELESS_11_24N: */ 983 /* case WIRELESS_11_5N: */ 984 if (pDM_Odm->RFType == RF_1T2R) 985 rate_bitmap = 0x000fffff; 986 else 987 rate_bitmap = 0x0fffffff; 988 break; 989 } 990 991 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 992 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", 993 rssi_level, WirelessMode, rate_bitmap)); 994 995 return rate_bitmap; 996} 997 998/*----------------------------------------------------------------------------- 999 * Function: odm_RefreshRateAdaptiveMask() 1000 * 1001 * Overview: Update rate table mask according to rssi 1002 * 1003 * Input: NONE 1004 * 1005 * Output: NONE 1006 * 1007 * Return: NONE 1008 * 1009 * Revised History: 1010 * When Who Remark 1011 * 05/27/2009 hpfan Create Version 0. 1012 * 1013 *---------------------------------------------------------------------------*/ 1014void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm) 1015{ 1016 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) 1017 return; 1018 /* */ 1019 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1020 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1021 /* HW dynamic mechanism. */ 1022 /* */ 1023 odm_RefreshRateAdaptiveMaskCE(pDM_Odm); 1024} 1025 1026void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm) 1027{ 1028 u8 i; 1029 struct adapter *pAdapter = pDM_Odm->Adapter; 1030 1031 if (pAdapter->bDriverStopped) { 1032 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); 1033 return; 1034 } 1035 1036 if (!pDM_Odm->bUseRAMask) { 1037 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); 1038 return; 1039 } 1040 1041 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1042 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; 1043 if (IS_STA_VALID(pstat)) { 1044 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) { 1045 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1046 ("RSSI:%d, RSSI_LEVEL:%d\n", 1047 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); 1048 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level); 1049 } 1050 } 1051 } 1052} 1053 1054/* Return Value: bool */ 1055/* - true: RATRState is changed. */ 1056bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState) 1057{ 1058 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive; 1059 const u8 GoUpGap = 5; 1060 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh; 1061 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; 1062 u8 RATRState; 1063 1064 /* Threshold Adjustment: */ 1065 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ 1066 /* Here GoUpGap is added to solve the boundary's level alternation issue. */ 1067 switch (*pRATRState) { 1068 case DM_RATR_STA_INIT: 1069 case DM_RATR_STA_HIGH: 1070 break; 1071 case DM_RATR_STA_MIDDLE: 1072 HighRSSIThreshForRA += GoUpGap; 1073 break; 1074 case DM_RATR_STA_LOW: 1075 HighRSSIThreshForRA += GoUpGap; 1076 LowRSSIThreshForRA += GoUpGap; 1077 break; 1078 default: 1079 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState)); 1080 break; 1081 } 1082 1083 /* Decide RATRState by RSSI. */ 1084 if (RSSI > HighRSSIThreshForRA) 1085 RATRState = DM_RATR_STA_HIGH; 1086 else if (RSSI > LowRSSIThreshForRA) 1087 RATRState = DM_RATR_STA_MIDDLE; 1088 else 1089 RATRState = DM_RATR_STA_LOW; 1090 1091 if (*pRATRState != RATRState || bForceUpdate) { 1092 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState)); 1093 *pRATRState = RATRState; 1094 return true; 1095 } 1096 return false; 1097} 1098 1099/* 3============================================================ */ 1100/* 3 Dynamic Tx Power */ 1101/* 3============================================================ */ 1102 1103void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm) 1104{ 1105 struct adapter *Adapter = pDM_Odm->Adapter; 1106 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1107 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1108 pdmpriv->bDynamicTxPowerEnable = false; 1109 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; 1110 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; 1111} 1112 1113void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm) 1114{ 1115 /* For AP/ADSL use struct rtl8192cd_priv * */ 1116 /* For CE/NIC use struct adapter * */ 1117 1118 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1119 return; 1120 1121 /* 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */ 1122 if (!pDM_Odm->ExtPA) 1123 return; 1124} 1125 1126/* 3============================================================ */ 1127/* 3 RSSI Monitor */ 1128/* 3============================================================ */ 1129 1130void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm) 1131{ 1132 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) 1133 return; 1134 1135 /* */ 1136 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1137 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1138 /* HW dynamic mechanism. */ 1139 /* */ 1140 odm_RSSIMonitorCheckCE(pDM_Odm); 1141} /* odm_RSSIMonitorCheck */ 1142 1143static void FindMinimumRSSI(struct adapter *pAdapter) 1144{ 1145 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); 1146 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1147 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; 1148 1149 /* 1 1.Determine the minimum RSSI */ 1150 if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) && 1151 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) 1152 pdmpriv->MinUndecoratedPWDBForDM = 0; 1153 if (check_fwstate(pmlmepriv, _FW_LINKED) == true) /* Default port */ 1154 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1155 else /* associated entry pwdb */ 1156 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1157} 1158 1159void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm) 1160{ 1161 struct adapter *Adapter = pDM_Odm->Adapter; 1162 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1163 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1164 int i; 1165 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; 1166 u8 sta_cnt = 0; 1167 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ 1168 struct sta_info *psta; 1169 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 1170 1171 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) 1172 return; 1173 1174 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1175 psta = pDM_Odm->pODM_StaInfo[i]; 1176 if (IS_STA_VALID(psta) && 1177 (psta->state & WIFI_ASOC_STATE) && 1178 memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) && 1179 memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) { 1180 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) 1181 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1182 1183 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) 1184 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1185 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) 1186 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16)); 1187 } 1188 } 1189 1190 for (i = 0; i < sta_cnt; i++) { 1191 if (PWDB_rssi[i] != (0)) { 1192 if (pHalData->fw_ractrl) { 1193 /* Report every sta's RSSI to FW */ 1194 } else { 1195 ODM_RA_SetRSSI_8188E( 1196 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); 1197 } 1198 } 1199 } 1200 1201 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */ 1202 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; 1203 else 1204 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; 1205 1206 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */ 1207 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; 1208 else 1209 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; 1210 1211 FindMinimumRSSI(Adapter); 1212 ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); 1213} 1214 1215/* 3============================================================ */ 1216/* 3 Tx Power Tracking */ 1217/* 3============================================================ */ 1218 1219void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm) 1220{ 1221 odm_TXPowerTrackingThermalMeterInit(pDM_Odm); 1222} 1223 1224void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm) 1225{ 1226 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; 1227 pDM_Odm->RFCalibrateInfo.TXPowercount = 0; 1228 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; 1229 if (*(pDM_Odm->mp_mode) != 1) 1230 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1231 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); 1232 1233 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1234} 1235 1236void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm) 1237{ 1238 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1239 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1240 /* HW dynamic mechanism. */ 1241 odm_TXPowerTrackingCheckCE(pDM_Odm); 1242} 1243 1244void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 1245{ 1246 struct adapter *Adapter = pDM_Odm->Adapter; 1247 1248 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) 1249 return; 1250 1251 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ 1252 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); 1253 1254 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; 1255 return; 1256 } else { 1257 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); 1258 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; 1259 } 1260} 1261 1262/* 3============================================================ */ 1263/* 3 SW Antenna Diversity */ 1264/* 3============================================================ */ 1265 1266void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) 1267{ 1268 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1269 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1270 return; 1271 } 1272 1273 ODM_AntennaDiversityInit_88E(pDM_Odm); 1274} 1275 1276void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) 1277{ 1278 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1279 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1280 return; 1281 } 1282 1283 ODM_AntennaDiversity_88E(pDM_Odm); 1284} 1285 1286/* EDCA Turbo */ 1287void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) 1288{ 1289 struct adapter *Adapter = pDM_Odm->Adapter; 1290 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1291 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; 1292 Adapter->recvpriv.bIsAnyNonBEPkts = false; 1293 1294 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_VO_PARAM))); 1295 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_VI_PARAM))); 1296 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_BE_PARAM))); 1297 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_BK_PARAM))); 1298} /* ODM_InitEdcaTurbo */ 1299 1300void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm) 1301{ 1302 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1303 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1304 /* HW dynamic mechanism. */ 1305 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n")); 1306 1307 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)) 1308 return; 1309 1310 odm_EdcaTurboCheckCE(pDM_Odm); 1311 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n")); 1312} /* odm_CheckEdcaTurbo */ 1313 1314void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm) 1315{ 1316 struct adapter *Adapter = pDM_Odm->Adapter; 1317 u32 trafficIndex; 1318 u32 edca_param; 1319 u64 cur_tx_bytes = 0; 1320 u64 cur_rx_bytes = 0; 1321 u8 bbtchange = false; 1322 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1323 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); 1324 struct recv_priv *precvpriv = &(Adapter->recvpriv); 1325 struct registry_priv *pregpriv = &Adapter->registrypriv; 1326 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); 1327 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 1328 1329 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */ 1330 goto dm_CheckEdcaTurbo_EXIT; 1331 1332 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) 1333 goto dm_CheckEdcaTurbo_EXIT; 1334 1335 /* Check if the status needs to be changed. */ 1336 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) { 1337 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; 1338 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; 1339 1340 /* traffic, TX or RX */ 1341 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) || 1342 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { 1343 if (cur_tx_bytes > (cur_rx_bytes << 2)) { 1344 /* Uplink TP is present. */ 1345 trafficIndex = UP_LINK; 1346 } else { 1347 /* Balance TP is present. */ 1348 trafficIndex = DOWN_LINK; 1349 } 1350 } else { 1351 if (cur_rx_bytes > (cur_tx_bytes << 2)) { 1352 /* Downlink TP is present. */ 1353 trafficIndex = DOWN_LINK; 1354 } else { 1355 /* Balance TP is present. */ 1356 trafficIndex = UP_LINK; 1357 } 1358 } 1359 1360 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) { 1361 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) 1362 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; 1363 else 1364 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; 1365 1366 usb_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); 1367 1368 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; 1369 } 1370 1371 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; 1372 } else { 1373 /* Turn Off EDCA turbo here. */ 1374 /* Restore original EDCA according to the declaration of AP. */ 1375 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { 1376 usb_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); 1377 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1378 } 1379 } 1380 1381dm_CheckEdcaTurbo_EXIT: 1382 /* Set variables for next time. */ 1383 precvpriv->bIsAnyNonBEPkts = false; 1384 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; 1385 precvpriv->last_rx_bytes = precvpriv->rx_bytes; 1386} 1387