odm.c revision f395036dbaf311a879b4a935e3f93b655e5f58da
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21/* include files */ 22 23#include "odm_precomp.h" 24 25static const u16 dB_Invert_Table[8][12] = { 26 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, 27 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, 28 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63}, 29 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251}, 30 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000}, 31 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, 32 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849}, 33 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} 34}; 35 36/* avoid to warn in FreeBSD ==> To DO modify */ 37static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { 38 /* UL DL */ 39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ 40 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ 41 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ 42 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ 43 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ 44 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ 45 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ 46 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ 47 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ 48 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ 49}; 50 51/* Global var */ 52u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { 53 0x7f8001fe, /* 0, +6.0dB */ 54 0x788001e2, /* 1, +5.5dB */ 55 0x71c001c7, /* 2, +5.0dB */ 56 0x6b8001ae, /* 3, +4.5dB */ 57 0x65400195, /* 4, +4.0dB */ 58 0x5fc0017f, /* 5, +3.5dB */ 59 0x5a400169, /* 6, +3.0dB */ 60 0x55400155, /* 7, +2.5dB */ 61 0x50800142, /* 8, +2.0dB */ 62 0x4c000130, /* 9, +1.5dB */ 63 0x47c0011f, /* 10, +1.0dB */ 64 0x43c0010f, /* 11, +0.5dB */ 65 0x40000100, /* 12, +0dB */ 66 0x3c8000f2, /* 13, -0.5dB */ 67 0x390000e4, /* 14, -1.0dB */ 68 0x35c000d7, /* 15, -1.5dB */ 69 0x32c000cb, /* 16, -2.0dB */ 70 0x300000c0, /* 17, -2.5dB */ 71 0x2d4000b5, /* 18, -3.0dB */ 72 0x2ac000ab, /* 19, -3.5dB */ 73 0x288000a2, /* 20, -4.0dB */ 74 0x26000098, /* 21, -4.5dB */ 75 0x24000090, /* 22, -5.0dB */ 76 0x22000088, /* 23, -5.5dB */ 77 0x20000080, /* 24, -6.0dB */ 78 0x1e400079, /* 25, -6.5dB */ 79 0x1c800072, /* 26, -7.0dB */ 80 0x1b00006c, /* 27. -7.5dB */ 81 0x19800066, /* 28, -8.0dB */ 82 0x18000060, /* 29, -8.5dB */ 83 0x16c0005b, /* 30, -9.0dB */ 84 0x15800056, /* 31, -9.5dB */ 85 0x14400051, /* 32, -10.0dB */ 86 0x1300004c, /* 33, -10.5dB */ 87 0x12000048, /* 34, -11.0dB */ 88 0x11000044, /* 35, -11.5dB */ 89 0x10000040, /* 36, -12.0dB */ 90 0x0f00003c,/* 37, -12.5dB */ 91 0x0e400039,/* 38, -13.0dB */ 92 0x0d800036,/* 39, -13.5dB */ 93 0x0cc00033,/* 40, -14.0dB */ 94 0x0c000030,/* 41, -14.5dB */ 95 0x0b40002d,/* 42, -15.0dB */ 96}; 97 98u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { 99 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 100 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 101 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 102 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 103 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 104 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 105 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 106 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 107 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 108 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 109 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 110 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 111 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 112 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 113 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 114 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 115 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 116 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 117 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 118 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 119 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ 120 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ 121 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ 122 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ 123 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ 124 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ 125 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ 126 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ 127 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ 128 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ 129 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ 130 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ 131 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ 132}; 133 134u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { 135 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 136 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 137 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 138 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 139 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 140 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 141 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 142 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 143 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 144 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 145 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 146 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 147 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 148 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 149 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 150 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 151 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 152 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 153 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 154 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 155 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ 156 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ 157 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ 158 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ 159 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ 160 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ 161 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ 162 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ 163 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ 164 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ 165 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ 166 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ 167 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ 168}; 169 170 171#define RxDefaultAnt1 0x65a9 172#define RxDefaultAnt2 0x569a 173 174/* 3 Export Interface */ 175 176/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ 177void ODM_DMInit(struct odm_dm_struct *pDM_Odm) 178{ 179 /* 2012.05.03 Luke: For all IC series */ 180 odm_CommonInfoSelfInit(pDM_Odm); 181 odm_CmnInfoInit_Debug(pDM_Odm); 182 odm_DIGInit(pDM_Odm); 183 odm_RateAdaptiveMaskInit(pDM_Odm); 184 185 odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ 186 odm_DynamicBBPowerSavingInit(pDM_Odm); 187 odm_DynamicTxPowerInit(pDM_Odm); 188 odm_TXPowerTrackingInit(pDM_Odm); 189 ODM_EdcaTurboInit(pDM_Odm); 190 ODM_RAInfo_Init_all(pDM_Odm); 191 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 192 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 193 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 194 odm_InitHybridAntDiv(pDM_Odm); 195} 196 197/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ 198/* You can not add any dummy function here, be care, you can only use DM structure */ 199/* to perform any new ODM_DM. */ 200void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) 201{ 202 /* 2012.05.03 Luke: For all IC series */ 203 odm_CmnInfoHook_Debug(pDM_Odm); 204 odm_CmnInfoUpdate_Debug(pDM_Odm); 205 odm_CommonInfoSelfUpdate(pDM_Odm); 206 odm_FalseAlarmCounterStatistics(pDM_Odm); 207 odm_RSSIMonitorCheck(pDM_Odm); 208 209 /* Fix Leave LPS issue */ 210 odm_DIG(pDM_Odm); 211 odm_CCKPacketDetectionThresh(pDM_Odm); 212 213 if (*(pDM_Odm->pbPowerSaving)) 214 return; 215 216 odm_RefreshRateAdaptiveMask(pDM_Odm); 217 218 odm_DynamicBBPowerSaving(pDM_Odm); 219 odm_DynamicPrimaryCCA(pDM_Odm); 220 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 221 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 222 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 223 odm_HwAntDiv(pDM_Odm); 224 225 ODM_TXPowerTrackingCheck(pDM_Odm); 226 odm_EdcaTurboCheck(pDM_Odm); 227 odm_DynamicTxPower(pDM_Odm); 228} 229 230/* Init /.. Fixed HW value. Only init time. */ 231void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value) 232{ 233 /* This section is used for init value */ 234 switch (CmnInfo) { 235 /* Fixed ODM value. */ 236 case ODM_CMNINFO_ABILITY: 237 pDM_Odm->SupportAbility = (u32)Value; 238 break; 239 case ODM_CMNINFO_PLATFORM: 240 pDM_Odm->SupportPlatform = (u8)Value; 241 break; 242 case ODM_CMNINFO_INTERFACE: 243 pDM_Odm->SupportInterface = (u8)Value; 244 break; 245 case ODM_CMNINFO_MP_TEST_CHIP: 246 pDM_Odm->bIsMPChip = (u8)Value; 247 break; 248 case ODM_CMNINFO_IC_TYPE: 249 pDM_Odm->SupportICType = Value; 250 break; 251 case ODM_CMNINFO_CUT_VER: 252 pDM_Odm->CutVersion = (u8)Value; 253 break; 254 case ODM_CMNINFO_FAB_VER: 255 pDM_Odm->FabVersion = (u8)Value; 256 break; 257 case ODM_CMNINFO_RF_TYPE: 258 pDM_Odm->RFType = (u8)Value; 259 break; 260 case ODM_CMNINFO_RF_ANTENNA_TYPE: 261 pDM_Odm->AntDivType = (u8)Value; 262 break; 263 case ODM_CMNINFO_BOARD_TYPE: 264 pDM_Odm->BoardType = (u8)Value; 265 break; 266 case ODM_CMNINFO_EXT_LNA: 267 pDM_Odm->ExtLNA = (u8)Value; 268 break; 269 case ODM_CMNINFO_EXT_PA: 270 pDM_Odm->ExtPA = (u8)Value; 271 break; 272 case ODM_CMNINFO_EXT_TRSW: 273 pDM_Odm->ExtTRSW = (u8)Value; 274 break; 275 case ODM_CMNINFO_PATCH_ID: 276 pDM_Odm->PatchID = (u8)Value; 277 break; 278 case ODM_CMNINFO_BINHCT_TEST: 279 pDM_Odm->bInHctTest = (bool)Value; 280 break; 281 case ODM_CMNINFO_BWIFI_TEST: 282 pDM_Odm->bWIFITest = (bool)Value; 283 break; 284 case ODM_CMNINFO_SMART_CONCURRENT: 285 pDM_Odm->bDualMacSmartConcurrent = (bool)Value; 286 break; 287 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 288 default: 289 /* do nothing */ 290 break; 291 } 292 293 /* Tx power tracking BB swing table. */ 294 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ 295 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */ 296 pDM_Odm->BbSwingIdxOfdmCurrent = 12; 297 pDM_Odm->BbSwingFlagOfdm = false; 298} 299 300void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue) 301{ 302 /* */ 303 /* Hook call by reference pointer. */ 304 /* */ 305 switch (CmnInfo) { 306 /* Dynamic call by reference pointer. */ 307 case ODM_CMNINFO_MAC_PHY_MODE: 308 pDM_Odm->pMacPhyMode = (u8 *)pValue; 309 break; 310 case ODM_CMNINFO_TX_UNI: 311 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue; 312 break; 313 case ODM_CMNINFO_RX_UNI: 314 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue; 315 break; 316 case ODM_CMNINFO_WM_MODE: 317 pDM_Odm->pWirelessMode = (u8 *)pValue; 318 break; 319 case ODM_CMNINFO_BAND: 320 pDM_Odm->pBandType = (u8 *)pValue; 321 break; 322 case ODM_CMNINFO_SEC_CHNL_OFFSET: 323 pDM_Odm->pSecChOffset = (u8 *)pValue; 324 break; 325 case ODM_CMNINFO_SEC_MODE: 326 pDM_Odm->pSecurity = (u8 *)pValue; 327 break; 328 case ODM_CMNINFO_BW: 329 pDM_Odm->pBandWidth = (u8 *)pValue; 330 break; 331 case ODM_CMNINFO_CHNL: 332 pDM_Odm->pChannel = (u8 *)pValue; 333 break; 334 case ODM_CMNINFO_DMSP_GET_VALUE: 335 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue; 336 break; 337 case ODM_CMNINFO_BUDDY_ADAPTOR: 338 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue; 339 break; 340 case ODM_CMNINFO_DMSP_IS_MASTER: 341 pDM_Odm->pbMasterOfDMSP = (bool *)pValue; 342 break; 343 case ODM_CMNINFO_SCAN: 344 pDM_Odm->pbScanInProcess = (bool *)pValue; 345 break; 346 case ODM_CMNINFO_POWER_SAVING: 347 pDM_Odm->pbPowerSaving = (bool *)pValue; 348 break; 349 case ODM_CMNINFO_ONE_PATH_CCA: 350 pDM_Odm->pOnePathCCA = (u8 *)pValue; 351 break; 352 case ODM_CMNINFO_DRV_STOP: 353 pDM_Odm->pbDriverStopped = (bool *)pValue; 354 break; 355 case ODM_CMNINFO_PNP_IN: 356 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue; 357 break; 358 case ODM_CMNINFO_INIT_ON: 359 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue; 360 break; 361 case ODM_CMNINFO_ANT_TEST: 362 pDM_Odm->pAntennaTest = (u8 *)pValue; 363 break; 364 case ODM_CMNINFO_NET_CLOSED: 365 pDM_Odm->pbNet_closed = (bool *)pValue; 366 break; 367 case ODM_CMNINFO_MP_MODE: 368 pDM_Odm->mp_mode = (u8 *)pValue; 369 break; 370 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 371 default: 372 /* do nothing */ 373 break; 374 } 375} 376 377void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue) 378{ 379 /* Hook call by reference pointer. */ 380 switch (CmnInfo) { 381 /* Dynamic call by reference pointer. */ 382 case ODM_CMNINFO_STA_STATUS: 383 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue; 384 break; 385 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 386 default: 387 /* do nothing */ 388 break; 389 } 390} 391 392/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ 393void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value) 394{ 395 /* */ 396 /* This init variable may be changed in run time. */ 397 /* */ 398 switch (CmnInfo) { 399 case ODM_CMNINFO_ABILITY: 400 pDM_Odm->SupportAbility = (u32)Value; 401 break; 402 case ODM_CMNINFO_RF_TYPE: 403 pDM_Odm->RFType = (u8)Value; 404 break; 405 case ODM_CMNINFO_WIFI_DIRECT: 406 pDM_Odm->bWIFI_Direct = (bool)Value; 407 break; 408 case ODM_CMNINFO_WIFI_DISPLAY: 409 pDM_Odm->bWIFI_Display = (bool)Value; 410 break; 411 case ODM_CMNINFO_LINK: 412 pDM_Odm->bLinked = (bool)Value; 413 break; 414 case ODM_CMNINFO_RSSI_MIN: 415 pDM_Odm->RSSI_Min = (u8)Value; 416 break; 417 case ODM_CMNINFO_DBG_COMP: 418 pDM_Odm->DebugComponents = Value; 419 break; 420 case ODM_CMNINFO_DBG_LEVEL: 421 pDM_Odm->DebugLevel = (u32)Value; 422 break; 423 case ODM_CMNINFO_RA_THRESHOLD_HIGH: 424 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value; 425 break; 426 case ODM_CMNINFO_RA_THRESHOLD_LOW: 427 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value; 428 break; 429 } 430} 431 432void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) 433{ 434 struct adapter *adapter = pDM_Odm->Adapter; 435 436 pDM_Odm->bCckHighPower = (bool) PHY_QueryBBReg(adapter, 0x824, BIT9); 437 pDM_Odm->RFPathRxEnable = (u8) PHY_QueryBBReg(adapter, 0xc04, 0x0F); 438 439 ODM_InitDebugSetting(pDM_Odm); 440} 441 442void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) 443{ 444 u8 EntryCnt = 0; 445 u8 i; 446 struct sta_info *pEntry; 447 448 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { 449 if (*(pDM_Odm->pSecChOffset) == 1) 450 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; 451 else if (*(pDM_Odm->pSecChOffset) == 2) 452 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; 453 } else { 454 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); 455 } 456 457 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 458 pEntry = pDM_Odm->pODM_StaInfo[i]; 459 if (IS_STA_VALID(pEntry)) 460 EntryCnt++; 461 } 462 if (EntryCnt == 1) 463 pDM_Odm->bOneEntryOnly = true; 464 else 465 pDM_Odm->bOneEntryOnly = false; 466} 467 468void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm) 469{ 470 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); 471 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform)); 472 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility)); 473 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface)); 474 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType)); 475 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion)); 476 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n", pDM_Odm->FabVersion)); 477 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n", pDM_Odm->RFType)); 478 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType)); 479 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA)); 480 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA)); 481 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW)); 482 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID)); 483 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest)); 484 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest)); 485 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent)); 486} 487 488void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm) 489{ 490 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); 491 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast))); 492 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast))); 493 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode))); 494 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset))); 495 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity))); 496 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth))); 497 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel))); 498 499 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess))); 500 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving))); 501} 502 503void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm) 504{ 505 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); 506 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct)); 507 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display)); 508 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked)); 509 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min)); 510} 511 512void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) 513{ 514 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 515 struct adapter *adapter = pDM_Odm->Adapter; 516 517 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 518 ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", 519 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm))); 520 521 if (pDM_DigTable->CurIGValue != CurrentIGI) { 522 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 523 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n", CurrentIGI)); 524 /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */ 525 pDM_DigTable->CurIGValue = CurrentIGI; 526 } 527 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x\n", CurrentIGI)); 528 529/* Add by Neil Chen to enable edcca to MP Platform */ 530} 531 532/* Need LPS mode for CE platform --2012--08--24--- */ 533/* 8723AS/8189ES */ 534void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm) 535{ 536 struct adapter *pAdapter = pDM_Odm->Adapter; 537 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 538 539 u8 RSSI_Lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */ 540 u8 bFwCurrentInPSMode = false; 541 u8 CurrentIGI = pDM_Odm->RSSI_Min; 542 543 CurrentIGI = CurrentIGI + RSSI_OFFSET_DIG; 544 bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode; 545 546 /* Using FW PS mode to make IGI */ 547 if (bFwCurrentInPSMode) { 548 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n")); 549 /* Adjust by FA in LPS MODE */ 550 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS) 551 CurrentIGI = CurrentIGI+2; 552 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) 553 CurrentIGI = CurrentIGI+1; 554 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) 555 CurrentIGI = CurrentIGI-1; 556 } else { 557 CurrentIGI = RSSI_Lower; 558 } 559 560 /* Lower bound checking */ 561 562 /* RSSI Lower bound check */ 563 if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) 564 RSSI_Lower = (pDM_Odm->RSSI_Min-10); 565 else 566 RSSI_Lower = DM_DIG_MIN_NIC; 567 568 /* Upper and Lower Bound checking */ 569 if (CurrentIGI > DM_DIG_MAX_NIC) 570 CurrentIGI = DM_DIG_MAX_NIC; 571 else if (CurrentIGI < RSSI_Lower) 572 CurrentIGI = RSSI_Lower; 573 574 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 575} 576 577void odm_DIGInit(struct odm_dm_struct *pDM_Odm) 578{ 579 struct adapter *adapter = pDM_Odm->Adapter; 580 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 581 582 pDM_DigTable->CurIGValue = (u8) PHY_QueryBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); 583 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; 584 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; 585 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW; 586 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH; 587 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) { 588 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 589 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 590 } else { 591 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 592 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 593 } 594 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; 595 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; 596 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; 597 pDM_DigTable->PreCCK_CCAThres = 0xFF; 598 pDM_DigTable->CurCCK_CCAThres = 0x83; 599 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; 600 pDM_DigTable->LargeFAHit = 0; 601 pDM_DigTable->Recover_cnt = 0; 602 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; 603 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; 604 pDM_DigTable->bMediaConnect_0 = false; 605 pDM_DigTable->bMediaConnect_1 = false; 606 607 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */ 608 pDM_Odm->bDMInitialGainEnable = true; 609} 610 611void odm_DIG(struct odm_dm_struct *pDM_Odm) 612{ 613 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 614 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 615 u8 DIG_Dynamic_MIN; 616 u8 DIG_MaxOfMin; 617 bool FirstConnect, FirstDisConnect; 618 u8 dm_dig_max, dm_dig_min; 619 u8 CurrentIGI = pDM_DigTable->CurIGValue; 620 621 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); 622 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) { 623 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 624 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); 625 return; 626 } 627 628 if (*(pDM_Odm->pbScanInProcess)) { 629 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n")); 630 return; 631 } 632 633 /* add by Neil Chen to avoid PSD is processing */ 634 if (pDM_Odm->bDMInitialGainEnable == false) { 635 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n")); 636 return; 637 } 638 639 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 640 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 641 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 642 643 /* 1 Boundary Decision */ 644 dm_dig_max = DM_DIG_MAX_NIC; 645 dm_dig_min = DM_DIG_MIN_NIC; 646 DIG_MaxOfMin = DM_DIG_MAX_AP; 647 648 if (pDM_Odm->bLinked) { 649 /* 2 Modify DIG upper bound */ 650 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) 651 pDM_DigTable->rx_gain_range_max = dm_dig_max; 652 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min) 653 pDM_DigTable->rx_gain_range_max = dm_dig_min; 654 else 655 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; 656 /* 2 Modify DIG lower bound */ 657 if (pDM_Odm->bOneEntryOnly) { 658 if (pDM_Odm->RSSI_Min < dm_dig_min) 659 DIG_Dynamic_MIN = dm_dig_min; 660 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) 661 DIG_Dynamic_MIN = DIG_MaxOfMin; 662 else 663 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; 664 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 665 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n", 666 DIG_Dynamic_MIN)); 667 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 668 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n", 669 pDM_Odm->RSSI_Min)); 670 } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) { 671 /* 1 Lower Bound for 88E AntDiv */ 672 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { 673 DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max; 674 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 675 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n", 676 pDM_DigTable->AntDiv_RSSI_max)); 677 } 678 } else { 679 DIG_Dynamic_MIN = dm_dig_min; 680 } 681 } else { 682 pDM_DigTable->rx_gain_range_max = dm_dig_max; 683 DIG_Dynamic_MIN = dm_dig_min; 684 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); 685 } 686 687 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ 688 if (pFalseAlmCnt->Cnt_all > 10000) { 689 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n")); 690 691 if (pDM_DigTable->LargeFAHit != 3) 692 pDM_DigTable->LargeFAHit++; 693 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { 694 pDM_DigTable->ForbiddenIGI = CurrentIGI; 695 pDM_DigTable->LargeFAHit = 1; 696 } 697 698 if (pDM_DigTable->LargeFAHit >= 3) { 699 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max) 700 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; 701 else 702 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 703 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ 704 } 705 706 } else { 707 /* Recovery mechanism for IGI lower bound */ 708 if (pDM_DigTable->Recover_cnt != 0) { 709 pDM_DigTable->Recover_cnt--; 710 } else { 711 if (pDM_DigTable->LargeFAHit < 3) { 712 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */ 713 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 714 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 715 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); 716 } else { 717 pDM_DigTable->ForbiddenIGI--; 718 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 719 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); 720 } 721 } else { 722 pDM_DigTable->LargeFAHit = 0; 723 } 724 } 725 } 726 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 727 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n", 728 pDM_DigTable->LargeFAHit)); 729 730 /* 1 Adjust initial gain by false alarm */ 731 if (pDM_Odm->bLinked) { 732 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); 733 if (FirstConnect) { 734 CurrentIGI = pDM_Odm->RSSI_Min; 735 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); 736 } else { 737 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) 738 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 739 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) 740 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 741 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) 742 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 743 } 744 } else { 745 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); 746 if (FirstDisConnect) { 747 CurrentIGI = pDM_DigTable->rx_gain_range_min; 748 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n")); 749 } else { 750 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ 751 if (pFalseAlmCnt->Cnt_all > 10000) 752 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 753 else if (pFalseAlmCnt->Cnt_all > 8000) 754 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 755 else if (pFalseAlmCnt->Cnt_all < 500) 756 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 757 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n")); 758 } 759 } 760 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); 761 /* 1 Check initial gain by upper/lower bound */ 762 if (CurrentIGI > pDM_DigTable->rx_gain_range_max) 763 CurrentIGI = pDM_DigTable->rx_gain_range_max; 764 if (CurrentIGI < pDM_DigTable->rx_gain_range_min) 765 CurrentIGI = pDM_DigTable->rx_gain_range_min; 766 767 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 768 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", 769 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); 770 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); 771 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); 772 773 /* 2 High power RSSI threshold */ 774 775 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 776 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; 777 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; 778} 779 780/* 3============================================================ */ 781/* 3 FASLE ALARM CHECK */ 782/* 3============================================================ */ 783 784void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 785{ 786 struct adapter *adapter = pDM_Odm->Adapter; 787 u32 ret_value; 788 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 789 790 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) 791 return; 792 793 /* hold ofdm counter */ 794 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ 795 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ 796 797 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); 798 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); 799 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); 800 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); 801 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); 802 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); 803 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); 804 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); 805 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); 806 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); 807 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); 808 809 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + 810 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + 811 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; 812 813 ret_value = PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); 814 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); 815 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); 816 817 /* hold cck counter */ 818 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); 819 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); 820 821 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); 822 FalseAlmCnt->Cnt_Cck_fail = ret_value; 823 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); 824 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8; 825 826 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); 827 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8); 828 829 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + 830 FalseAlmCnt->Cnt_SB_Search_fail + 831 FalseAlmCnt->Cnt_Parity_Fail + 832 FalseAlmCnt->Cnt_Rate_Illegal + 833 FalseAlmCnt->Cnt_Crc8_fail + 834 FalseAlmCnt->Cnt_Mcs_fail + 835 FalseAlmCnt->Cnt_Cck_fail); 836 837 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; 838 839 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); 840 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 841 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", 842 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); 843 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 844 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", 845 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); 846 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 847 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", 848 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); 849 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); 850 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); 851 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); 852} 853 854/* 3============================================================ */ 855/* 3 CCK Packet Detect Threshold */ 856/* 3============================================================ */ 857 858void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) 859{ 860 u8 CurCCK_CCAThres; 861 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 862 863 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) 864 return; 865 if (pDM_Odm->ExtLNA) 866 return; 867 if (pDM_Odm->bLinked) { 868 if (pDM_Odm->RSSI_Min > 25) { 869 CurCCK_CCAThres = 0xcd; 870 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) { 871 CurCCK_CCAThres = 0x83; 872 } else { 873 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 874 CurCCK_CCAThres = 0x83; 875 else 876 CurCCK_CCAThres = 0x40; 877 } 878 } else { 879 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 880 CurCCK_CCAThres = 0x83; 881 else 882 CurCCK_CCAThres = 0x40; 883 } 884 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); 885} 886 887void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres) 888{ 889 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 890 891 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ 892 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres); 893 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; 894 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; 895} 896 897/* 3============================================================ */ 898/* 3 BB Power Save */ 899/* 3============================================================ */ 900void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm) 901{ 902 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 903 904 pDM_PSTable->PreCCAState = CCA_MAX; 905 pDM_PSTable->CurCCAState = CCA_MAX; 906 pDM_PSTable->PreRFState = RF_MAX; 907 pDM_PSTable->CurRFState = RF_MAX; 908 pDM_PSTable->Rssi_val_min = 0; 909 pDM_PSTable->initialize = 0; 910} 911 912void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm) 913{ 914} 915 916void odm_1R_CCA(struct odm_dm_struct *pDM_Odm) 917{ 918 struct adapter *adapter = pDM_Odm->Adapter; 919 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 920 921 if (pDM_Odm->RSSI_Min != 0xFF) { 922 if (pDM_PSTable->PreCCAState == CCA_2R) { 923 if (pDM_Odm->RSSI_Min >= 35) 924 pDM_PSTable->CurCCAState = CCA_1R; 925 else 926 pDM_PSTable->CurCCAState = CCA_2R; 927 } else { 928 if (pDM_Odm->RSSI_Min <= 30) 929 pDM_PSTable->CurCCAState = CCA_2R; 930 else 931 pDM_PSTable->CurCCAState = CCA_1R; 932 } 933 } else { 934 pDM_PSTable->CurCCAState = CCA_MAX; 935 } 936 937 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) { 938 if (pDM_PSTable->CurCCAState == CCA_1R) { 939 if (pDM_Odm->RFType == ODM_2T2R) 940 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x13); 941 else 942 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x23); 943 } else { 944 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x33); 945 } 946 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; 947 } 948} 949 950void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 951{ 952 struct adapter *adapter = pDM_Odm->Adapter; 953 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 954 u8 Rssi_Up_bound = 30; 955 u8 Rssi_Low_bound = 25; 956 957 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */ 958 Rssi_Up_bound = 50; 959 Rssi_Low_bound = 45; 960 } 961 if (pDM_PSTable->initialize == 0) { 962 pDM_PSTable->Reg874 = (PHY_QueryBBReg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14; 963 pDM_PSTable->RegC70 = (PHY_QueryBBReg(adapter, 0xc70, bMaskDWord)&BIT3)>>3; 964 pDM_PSTable->Reg85C = (PHY_QueryBBReg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; 965 pDM_PSTable->RegA74 = (PHY_QueryBBReg(adapter, 0xa74, bMaskDWord)&0xF000)>>12; 966 pDM_PSTable->initialize = 1; 967 } 968 969 if (!bForceInNormal) { 970 if (pDM_Odm->RSSI_Min != 0xFF) { 971 if (pDM_PSTable->PreRFState == RF_Normal) { 972 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound) 973 pDM_PSTable->CurRFState = RF_Save; 974 else 975 pDM_PSTable->CurRFState = RF_Normal; 976 } else { 977 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound) 978 pDM_PSTable->CurRFState = RF_Normal; 979 else 980 pDM_PSTable->CurRFState = RF_Save; 981 } 982 } else { 983 pDM_PSTable->CurRFState = RF_MAX; 984 } 985 } else { 986 pDM_PSTable->CurRFState = RF_Normal; 987 } 988 989 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { 990 if (pDM_PSTable->CurRFState == RF_Save) { 991 PHY_SetBBReg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ 992 PHY_SetBBReg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ 993 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ 994 PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ 995 PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ 996 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ 997 PHY_SetBBReg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ 998 } else { 999 PHY_SetBBReg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); 1000 PHY_SetBBReg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); 1001 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); 1002 PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); 1003 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); 1004 } 1005 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; 1006 } 1007} 1008 1009/* 3============================================================ */ 1010/* 3 RATR MASK */ 1011/* 3============================================================ */ 1012/* 3============================================================ */ 1013/* 3 Rate Adaptive */ 1014/* 3============================================================ */ 1015 1016void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm) 1017{ 1018 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive; 1019 1020 pOdmRA->Type = DM_Type_ByDriver; 1021 if (pOdmRA->Type == DM_Type_ByDriver) 1022 pDM_Odm->bUseRAMask = true; 1023 else 1024 pDM_Odm->bUseRAMask = false; 1025 1026 pOdmRA->RATRState = DM_RATR_STA_INIT; 1027 pOdmRA->HighRSSIThresh = 50; 1028 pOdmRA->LowRSSIThresh = 20; 1029} 1030 1031u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level) 1032{ 1033 struct sta_info *pEntry; 1034 u32 rate_bitmap = 0x0fffffff; 1035 u8 WirelessMode; 1036 1037 pEntry = pDM_Odm->pODM_StaInfo[macid]; 1038 if (!IS_STA_VALID(pEntry)) 1039 return ra_mask; 1040 1041 WirelessMode = pEntry->wireless_mode; 1042 1043 switch (WirelessMode) { 1044 case ODM_WM_B: 1045 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ 1046 rate_bitmap = 0x0000000d; 1047 else 1048 rate_bitmap = 0x0000000f; 1049 break; 1050 case (ODM_WM_A|ODM_WM_G): 1051 if (rssi_level == DM_RATR_STA_HIGH) 1052 rate_bitmap = 0x00000f00; 1053 else 1054 rate_bitmap = 0x00000ff0; 1055 break; 1056 case (ODM_WM_B|ODM_WM_G): 1057 if (rssi_level == DM_RATR_STA_HIGH) 1058 rate_bitmap = 0x00000f00; 1059 else if (rssi_level == DM_RATR_STA_MIDDLE) 1060 rate_bitmap = 0x00000ff0; 1061 else 1062 rate_bitmap = 0x00000ff5; 1063 break; 1064 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1065 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1066 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { 1067 if (rssi_level == DM_RATR_STA_HIGH) { 1068 rate_bitmap = 0x000f0000; 1069 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1070 rate_bitmap = 0x000ff000; 1071 } else { 1072 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1073 rate_bitmap = 0x000ff015; 1074 else 1075 rate_bitmap = 0x000ff005; 1076 } 1077 } else { 1078 if (rssi_level == DM_RATR_STA_HIGH) { 1079 rate_bitmap = 0x0f8f0000; 1080 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1081 rate_bitmap = 0x0f8ff000; 1082 } else { 1083 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1084 rate_bitmap = 0x0f8ff015; 1085 else 1086 rate_bitmap = 0x0f8ff005; 1087 } 1088 } 1089 break; 1090 default: 1091 /* case WIRELESS_11_24N: */ 1092 /* case WIRELESS_11_5N: */ 1093 if (pDM_Odm->RFType == RF_1T2R) 1094 rate_bitmap = 0x000fffff; 1095 else 1096 rate_bitmap = 0x0fffffff; 1097 break; 1098 } 1099 1100 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1101 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", 1102 rssi_level, WirelessMode, rate_bitmap)); 1103 1104 return rate_bitmap; 1105} 1106 1107/*----------------------------------------------------------------------------- 1108 * Function: odm_RefreshRateAdaptiveMask() 1109 * 1110 * Overview: Update rate table mask according to rssi 1111 * 1112 * Input: NONE 1113 * 1114 * Output: NONE 1115 * 1116 * Return: NONE 1117 * 1118 * Revised History: 1119 * When Who Remark 1120 * 05/27/2009 hpfan Create Version 0. 1121 * 1122 *---------------------------------------------------------------------------*/ 1123void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm) 1124{ 1125 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) 1126 return; 1127 /* */ 1128 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1129 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1130 /* HW dynamic mechanism. */ 1131 /* */ 1132 odm_RefreshRateAdaptiveMaskCE(pDM_Odm); 1133} 1134 1135void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm) 1136{ 1137} 1138 1139void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm) 1140{ 1141 u8 i; 1142 struct adapter *pAdapter = pDM_Odm->Adapter; 1143 1144 if (pAdapter->bDriverStopped) { 1145 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); 1146 return; 1147 } 1148 1149 if (!pDM_Odm->bUseRAMask) { 1150 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); 1151 return; 1152 } 1153 1154 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1155 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; 1156 if (IS_STA_VALID(pstat)) { 1157 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) { 1158 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1159 ("RSSI:%d, RSSI_LEVEL:%d\n", 1160 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); 1161 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level); 1162 } 1163 } 1164 } 1165} 1166 1167void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm) 1168{ 1169} 1170 1171/* Return Value: bool */ 1172/* - true: RATRState is changed. */ 1173bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState) 1174{ 1175 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive; 1176 const u8 GoUpGap = 5; 1177 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh; 1178 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; 1179 u8 RATRState; 1180 1181 /* Threshold Adjustment: */ 1182 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ 1183 /* Here GoUpGap is added to solve the boundary's level alternation issue. */ 1184 switch (*pRATRState) { 1185 case DM_RATR_STA_INIT: 1186 case DM_RATR_STA_HIGH: 1187 break; 1188 case DM_RATR_STA_MIDDLE: 1189 HighRSSIThreshForRA += GoUpGap; 1190 break; 1191 case DM_RATR_STA_LOW: 1192 HighRSSIThreshForRA += GoUpGap; 1193 LowRSSIThreshForRA += GoUpGap; 1194 break; 1195 default: 1196 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState)); 1197 break; 1198 } 1199 1200 /* Decide RATRState by RSSI. */ 1201 if (RSSI > HighRSSIThreshForRA) 1202 RATRState = DM_RATR_STA_HIGH; 1203 else if (RSSI > LowRSSIThreshForRA) 1204 RATRState = DM_RATR_STA_MIDDLE; 1205 else 1206 RATRState = DM_RATR_STA_LOW; 1207 1208 if (*pRATRState != RATRState || bForceUpdate) { 1209 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState)); 1210 *pRATRState = RATRState; 1211 return true; 1212 } 1213 return false; 1214} 1215 1216/* 3============================================================ */ 1217/* 3 Dynamic Tx Power */ 1218/* 3============================================================ */ 1219 1220void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm) 1221{ 1222 struct adapter *Adapter = pDM_Odm->Adapter; 1223 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1224 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1225 pdmpriv->bDynamicTxPowerEnable = false; 1226 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; 1227 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; 1228} 1229 1230void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm) 1231{ 1232 /* For AP/ADSL use struct rtl8192cd_priv * */ 1233 /* For CE/NIC use struct adapter * */ 1234 1235 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1236 return; 1237 1238 /* 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */ 1239 if (!pDM_Odm->ExtPA) 1240 return; 1241 1242 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1243 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1244 /* HW dynamic mechanism. */ 1245 odm_DynamicTxPowerNIC(pDM_Odm); 1246} 1247 1248void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm) 1249{ 1250} 1251 1252/* 3============================================================ */ 1253/* 3 RSSI Monitor */ 1254/* 3============================================================ */ 1255 1256void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm) 1257{ 1258 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) 1259 return; 1260 1261 /* */ 1262 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1263 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1264 /* HW dynamic mechanism. */ 1265 /* */ 1266 odm_RSSIMonitorCheckCE(pDM_Odm); 1267} /* odm_RSSIMonitorCheck */ 1268 1269static void FindMinimumRSSI(struct adapter *pAdapter) 1270{ 1271 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); 1272 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1273 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; 1274 1275 /* 1 1.Determine the minimum RSSI */ 1276 if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) && 1277 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) 1278 pdmpriv->MinUndecoratedPWDBForDM = 0; 1279 if (check_fwstate(pmlmepriv, _FW_LINKED) == true) /* Default port */ 1280 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1281 else /* associated entry pwdb */ 1282 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1283} 1284 1285void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm) 1286{ 1287 struct adapter *Adapter = pDM_Odm->Adapter; 1288 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1289 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1290 int i; 1291 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; 1292 u8 sta_cnt = 0; 1293 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ 1294 struct sta_info *psta; 1295 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 1296 1297 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) 1298 return; 1299 1300 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1301 psta = pDM_Odm->pODM_StaInfo[i]; 1302 if (IS_STA_VALID(psta) && 1303 (psta->state & WIFI_ASOC_STATE) && 1304 !_rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) && 1305 !_rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) { 1306 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) 1307 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1308 1309 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) 1310 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1311 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) 1312 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16)); 1313 } 1314 } 1315 1316 for (i = 0; i < sta_cnt; i++) { 1317 if (PWDB_rssi[i] != (0)) { 1318 if (pHalData->fw_ractrl) { 1319 /* Report every sta's RSSI to FW */ 1320 } else { 1321 ODM_RA_SetRSSI_8188E( 1322 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); 1323 } 1324 } 1325 } 1326 1327 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */ 1328 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; 1329 else 1330 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; 1331 1332 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */ 1333 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; 1334 else 1335 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; 1336 1337 FindMinimumRSSI(Adapter); 1338 ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); 1339} 1340 1341/* 3============================================================ */ 1342/* 3 Tx Power Tracking */ 1343/* 3============================================================ */ 1344 1345void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm) 1346{ 1347 odm_TXPowerTrackingThermalMeterInit(pDM_Odm); 1348} 1349 1350void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm) 1351{ 1352 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; 1353 pDM_Odm->RFCalibrateInfo.TXPowercount = 0; 1354 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; 1355 if (*(pDM_Odm->mp_mode) != 1) 1356 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1357 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); 1358 1359 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1360} 1361 1362void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm) 1363{ 1364 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1365 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1366 /* HW dynamic mechanism. */ 1367 odm_TXPowerTrackingCheckCE(pDM_Odm); 1368} 1369 1370void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 1371{ 1372 struct adapter *Adapter = pDM_Odm->Adapter; 1373 1374 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) 1375 return; 1376 1377 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ 1378 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); 1379 1380 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; 1381 return; 1382 } else { 1383 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); 1384 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; 1385 } 1386} 1387 1388/* antenna mapping info */ 1389/* 1: right-side antenna */ 1390/* 2/0: left-side antenna */ 1391/* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */ 1392/* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */ 1393/* We select left antenna as default antenna in initial process, modify it as needed */ 1394/* */ 1395 1396/* 3============================================================ */ 1397/* 3 SW Antenna Diversity */ 1398/* 3============================================================ */ 1399 1400void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) 1401{ 1402} 1403 1404/* 3============================================================ */ 1405/* 3 SW Antenna Diversity */ 1406/* 3============================================================ */ 1407 1408void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) 1409{ 1410 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1411 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1412 return; 1413 } 1414 1415 ODM_AntennaDiversityInit_88E(pDM_Odm); 1416} 1417 1418void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) 1419{ 1420 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1421 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1422 return; 1423 } 1424 1425 ODM_AntennaDiversity_88E(pDM_Odm); 1426} 1427 1428/* EDCA Turbo */ 1429void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) 1430{ 1431 struct adapter *Adapter = pDM_Odm->Adapter; 1432 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1433 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; 1434 Adapter->recvpriv.bIsAnyNonBEPkts = false; 1435 1436 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM))); 1437 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM))); 1438 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM))); 1439 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM))); 1440} /* ODM_InitEdcaTurbo */ 1441 1442void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm) 1443{ 1444 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1445 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1446 /* HW dynamic mechanism. */ 1447 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n")); 1448 1449 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)) 1450 return; 1451 1452 odm_EdcaTurboCheckCE(pDM_Odm); 1453 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n")); 1454} /* odm_CheckEdcaTurbo */ 1455 1456void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm) 1457{ 1458 struct adapter *Adapter = pDM_Odm->Adapter; 1459 u32 trafficIndex; 1460 u32 edca_param; 1461 u64 cur_tx_bytes = 0; 1462 u64 cur_rx_bytes = 0; 1463 u8 bbtchange = false; 1464 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1465 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); 1466 struct recv_priv *precvpriv = &(Adapter->recvpriv); 1467 struct registry_priv *pregpriv = &Adapter->registrypriv; 1468 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); 1469 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 1470 1471 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */ 1472 goto dm_CheckEdcaTurbo_EXIT; 1473 1474 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) 1475 goto dm_CheckEdcaTurbo_EXIT; 1476 1477 /* Check if the status needs to be changed. */ 1478 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) { 1479 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; 1480 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; 1481 1482 /* traffic, TX or RX */ 1483 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) || 1484 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { 1485 if (cur_tx_bytes > (cur_rx_bytes << 2)) { 1486 /* Uplink TP is present. */ 1487 trafficIndex = UP_LINK; 1488 } else { 1489 /* Balance TP is present. */ 1490 trafficIndex = DOWN_LINK; 1491 } 1492 } else { 1493 if (cur_rx_bytes > (cur_tx_bytes << 2)) { 1494 /* Downlink TP is present. */ 1495 trafficIndex = DOWN_LINK; 1496 } else { 1497 /* Balance TP is present. */ 1498 trafficIndex = UP_LINK; 1499 } 1500 } 1501 1502 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) { 1503 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) 1504 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; 1505 else 1506 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; 1507 1508 rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); 1509 1510 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; 1511 } 1512 1513 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; 1514 } else { 1515 /* Turn Off EDCA turbo here. */ 1516 /* Restore original EDCA according to the declaration of AP. */ 1517 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { 1518 rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); 1519 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1520 } 1521 } 1522 1523dm_CheckEdcaTurbo_EXIT: 1524 /* Set variables for next time. */ 1525 precvpriv->bIsAnyNonBEPkts = false; 1526 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; 1527 precvpriv->last_rx_bytes = precvpriv->rx_bytes; 1528} 1529 1530u32 ConvertTo_dB(u32 Value) 1531{ 1532 u8 i; 1533 u8 j; 1534 u32 dB; 1535 1536 Value = Value & 0xFFFF; 1537 for (i = 0; i < 8; i++) { 1538 if (Value <= dB_Invert_Table[i][11]) 1539 break; 1540 } 1541 1542 if (i >= 8) 1543 return 96; /* maximum 96 dB */ 1544 1545 for (j = 0; j < 12; j++) { 1546 if (Value <= dB_Invert_Table[i][j]) 1547 break; 1548 } 1549 1550 dB = i*12 + j + 1; 1551 1552 return dB; 1553} 1554