odm.c revision ffb2507078ec820007c09c82c356ca7694c31824
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 21/* include files */ 22 23#include "odm_precomp.h" 24 25static const u16 dB_Invert_Table[8][12] = { 26 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4}, 27 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16}, 28 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63}, 29 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251}, 30 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000}, 31 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, 32 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849}, 33 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} 34}; 35 36/* avoid to warn in FreeBSD ==> To DO modify */ 37static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { 38 /* UL DL */ 39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */ 40 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */ 41 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */ 42 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */ 43 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */ 44 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */ 45 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */ 46 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */ 47 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP=> 92U AP */ 48 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */ 49}; 50 51/* Global var */ 52u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { 53 0x7f8001fe, /* 0, +6.0dB */ 54 0x788001e2, /* 1, +5.5dB */ 55 0x71c001c7, /* 2, +5.0dB */ 56 0x6b8001ae, /* 3, +4.5dB */ 57 0x65400195, /* 4, +4.0dB */ 58 0x5fc0017f, /* 5, +3.5dB */ 59 0x5a400169, /* 6, +3.0dB */ 60 0x55400155, /* 7, +2.5dB */ 61 0x50800142, /* 8, +2.0dB */ 62 0x4c000130, /* 9, +1.5dB */ 63 0x47c0011f, /* 10, +1.0dB */ 64 0x43c0010f, /* 11, +0.5dB */ 65 0x40000100, /* 12, +0dB */ 66 0x3c8000f2, /* 13, -0.5dB */ 67 0x390000e4, /* 14, -1.0dB */ 68 0x35c000d7, /* 15, -1.5dB */ 69 0x32c000cb, /* 16, -2.0dB */ 70 0x300000c0, /* 17, -2.5dB */ 71 0x2d4000b5, /* 18, -3.0dB */ 72 0x2ac000ab, /* 19, -3.5dB */ 73 0x288000a2, /* 20, -4.0dB */ 74 0x26000098, /* 21, -4.5dB */ 75 0x24000090, /* 22, -5.0dB */ 76 0x22000088, /* 23, -5.5dB */ 77 0x20000080, /* 24, -6.0dB */ 78 0x1e400079, /* 25, -6.5dB */ 79 0x1c800072, /* 26, -7.0dB */ 80 0x1b00006c, /* 27. -7.5dB */ 81 0x19800066, /* 28, -8.0dB */ 82 0x18000060, /* 29, -8.5dB */ 83 0x16c0005b, /* 30, -9.0dB */ 84 0x15800056, /* 31, -9.5dB */ 85 0x14400051, /* 32, -10.0dB */ 86 0x1300004c, /* 33, -10.5dB */ 87 0x12000048, /* 34, -11.0dB */ 88 0x11000044, /* 35, -11.5dB */ 89 0x10000040, /* 36, -12.0dB */ 90 0x0f00003c,/* 37, -12.5dB */ 91 0x0e400039,/* 38, -13.0dB */ 92 0x0d800036,/* 39, -13.5dB */ 93 0x0cc00033,/* 40, -14.0dB */ 94 0x0c000030,/* 41, -14.5dB */ 95 0x0b40002d,/* 42, -15.0dB */ 96}; 97 98u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { 99 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ 100 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ 101 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ 102 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ 103 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ 104 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ 105 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ 106 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ 107 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ 108 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ 109 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ 110 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ 111 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ 112 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ 113 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ 114 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ 115 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ 116 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ 117 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ 118 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ 119 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ 120 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ 121 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ 122 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ 123 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ 124 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ 125 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ 126 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ 127 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ 128 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ 129 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ 130 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ 131 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ 132}; 133 134u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { 135 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ 136 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ 137 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ 138 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ 139 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ 140 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ 141 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ 142 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ 143 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ 144 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ 145 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ 146 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ 147 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ 148 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ 149 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ 150 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ 151 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ 152 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ 153 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ 154 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ 155 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ 156 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ 157 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ 158 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ 159 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ 160 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ 161 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ 162 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ 163 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ 164 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ 165 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ 166 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ 167 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ 168}; 169 170 171#define RxDefaultAnt1 0x65a9 172#define RxDefaultAnt2 0x569a 173 174/* 3 Export Interface */ 175 176/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */ 177void ODM_DMInit(struct odm_dm_struct *pDM_Odm) 178{ 179 /* 2012.05.03 Luke: For all IC series */ 180 odm_CommonInfoSelfInit(pDM_Odm); 181 odm_CmnInfoInit_Debug(pDM_Odm); 182 odm_DIGInit(pDM_Odm); 183 odm_RateAdaptiveMaskInit(pDM_Odm); 184 185 odm_PrimaryCCA_Init(pDM_Odm); /* Gary */ 186 odm_DynamicBBPowerSavingInit(pDM_Odm); 187 odm_DynamicTxPowerInit(pDM_Odm); 188 odm_TXPowerTrackingInit(pDM_Odm); 189 ODM_EdcaTurboInit(pDM_Odm); 190 ODM_RAInfo_Init_all(pDM_Odm); 191 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 192 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 193 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 194 odm_InitHybridAntDiv(pDM_Odm); 195} 196 197/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */ 198/* You can not add any dummy function here, be care, you can only use DM structure */ 199/* to perform any new ODM_DM. */ 200void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm) 201{ 202 /* 2012.05.03 Luke: For all IC series */ 203 odm_CmnInfoHook_Debug(pDM_Odm); 204 odm_CmnInfoUpdate_Debug(pDM_Odm); 205 odm_CommonInfoSelfUpdate(pDM_Odm); 206 odm_FalseAlarmCounterStatistics(pDM_Odm); 207 odm_RSSIMonitorCheck(pDM_Odm); 208 209 /* Fix Leave LPS issue */ 210 odm_DIG(pDM_Odm); 211 odm_CCKPacketDetectionThresh(pDM_Odm); 212 213 if (*(pDM_Odm->pbPowerSaving)) 214 return; 215 216 odm_RefreshRateAdaptiveMask(pDM_Odm); 217 218 odm_DynamicBBPowerSaving(pDM_Odm); 219 odm_DynamicPrimaryCCA(pDM_Odm); 220 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) || 221 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) || 222 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)) 223 odm_HwAntDiv(pDM_Odm); 224 225 ODM_TXPowerTrackingCheck(pDM_Odm); 226 odm_EdcaTurboCheck(pDM_Odm); 227 odm_DynamicTxPower(pDM_Odm); 228} 229 230/* Init /.. Fixed HW value. Only init time. */ 231void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u32 Value) 232{ 233 /* This section is used for init value */ 234 switch (CmnInfo) { 235 /* Fixed ODM value. */ 236 case ODM_CMNINFO_ABILITY: 237 pDM_Odm->SupportAbility = (u32)Value; 238 break; 239 case ODM_CMNINFO_PLATFORM: 240 pDM_Odm->SupportPlatform = (u8)Value; 241 break; 242 case ODM_CMNINFO_INTERFACE: 243 pDM_Odm->SupportInterface = (u8)Value; 244 break; 245 case ODM_CMNINFO_MP_TEST_CHIP: 246 pDM_Odm->bIsMPChip = (u8)Value; 247 break; 248 case ODM_CMNINFO_IC_TYPE: 249 pDM_Odm->SupportICType = Value; 250 break; 251 case ODM_CMNINFO_CUT_VER: 252 pDM_Odm->CutVersion = (u8)Value; 253 break; 254 case ODM_CMNINFO_FAB_VER: 255 pDM_Odm->FabVersion = (u8)Value; 256 break; 257 case ODM_CMNINFO_RF_TYPE: 258 pDM_Odm->RFType = (u8)Value; 259 break; 260 case ODM_CMNINFO_RF_ANTENNA_TYPE: 261 pDM_Odm->AntDivType = (u8)Value; 262 break; 263 case ODM_CMNINFO_BOARD_TYPE: 264 pDM_Odm->BoardType = (u8)Value; 265 break; 266 case ODM_CMNINFO_EXT_LNA: 267 pDM_Odm->ExtLNA = (u8)Value; 268 break; 269 case ODM_CMNINFO_EXT_PA: 270 pDM_Odm->ExtPA = (u8)Value; 271 break; 272 case ODM_CMNINFO_EXT_TRSW: 273 pDM_Odm->ExtTRSW = (u8)Value; 274 break; 275 case ODM_CMNINFO_PATCH_ID: 276 pDM_Odm->PatchID = (u8)Value; 277 break; 278 case ODM_CMNINFO_BINHCT_TEST: 279 pDM_Odm->bInHctTest = (bool)Value; 280 break; 281 case ODM_CMNINFO_BWIFI_TEST: 282 pDM_Odm->bWIFITest = (bool)Value; 283 break; 284 case ODM_CMNINFO_SMART_CONCURRENT: 285 pDM_Odm->bDualMacSmartConcurrent = (bool)Value; 286 break; 287 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 288 default: 289 /* do nothing */ 290 break; 291 } 292 293 /* Tx power tracking BB swing table. */ 294 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */ 295 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */ 296 pDM_Odm->BbSwingIdxOfdmCurrent = 12; 297 pDM_Odm->BbSwingFlagOfdm = false; 298} 299 300void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, void *pValue) 301{ 302 /* */ 303 /* Hook call by reference pointer. */ 304 /* */ 305 switch (CmnInfo) { 306 /* Dynamic call by reference pointer. */ 307 case ODM_CMNINFO_MAC_PHY_MODE: 308 pDM_Odm->pMacPhyMode = (u8 *)pValue; 309 break; 310 case ODM_CMNINFO_TX_UNI: 311 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue; 312 break; 313 case ODM_CMNINFO_RX_UNI: 314 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue; 315 break; 316 case ODM_CMNINFO_WM_MODE: 317 pDM_Odm->pWirelessMode = (u8 *)pValue; 318 break; 319 case ODM_CMNINFO_BAND: 320 pDM_Odm->pBandType = (u8 *)pValue; 321 break; 322 case ODM_CMNINFO_SEC_CHNL_OFFSET: 323 pDM_Odm->pSecChOffset = (u8 *)pValue; 324 break; 325 case ODM_CMNINFO_SEC_MODE: 326 pDM_Odm->pSecurity = (u8 *)pValue; 327 break; 328 case ODM_CMNINFO_BW: 329 pDM_Odm->pBandWidth = (u8 *)pValue; 330 break; 331 case ODM_CMNINFO_CHNL: 332 pDM_Odm->pChannel = (u8 *)pValue; 333 break; 334 case ODM_CMNINFO_DMSP_GET_VALUE: 335 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue; 336 break; 337 case ODM_CMNINFO_BUDDY_ADAPTOR: 338 pDM_Odm->pBuddyAdapter = (struct adapter **)pValue; 339 break; 340 case ODM_CMNINFO_DMSP_IS_MASTER: 341 pDM_Odm->pbMasterOfDMSP = (bool *)pValue; 342 break; 343 case ODM_CMNINFO_SCAN: 344 pDM_Odm->pbScanInProcess = (bool *)pValue; 345 break; 346 case ODM_CMNINFO_POWER_SAVING: 347 pDM_Odm->pbPowerSaving = (bool *)pValue; 348 break; 349 case ODM_CMNINFO_ONE_PATH_CCA: 350 pDM_Odm->pOnePathCCA = (u8 *)pValue; 351 break; 352 case ODM_CMNINFO_DRV_STOP: 353 pDM_Odm->pbDriverStopped = (bool *)pValue; 354 break; 355 case ODM_CMNINFO_PNP_IN: 356 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue; 357 break; 358 case ODM_CMNINFO_INIT_ON: 359 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue; 360 break; 361 case ODM_CMNINFO_ANT_TEST: 362 pDM_Odm->pAntennaTest = (u8 *)pValue; 363 break; 364 case ODM_CMNINFO_NET_CLOSED: 365 pDM_Odm->pbNet_closed = (bool *)pValue; 366 break; 367 case ODM_CMNINFO_MP_MODE: 368 pDM_Odm->mp_mode = (u8 *)pValue; 369 break; 370 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 371 default: 372 /* do nothing */ 373 break; 374 } 375} 376 377void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm, enum odm_common_info_def CmnInfo, u16 Index, void *pValue) 378{ 379 /* Hook call by reference pointer. */ 380 switch (CmnInfo) { 381 /* Dynamic call by reference pointer. */ 382 case ODM_CMNINFO_STA_STATUS: 383 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue; 384 break; 385 /* To remove the compiler warning, must add an empty default statement to handle the other values. */ 386 default: 387 /* do nothing */ 388 break; 389 } 390} 391 392/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */ 393void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value) 394{ 395 /* */ 396 /* This init variable may be changed in run time. */ 397 /* */ 398 switch (CmnInfo) { 399 case ODM_CMNINFO_ABILITY: 400 pDM_Odm->SupportAbility = (u32)Value; 401 break; 402 case ODM_CMNINFO_RF_TYPE: 403 pDM_Odm->RFType = (u8)Value; 404 break; 405 case ODM_CMNINFO_WIFI_DIRECT: 406 pDM_Odm->bWIFI_Direct = (bool)Value; 407 break; 408 case ODM_CMNINFO_WIFI_DISPLAY: 409 pDM_Odm->bWIFI_Display = (bool)Value; 410 break; 411 case ODM_CMNINFO_LINK: 412 pDM_Odm->bLinked = (bool)Value; 413 break; 414 case ODM_CMNINFO_RSSI_MIN: 415 pDM_Odm->RSSI_Min = (u8)Value; 416 break; 417 case ODM_CMNINFO_DBG_COMP: 418 pDM_Odm->DebugComponents = Value; 419 break; 420 case ODM_CMNINFO_DBG_LEVEL: 421 pDM_Odm->DebugLevel = (u32)Value; 422 break; 423 case ODM_CMNINFO_RA_THRESHOLD_HIGH: 424 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value; 425 break; 426 case ODM_CMNINFO_RA_THRESHOLD_LOW: 427 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value; 428 break; 429 } 430} 431 432void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm) 433{ 434 struct adapter *adapter = pDM_Odm->Adapter; 435 436 pDM_Odm->bCckHighPower = (bool) PHY_QueryBBReg(adapter, 0x824, BIT9); 437 pDM_Odm->RFPathRxEnable = (u8) PHY_QueryBBReg(adapter, 0xc04, 0x0F); 438 439 ODM_InitDebugSetting(pDM_Odm); 440} 441 442void odm_CommonInfoSelfUpdate(struct odm_dm_struct *pDM_Odm) 443{ 444 u8 EntryCnt = 0; 445 u8 i; 446 struct sta_info *pEntry; 447 448 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { 449 if (*(pDM_Odm->pSecChOffset) == 1) 450 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; 451 else if (*(pDM_Odm->pSecChOffset) == 2) 452 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; 453 } else { 454 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); 455 } 456 457 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 458 pEntry = pDM_Odm->pODM_StaInfo[i]; 459 if (IS_STA_VALID(pEntry)) 460 EntryCnt++; 461 } 462 if (EntryCnt == 1) 463 pDM_Odm->bOneEntryOnly = true; 464 else 465 pDM_Odm->bOneEntryOnly = false; 466} 467 468void odm_CmnInfoInit_Debug(struct odm_dm_struct *pDM_Odm) 469{ 470 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n")); 471 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n", pDM_Odm->SupportPlatform)); 472 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n", pDM_Odm->SupportAbility)); 473 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n", pDM_Odm->SupportInterface)); 474 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n", pDM_Odm->SupportICType)); 475 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n", pDM_Odm->CutVersion)); 476 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n", pDM_Odm->FabVersion)); 477 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n", pDM_Odm->RFType)); 478 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n", pDM_Odm->BoardType)); 479 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n", pDM_Odm->ExtLNA)); 480 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n", pDM_Odm->ExtPA)); 481 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n", pDM_Odm->ExtTRSW)); 482 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n", pDM_Odm->PatchID)); 483 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n", pDM_Odm->bInHctTest)); 484 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n", pDM_Odm->bWIFITest)); 485 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n", pDM_Odm->bDualMacSmartConcurrent)); 486} 487 488void odm_CmnInfoHook_Debug(struct odm_dm_struct *pDM_Odm) 489{ 490 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n")); 491 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n", *(pDM_Odm->pNumTxBytesUnicast))); 492 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n", *(pDM_Odm->pNumRxBytesUnicast))); 493 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n", *(pDM_Odm->pWirelessMode))); 494 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n", *(pDM_Odm->pSecChOffset))); 495 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n", *(pDM_Odm->pSecurity))); 496 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n", *(pDM_Odm->pBandWidth))); 497 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n", *(pDM_Odm->pChannel))); 498 499 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n", *(pDM_Odm->pbScanInProcess))); 500 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n", *(pDM_Odm->pbPowerSaving))); 501} 502 503void odm_CmnInfoUpdate_Debug(struct odm_dm_struct *pDM_Odm) 504{ 505 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n")); 506 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n", pDM_Odm->bWIFI_Direct)); 507 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n", pDM_Odm->bWIFI_Display)); 508 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n", pDM_Odm->bLinked)); 509 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n", pDM_Odm->RSSI_Min)); 510} 511 512void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI) 513{ 514 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 515 struct adapter *adapter = pDM_Odm->Adapter; 516 517 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 518 ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", 519 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm))); 520 521 if (pDM_DigTable->CurIGValue != CurrentIGI) { 522 PHY_SetBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI); 523 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x).\n", CurrentIGI)); 524 /* pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue; */ 525 pDM_DigTable->CurIGValue = CurrentIGI; 526 } 527 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x\n", CurrentIGI)); 528 529/* Add by Neil Chen to enable edcca to MP Platform */ 530} 531 532void odm_DIGInit(struct odm_dm_struct *pDM_Odm) 533{ 534 struct adapter *adapter = pDM_Odm->Adapter; 535 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 536 537 pDM_DigTable->CurIGValue = (u8) PHY_QueryBBReg(adapter, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)); 538 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; 539 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; 540 pDM_DigTable->FALowThresh = DM_false_ALARM_THRESH_LOW; 541 pDM_DigTable->FAHighThresh = DM_false_ALARM_THRESH_HIGH; 542 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) { 543 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 544 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 545 } else { 546 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; 547 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; 548 } 549 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; 550 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; 551 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; 552 pDM_DigTable->PreCCK_CCAThres = 0xFF; 553 pDM_DigTable->CurCCK_CCAThres = 0x83; 554 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; 555 pDM_DigTable->LargeFAHit = 0; 556 pDM_DigTable->Recover_cnt = 0; 557 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; 558 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; 559 pDM_DigTable->bMediaConnect_0 = false; 560 pDM_DigTable->bMediaConnect_1 = false; 561 562 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */ 563 pDM_Odm->bDMInitialGainEnable = true; 564} 565 566void odm_DIG(struct odm_dm_struct *pDM_Odm) 567{ 568 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 569 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt; 570 u8 DIG_Dynamic_MIN; 571 u8 DIG_MaxOfMin; 572 bool FirstConnect, FirstDisConnect; 573 u8 dm_dig_max, dm_dig_min; 574 u8 CurrentIGI = pDM_DigTable->CurIGValue; 575 576 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n")); 577 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) { 578 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 579 ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n")); 580 return; 581 } 582 583 if (*(pDM_Odm->pbScanInProcess)) { 584 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress\n")); 585 return; 586 } 587 588 /* add by Neil Chen to avoid PSD is processing */ 589 if (pDM_Odm->bDMInitialGainEnable == false) { 590 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing\n")); 591 return; 592 } 593 594 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; 595 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0); 596 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0); 597 598 /* 1 Boundary Decision */ 599 dm_dig_max = DM_DIG_MAX_NIC; 600 dm_dig_min = DM_DIG_MIN_NIC; 601 DIG_MaxOfMin = DM_DIG_MAX_AP; 602 603 if (pDM_Odm->bLinked) { 604 /* 2 Modify DIG upper bound */ 605 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max) 606 pDM_DigTable->rx_gain_range_max = dm_dig_max; 607 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min) 608 pDM_DigTable->rx_gain_range_max = dm_dig_min; 609 else 610 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20; 611 /* 2 Modify DIG lower bound */ 612 if (pDM_Odm->bOneEntryOnly) { 613 if (pDM_Odm->RSSI_Min < dm_dig_min) 614 DIG_Dynamic_MIN = dm_dig_min; 615 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) 616 DIG_Dynamic_MIN = DIG_MaxOfMin; 617 else 618 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; 619 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 620 ("odm_DIG() : bOneEntryOnly=true, DIG_Dynamic_MIN=0x%x\n", 621 DIG_Dynamic_MIN)); 622 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 623 ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n", 624 pDM_Odm->RSSI_Min)); 625 } else if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) { 626 /* 1 Lower Bound for 88E AntDiv */ 627 if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { 628 DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max; 629 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, 630 ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d\n", 631 pDM_DigTable->AntDiv_RSSI_max)); 632 } 633 } else { 634 DIG_Dynamic_MIN = dm_dig_min; 635 } 636 } else { 637 pDM_DigTable->rx_gain_range_max = dm_dig_max; 638 DIG_Dynamic_MIN = dm_dig_min; 639 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n")); 640 } 641 642 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */ 643 if (pFalseAlmCnt->Cnt_all > 10000) { 644 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case.\n")); 645 646 if (pDM_DigTable->LargeFAHit != 3) 647 pDM_DigTable->LargeFAHit++; 648 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) { 649 pDM_DigTable->ForbiddenIGI = CurrentIGI; 650 pDM_DigTable->LargeFAHit = 1; 651 } 652 653 if (pDM_DigTable->LargeFAHit >= 3) { 654 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max) 655 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; 656 else 657 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 658 pDM_DigTable->Recover_cnt = 3600; /* 3600=2hr */ 659 } 660 661 } else { 662 /* Recovery mechanism for IGI lower bound */ 663 if (pDM_DigTable->Recover_cnt != 0) { 664 pDM_DigTable->Recover_cnt--; 665 } else { 666 if (pDM_DigTable->LargeFAHit < 3) { 667 if ((pDM_DigTable->ForbiddenIGI-1) < DIG_Dynamic_MIN) { /* DM_DIG_MIN) */ 668 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 669 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */ 670 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); 671 } else { 672 pDM_DigTable->ForbiddenIGI--; 673 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1); 674 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); 675 } 676 } else { 677 pDM_DigTable->LargeFAHit = 0; 678 } 679 } 680 } 681 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 682 ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n", 683 pDM_DigTable->LargeFAHit)); 684 685 /* 1 Adjust initial gain by false alarm */ 686 if (pDM_Odm->bLinked) { 687 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n")); 688 if (FirstConnect) { 689 CurrentIGI = pDM_Odm->RSSI_Min; 690 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n")); 691 } else { 692 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2) 693 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 694 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1) 695 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 696 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) 697 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 698 } 699 } else { 700 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n")); 701 if (FirstDisConnect) { 702 CurrentIGI = pDM_DigTable->rx_gain_range_min; 703 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect\n")); 704 } else { 705 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */ 706 if (pFalseAlmCnt->Cnt_all > 10000) 707 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */ 708 else if (pFalseAlmCnt->Cnt_all > 8000) 709 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */ 710 else if (pFalseAlmCnt->Cnt_all < 500) 711 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1; */ 712 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG\n")); 713 } 714 } 715 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n")); 716 /* 1 Check initial gain by upper/lower bound */ 717 if (CurrentIGI > pDM_DigTable->rx_gain_range_max) 718 CurrentIGI = pDM_DigTable->rx_gain_range_max; 719 if (CurrentIGI < pDM_DigTable->rx_gain_range_min) 720 CurrentIGI = pDM_DigTable->rx_gain_range_min; 721 722 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, 723 ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n", 724 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min)); 725 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all)); 726 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI)); 727 728 /* 2 High power RSSI threshold */ 729 730 ODM_Write_DIG(pDM_Odm, CurrentIGI);/* ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); */ 731 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; 732 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; 733} 734 735/* 3============================================================ */ 736/* 3 FASLE ALARM CHECK */ 737/* 3============================================================ */ 738 739void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm) 740{ 741 struct adapter *adapter = pDM_Odm->Adapter; 742 u32 ret_value; 743 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 744 745 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) 746 return; 747 748 /* hold ofdm counter */ 749 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */ 750 PHY_SetBBReg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */ 751 752 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); 753 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); 754 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); 755 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); 756 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); 757 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); 758 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); 759 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); 760 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); 761 ret_value = PHY_QueryBBReg(adapter, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); 762 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); 763 764 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + 765 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + 766 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; 767 768 ret_value = PHY_QueryBBReg(adapter, ODM_REG_SC_CNT_11N, bMaskDWord); 769 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); 770 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); 771 772 /* hold cck counter */ 773 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1); 774 PHY_SetBBReg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1); 775 776 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); 777 FalseAlmCnt->Cnt_Cck_fail = ret_value; 778 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); 779 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff)<<8; 780 781 ret_value = PHY_QueryBBReg(adapter, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); 782 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8); 783 784 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync + 785 FalseAlmCnt->Cnt_SB_Search_fail + 786 FalseAlmCnt->Cnt_Parity_Fail + 787 FalseAlmCnt->Cnt_Rate_Illegal + 788 FalseAlmCnt->Cnt_Crc8_fail + 789 FalseAlmCnt->Cnt_Mcs_fail + 790 FalseAlmCnt->Cnt_Cck_fail); 791 792 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; 793 794 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n")); 795 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 796 ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", 797 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); 798 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 799 ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", 800 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); 801 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, 802 ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", 803 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); 804 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); 805 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); 806 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n", FalseAlmCnt->Cnt_all)); 807} 808 809/* 3============================================================ */ 810/* 3 CCK Packet Detect Threshold */ 811/* 3============================================================ */ 812 813void odm_CCKPacketDetectionThresh(struct odm_dm_struct *pDM_Odm) 814{ 815 u8 CurCCK_CCAThres; 816 struct false_alarm_stats *FalseAlmCnt = &(pDM_Odm->FalseAlmCnt); 817 818 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT))) 819 return; 820 if (pDM_Odm->ExtLNA) 821 return; 822 if (pDM_Odm->bLinked) { 823 if (pDM_Odm->RSSI_Min > 25) { 824 CurCCK_CCAThres = 0xcd; 825 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) { 826 CurCCK_CCAThres = 0x83; 827 } else { 828 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 829 CurCCK_CCAThres = 0x83; 830 else 831 CurCCK_CCAThres = 0x40; 832 } 833 } else { 834 if (FalseAlmCnt->Cnt_Cck_fail > 1000) 835 CurCCK_CCAThres = 0x83; 836 else 837 CurCCK_CCAThres = 0x40; 838 } 839 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); 840} 841 842void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres) 843{ 844 struct rtw_dig *pDM_DigTable = &pDM_Odm->DM_DigTable; 845 struct adapter *adapt = pDM_Odm->Adapter; 846 847 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres) /* modify by Guo.Mingzhi 2012-01-03 */ 848 rtw_write8(adapt, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres); 849 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; 850 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; 851} 852 853/* 3============================================================ */ 854/* 3 BB Power Save */ 855/* 3============================================================ */ 856void odm_DynamicBBPowerSavingInit(struct odm_dm_struct *pDM_Odm) 857{ 858 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 859 860 pDM_PSTable->PreCCAState = CCA_MAX; 861 pDM_PSTable->CurCCAState = CCA_MAX; 862 pDM_PSTable->PreRFState = RF_MAX; 863 pDM_PSTable->CurRFState = RF_MAX; 864 pDM_PSTable->Rssi_val_min = 0; 865 pDM_PSTable->initialize = 0; 866} 867 868void odm_DynamicBBPowerSaving(struct odm_dm_struct *pDM_Odm) 869{ 870} 871 872void odm_1R_CCA(struct odm_dm_struct *pDM_Odm) 873{ 874 struct adapter *adapter = pDM_Odm->Adapter; 875 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 876 877 if (pDM_Odm->RSSI_Min != 0xFF) { 878 if (pDM_PSTable->PreCCAState == CCA_2R) { 879 if (pDM_Odm->RSSI_Min >= 35) 880 pDM_PSTable->CurCCAState = CCA_1R; 881 else 882 pDM_PSTable->CurCCAState = CCA_2R; 883 } else { 884 if (pDM_Odm->RSSI_Min <= 30) 885 pDM_PSTable->CurCCAState = CCA_2R; 886 else 887 pDM_PSTable->CurCCAState = CCA_1R; 888 } 889 } else { 890 pDM_PSTable->CurCCAState = CCA_MAX; 891 } 892 893 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) { 894 if (pDM_PSTable->CurCCAState == CCA_1R) { 895 if (pDM_Odm->RFType == ODM_2T2R) 896 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x13); 897 else 898 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x23); 899 } else { 900 PHY_SetBBReg(adapter, 0xc04, bMaskByte0, 0x33); 901 } 902 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; 903 } 904} 905 906void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal) 907{ 908 struct adapter *adapter = pDM_Odm->Adapter; 909 struct rtl_ps *pDM_PSTable = &pDM_Odm->DM_PSTable; 910 u8 Rssi_Up_bound = 30; 911 u8 Rssi_Low_bound = 25; 912 913 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */ 914 Rssi_Up_bound = 50; 915 Rssi_Low_bound = 45; 916 } 917 if (pDM_PSTable->initialize == 0) { 918 pDM_PSTable->Reg874 = (PHY_QueryBBReg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14; 919 pDM_PSTable->RegC70 = (PHY_QueryBBReg(adapter, 0xc70, bMaskDWord)&BIT3)>>3; 920 pDM_PSTable->Reg85C = (PHY_QueryBBReg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; 921 pDM_PSTable->RegA74 = (PHY_QueryBBReg(adapter, 0xa74, bMaskDWord)&0xF000)>>12; 922 pDM_PSTable->initialize = 1; 923 } 924 925 if (!bForceInNormal) { 926 if (pDM_Odm->RSSI_Min != 0xFF) { 927 if (pDM_PSTable->PreRFState == RF_Normal) { 928 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound) 929 pDM_PSTable->CurRFState = RF_Save; 930 else 931 pDM_PSTable->CurRFState = RF_Normal; 932 } else { 933 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound) 934 pDM_PSTable->CurRFState = RF_Normal; 935 else 936 pDM_PSTable->CurRFState = RF_Save; 937 } 938 } else { 939 pDM_PSTable->CurRFState = RF_MAX; 940 } 941 } else { 942 pDM_PSTable->CurRFState = RF_Normal; 943 } 944 945 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) { 946 if (pDM_PSTable->CurRFState == RF_Save) { 947 PHY_SetBBReg(adapter, 0x874 , 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ 948 PHY_SetBBReg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */ 949 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */ 950 PHY_SetBBReg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */ 951 PHY_SetBBReg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */ 952 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */ 953 PHY_SetBBReg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */ 954 } else { 955 PHY_SetBBReg(adapter, 0x874 , 0x1CC000, pDM_PSTable->Reg874); 956 PHY_SetBBReg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70); 957 PHY_SetBBReg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); 958 PHY_SetBBReg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74); 959 PHY_SetBBReg(adapter, 0x818, BIT28, 0x0); 960 } 961 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState; 962 } 963} 964 965/* 3============================================================ */ 966/* 3 RATR MASK */ 967/* 3============================================================ */ 968/* 3============================================================ */ 969/* 3 Rate Adaptive */ 970/* 3============================================================ */ 971 972void odm_RateAdaptiveMaskInit(struct odm_dm_struct *pDM_Odm) 973{ 974 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive; 975 976 pOdmRA->Type = DM_Type_ByDriver; 977 if (pOdmRA->Type == DM_Type_ByDriver) 978 pDM_Odm->bUseRAMask = true; 979 else 980 pDM_Odm->bUseRAMask = false; 981 982 pOdmRA->RATRState = DM_RATR_STA_INIT; 983 pOdmRA->HighRSSIThresh = 50; 984 pOdmRA->LowRSSIThresh = 20; 985} 986 987u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level) 988{ 989 struct sta_info *pEntry; 990 u32 rate_bitmap = 0x0fffffff; 991 u8 WirelessMode; 992 993 pEntry = pDM_Odm->pODM_StaInfo[macid]; 994 if (!IS_STA_VALID(pEntry)) 995 return ra_mask; 996 997 WirelessMode = pEntry->wireless_mode; 998 999 switch (WirelessMode) { 1000 case ODM_WM_B: 1001 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ 1002 rate_bitmap = 0x0000000d; 1003 else 1004 rate_bitmap = 0x0000000f; 1005 break; 1006 case (ODM_WM_A|ODM_WM_G): 1007 if (rssi_level == DM_RATR_STA_HIGH) 1008 rate_bitmap = 0x00000f00; 1009 else 1010 rate_bitmap = 0x00000ff0; 1011 break; 1012 case (ODM_WM_B|ODM_WM_G): 1013 if (rssi_level == DM_RATR_STA_HIGH) 1014 rate_bitmap = 0x00000f00; 1015 else if (rssi_level == DM_RATR_STA_MIDDLE) 1016 rate_bitmap = 0x00000ff0; 1017 else 1018 rate_bitmap = 0x00000ff5; 1019 break; 1020 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1021 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G): 1022 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { 1023 if (rssi_level == DM_RATR_STA_HIGH) { 1024 rate_bitmap = 0x000f0000; 1025 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1026 rate_bitmap = 0x000ff000; 1027 } else { 1028 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1029 rate_bitmap = 0x000ff015; 1030 else 1031 rate_bitmap = 0x000ff005; 1032 } 1033 } else { 1034 if (rssi_level == DM_RATR_STA_HIGH) { 1035 rate_bitmap = 0x0f8f0000; 1036 } else if (rssi_level == DM_RATR_STA_MIDDLE) { 1037 rate_bitmap = 0x0f8ff000; 1038 } else { 1039 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) 1040 rate_bitmap = 0x0f8ff015; 1041 else 1042 rate_bitmap = 0x0f8ff005; 1043 } 1044 } 1045 break; 1046 default: 1047 /* case WIRELESS_11_24N: */ 1048 /* case WIRELESS_11_5N: */ 1049 if (pDM_Odm->RFType == RF_1T2R) 1050 rate_bitmap = 0x000fffff; 1051 else 1052 rate_bitmap = 0x0fffffff; 1053 break; 1054 } 1055 1056 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1057 (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", 1058 rssi_level, WirelessMode, rate_bitmap)); 1059 1060 return rate_bitmap; 1061} 1062 1063/*----------------------------------------------------------------------------- 1064 * Function: odm_RefreshRateAdaptiveMask() 1065 * 1066 * Overview: Update rate table mask according to rssi 1067 * 1068 * Input: NONE 1069 * 1070 * Output: NONE 1071 * 1072 * Return: NONE 1073 * 1074 * Revised History: 1075 * When Who Remark 1076 * 05/27/2009 hpfan Create Version 0. 1077 * 1078 *---------------------------------------------------------------------------*/ 1079void odm_RefreshRateAdaptiveMask(struct odm_dm_struct *pDM_Odm) 1080{ 1081 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) 1082 return; 1083 /* */ 1084 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1085 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1086 /* HW dynamic mechanism. */ 1087 /* */ 1088 odm_RefreshRateAdaptiveMaskCE(pDM_Odm); 1089} 1090 1091void odm_RefreshRateAdaptiveMaskMP(struct odm_dm_struct *pDM_Odm) 1092{ 1093} 1094 1095void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm) 1096{ 1097 u8 i; 1098 struct adapter *pAdapter = pDM_Odm->Adapter; 1099 1100 if (pAdapter->bDriverStopped) { 1101 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); 1102 return; 1103 } 1104 1105 if (!pDM_Odm->bUseRAMask) { 1106 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); 1107 return; 1108 } 1109 1110 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1111 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; 1112 if (IS_STA_VALID(pstat)) { 1113 if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false , &pstat->rssi_level)) { 1114 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, 1115 ("RSSI:%d, RSSI_LEVEL:%d\n", 1116 pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); 1117 rtw_hal_update_ra_mask(pAdapter, i, pstat->rssi_level); 1118 } 1119 } 1120 } 1121} 1122 1123void odm_RefreshRateAdaptiveMaskAPADSL(struct odm_dm_struct *pDM_Odm) 1124{ 1125} 1126 1127/* Return Value: bool */ 1128/* - true: RATRState is changed. */ 1129bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI, bool bForceUpdate, u8 *pRATRState) 1130{ 1131 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive; 1132 const u8 GoUpGap = 5; 1133 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh; 1134 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh; 1135 u8 RATRState; 1136 1137 /* Threshold Adjustment: */ 1138 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */ 1139 /* Here GoUpGap is added to solve the boundary's level alternation issue. */ 1140 switch (*pRATRState) { 1141 case DM_RATR_STA_INIT: 1142 case DM_RATR_STA_HIGH: 1143 break; 1144 case DM_RATR_STA_MIDDLE: 1145 HighRSSIThreshForRA += GoUpGap; 1146 break; 1147 case DM_RATR_STA_LOW: 1148 HighRSSIThreshForRA += GoUpGap; 1149 LowRSSIThreshForRA += GoUpGap; 1150 break; 1151 default: 1152 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState)); 1153 break; 1154 } 1155 1156 /* Decide RATRState by RSSI. */ 1157 if (RSSI > HighRSSIThreshForRA) 1158 RATRState = DM_RATR_STA_HIGH; 1159 else if (RSSI > LowRSSIThreshForRA) 1160 RATRState = DM_RATR_STA_MIDDLE; 1161 else 1162 RATRState = DM_RATR_STA_LOW; 1163 1164 if (*pRATRState != RATRState || bForceUpdate) { 1165 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState)); 1166 *pRATRState = RATRState; 1167 return true; 1168 } 1169 return false; 1170} 1171 1172/* 3============================================================ */ 1173/* 3 Dynamic Tx Power */ 1174/* 3============================================================ */ 1175 1176void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm) 1177{ 1178 struct adapter *Adapter = pDM_Odm->Adapter; 1179 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1180 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1181 pdmpriv->bDynamicTxPowerEnable = false; 1182 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; 1183 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; 1184} 1185 1186void odm_DynamicTxPower(struct odm_dm_struct *pDM_Odm) 1187{ 1188 /* For AP/ADSL use struct rtl8192cd_priv * */ 1189 /* For CE/NIC use struct adapter * */ 1190 1191 if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) 1192 return; 1193 1194 /* 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. */ 1195 if (!pDM_Odm->ExtPA) 1196 return; 1197 1198 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1199 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1200 /* HW dynamic mechanism. */ 1201 odm_DynamicTxPowerNIC(pDM_Odm); 1202} 1203 1204void odm_DynamicTxPowerNIC(struct odm_dm_struct *pDM_Odm) 1205{ 1206} 1207 1208/* 3============================================================ */ 1209/* 3 RSSI Monitor */ 1210/* 3============================================================ */ 1211 1212void odm_RSSIMonitorCheck(struct odm_dm_struct *pDM_Odm) 1213{ 1214 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) 1215 return; 1216 1217 /* */ 1218 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1219 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1220 /* HW dynamic mechanism. */ 1221 /* */ 1222 odm_RSSIMonitorCheckCE(pDM_Odm); 1223} /* odm_RSSIMonitorCheck */ 1224 1225static void FindMinimumRSSI(struct adapter *pAdapter) 1226{ 1227 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter); 1228 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1229 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; 1230 1231 /* 1 1.Determine the minimum RSSI */ 1232 if ((check_fwstate(pmlmepriv, _FW_LINKED) == false) && 1233 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) 1234 pdmpriv->MinUndecoratedPWDBForDM = 0; 1235 if (check_fwstate(pmlmepriv, _FW_LINKED) == true) /* Default port */ 1236 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1237 else /* associated entry pwdb */ 1238 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB; 1239} 1240 1241void odm_RSSIMonitorCheckCE(struct odm_dm_struct *pDM_Odm) 1242{ 1243 struct adapter *Adapter = pDM_Odm->Adapter; 1244 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1245 struct dm_priv *pdmpriv = &pHalData->dmpriv; 1246 int i; 1247 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; 1248 u8 sta_cnt = 0; 1249 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */ 1250 struct sta_info *psta; 1251 u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 1252 1253 if (!check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) 1254 return; 1255 1256 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { 1257 psta = pDM_Odm->pODM_StaInfo[i]; 1258 if (IS_STA_VALID(psta) && 1259 (psta->state & WIFI_ASOC_STATE) && 1260 memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) && 1261 memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) { 1262 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) 1263 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1264 1265 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) 1266 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; 1267 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) 1268 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16)); 1269 } 1270 } 1271 1272 for (i = 0; i < sta_cnt; i++) { 1273 if (PWDB_rssi[i] != (0)) { 1274 if (pHalData->fw_ractrl) { 1275 /* Report every sta's RSSI to FW */ 1276 } else { 1277 ODM_RA_SetRSSI_8188E( 1278 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF)); 1279 } 1280 } 1281 } 1282 1283 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */ 1284 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; 1285 else 1286 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; 1287 1288 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */ 1289 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; 1290 else 1291 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; 1292 1293 FindMinimumRSSI(Adapter); 1294 ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); 1295} 1296 1297/* 3============================================================ */ 1298/* 3 Tx Power Tracking */ 1299/* 3============================================================ */ 1300 1301void odm_TXPowerTrackingInit(struct odm_dm_struct *pDM_Odm) 1302{ 1303 odm_TXPowerTrackingThermalMeterInit(pDM_Odm); 1304} 1305 1306void odm_TXPowerTrackingThermalMeterInit(struct odm_dm_struct *pDM_Odm) 1307{ 1308 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true; 1309 pDM_Odm->RFCalibrateInfo.TXPowercount = 0; 1310 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false; 1311 if (*(pDM_Odm->mp_mode) != 1) 1312 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1313 MSG_88E("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); 1314 1315 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true; 1316} 1317 1318void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm) 1319{ 1320 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1321 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1322 /* HW dynamic mechanism. */ 1323 odm_TXPowerTrackingCheckCE(pDM_Odm); 1324} 1325 1326void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm) 1327{ 1328 struct adapter *Adapter = pDM_Odm->Adapter; 1329 1330 if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) 1331 return; 1332 1333 if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */ 1334 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); 1335 1336 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; 1337 return; 1338 } else { 1339 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); 1340 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; 1341 } 1342} 1343 1344/* antenna mapping info */ 1345/* 1: right-side antenna */ 1346/* 2/0: left-side antenna */ 1347/* PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */ 1348/* PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */ 1349/* We select left antenna as default antenna in initial process, modify it as needed */ 1350/* */ 1351 1352/* 3============================================================ */ 1353/* 3 SW Antenna Diversity */ 1354/* 3============================================================ */ 1355 1356void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext) 1357{ 1358} 1359 1360/* 3============================================================ */ 1361/* 3 SW Antenna Diversity */ 1362/* 3============================================================ */ 1363 1364void odm_InitHybridAntDiv(struct odm_dm_struct *pDM_Odm) 1365{ 1366 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1367 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1368 return; 1369 } 1370 1371 ODM_AntennaDiversityInit_88E(pDM_Odm); 1372} 1373 1374void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm) 1375{ 1376 if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) { 1377 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Return: Not Support HW AntDiv\n")); 1378 return; 1379 } 1380 1381 ODM_AntennaDiversity_88E(pDM_Odm); 1382} 1383 1384/* EDCA Turbo */ 1385void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) 1386{ 1387 struct adapter *Adapter = pDM_Odm->Adapter; 1388 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1389 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; 1390 Adapter->recvpriv.bIsAnyNonBEPkts = false; 1391 1392 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_VO_PARAM))); 1393 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_VI_PARAM))); 1394 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_BE_PARAM))); 1395 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", rtw_read32(Adapter, ODM_EDCA_BK_PARAM))); 1396} /* ODM_InitEdcaTurbo */ 1397 1398void odm_EdcaTurboCheck(struct odm_dm_struct *pDM_Odm) 1399{ 1400 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ 1401 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ 1402 /* HW dynamic mechanism. */ 1403 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck========================>\n")); 1404 1405 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)) 1406 return; 1407 1408 odm_EdcaTurboCheckCE(pDM_Odm); 1409 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<========================odm_EdcaTurboCheck\n")); 1410} /* odm_CheckEdcaTurbo */ 1411 1412void odm_EdcaTurboCheckCE(struct odm_dm_struct *pDM_Odm) 1413{ 1414 struct adapter *Adapter = pDM_Odm->Adapter; 1415 u32 trafficIndex; 1416 u32 edca_param; 1417 u64 cur_tx_bytes = 0; 1418 u64 cur_rx_bytes = 0; 1419 u8 bbtchange = false; 1420 struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); 1421 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); 1422 struct recv_priv *precvpriv = &(Adapter->recvpriv); 1423 struct registry_priv *pregpriv = &Adapter->registrypriv; 1424 struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); 1425 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 1426 1427 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */ 1428 goto dm_CheckEdcaTurbo_EXIT; 1429 1430 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX) 1431 goto dm_CheckEdcaTurbo_EXIT; 1432 1433 /* Check if the status needs to be changed. */ 1434 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) { 1435 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; 1436 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; 1437 1438 /* traffic, TX or RX */ 1439 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) || 1440 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) { 1441 if (cur_tx_bytes > (cur_rx_bytes << 2)) { 1442 /* Uplink TP is present. */ 1443 trafficIndex = UP_LINK; 1444 } else { 1445 /* Balance TP is present. */ 1446 trafficIndex = DOWN_LINK; 1447 } 1448 } else { 1449 if (cur_rx_bytes > (cur_tx_bytes << 2)) { 1450 /* Downlink TP is present. */ 1451 trafficIndex = DOWN_LINK; 1452 } else { 1453 /* Balance TP is present. */ 1454 trafficIndex = UP_LINK; 1455 } 1456 } 1457 1458 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) { 1459 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) 1460 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; 1461 else 1462 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex]; 1463 1464 rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); 1465 1466 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; 1467 } 1468 1469 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true; 1470 } else { 1471 /* Turn Off EDCA turbo here. */ 1472 /* Restore original EDCA according to the declaration of AP. */ 1473 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) { 1474 rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); 1475 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; 1476 } 1477 } 1478 1479dm_CheckEdcaTurbo_EXIT: 1480 /* Set variables for next time. */ 1481 precvpriv->bIsAnyNonBEPkts = false; 1482 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; 1483 precvpriv->last_rx_bytes = precvpriv->rx_bytes; 1484} 1485 1486u32 ConvertTo_dB(u32 Value) 1487{ 1488 u8 i; 1489 u8 j; 1490 u32 dB; 1491 1492 Value = Value & 0xFFFF; 1493 for (i = 0; i < 8; i++) { 1494 if (Value <= dB_Invert_Table[i][11]) 1495 break; 1496 } 1497 1498 if (i >= 8) 1499 return 96; /* maximum 96 dB */ 1500 1501 for (j = 0; j < 12; j++) { 1502 if (Value <= dB_Invert_Table[i][j]) 1503 break; 1504 } 1505 1506 dB = i*12 + j + 1; 1507 1508 return dB; 1509} 1510