18fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang/* 28fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang This is part of rtl8187 OpenSource driver. 3559a4c318ca303880fc9f26d50711791c16ae2f3Andrea Merello Copyright (C) Andrea Merello 2004-2005 <andrea.merello@gmail.com> 48fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang Released under the terms of GPL (General Public Licence) 58fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 68fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang Parts of this driver are based on the GPL part of the 78fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang official Realtek driver. 88fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang Parts of this driver are based on the rtl8180 driver skeleton 98fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang from Patric Schenke & Andres Salomon. 108fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang Parts of this driver are based on the Intel Pro Wireless 118fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 2100 GPL driver. 128fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 13ffae3055d23275b7b0abd4c1b0b750662b62ccf1Justin P. Mattock We want to thank the Authors of those projects 148fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang and the Ndiswrapper project Authors. 158fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang*/ 168fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 178fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang/* Mariusz Matuszek added full registers definition with Realtek's name */ 188fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 198fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang/* this file contains register definitions for the rtl8187 MAC controller */ 208fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#ifndef R8192_HW 218fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define R8192_HW 228fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 238fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuangtypedef enum _VERSION_819xU{ 248fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang VERSION_819xU_A, // A-cut 258fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang VERSION_819xU_B, // B-cut 268fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang VERSION_819xU_C,// C-cut 2741389e29e70d0e6529af60a4d135f67c226c028eGreg Donald} VERSION_819xU, *PVERSION_819xU; 288fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//added for different RF type 298fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuangtypedef enum _RT_RF_TYPE_DEF 308fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang{ 318fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RF_1T2R = 0, 328fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RF_2T4R, 338fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 348fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RF_819X_MAX_TYPE 358fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang}RT_RF_TYPE_DEF; 368fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 378fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 388fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuangtypedef enum _BaseBand_Config_Type{ 398fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BaseBand_Config_PHY_REG = 0, //Radio Path A 408fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BaseBand_Config_AGC_TAB = 1, //Radio Path B 418fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang}BaseBand_Config_Type, *PBaseBand_Config_Type; 428fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RTL8187_REQT_READ 0xc0 438fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RTL8187_REQT_WRITE 0x40 448fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RTL8187_REQ_GET_REGS 0x05 458fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RTL8187_REQ_SET_REGS 0x05 468fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 478fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MAX_TX_URB 5 488fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MAX_RX_URB 16 498fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 508fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define R8180_MAX_RETRY 255 518fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//#define MAX_RX_NORMAL_URB 3 528fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//#define MAX_RX_COMMAND_URB 2 538fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RX_URB_SIZE 9100 548fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 558fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BB_ANTATTEN_CHAN14 0x0c 568fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BB_ANTENNA_B 0x40 578fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 588fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BB_HOST_BANG (1<<30) 598fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BB_HOST_BANG_EN (1<<2) 608fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BB_HOST_BANG_CLK (1<<1) 618fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BB_HOST_BANG_RW (1<<3) 628fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BB_HOST_BANG_DATA 1 638fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 648fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920) 658fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AFR 0x010 668fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AFR_CardBEn (1<<0) 678fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AFR_CLKRUN_SEL (1<<1) 688fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AFR_FuncRegEn (1<<2) 698fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RTL8190_EEPROM_ID 0x8129 708fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_VID 0x02 718fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_PID 0x04 728fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C 738fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 748fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_TxPowerDiff 0x1F 758fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_ThermalMeter 0x20 768fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_PwDiff 0x21 //0x21 778fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CrystalCap 0x22 //0x22 788fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 798fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_TxPwIndex_CCK 0x23 //0x23 808fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_TxPwIndex_OFDM_24G 0x24 //0x24~0x26 818fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B 828fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E 838fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_TxPwIndex_Ver 0x27 //0x27 848fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 858fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_Default_TxPowerDiff 0x0 868fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_Default_ThermalMeter 0x7 878fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_Default_PwDiff 0x4 888fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_Default_CrystalCap 0x5 898fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_Default_TxPower 0x1010 908fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_Customer_ID 0x7B //0x7B:CustomerID 918fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_ChannelPlan 0x16 //0x7C 928fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_IC_VER 0x7d //0x7D 938fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CRC 0x7e //0x7E~0x7F 948fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 958fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CID_DEFAULT 0x0 968fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CID_CAMEO 0x1 978fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CID_RUNTOP 0x2 988fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CID_Senao 0x3 998fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31 1008fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CID_NetCore 0x5 1018fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CID_Nettronix 0x6 1028fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CID_Pronet 0x7 1038fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EEPROM_CID_DLINK 0x8 1048fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 1058fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1068fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AC_PARAM_ECW_MAX_OFFSET 12 1078fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AC_PARAM_ECW_MIN_OFFSET 8 1088fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AC_PARAM_AIFS_OFFSET 0 1098fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 1108fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//#endif 1118fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuangenum _RTL8192Usb_HW { 1128fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 1138fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang PCIF = 0x009, // PCI Function Register 0x0009h~0x000bh 1148fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BB_GLOBAL_RESET_BIT 0x1 1158fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register 1168fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BSSIDR = 0x02E, // BSSID Register 1178fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang CMDR = 0x037, // Command register 1188fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CR_RST 0x10 1198fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CR_RE 0x08 1208fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CR_TE 0x04 1218fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CR_MulRW 0x01 1228fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang SIFS = 0x03E, // SIFS register 1238fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang TCR = 0x040, // Transmit Configuration Register 1248fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 12535997ff0cadda701711416abf6676b77358b0008Sebastian Hahn#define TCR_MXDMA_2048 7 1268fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define TCR_LRL_OFFSET 0 1278fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define TCR_SRL_OFFSET 8 1288fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define TCR_MXDMA_OFFSET 21 1298fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer 1308fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RCR = 0x044, // Receive Configuration Register 1318fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ 1328fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) 1338fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) 1348fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RX_FIFO_THRESHOLD_SHIFT 13 1358fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RX_FIFO_THRESHOLD_128 3 1368fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RX_FIFO_THRESHOLD_256 4 1378fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RX_FIFO_THRESHOLD_512 5 1388fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RX_FIFO_THRESHOLD_1024 6 1398fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RX_FIFO_THRESHOLD_NONE 7 1408fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) 1418fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_MXDMA_OFFSET 8 1428fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_FIFO_OFFSET 13 1438fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size. 1448fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2 1458fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1 1468fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_ENMBID BIT27 // Enable Multiple BssId. 1478fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames 1488fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_CBSSID BIT23 // Accept BSSID match packet 1498fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_APWRMGT BIT22 // Accept power management packet 1508fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_ADD3 BIT21 // Accept address 3 match packet 1518fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_AMF BIT20 // Accept management type frame 1528fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_ACF BIT19 // Accept control type frame 1538fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_ADF BIT18 // Accept data type frame 1548fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_RXFTH BIT13 // Rx FIFO Threshold 1558fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_AICV BIT12 // Accept ICV error packet 1568fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_ACRC32 BIT5 // Accept CRC32 error packet 1578fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_AB BIT3 // Accept broadcast packet 1588fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_AM BIT2 // Accept multicast packet 1598fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_APM BIT1 // Accept physical match packet 1608fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RCR_AAP BIT0 // Accept all unicast packet 1618fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang SLOT_TIME = 0x049, // Slot Time Register 1628fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang ACK_TIMEOUT = 0x04c, // Ack Timeout Register 1638fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang PIFS_TIME = 0x04d, // PIFS time 1648fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang USTIME = 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock. 1658fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE 1668fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK 1678fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO 1688fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI 1698fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RFPC = 0x05F, // Rx FIFO Packet Count 1708fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang CWRR = 0x060, // Contention Window Report Register 1718fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BCN_TCFG = 0x062, // Beacon Time Configuration 1728fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BCN_TCFG_CW_SHIFT 8 1738fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BCN_TCFG_IFS 0 1748fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BCN_INTERVAL = 0x070, // Beacon Interval (TU) 1758fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang ATIMWND = 0x072, // ATIM Window Size (TU) 1768fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT 1778fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA 1788fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BCN_ERR_THRESH = 0x078, // Beacon Error Threshold 1798fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd 1808fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang WCAMI = 0x0A4, // Software write CAM input content 1818fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RCAMO = 0x0A8, // Software read/write CAM config 1828fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang SECR = 0x0B0, //Security Configuration Register 1838fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define SCR_TxUseDK BIT0 //Force Tx Use Default Key 1848fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define SCR_RxUseDK BIT1 //Force Rx Use Default Key 1858fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define SCR_TxEncEnable BIT2 //Enable Tx Encryption 1868fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define SCR_RxDecEnable BIT3 //Enable Rx Decryption 1878fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define SCR_SKByA2 BIT4 //Search kEY BY A2 1888fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define SCR_NoSKMC BIT5 //No Key Search for Multicast 1898fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define SCR_UseDK 0x01 1908fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define SCR_TxSecEnable 0x02 1918fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define SCR_RxSecEnable 0x04 1928fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang TPPoll = 0x0fd, // Transmit priority polling register 1938fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang PSR = 0x0ff, // Page Select Register 1948fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_CCK_LOOPBACK 0x00030000 1958fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_SYSTEM_RESET 0x00000001 1968fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_FIRMWARE_RESET 0x00000008 1978fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_BOOT_RDY 0x00000010 1988fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_FIRM_RDY 0x00000020 1998fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_PUT_CODE_OK 0x00000080 2008fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_BB_RST 0x00000100 2018fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_PWR_STB_CPU 0x00000004 2028fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 2038fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 2048fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 2058fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//---------------------------------------------------------------------------- 2068fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang// 8190 CPU General Register (offset 0x100, 4 byte) 2078fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//---------------------------------------------------------------------------- 2088fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_CCK_LOOPBACK 0x00030000 2098fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_SYSTEM_RESET 0x00000001 2108fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_FIRMWARE_RESET 0x00000008 2118fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_BOOT_RDY 0x00000010 2128fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_FIRM_RDY 0x00000020 2138fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_PUT_CODE_OK 0x00000080 2148fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_BB_RST 0x00000100 2158fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_PWR_STB_CPU 0x00000004 2168fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 2178fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 2188fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang CPU_GEN = 0x100, // CPU Reset Register 2198fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang LED1Cfg = 0x154,// LED1 Configuration Register 220e406322b4b963e622f41d76193d8ca9e5435adb8Mauro Carvalho Chehab LED0Cfg = 0x155,// LED0 Configuration Register 2218fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 2228fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang AcmAvg = 0x170, // ACM Average Period Register 2238fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang AcmHwCtrl = 0x171, // ACM Hardware Control Register 2248fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//---------------------------------------------------------------------------- 2258fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//// 2268fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//// 8190 AcmHwCtrl bits (offset 0x171, 1 byte) 2278fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang////---------------------------------------------------------------------------- 2288fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang// 2298fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AcmHw_HwEn BIT0 2308fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AcmHw_BeqEn BIT1 2318fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AcmHw_ViqEn BIT2 2328fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AcmHw_VoqEn BIT3 2338fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AcmHw_BeqStatus BIT4 2348fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AcmHw_ViqStatus BIT5 2358fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define AcmHw_VoqStatus BIT6 2368fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 2378fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang AcmFwCtrl = 0x172, // ACM Firmware Control Register 2388fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang AES_11N_FIX = 0x173, 2398fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang VOAdmTime = 0x174, // VO Queue Admitted Time Register 2408fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang VIAdmTime = 0x178, // VI Queue Admitted Time Register 2418fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BEAdmTime = 0x17C, // BE Queue Admitted Time Register 2428fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk 2438fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High 2448fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public, 2458fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang// QPRR = 0x1E0, // Queue Page Report per TID 2468fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang QPNR = 0x1D0, //0x1F0, // Queue Packet Number report per TID 2478fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BQDA = 0x200, // Beacon Queue Descriptor Address 2488fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang HQDA = 0x204, // High Priority Queue Descriptor Address 2498fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang CQDA = 0x208, // Command Queue Descriptor Address 2508fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang MQDA = 0x20C, // Management Queue Descriptor Address 2518fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang HCCAQDA = 0x210, // HCCA Queue Descriptor Address 2528fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang VOQDA = 0x214, // VO Queue Descriptor Address 2538fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang VIQDA = 0x218, // VI Queue Descriptor Address 2548fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BEQDA = 0x21C, // BE Queue Descriptor Address 2558fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BKQDA = 0x220, // BK Queue Descriptor Address 2568fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RCQDA = 0x224, // Receive command Queue Descriptor Address 2578fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RDQDA = 0x228, // Receive Queue Descriptor Start Address 2588fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 2598fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang MAR0 = 0x240, // Multicast filter. 2608fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang MAR4 = 0x244, 2618fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 2628fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang CCX_PERIOD = 0x250, // CCX Measurement Period Register, in unit of TU. 2638fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang CLM_RESULT = 0x251, // CCA Busy fraction register. 2648fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_PERIOD = 0x252, // NHM Measurement Period register, in unit of TU. 2658fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 2668fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_THRESHOLD0 = 0x253, // Noise Histogram Meashorement0. 2678fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_THRESHOLD1 = 0x254, // Noise Histogram Meashorement1. 2688fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_THRESHOLD2 = 0x255, // Noise Histogram Meashorement2. 2698fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_THRESHOLD3 = 0x256, // Noise Histogram Meashorement3. 2708fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_THRESHOLD4 = 0x257, // Noise Histogram Meashorement4. 2718fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_THRESHOLD5 = 0x258, // Noise Histogram Meashorement5. 2728fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_THRESHOLD6 = 0x259, // Noise Histogram Meashorement6 2738fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 2748fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang MCTRL = 0x25A, // Measurement Control 2758fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 2768fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_RPI_COUNTER0 = 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0. 2778fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_RPI_COUNTER1 = 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1]. 2788fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_RPI_COUNTER2 = 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2]. 2798fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_RPI_COUNTER3 = 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3]. 2808fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_RPI_COUNTER4 = 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4]. 2818fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_RPI_COUNTER5 = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5]. 2828fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_RPI_COUNTER6 = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6]. 2838fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang NHM_RPI_COUNTER7 = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7]. 2848fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BW_OPMODE_11J BIT0 2858fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BW_OPMODE_5G BIT1 2868fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BW_OPMODE_20MHZ BIT2 2878fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang BW_OPMODE = 0x300, // Bandwidth operation mode 2888fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang MSR = 0x303, // Media Status register 2898fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MSR_LINK_MASK ((1<<0)|(1<<1)) 2908fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MSR_LINK_MANAGED 2 2918fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MSR_LINK_NONE 0 2928fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MSR_LINK_SHIFT 0 2938fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MSR_LINK_ADHOC 1 2948fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MSR_LINK_MASTER 3 2958fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define MSR_LINK_ENEDCA (1<<4) 2968fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long 2978fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RETRY_LIMIT_SHORT_SHIFT 8 2988fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RETRY_LIMIT_LONG_SHIFT 0 2998fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang TSFR = 0x308, 3008fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RRSR = 0x310, // Response Rate Set 3018fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_RSC_OFFSET 21 3028fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_SHORT_OFFSET 23 3038fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_RSC_DUPLICATE 0x600000 3048fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_RSC_LOWSUBCHNL 0x400000 3058fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_RSC_UPSUBCHANL 0x200000 3068fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_SHORT 0x800000 3078fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_1M BIT0 3088fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_2M BIT1 3098fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_5_5M BIT2 3108fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_11M BIT3 3118fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_6M BIT4 3128fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_9M BIT5 3138fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_12M BIT6 3148fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_18M BIT7 3158fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_24M BIT8 3168fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_36M BIT9 3178fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_48M BIT10 3188fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_54M BIT11 3198fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_MCS0 BIT12 3208fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_MCS1 BIT13 3218fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_MCS2 BIT14 3228fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_MCS3 BIT15 3238fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_MCS4 BIT16 3248fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_MCS5 BIT17 3258fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_MCS6 BIT18 3268fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RRSR_MCS7 BIT19 3278fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define BRSR_AckShortPmb BIT23 // CCK ACK: use Short Preamble or not. 3288fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RATR0 = 0x320, // Rate Adaptive Table register1 3298fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang UFWP = 0x318, 3308fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI 3318fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//---------------------------------------------------------------------------- 3328fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang// 8190 Rate Adaptive Table Register (offset 0x320, 4 byte) 3338fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//---------------------------------------------------------------------------- 3348fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//CCK 3358fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_1M 0x00000001 3368fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_2M 0x00000002 3378fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_55M 0x00000004 3388fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_11M 0x00000008 3398fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//OFDM 3408fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_6M 0x00000010 3418fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_9M 0x00000020 3428fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_12M 0x00000040 3438fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_18M 0x00000080 3448fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_24M 0x00000100 3458fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_36M 0x00000200 3468fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_48M 0x00000400 3478fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_54M 0x00000800 3488fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//MCS 1 Spatial Stream 3498fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS0 0x00001000 3508fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS1 0x00002000 3518fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS2 0x00004000 3528fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS3 0x00008000 3538fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS4 0x00010000 3548fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS5 0x00020000 3558fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS6 0x00040000 3568fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS7 0x00080000 3578fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//MCS 2 Spatial Stream 3588fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS8 0x00100000 3598fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS9 0x00200000 3608fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS10 0x00400000 3618fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS11 0x00800000 3628fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS12 0x01000000 3638fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS13 0x02000000 3648fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS14 0x04000000 3658fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATR_MCS15 0x08000000 3668fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang// ALL CCK Rate 3678fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M 3688fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\ 3698fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang |RATR_36M|RATR_48M|RATR_54M 3708fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \ 3718fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RATR_MCS4|RATR_MCS5|RATR_MCS6|RATR_MCS7 3728fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \ 3738fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 3748fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 3758fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang MCS_TXAGC = 0x340, // MCS AGC 3768fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang CCK_TXAGC = 0x348, // CCK AGC 3778fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang// ISR = 0x350, // Interrupt Status Register 3788fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang// IMR = 0x354, // Interrupt Mask Register 3798fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang// IMR_POLL = 0x360, 3808fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang MacBlkCtrl = 0x403, // Mac block on/off control register 3818fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 38235997ff0cadda701711416abf6676b77358b0008Sebastian Hahn EPROM_CMD = 0xfe58, 3838fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define Cmd9346CR_9356SEL (1<<4) 3848fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EPROM_CMD_RESERVED_MASK (1<<5) 3858fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EPROM_CMD_OPERATING_MODE_SHIFT 6 3868fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 3878fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EPROM_CMD_CONFIG 0x3 3888fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EPROM_CMD_NORMAL 0 3898fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EPROM_CMD_LOAD 1 3908fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define EPROM_CMD_PROGRAM 2 391b3d42bf18784607b90b0661ac43f410713ff428bXenia Ragiadakou#define EPROM_CS_BIT BIT(3) 392b3d42bf18784607b90b0661ac43f410713ff428bXenia Ragiadakou#define EPROM_CK_BIT BIT(2) 393b3d42bf18784607b90b0661ac43f410713ff428bXenia Ragiadakou#define EPROM_W_BIT BIT(1) 394b3d42bf18784607b90b0661ac43f410713ff428bXenia Ragiadakou#define EPROM_R_BIT BIT(0) 395b3d42bf18784607b90b0661ac43f410713ff428bXenia Ragiadakou 39635997ff0cadda701711416abf6676b77358b0008Sebastian Hahn MAC0 = 0x000, 39735997ff0cadda701711416abf6676b77358b0008Sebastian Hahn MAC1 = 0x001, 39835997ff0cadda701711416abf6676b77358b0008Sebastian Hahn MAC2 = 0x002, 39935997ff0cadda701711416abf6676b77358b0008Sebastian Hahn MAC3 = 0x003, 40035997ff0cadda701711416abf6676b77358b0008Sebastian Hahn MAC4 = 0x004, 40135997ff0cadda701711416abf6676b77358b0008Sebastian Hahn MAC5 = 0x005, 4028fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang 4038fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang}; 4048fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//---------------------------------------------------------------------------- 4058fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang// 818xB AnaParm & AnaParm2 Register 4068fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//---------------------------------------------------------------------------- 4078fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//#define ANAPARM_ASIC_ON 0x45090658 4088fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang//#define ANAPARM2_ASIC_ON 0x727f3f52 4098fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define GPI 0x108 4108fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define GPO 0x109 4118fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#define GPE 0x10a 4128fc8598e61f6f384f3eaf1d9b09500c12af47b37Jerry Chuang#endif 413