rtl871x_mp.c revision 400838659314cc67032f35962eee5a8639981b61
1/****************************************************************************** 2 * rtl871x_mp.c 3 * 4 * Description : 5 * 6 * Author : 7 * 8 * History : 9 * 10 * Copyright 2007, Realtek Corp. 11 * 12 * The contents of this file is the sole property of Realtek Corp. It can not be 13 * be used, copied or modified without written permission from Realtek Corp. 14 * 15*******************************************************************************/ 16#define _RTL871X_MP_C_ 17 18#include "osdep_service.h" 19#include "drv_types.h" 20#include "rtl871x_mp_phy_regdef.h" 21#include "rtl8712_cmd.h" 22 23static void _init_mp_priv_(struct mp_priv *pmp_priv) 24{ 25 pmp_priv->mode = _LOOPBOOK_MODE_; 26 pmp_priv->curr_ch = 1; 27 pmp_priv->curr_modem = MIXED_PHY; 28 pmp_priv->curr_rateidx = 0; 29 pmp_priv->curr_txpoweridx = 0x14; 30 pmp_priv->antenna_tx = ANTENNA_A; 31 pmp_priv->antenna_rx = ANTENNA_AB; 32 pmp_priv->check_mp_pkt = 0; 33 pmp_priv->tx_pktcount = 0; 34 pmp_priv->rx_pktcount = 0; 35 pmp_priv->rx_crcerrpktcount = 0; 36} 37 38static int init_mp_priv(struct mp_priv *pmp_priv) 39{ 40 int i, res; 41 struct mp_xmit_frame *pmp_xmitframe; 42 43 _init_mp_priv_(pmp_priv); 44 _init_queue(&pmp_priv->free_mp_xmitqueue); 45 pmp_priv->pallocated_mp_xmitframe_buf = NULL; 46 pmp_priv->pallocated_mp_xmitframe_buf = _malloc(NR_MP_XMITFRAME * 47 sizeof(struct mp_xmit_frame) + 4); 48 if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) { 49 res = _FAIL; 50 goto _exit_init_mp_priv; 51 } 52 pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 53 4 - 54 ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3); 55 pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf; 56 for (i = 0; i < NR_MP_XMITFRAME; i++) { 57 _init_listhead(&(pmp_xmitframe->list)); 58 list_insert_tail(&(pmp_xmitframe->list), 59 &(pmp_priv->free_mp_xmitqueue.queue)); 60 pmp_xmitframe->pkt = NULL; 61 pmp_xmitframe->frame_tag = MP_FRAMETAG; 62 pmp_xmitframe->padapter = pmp_priv->papdater; 63 pmp_xmitframe++; 64 } 65 pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME; 66 res = _SUCCESS; 67_exit_init_mp_priv: 68 return res; 69} 70 71static int free_mp_priv(struct mp_priv *pmp_priv) 72{ 73 int res = 0; 74 kfree(pmp_priv->pallocated_mp_xmitframe_buf); 75 return res; 76} 77 78void mp871xinit(struct _adapter *padapter) 79{ 80 struct mp_priv *pmppriv = &padapter->mppriv; 81 82 pmppriv->papdater = padapter; 83 init_mp_priv(pmppriv); 84} 85 86void mp871xdeinit(struct _adapter *padapter) 87{ 88 struct mp_priv *pmppriv = &padapter->mppriv; 89 90 free_mp_priv(pmppriv); 91} 92 93/* 94 * Special for bb and rf reg read/write 95 */ 96static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd) 97{ 98 u32 cmd32 = 0, val32 = 0; 99 u8 iocmd_class = iocmd.cmdclass; 100 u16 iocmd_value = iocmd.value; 101 u8 iocmd_idx = iocmd.index; 102 103 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx ; 104 if (r8712_fw_cmd(pAdapter, cmd32)) 105 r8712_fw_cmd_data(pAdapter, &val32, 1); 106 else 107 val32 = 0; 108 return val32; 109} 110 111static u8 fw_iocmd_write(struct _adapter *pAdapter, 112 struct IOCMD_STRUCT iocmd, u32 value) 113{ 114 u32 cmd32 = 0; 115 u8 iocmd_class = iocmd.cmdclass; 116 u32 iocmd_value = iocmd.value; 117 u8 iocmd_idx = iocmd.index; 118 119 r8712_fw_cmd_data(pAdapter, &value, 0); 120 msleep(100); 121 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx ; 122 return r8712_fw_cmd(pAdapter, cmd32); 123} 124 125/* offset : 0X800~0XFFF */ 126u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset) 127{ 128 u8 shift = offset & 0x0003; /* 4 byte access */ 129 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */ 130 u32 bb_val = 0; 131 struct IOCMD_STRUCT iocmd; 132 133 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 134 iocmd.value = bb_addr; 135 iocmd.index = IOCMD_BB_READ_IDX; 136 bb_val = fw_iocmd_read(pAdapter, iocmd); 137 if (shift != 0) { 138 u32 bb_val2 = 0; 139 bb_val >>= (shift * 8); 140 iocmd.value += 4; 141 bb_val2 = fw_iocmd_read(pAdapter, iocmd); 142 bb_val2 <<= ((4 - shift) * 8); 143 bb_val |= bb_val2; 144 } 145 return bb_val; 146} 147 148/* offset : 0X800~0XFFF */ 149u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value) 150{ 151 u8 shift = offset & 0x0003; /* 4 byte access */ 152 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */ 153 struct IOCMD_STRUCT iocmd; 154 155 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 156 iocmd.value = bb_addr; 157 iocmd.index = IOCMD_BB_WRITE_IDX; 158 if (shift != 0) { 159 u32 oldValue = 0; 160 u32 newValue = value; 161 162 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value); 163 oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8)); 164 value = oldValue | (newValue << (shift * 8)); 165 if (fw_iocmd_write(pAdapter, iocmd, value) == false) 166 return false; 167 iocmd.value += 4; 168 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value); 169 oldValue &= (0xFFFFFFFF << (shift * 8)); 170 value = oldValue | (newValue >> ((4 - shift) * 8)); 171 } 172 return fw_iocmd_write(pAdapter, iocmd, value); 173} 174 175/* offset : 0x00 ~ 0xFF */ 176u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset) 177{ 178 u16 rf_addr = (path << 8) | offset; 179 u32 rf_data; 180 struct IOCMD_STRUCT iocmd; 181 182 iocmd.cmdclass = IOCMD_CLASS_BB_RF ; 183 iocmd.value = rf_addr ; 184 iocmd.index = IOCMD_RF_READ_IDX; 185 rf_data = fw_iocmd_read(pAdapter, iocmd); 186 return rf_data; 187} 188 189u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value) 190{ 191 u16 rf_addr = (path << 8) | offset; 192 struct IOCMD_STRUCT iocmd; 193 194 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 195 iocmd.value = rf_addr; 196 iocmd.index = IOCMD_RF_WRIT_IDX; 197 return fw_iocmd_write(pAdapter, iocmd, value); 198} 199 200static u32 bitshift(u32 bitmask) 201{ 202 u32 i; 203 204 for (i = 0; i <= 31; i++) 205 if (((bitmask>>i) & 0x1) == 1) 206 break; 207 return i; 208} 209 210static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask) 211{ 212 u32 org_value, bit_shift, new_value; 213 214 org_value = r8712_bb_reg_read(pAdapter, offset); 215 bit_shift = bitshift(bitmask); 216 new_value = (org_value & bitmask) >> bit_shift; 217 return new_value; 218} 219 220static u8 set_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask, u32 value) 221{ 222 u32 org_value, bit_shift, new_value; 223 224 if (bitmask != bMaskDWord) { 225 org_value = r8712_bb_reg_read(pAdapter, offset); 226 bit_shift = bitshift(bitmask); 227 new_value = ((org_value & (~bitmask)) | (value << bit_shift)); 228 } else 229 new_value = value; 230 return r8712_bb_reg_write(pAdapter, offset, new_value); 231} 232 233static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, 234 u32 bitmask) 235{ 236 u32 org_value, bit_shift, new_value; 237 238 org_value = r8712_rf_reg_read(pAdapter, path, offset); 239 bit_shift = bitshift(bitmask); 240 new_value = (org_value & bitmask) >> bit_shift; 241 return new_value; 242} 243 244static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask, 245 u32 value) 246{ 247 u32 org_value, bit_shift, new_value; 248 249 if (bitmask != bMaskDWord) { 250 org_value = r8712_rf_reg_read(pAdapter, path, offset); 251 bit_shift = bitshift(bitmask); 252 new_value = ((org_value & (~bitmask)) | (value << bit_shift)); 253 } else 254 new_value = value; 255 return r8712_rf_reg_write(pAdapter, path, offset, new_value); 256} 257 258/* 259 * SetChannel 260 * Description 261 * Use H2C command to change channel, 262 * not only modify rf register, but also other setting need to be done. 263 */ 264void r8712_SetChannel(struct _adapter *pAdapter) 265{ 266 struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv; 267 struct cmd_obj *pcmd = NULL; 268 struct SetChannel_parm *pparm = NULL; 269 u16 code = GEN_CMD_CODE(_SetChannel); 270 271 pcmd = (struct cmd_obj *)_malloc(sizeof(struct cmd_obj)); 272 if (pcmd == NULL) 273 return; 274 pparm = (struct SetChannel_parm *)_malloc(sizeof(struct 275 SetChannel_parm)); 276 if (pparm == NULL) { 277 kfree(pcmd); 278 return; 279 } 280 pparm->curr_ch = pAdapter->mppriv.curr_ch; 281 init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code); 282 r8712_enqueue_cmd(pcmdpriv, pcmd); 283} 284 285static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower) 286{ 287 u16 TxAGC = 0; 288 289 TxAGC = TxPower; 290 set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); 291} 292 293static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower) 294{ 295 u32 TxAGC = 0; 296 297 TxAGC |= ((TxPower<<24)|(TxPower<<16)|(TxPower<<8)|TxPower); 298 set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC); 299 set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC); 300 set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC); 301 set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC); 302 set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC); 303 set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC); 304} 305 306void r8712_SetTxPower(struct _adapter *pAdapter) 307{ 308 u8 TxPower = pAdapter->mppriv.curr_txpoweridx; 309 SetCCKTxPower(pAdapter, TxPower); 310 SetOFDMTxPower(pAdapter, TxPower); 311} 312 313void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset) 314{ 315 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC; 316 317 TxAGCOffset_B = (ulTxAGCOffset&0x000000ff); 318 TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8); 319 TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16); 320 tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B); 321 set_bb_reg(pAdapter, rFPGA0_TxGainStage, 322 (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC); 323} 324 325void r8712_SetDataRate(struct _adapter *pAdapter) 326{ 327 u8 path = RF_PATH_A; 328 u8 offset = RF_SYN_G2; 329 u32 value; 330 331 value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200; 332 r8712_rf_reg_write(pAdapter, path, offset, value); 333} 334 335void r8712_SwitchBandwidth(struct _adapter *pAdapter) 336{ 337 /* 3 1.Set MAC register : BWOPMODE bit2:1 20MhzBW */ 338 u8 regBwOpMode = 0; 339 u8 Bandwidth = pAdapter->mppriv.curr_bandwidth; 340 341 regBwOpMode = r8712_read8(pAdapter, 0x10250203); 342 if (Bandwidth == HT_CHANNEL_WIDTH_20) 343 regBwOpMode |= BIT(2); 344 else 345 regBwOpMode &= ~(BIT(2)); 346 r8712_write8(pAdapter, 0x10250203, regBwOpMode); 347 /* 3 2.Set PHY related register */ 348 switch (Bandwidth) { 349 /* 20 MHz channel*/ 350 case HT_CHANNEL_WIDTH_20: 351 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0); 352 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0); 353 /* Use PHY_REG.txt default value. Do not need to change. 354 * Correct the tx power for CCK rate in 40M. 355 * It is set in Tx descriptor for 8192x series 356 */ 357 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58); 358 break; 359 /* 40 MHz channel*/ 360 case HT_CHANNEL_WIDTH_40: 361 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1); 362 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1); 363 /* Use PHY_REG.txt default value. Do not need to change. 364 * Correct the tx power for CCK rate in 40M. 365 * Set Control channel to upper or lower. These settings are 366 * required only for 40MHz */ 367 set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand, 368 (HAL_PRIME_CHNL_OFFSET_DONT_CARE>>1)); 369 set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00, 370 HAL_PRIME_CHNL_OFFSET_DONT_CARE); 371 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18); 372 break; 373 default: 374 break; 375 } 376 377 /* 3 3.Set RF related register */ 378 switch (Bandwidth) { 379 case HT_CHANNEL_WIDTH_20: 380 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW, 381 BIT(10) | BIT(11), 0x01); 382 break; 383 case HT_CHANNEL_WIDTH_40: 384 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW, 385 BIT(10) | BIT(11), 0x00); 386 break; 387 default: 388 break; 389 } 390} 391/*------------------------------Define structure----------------------------*/ 392struct R_ANTENNA_SELECT_OFDM { 393 u32 r_tx_antenna:4; 394 u32 r_ant_l:4; 395 u32 r_ant_non_ht:4; 396 u32 r_ant_ht1:4; 397 u32 r_ant_ht2:4; 398 u32 r_ant_ht_s1:4; 399 u32 r_ant_non_ht_s1:4; 400 u32 OFDM_TXSC:2; 401 u32 Reserved:2; 402}; 403 404struct R_ANTENNA_SELECT_CCK { 405 u8 r_cckrx_enable_2:2; 406 u8 r_cckrx_enable:2; 407 u8 r_ccktx_enable:4; 408}; 409 410void r8712_SwitchAntenna(struct _adapter *pAdapter) 411{ 412 u32 ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0; 413 u8 ofdm_rx_ant_sel_val = 0; 414 u8 cck_ant_select_val = 0; 415 u32 cck_ant_sel_val = 0; 416 struct R_ANTENNA_SELECT_CCK *p_cck_txrx; 417 418 p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val; 419 420 switch (pAdapter->mppriv.antenna_tx) { 421 case ANTENNA_A: 422 /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/ 423 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); 424 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1); 425 ofdm_tx_en_val = 0x3; 426 ofdm_tx_ant_sel_val = 0x11111111;/* Power save */ 427 p_cck_txrx->r_ccktx_enable = 0x8; 428 break; 429 case ANTENNA_B: 430 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); 431 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); 432 ofdm_tx_en_val = 0x3; 433 ofdm_tx_ant_sel_val = 0x22222222;/* Power save */ 434 p_cck_txrx->r_ccktx_enable = 0x4; 435 break; 436 case ANTENNA_AB: /* For 8192S */ 437 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); 438 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); 439 ofdm_tx_en_val = 0x3; 440 ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */ 441 p_cck_txrx->r_ccktx_enable = 0xC; 442 break; 443 default: 444 break; 445 } 446 /*OFDM Tx*/ 447 set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val); 448 /*OFDM Tx*/ 449 set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val); 450 switch (pAdapter->mppriv.antenna_rx) { 451 case ANTENNA_A: 452 ofdm_rx_ant_sel_val = 0x1; /* A */ 453 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */ 454 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */ 455 break; 456 case ANTENNA_B: 457 ofdm_rx_ant_sel_val = 0x2; /* B */ 458 p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */ 459 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */ 460 break; 461 case ANTENNA_AB: 462 ofdm_rx_ant_sel_val = 0x3; /* AB */ 463 p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */ 464 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */ 465 break; 466 default: 467 break; 468 } 469 /*OFDM Rx*/ 470 set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, 471 ofdm_rx_ant_sel_val); 472 /*OFDM Rx*/ 473 set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, 474 ofdm_rx_ant_sel_val); 475 476 cck_ant_sel_val = cck_ant_select_val; 477 /*CCK TxRx*/ 478 set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val); 479} 480 481void r8712_SetCrystalCap(struct _adapter *pAdapter) 482{ 483 set_bb_reg(pAdapter, rFPGA0_AnalogParameter1, bXtalCap, 484 pAdapter->mppriv.curr_crystalcap); 485} 486 487static void TriggerRFThermalMeter(struct _adapter *pAdapter) 488{ 489 /* 0x24: RF Reg[6:5] */ 490 set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); 491} 492 493static u32 ReadRFThermalMeter(struct _adapter *pAdapter) 494{ 495 u32 ThermalValue = 0; 496 497 /* 0x24: RF Reg[4:0] */ 498 ThermalValue = get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); 499 return ThermalValue; 500} 501 502void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value) 503{ 504 TriggerRFThermalMeter(pAdapter); 505 msleep(1000); 506 *value = ReadRFThermalMeter(pAdapter); 507} 508 509void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart) 510{ 511 if (bStart) { /* Start Single Carrier. */ 512 /* 1. if OFDM block on? */ 513 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) 514 /*set OFDM block on*/ 515 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); 516 /* 2. set CCK test mode off, set to CCK normal mode */ 517 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); 518 /* 3. turn on scramble setting */ 519 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 520 /* 4. Turn On Single Carrier Tx and off the other test modes. */ 521 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 522 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable); 523 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 524 } else { /* Stop Single Carrier.*/ 525 /* Turn off all test modes.*/ 526 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 527 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, 528 bDisable); 529 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 530 msleep(20); 531 /*BB Reset*/ 532 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 533 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 534 } 535} 536 537void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart) 538{ 539 u8 rfPath = pAdapter->mppriv.curr_rfpath; 540 switch (pAdapter->mppriv.antenna_tx) { 541 case ANTENNA_B: 542 rfPath = RF_PATH_B; 543 break; 544 case ANTENNA_A: 545 default: 546 rfPath = RF_PATH_A; 547 break; 548 } 549 if (bStart) { /* Start Single Tone.*/ 550 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable); 551 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable); 552 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask, 553 0xd4000); 554 msleep(100); 555 /* PAD all on.*/ 556 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f); 557 msleep(100); 558 } else { /* Stop Single Tone.*/ 559 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); 560 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); 561 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask, 562 0x54000); 563 msleep(100); 564 /* PAD all on.*/ 565 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000); 566 msleep(100); 567 } 568} 569 570void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart) 571{ 572 if (bStart) { /* Start Carrier Suppression.*/ 573 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) { 574 /* 1. if CCK block on? */ 575 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { 576 /*set CCK block on*/ 577 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 578 bEnable); 579 } 580 /* Turn Off All Test Mode */ 581 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, 582 bDisable); 583 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, 584 bDisable); 585 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, 586 bDisable); 587 /*transmit mode*/ 588 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); 589 /*turn off scramble setting*/ 590 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 591 bDisable); 592 /*Set CCK Tx Test Rate*/ 593 /*Set FTxRate to 1Mbps*/ 594 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); 595 } 596 } else { /* Stop Carrier Suppression. */ 597 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) { 598 /*normal mode*/ 599 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); 600 /*turn on scramble setting*/ 601 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 602 bEnable); 603 /*BB Reset*/ 604 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 605 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 606 } 607 } 608} 609 610static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart) 611{ 612 u32 cckrate; 613 614 if (bStart) { 615 /* 1. if CCK block on? */ 616 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { 617 /*set CCK block on*/ 618 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); 619 } 620 /* Turn Off All Test Mode */ 621 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 622 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); 623 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 624 /*Set CCK Tx Test Rate*/ 625 cckrate = pAdapter->mppriv.curr_rateidx; 626 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); 627 /*transmit mode*/ 628 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); 629 /*turn on scramble setting*/ 630 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 631 } else { 632 /*normal mode*/ 633 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); 634 /*turn on scramble setting*/ 635 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 636 /*BB Reset*/ 637 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 638 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 639 } 640} /* mpt_StartCckContTx */ 641 642static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart) 643{ 644 if (bStart) { 645 /* 1. if OFDM block on? */ 646 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) { 647 /*set OFDM block on*/ 648 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); 649 } 650 /* 2. set CCK test mode off, set to CCK normal mode*/ 651 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); 652 /* 3. turn on scramble setting */ 653 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 654 /* 4. Turn On Continue Tx and turn off the other test modes.*/ 655 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable); 656 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); 657 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 658 } else { 659 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 660 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, 661 bDisable); 662 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 663 msleep(20); 664 /*BB Reset*/ 665 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 666 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 667 } 668} /* mpt_StartOfdmContTx */ 669 670void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart) 671{ 672 /* ADC turn off [bit24-21] adc port0 ~ port1 */ 673 if (bStart) { 674 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA, 675 r8712_bb_reg_read(pAdapter, 676 rRx_Wait_CCCA) & 0xFE1FFFFF); 677 msleep(100); 678 } 679 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) 680 SetCCKContinuousTx(pAdapter, bStart); 681 else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) && 682 (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15)) 683 SetOFDMContinuousTx(pAdapter, bStart); 684 /* ADC turn on [bit24-21] adc port0 ~ port1 */ 685 if (!bStart) 686 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA, 687 r8712_bb_reg_read(pAdapter, 688 rRx_Wait_CCCA) | 0x01E00000); 689} 690 691void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter) 692{ 693 u32 i, phyrx_set = 0; 694 695 for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) { 696 phyrx_set = 0; 697 phyrx_set |= (i << 28); /*select*/ 698 phyrx_set |= 0x08000000; /* set counter to zero*/ 699 r8712_write32(pAdapter, RXERR_RPT, phyrx_set); 700 } 701} 702 703static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit) 704{ 705 /*selection*/ 706 u32 phyrx_set = 0, count = 0; 707 u32 SelectBit; 708 709 SelectBit = selbit << 28; 710 phyrx_set |= (SelectBit & 0xF0000000); 711 r8712_write32(pAdapter, RXERR_RPT, phyrx_set); 712 /*Read packet count*/ 713 count = r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount; 714 return count; 715} 716 717u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter) 718{ 719 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; 720 721 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT); 722 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT); 723 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT); 724 return OFDM_cnt + CCK_cnt + HT_cnt; 725} 726 727u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter) 728{ 729 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; 730 731 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT); 732 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT); 733 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT); 734 return OFDM_cnt + CCK_cnt + HT_cnt; 735} 736