rtl871x_mp.c revision 534c4acd1d45942eaae0db5858c82a33fac47468
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * Modifications for inclusion into the Linux staging tree are 19 * Copyright(c) 2010 Larry Finger. All rights reserved. 20 * 21 * Contact information: 22 * WLAN FAE <wlanfae@realtek.com> 23 * Larry Finger <Larry.Finger@lwfinger.net> 24 * 25 ******************************************************************************/ 26#define _RTL871X_MP_C_ 27 28#include "osdep_service.h" 29#include "drv_types.h" 30#include "rtl871x_mp_phy_regdef.h" 31#include "rtl8712_cmd.h" 32 33static void _init_mp_priv_(struct mp_priv *pmp_priv) 34{ 35 pmp_priv->mode = _LOOPBOOK_MODE_; 36 pmp_priv->curr_ch = 1; 37 pmp_priv->curr_modem = MIXED_PHY; 38 pmp_priv->curr_rateidx = 0; 39 pmp_priv->curr_txpoweridx = 0x14; 40 pmp_priv->antenna_tx = ANTENNA_A; 41 pmp_priv->antenna_rx = ANTENNA_AB; 42 pmp_priv->check_mp_pkt = 0; 43 pmp_priv->tx_pktcount = 0; 44 pmp_priv->rx_pktcount = 0; 45 pmp_priv->rx_crcerrpktcount = 0; 46} 47 48static int init_mp_priv(struct mp_priv *pmp_priv) 49{ 50 int i, res; 51 struct mp_xmit_frame *pmp_xmitframe; 52 53 _init_mp_priv_(pmp_priv); 54 _init_queue(&pmp_priv->free_mp_xmitqueue); 55 pmp_priv->pallocated_mp_xmitframe_buf = NULL; 56 pmp_priv->pallocated_mp_xmitframe_buf = kmalloc(NR_MP_XMITFRAME * 57 sizeof(struct mp_xmit_frame) + 4, 58 GFP_ATOMIC); 59 if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) { 60 res = _FAIL; 61 goto _exit_init_mp_priv; 62 } 63 pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 64 4 - 65 ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3); 66 pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf; 67 for (i = 0; i < NR_MP_XMITFRAME; i++) { 68 INIT_LIST_HEAD(&(pmp_xmitframe->list)); 69 list_insert_tail(&(pmp_xmitframe->list), 70 &(pmp_priv->free_mp_xmitqueue.queue)); 71 pmp_xmitframe->pkt = NULL; 72 pmp_xmitframe->frame_tag = MP_FRAMETAG; 73 pmp_xmitframe->padapter = pmp_priv->papdater; 74 pmp_xmitframe++; 75 } 76 pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME; 77 res = _SUCCESS; 78_exit_init_mp_priv: 79 return res; 80} 81 82static int free_mp_priv(struct mp_priv *pmp_priv) 83{ 84 kfree(pmp_priv->pallocated_mp_xmitframe_buf); 85 return 0; 86} 87 88void mp871xinit(struct _adapter *padapter) 89{ 90 struct mp_priv *pmppriv = &padapter->mppriv; 91 92 pmppriv->papdater = padapter; 93 init_mp_priv(pmppriv); 94} 95 96void mp871xdeinit(struct _adapter *padapter) 97{ 98 struct mp_priv *pmppriv = &padapter->mppriv; 99 100 free_mp_priv(pmppriv); 101} 102 103/* 104 * Special for bb and rf reg read/write 105 */ 106static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd) 107{ 108 u32 cmd32 = 0, val32 = 0; 109 u8 iocmd_class = iocmd.cmdclass; 110 u16 iocmd_value = iocmd.value; 111 u8 iocmd_idx = iocmd.index; 112 113 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx; 114 if (r8712_fw_cmd(pAdapter, cmd32)) 115 r8712_fw_cmd_data(pAdapter, &val32, 1); 116 else 117 val32 = 0; 118 return val32; 119} 120 121static u8 fw_iocmd_write(struct _adapter *pAdapter, 122 struct IOCMD_STRUCT iocmd, u32 value) 123{ 124 u32 cmd32 = 0; 125 u8 iocmd_class = iocmd.cmdclass; 126 u32 iocmd_value = iocmd.value; 127 u8 iocmd_idx = iocmd.index; 128 129 r8712_fw_cmd_data(pAdapter, &value, 0); 130 msleep(100); 131 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx; 132 return r8712_fw_cmd(pAdapter, cmd32); 133} 134 135/* offset : 0X800~0XFFF */ 136u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset) 137{ 138 u8 shift = offset & 0x0003; /* 4 byte access */ 139 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */ 140 u32 bb_val = 0; 141 struct IOCMD_STRUCT iocmd; 142 143 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 144 iocmd.value = bb_addr; 145 iocmd.index = IOCMD_BB_READ_IDX; 146 bb_val = fw_iocmd_read(pAdapter, iocmd); 147 if (shift != 0) { 148 u32 bb_val2 = 0; 149 bb_val >>= (shift * 8); 150 iocmd.value += 4; 151 bb_val2 = fw_iocmd_read(pAdapter, iocmd); 152 bb_val2 <<= ((4 - shift) * 8); 153 bb_val |= bb_val2; 154 } 155 return bb_val; 156} 157 158/* offset : 0X800~0XFFF */ 159u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value) 160{ 161 u8 shift = offset & 0x0003; /* 4 byte access */ 162 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */ 163 struct IOCMD_STRUCT iocmd; 164 165 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 166 iocmd.value = bb_addr; 167 iocmd.index = IOCMD_BB_WRITE_IDX; 168 if (shift != 0) { 169 u32 oldValue = 0; 170 u32 newValue = value; 171 172 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value); 173 oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8)); 174 value = oldValue | (newValue << (shift * 8)); 175 if (fw_iocmd_write(pAdapter, iocmd, value) == false) 176 return false; 177 iocmd.value += 4; 178 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value); 179 oldValue &= (0xFFFFFFFF << (shift * 8)); 180 value = oldValue | (newValue >> ((4 - shift) * 8)); 181 } 182 return fw_iocmd_write(pAdapter, iocmd, value); 183} 184 185/* offset : 0x00 ~ 0xFF */ 186u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset) 187{ 188 u16 rf_addr = (path << 8) | offset; 189 u32 rf_data; 190 struct IOCMD_STRUCT iocmd; 191 192 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 193 iocmd.value = rf_addr; 194 iocmd.index = IOCMD_RF_READ_IDX; 195 rf_data = fw_iocmd_read(pAdapter, iocmd); 196 return rf_data; 197} 198 199u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value) 200{ 201 u16 rf_addr = (path << 8) | offset; 202 struct IOCMD_STRUCT iocmd; 203 204 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 205 iocmd.value = rf_addr; 206 iocmd.index = IOCMD_RF_WRIT_IDX; 207 return fw_iocmd_write(pAdapter, iocmd, value); 208} 209 210static u32 bitshift(u32 bitmask) 211{ 212 u32 i; 213 214 for (i = 0; i <= 31; i++) 215 if (((bitmask>>i) & 0x1) == 1) 216 break; 217 return i; 218} 219 220static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask) 221{ 222 u32 org_value, bit_shift, new_value; 223 224 org_value = r8712_bb_reg_read(pAdapter, offset); 225 bit_shift = bitshift(bitmask); 226 new_value = (org_value & bitmask) >> bit_shift; 227 return new_value; 228} 229 230static u8 set_bb_reg(struct _adapter *pAdapter, 231 u16 offset, 232 u32 bitmask, 233 u32 value) 234{ 235 u32 org_value, bit_shift, new_value; 236 237 if (bitmask != bMaskDWord) { 238 org_value = r8712_bb_reg_read(pAdapter, offset); 239 bit_shift = bitshift(bitmask); 240 new_value = ((org_value & (~bitmask)) | (value << bit_shift)); 241 } else 242 new_value = value; 243 return r8712_bb_reg_write(pAdapter, offset, new_value); 244} 245 246static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, 247 u32 bitmask) 248{ 249 u32 org_value, bit_shift, new_value; 250 251 org_value = r8712_rf_reg_read(pAdapter, path, offset); 252 bit_shift = bitshift(bitmask); 253 new_value = (org_value & bitmask) >> bit_shift; 254 return new_value; 255} 256 257static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask, 258 u32 value) 259{ 260 u32 org_value, bit_shift, new_value; 261 262 if (bitmask != bMaskDWord) { 263 org_value = r8712_rf_reg_read(pAdapter, path, offset); 264 bit_shift = bitshift(bitmask); 265 new_value = ((org_value & (~bitmask)) | (value << bit_shift)); 266 } else 267 new_value = value; 268 return r8712_rf_reg_write(pAdapter, path, offset, new_value); 269} 270 271/* 272 * SetChannel 273 * Description 274 * Use H2C command to change channel, 275 * not only modify rf register, but also other setting need to be done. 276 */ 277void r8712_SetChannel(struct _adapter *pAdapter) 278{ 279 struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv; 280 struct cmd_obj *pcmd = NULL; 281 struct SetChannel_parm *pparm = NULL; 282 u16 code = GEN_CMD_CODE(_SetChannel); 283 284 pcmd = kmalloc(sizeof(*pcmd), GFP_ATOMIC); 285 if (pcmd == NULL) 286 return; 287 pparm = kmalloc(sizeof(*pparm), GFP_ATOMIC); 288 if (pparm == NULL) { 289 kfree(pcmd); 290 return; 291 } 292 pparm->curr_ch = pAdapter->mppriv.curr_ch; 293 init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code); 294 r8712_enqueue_cmd(pcmdpriv, pcmd); 295} 296 297static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower) 298{ 299 u16 TxAGC = 0; 300 301 TxAGC = TxPower; 302 set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); 303} 304 305static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower) 306{ 307 u32 TxAGC = 0; 308 309 TxAGC |= ((TxPower<<24)|(TxPower<<16)|(TxPower<<8)|TxPower); 310 set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC); 311 set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC); 312 set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC); 313 set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC); 314 set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC); 315 set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC); 316} 317 318void r8712_SetTxPower(struct _adapter *pAdapter) 319{ 320 u8 TxPower = pAdapter->mppriv.curr_txpoweridx; 321 SetCCKTxPower(pAdapter, TxPower); 322 SetOFDMTxPower(pAdapter, TxPower); 323} 324 325void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset) 326{ 327 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC; 328 329 TxAGCOffset_B = (ulTxAGCOffset&0x000000ff); 330 TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8); 331 TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16); 332 tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B); 333 set_bb_reg(pAdapter, rFPGA0_TxGainStage, 334 (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC); 335} 336 337void r8712_SetDataRate(struct _adapter *pAdapter) 338{ 339 u8 path = RF_PATH_A; 340 u8 offset = RF_SYN_G2; 341 u32 value; 342 343 value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200; 344 r8712_rf_reg_write(pAdapter, path, offset, value); 345} 346 347void r8712_SwitchBandwidth(struct _adapter *pAdapter) 348{ 349 /* 3 1.Set MAC register : BWOPMODE bit2:1 20MhzBW */ 350 u8 regBwOpMode = 0; 351 u8 Bandwidth = pAdapter->mppriv.curr_bandwidth; 352 353 regBwOpMode = r8712_read8(pAdapter, 0x10250203); 354 if (Bandwidth == HT_CHANNEL_WIDTH_20) 355 regBwOpMode |= BIT(2); 356 else 357 regBwOpMode &= ~(BIT(2)); 358 r8712_write8(pAdapter, 0x10250203, regBwOpMode); 359 /* 3 2.Set PHY related register */ 360 switch (Bandwidth) { 361 /* 20 MHz channel*/ 362 case HT_CHANNEL_WIDTH_20: 363 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0); 364 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0); 365 /* Use PHY_REG.txt default value. Do not need to change. 366 * Correct the tx power for CCK rate in 40M. 367 * It is set in Tx descriptor for 8192x series 368 */ 369 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58); 370 break; 371 /* 40 MHz channel*/ 372 case HT_CHANNEL_WIDTH_40: 373 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1); 374 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1); 375 /* Use PHY_REG.txt default value. Do not need to change. 376 * Correct the tx power for CCK rate in 40M. 377 * Set Control channel to upper or lower. These settings are 378 * required only for 40MHz */ 379 set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand, 380 (HAL_PRIME_CHNL_OFFSET_DONT_CARE>>1)); 381 set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00, 382 HAL_PRIME_CHNL_OFFSET_DONT_CARE); 383 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18); 384 break; 385 default: 386 break; 387 } 388 389 /* 3 3.Set RF related register */ 390 switch (Bandwidth) { 391 case HT_CHANNEL_WIDTH_20: 392 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW, 393 BIT(10) | BIT(11), 0x01); 394 break; 395 case HT_CHANNEL_WIDTH_40: 396 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW, 397 BIT(10) | BIT(11), 0x00); 398 break; 399 default: 400 break; 401 } 402} 403/*------------------------------Define structure----------------------------*/ 404struct R_ANTENNA_SELECT_OFDM { 405 u32 r_tx_antenna:4; 406 u32 r_ant_l:4; 407 u32 r_ant_non_ht:4; 408 u32 r_ant_ht1:4; 409 u32 r_ant_ht2:4; 410 u32 r_ant_ht_s1:4; 411 u32 r_ant_non_ht_s1:4; 412 u32 OFDM_TXSC:2; 413 u32 Reserved:2; 414}; 415 416struct R_ANTENNA_SELECT_CCK { 417 u8 r_cckrx_enable_2:2; 418 u8 r_cckrx_enable:2; 419 u8 r_ccktx_enable:4; 420}; 421 422void r8712_SwitchAntenna(struct _adapter *pAdapter) 423{ 424 u32 ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0; 425 u8 ofdm_rx_ant_sel_val = 0; 426 u8 cck_ant_select_val = 0; 427 u32 cck_ant_sel_val = 0; 428 struct R_ANTENNA_SELECT_CCK *p_cck_txrx; 429 430 p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val; 431 432 switch (pAdapter->mppriv.antenna_tx) { 433 case ANTENNA_A: 434 /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/ 435 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); 436 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1); 437 ofdm_tx_en_val = 0x3; 438 ofdm_tx_ant_sel_val = 0x11111111;/* Power save */ 439 p_cck_txrx->r_ccktx_enable = 0x8; 440 break; 441 case ANTENNA_B: 442 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); 443 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); 444 ofdm_tx_en_val = 0x3; 445 ofdm_tx_ant_sel_val = 0x22222222;/* Power save */ 446 p_cck_txrx->r_ccktx_enable = 0x4; 447 break; 448 case ANTENNA_AB: /* For 8192S */ 449 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); 450 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); 451 ofdm_tx_en_val = 0x3; 452 ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */ 453 p_cck_txrx->r_ccktx_enable = 0xC; 454 break; 455 default: 456 break; 457 } 458 /*OFDM Tx*/ 459 set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val); 460 /*OFDM Tx*/ 461 set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val); 462 switch (pAdapter->mppriv.antenna_rx) { 463 case ANTENNA_A: 464 ofdm_rx_ant_sel_val = 0x1; /* A */ 465 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */ 466 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */ 467 break; 468 case ANTENNA_B: 469 ofdm_rx_ant_sel_val = 0x2; /* B */ 470 p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */ 471 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */ 472 break; 473 case ANTENNA_AB: 474 ofdm_rx_ant_sel_val = 0x3; /* AB */ 475 p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */ 476 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */ 477 break; 478 default: 479 break; 480 } 481 /*OFDM Rx*/ 482 set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, 483 ofdm_rx_ant_sel_val); 484 /*OFDM Rx*/ 485 set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, 486 ofdm_rx_ant_sel_val); 487 488 cck_ant_sel_val = cck_ant_select_val; 489 /*CCK TxRx*/ 490 set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val); 491} 492 493void r8712_SetCrystalCap(struct _adapter *pAdapter) 494{ 495 set_bb_reg(pAdapter, rFPGA0_AnalogParameter1, bXtalCap, 496 pAdapter->mppriv.curr_crystalcap); 497} 498 499static void TriggerRFThermalMeter(struct _adapter *pAdapter) 500{ 501 /* 0x24: RF Reg[6:5] */ 502 set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); 503} 504 505static u32 ReadRFThermalMeter(struct _adapter *pAdapter) 506{ 507 u32 ThermalValue = 0; 508 509 /* 0x24: RF Reg[4:0] */ 510 ThermalValue = get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); 511 return ThermalValue; 512} 513 514void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value) 515{ 516 TriggerRFThermalMeter(pAdapter); 517 msleep(1000); 518 *value = ReadRFThermalMeter(pAdapter); 519} 520 521void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart) 522{ 523 if (bStart) { /* Start Single Carrier. */ 524 /* 1. if OFDM block on? */ 525 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) 526 /*set OFDM block on*/ 527 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); 528 /* 2. set CCK test mode off, set to CCK normal mode */ 529 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); 530 /* 3. turn on scramble setting */ 531 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 532 /* 4. Turn On Single Carrier Tx and off the other test modes. */ 533 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 534 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable); 535 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 536 } else { /* Stop Single Carrier.*/ 537 /* Turn off all test modes.*/ 538 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 539 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, 540 bDisable); 541 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 542 msleep(20); 543 /*BB Reset*/ 544 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 545 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 546 } 547} 548 549void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart) 550{ 551 u8 rfPath = pAdapter->mppriv.curr_rfpath; 552 switch (pAdapter->mppriv.antenna_tx) { 553 case ANTENNA_B: 554 rfPath = RF_PATH_B; 555 break; 556 case ANTENNA_A: 557 default: 558 rfPath = RF_PATH_A; 559 break; 560 } 561 if (bStart) { /* Start Single Tone.*/ 562 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable); 563 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable); 564 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask, 565 0xd4000); 566 msleep(100); 567 /* PAD all on.*/ 568 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f); 569 msleep(100); 570 } else { /* Stop Single Tone.*/ 571 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); 572 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); 573 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask, 574 0x54000); 575 msleep(100); 576 /* PAD all on.*/ 577 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000); 578 msleep(100); 579 } 580} 581 582void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart) 583{ 584 if (bStart) { /* Start Carrier Suppression.*/ 585 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) { 586 /* 1. if CCK block on? */ 587 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { 588 /*set CCK block on*/ 589 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 590 bEnable); 591 } 592 /* Turn Off All Test Mode */ 593 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, 594 bDisable); 595 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, 596 bDisable); 597 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, 598 bDisable); 599 /*transmit mode*/ 600 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); 601 /*turn off scramble setting*/ 602 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 603 bDisable); 604 /*Set CCK Tx Test Rate*/ 605 /*Set FTxRate to 1Mbps*/ 606 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); 607 } 608 } else { /* Stop Carrier Suppression. */ 609 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) { 610 /*normal mode*/ 611 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); 612 /*turn on scramble setting*/ 613 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 614 bEnable); 615 /*BB Reset*/ 616 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 617 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 618 } 619 } 620} 621 622static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart) 623{ 624 u32 cckrate; 625 626 if (bStart) { 627 /* 1. if CCK block on? */ 628 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { 629 /*set CCK block on*/ 630 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); 631 } 632 /* Turn Off All Test Mode */ 633 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 634 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); 635 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 636 /*Set CCK Tx Test Rate*/ 637 cckrate = pAdapter->mppriv.curr_rateidx; 638 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); 639 /*transmit mode*/ 640 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); 641 /*turn on scramble setting*/ 642 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 643 } else { 644 /*normal mode*/ 645 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); 646 /*turn on scramble setting*/ 647 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 648 /*BB Reset*/ 649 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 650 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 651 } 652} /* mpt_StartCckContTx */ 653 654static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart) 655{ 656 if (bStart) { 657 /* 1. if OFDM block on? */ 658 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) { 659 /*set OFDM block on*/ 660 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); 661 } 662 /* 2. set CCK test mode off, set to CCK normal mode*/ 663 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); 664 /* 3. turn on scramble setting */ 665 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 666 /* 4. Turn On Continue Tx and turn off the other test modes.*/ 667 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable); 668 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); 669 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 670 } else { 671 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 672 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, 673 bDisable); 674 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 675 msleep(20); 676 /*BB Reset*/ 677 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 678 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 679 } 680} /* mpt_StartOfdmContTx */ 681 682void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart) 683{ 684 /* ADC turn off [bit24-21] adc port0 ~ port1 */ 685 if (bStart) { 686 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA, 687 r8712_bb_reg_read(pAdapter, 688 rRx_Wait_CCCA) & 0xFE1FFFFF); 689 msleep(100); 690 } 691 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) 692 SetCCKContinuousTx(pAdapter, bStart); 693 else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) && 694 (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15)) 695 SetOFDMContinuousTx(pAdapter, bStart); 696 /* ADC turn on [bit24-21] adc port0 ~ port1 */ 697 if (!bStart) 698 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA, 699 r8712_bb_reg_read(pAdapter, 700 rRx_Wait_CCCA) | 0x01E00000); 701} 702 703void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter) 704{ 705 u32 i, phyrx_set = 0; 706 707 for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) { 708 phyrx_set = 0; 709 phyrx_set |= (i << 28); /*select*/ 710 phyrx_set |= 0x08000000; /* set counter to zero*/ 711 r8712_write32(pAdapter, RXERR_RPT, phyrx_set); 712 } 713} 714 715static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit) 716{ 717 /*selection*/ 718 u32 phyrx_set = 0, count = 0; 719 u32 SelectBit; 720 721 SelectBit = selbit << 28; 722 phyrx_set |= (SelectBit & 0xF0000000); 723 r8712_write32(pAdapter, RXERR_RPT, phyrx_set); 724 /*Read packet count*/ 725 count = r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount; 726 return count; 727} 728 729u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter) 730{ 731 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; 732 733 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT); 734 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT); 735 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT); 736 return OFDM_cnt + CCK_cnt + HT_cnt; 737} 738 739u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter) 740{ 741 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; 742 743 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT); 744 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT); 745 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT); 746 return OFDM_cnt + CCK_cnt + HT_cnt; 747} 748