rtl871x_mp.c revision ddcb81e7419baa90fab79dbbb1b983a69a235c91
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * Modifications for inclusion into the Linux staging tree are 19 * Copyright(c) 2010 Larry Finger. All rights reserved. 20 * 21 * Contact information: 22 * WLAN FAE <wlanfae@realtek.com> 23 * Larry Finger <Larry.Finger@lwfinger.net> 24 * 25 ******************************************************************************/ 26#define _RTL871X_MP_C_ 27 28#include "osdep_service.h" 29#include "drv_types.h" 30#include "rtl871x_mp_phy_regdef.h" 31#include "rtl8712_cmd.h" 32 33static void _init_mp_priv_(struct mp_priv *pmp_priv) 34{ 35 pmp_priv->mode = _LOOPBOOK_MODE_; 36 pmp_priv->curr_ch = 1; 37 pmp_priv->curr_modem = MIXED_PHY; 38 pmp_priv->curr_rateidx = 0; 39 pmp_priv->curr_txpoweridx = 0x14; 40 pmp_priv->antenna_tx = ANTENNA_A; 41 pmp_priv->antenna_rx = ANTENNA_AB; 42 pmp_priv->check_mp_pkt = 0; 43 pmp_priv->tx_pktcount = 0; 44 pmp_priv->rx_pktcount = 0; 45 pmp_priv->rx_crcerrpktcount = 0; 46} 47 48static int init_mp_priv(struct mp_priv *pmp_priv) 49{ 50 int i, res; 51 struct mp_xmit_frame *pmp_xmitframe; 52 53 _init_mp_priv_(pmp_priv); 54 _init_queue(&pmp_priv->free_mp_xmitqueue); 55 pmp_priv->pallocated_mp_xmitframe_buf = NULL; 56 pmp_priv->pallocated_mp_xmitframe_buf = kmalloc(NR_MP_XMITFRAME * 57 sizeof(struct mp_xmit_frame) + 4, 58 GFP_ATOMIC); 59 if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) { 60 res = _FAIL; 61 goto _exit_init_mp_priv; 62 } 63 pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 64 4 - 65 ((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3); 66 pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf; 67 for (i = 0; i < NR_MP_XMITFRAME; i++) { 68 INIT_LIST_HEAD(&(pmp_xmitframe->list)); 69 list_add_tail(&(pmp_xmitframe->list), 70 &(pmp_priv->free_mp_xmitqueue.queue)); 71 pmp_xmitframe->pkt = NULL; 72 pmp_xmitframe->frame_tag = MP_FRAMETAG; 73 pmp_xmitframe->padapter = pmp_priv->papdater; 74 pmp_xmitframe++; 75 } 76 pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME; 77 res = _SUCCESS; 78_exit_init_mp_priv: 79 return res; 80} 81 82static int free_mp_priv(struct mp_priv *pmp_priv) 83{ 84 kfree(pmp_priv->pallocated_mp_xmitframe_buf); 85 return 0; 86} 87 88void mp871xinit(struct _adapter *padapter) 89{ 90 struct mp_priv *pmppriv = &padapter->mppriv; 91 92 pmppriv->papdater = padapter; 93 init_mp_priv(pmppriv); 94} 95 96void mp871xdeinit(struct _adapter *padapter) 97{ 98 struct mp_priv *pmppriv = &padapter->mppriv; 99 100 free_mp_priv(pmppriv); 101} 102 103/* 104 * Special for bb and rf reg read/write 105 */ 106static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd) 107{ 108 u32 cmd32 = 0, val32 = 0; 109 u8 iocmd_class = iocmd.cmdclass; 110 u16 iocmd_value = iocmd.value; 111 u8 iocmd_idx = iocmd.index; 112 113 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx; 114 if (r8712_fw_cmd(pAdapter, cmd32)) 115 r8712_fw_cmd_data(pAdapter, &val32, 1); 116 else 117 val32 = 0; 118 return val32; 119} 120 121static u8 fw_iocmd_write(struct _adapter *pAdapter, 122 struct IOCMD_STRUCT iocmd, u32 value) 123{ 124 u32 cmd32 = 0; 125 u8 iocmd_class = iocmd.cmdclass; 126 u32 iocmd_value = iocmd.value; 127 u8 iocmd_idx = iocmd.index; 128 129 r8712_fw_cmd_data(pAdapter, &value, 0); 130 msleep(100); 131 cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx; 132 return r8712_fw_cmd(pAdapter, cmd32); 133} 134 135/* offset : 0X800~0XFFF */ 136u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset) 137{ 138 u8 shift = offset & 0x0003; /* 4 byte access */ 139 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */ 140 u32 bb_val = 0; 141 struct IOCMD_STRUCT iocmd; 142 143 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 144 iocmd.value = bb_addr; 145 iocmd.index = IOCMD_BB_READ_IDX; 146 bb_val = fw_iocmd_read(pAdapter, iocmd); 147 if (shift != 0) { 148 u32 bb_val2 = 0; 149 bb_val >>= (shift * 8); 150 iocmd.value += 4; 151 bb_val2 = fw_iocmd_read(pAdapter, iocmd); 152 bb_val2 <<= ((4 - shift) * 8); 153 bb_val |= bb_val2; 154 } 155 return bb_val; 156} 157 158/* offset : 0X800~0XFFF */ 159u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value) 160{ 161 u8 shift = offset & 0x0003; /* 4 byte access */ 162 u16 bb_addr = offset & 0x0FFC; /* 4 byte access */ 163 struct IOCMD_STRUCT iocmd; 164 165 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 166 iocmd.value = bb_addr; 167 iocmd.index = IOCMD_BB_WRITE_IDX; 168 if (shift != 0) { 169 u32 oldValue = 0; 170 u32 newValue = value; 171 172 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value); 173 oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8)); 174 value = oldValue | (newValue << (shift * 8)); 175 if (fw_iocmd_write(pAdapter, iocmd, value) == false) 176 return false; 177 iocmd.value += 4; 178 oldValue = r8712_bb_reg_read(pAdapter, iocmd.value); 179 oldValue &= (0xFFFFFFFF << (shift * 8)); 180 value = oldValue | (newValue >> ((4 - shift) * 8)); 181 } 182 return fw_iocmd_write(pAdapter, iocmd, value); 183} 184 185/* offset : 0x00 ~ 0xFF */ 186u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset) 187{ 188 u16 rf_addr = (path << 8) | offset; 189 struct IOCMD_STRUCT iocmd; 190 191 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 192 iocmd.value = rf_addr; 193 iocmd.index = IOCMD_RF_READ_IDX; 194 return fw_iocmd_read(pAdapter, iocmd); 195} 196 197u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value) 198{ 199 u16 rf_addr = (path << 8) | offset; 200 struct IOCMD_STRUCT iocmd; 201 202 iocmd.cmdclass = IOCMD_CLASS_BB_RF; 203 iocmd.value = rf_addr; 204 iocmd.index = IOCMD_RF_WRIT_IDX; 205 return fw_iocmd_write(pAdapter, iocmd, value); 206} 207 208static u32 bitshift(u32 bitmask) 209{ 210 u32 i; 211 212 for (i = 0; i <= 31; i++) 213 if (((bitmask>>i) & 0x1) == 1) 214 break; 215 return i; 216} 217 218static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask) 219{ 220 u32 org_value, bit_shift, new_value; 221 222 org_value = r8712_bb_reg_read(pAdapter, offset); 223 bit_shift = bitshift(bitmask); 224 new_value = (org_value & bitmask) >> bit_shift; 225 return new_value; 226} 227 228static u8 set_bb_reg(struct _adapter *pAdapter, 229 u16 offset, 230 u32 bitmask, 231 u32 value) 232{ 233 u32 org_value, bit_shift, new_value; 234 235 if (bitmask != bMaskDWord) { 236 org_value = r8712_bb_reg_read(pAdapter, offset); 237 bit_shift = bitshift(bitmask); 238 new_value = ((org_value & (~bitmask)) | (value << bit_shift)); 239 } else 240 new_value = value; 241 return r8712_bb_reg_write(pAdapter, offset, new_value); 242} 243 244static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, 245 u32 bitmask) 246{ 247 u32 org_value, bit_shift, new_value; 248 249 org_value = r8712_rf_reg_read(pAdapter, path, offset); 250 bit_shift = bitshift(bitmask); 251 new_value = (org_value & bitmask) >> bit_shift; 252 return new_value; 253} 254 255static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask, 256 u32 value) 257{ 258 u32 org_value, bit_shift, new_value; 259 260 if (bitmask != bMaskDWord) { 261 org_value = r8712_rf_reg_read(pAdapter, path, offset); 262 bit_shift = bitshift(bitmask); 263 new_value = ((org_value & (~bitmask)) | (value << bit_shift)); 264 } else 265 new_value = value; 266 return r8712_rf_reg_write(pAdapter, path, offset, new_value); 267} 268 269/* 270 * SetChannel 271 * Description 272 * Use H2C command to change channel, 273 * not only modify rf register, but also other setting need to be done. 274 */ 275void r8712_SetChannel(struct _adapter *pAdapter) 276{ 277 struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv; 278 struct cmd_obj *pcmd = NULL; 279 struct SetChannel_parm *pparm = NULL; 280 u16 code = GEN_CMD_CODE(_SetChannel); 281 282 pcmd = kmalloc(sizeof(*pcmd), GFP_ATOMIC); 283 if (pcmd == NULL) 284 return; 285 pparm = kmalloc(sizeof(*pparm), GFP_ATOMIC); 286 if (pparm == NULL) { 287 kfree(pcmd); 288 return; 289 } 290 pparm->curr_ch = pAdapter->mppriv.curr_ch; 291 init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code); 292 r8712_enqueue_cmd(pcmdpriv, pcmd); 293} 294 295static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower) 296{ 297 u16 TxAGC = 0; 298 299 TxAGC = TxPower; 300 set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); 301} 302 303static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower) 304{ 305 u32 TxAGC = 0; 306 307 TxAGC |= ((TxPower<<24)|(TxPower<<16)|(TxPower<<8)|TxPower); 308 set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC); 309 set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC); 310 set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC); 311 set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC); 312 set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC); 313 set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC); 314} 315 316void r8712_SetTxPower(struct _adapter *pAdapter) 317{ 318 u8 TxPower = pAdapter->mppriv.curr_txpoweridx; 319 SetCCKTxPower(pAdapter, TxPower); 320 SetOFDMTxPower(pAdapter, TxPower); 321} 322 323void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset) 324{ 325 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC; 326 327 TxAGCOffset_B = (ulTxAGCOffset&0x000000ff); 328 TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8); 329 TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16); 330 tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B); 331 set_bb_reg(pAdapter, rFPGA0_TxGainStage, 332 (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC); 333} 334 335void r8712_SetDataRate(struct _adapter *pAdapter) 336{ 337 u8 path = RF_PATH_A; 338 u8 offset = RF_SYN_G2; 339 u32 value; 340 341 value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200; 342 r8712_rf_reg_write(pAdapter, path, offset, value); 343} 344 345void r8712_SwitchBandwidth(struct _adapter *pAdapter) 346{ 347 /* 3 1.Set MAC register : BWOPMODE bit2:1 20MhzBW */ 348 u8 regBwOpMode = 0; 349 u8 Bandwidth = pAdapter->mppriv.curr_bandwidth; 350 351 regBwOpMode = r8712_read8(pAdapter, 0x10250203); 352 if (Bandwidth == HT_CHANNEL_WIDTH_20) 353 regBwOpMode |= BIT(2); 354 else 355 regBwOpMode &= ~(BIT(2)); 356 r8712_write8(pAdapter, 0x10250203, regBwOpMode); 357 /* 3 2.Set PHY related register */ 358 switch (Bandwidth) { 359 /* 20 MHz channel*/ 360 case HT_CHANNEL_WIDTH_20: 361 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0); 362 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0); 363 /* Use PHY_REG.txt default value. Do not need to change. 364 * Correct the tx power for CCK rate in 40M. 365 * It is set in Tx descriptor for 8192x series 366 */ 367 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58); 368 break; 369 /* 40 MHz channel*/ 370 case HT_CHANNEL_WIDTH_40: 371 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1); 372 set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1); 373 /* Use PHY_REG.txt default value. Do not need to change. 374 * Correct the tx power for CCK rate in 40M. 375 * Set Control channel to upper or lower. These settings are 376 * required only for 40MHz */ 377 set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand, 378 (HAL_PRIME_CHNL_OFFSET_DONT_CARE>>1)); 379 set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00, 380 HAL_PRIME_CHNL_OFFSET_DONT_CARE); 381 set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18); 382 break; 383 default: 384 break; 385 } 386 387 /* 3 3.Set RF related register */ 388 switch (Bandwidth) { 389 case HT_CHANNEL_WIDTH_20: 390 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW, 391 BIT(10) | BIT(11), 0x01); 392 break; 393 case HT_CHANNEL_WIDTH_40: 394 set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW, 395 BIT(10) | BIT(11), 0x00); 396 break; 397 default: 398 break; 399 } 400} 401/*------------------------------Define structure----------------------------*/ 402struct R_ANTENNA_SELECT_OFDM { 403 u32 r_tx_antenna:4; 404 u32 r_ant_l:4; 405 u32 r_ant_non_ht:4; 406 u32 r_ant_ht1:4; 407 u32 r_ant_ht2:4; 408 u32 r_ant_ht_s1:4; 409 u32 r_ant_non_ht_s1:4; 410 u32 OFDM_TXSC:2; 411 u32 Reserved:2; 412}; 413 414struct R_ANTENNA_SELECT_CCK { 415 u8 r_cckrx_enable_2:2; 416 u8 r_cckrx_enable:2; 417 u8 r_ccktx_enable:4; 418}; 419 420void r8712_SwitchAntenna(struct _adapter *pAdapter) 421{ 422 u32 ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0; 423 u8 ofdm_rx_ant_sel_val = 0; 424 u8 cck_ant_select_val = 0; 425 u32 cck_ant_sel_val = 0; 426 struct R_ANTENNA_SELECT_CCK *p_cck_txrx; 427 428 p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val; 429 430 switch (pAdapter->mppriv.antenna_tx) { 431 case ANTENNA_A: 432 /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/ 433 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); 434 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1); 435 ofdm_tx_en_val = 0x3; 436 ofdm_tx_ant_sel_val = 0x11111111;/* Power save */ 437 p_cck_txrx->r_ccktx_enable = 0x8; 438 break; 439 case ANTENNA_B: 440 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); 441 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); 442 ofdm_tx_en_val = 0x3; 443 ofdm_tx_ant_sel_val = 0x22222222;/* Power save */ 444 p_cck_txrx->r_ccktx_enable = 0x4; 445 break; 446 case ANTENNA_AB: /* For 8192S */ 447 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); 448 set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); 449 ofdm_tx_en_val = 0x3; 450 ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */ 451 p_cck_txrx->r_ccktx_enable = 0xC; 452 break; 453 default: 454 break; 455 } 456 /*OFDM Tx*/ 457 set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val); 458 /*OFDM Tx*/ 459 set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val); 460 switch (pAdapter->mppriv.antenna_rx) { 461 case ANTENNA_A: 462 ofdm_rx_ant_sel_val = 0x1; /* A */ 463 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */ 464 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */ 465 break; 466 case ANTENNA_B: 467 ofdm_rx_ant_sel_val = 0x2; /* B */ 468 p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */ 469 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */ 470 break; 471 case ANTENNA_AB: 472 ofdm_rx_ant_sel_val = 0x3; /* AB */ 473 p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */ 474 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */ 475 break; 476 default: 477 break; 478 } 479 /*OFDM Rx*/ 480 set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, 481 ofdm_rx_ant_sel_val); 482 /*OFDM Rx*/ 483 set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, 484 ofdm_rx_ant_sel_val); 485 486 cck_ant_sel_val = cck_ant_select_val; 487 /*CCK TxRx*/ 488 set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val); 489} 490 491void r8712_SetCrystalCap(struct _adapter *pAdapter) 492{ 493 set_bb_reg(pAdapter, rFPGA0_AnalogParameter1, bXtalCap, 494 pAdapter->mppriv.curr_crystalcap); 495} 496 497static void TriggerRFThermalMeter(struct _adapter *pAdapter) 498{ 499 /* 0x24: RF Reg[6:5] */ 500 set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); 501} 502 503static u32 ReadRFThermalMeter(struct _adapter *pAdapter) 504{ 505 /* 0x24: RF Reg[4:0] */ 506 return get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); 507} 508 509void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value) 510{ 511 TriggerRFThermalMeter(pAdapter); 512 msleep(1000); 513 *value = ReadRFThermalMeter(pAdapter); 514} 515 516void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart) 517{ 518 if (bStart) { /* Start Single Carrier. */ 519 /* 1. if OFDM block on? */ 520 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) 521 /*set OFDM block on*/ 522 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); 523 /* 2. set CCK test mode off, set to CCK normal mode */ 524 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); 525 /* 3. turn on scramble setting */ 526 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 527 /* 4. Turn On Single Carrier Tx and off the other test modes. */ 528 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 529 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable); 530 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 531 } else { /* Stop Single Carrier.*/ 532 /* Turn off all test modes.*/ 533 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 534 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, 535 bDisable); 536 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 537 msleep(20); 538 /*BB Reset*/ 539 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 540 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 541 } 542} 543 544void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart) 545{ 546 u8 rfPath = pAdapter->mppriv.curr_rfpath; 547 switch (pAdapter->mppriv.antenna_tx) { 548 case ANTENNA_B: 549 rfPath = RF_PATH_B; 550 break; 551 case ANTENNA_A: 552 default: 553 rfPath = RF_PATH_A; 554 break; 555 } 556 if (bStart) { /* Start Single Tone.*/ 557 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable); 558 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable); 559 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask, 560 0xd4000); 561 msleep(100); 562 /* PAD all on.*/ 563 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f); 564 msleep(100); 565 } else { /* Stop Single Tone.*/ 566 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); 567 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); 568 set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask, 569 0x54000); 570 msleep(100); 571 /* PAD all on.*/ 572 set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000); 573 msleep(100); 574 } 575} 576 577void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart) 578{ 579 if (bStart) { /* Start Carrier Suppression.*/ 580 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) { 581 /* 1. if CCK block on? */ 582 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { 583 /*set CCK block on*/ 584 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 585 bEnable); 586 } 587 /* Turn Off All Test Mode */ 588 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, 589 bDisable); 590 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, 591 bDisable); 592 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, 593 bDisable); 594 /*transmit mode*/ 595 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); 596 /*turn off scramble setting*/ 597 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 598 bDisable); 599 /*Set CCK Tx Test Rate*/ 600 /*Set FTxRate to 1Mbps*/ 601 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); 602 } 603 } else { /* Stop Carrier Suppression. */ 604 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) { 605 /*normal mode*/ 606 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); 607 /*turn on scramble setting*/ 608 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 609 bEnable); 610 /*BB Reset*/ 611 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 612 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 613 } 614 } 615} 616 617static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart) 618{ 619 u32 cckrate; 620 621 if (bStart) { 622 /* 1. if CCK block on? */ 623 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { 624 /*set CCK block on*/ 625 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); 626 } 627 /* Turn Off All Test Mode */ 628 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 629 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); 630 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 631 /*Set CCK Tx Test Rate*/ 632 cckrate = pAdapter->mppriv.curr_rateidx; 633 set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); 634 /*transmit mode*/ 635 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); 636 /*turn on scramble setting*/ 637 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 638 } else { 639 /*normal mode*/ 640 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); 641 /*turn on scramble setting*/ 642 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 643 /*BB Reset*/ 644 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 645 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 646 } 647} /* mpt_StartCckContTx */ 648 649static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart) 650{ 651 if (bStart) { 652 /* 1. if OFDM block on? */ 653 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) { 654 /*set OFDM block on*/ 655 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); 656 } 657 /* 2. set CCK test mode off, set to CCK normal mode*/ 658 set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); 659 /* 3. turn on scramble setting */ 660 set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable); 661 /* 4. Turn On Continue Tx and turn off the other test modes.*/ 662 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable); 663 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); 664 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 665 } else { 666 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); 667 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, 668 bDisable); 669 set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); 670 msleep(20); 671 /*BB Reset*/ 672 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); 673 set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); 674 } 675} /* mpt_StartOfdmContTx */ 676 677void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart) 678{ 679 /* ADC turn off [bit24-21] adc port0 ~ port1 */ 680 if (bStart) { 681 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA, 682 r8712_bb_reg_read(pAdapter, 683 rRx_Wait_CCCA) & 0xFE1FFFFF); 684 msleep(100); 685 } 686 if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) 687 SetCCKContinuousTx(pAdapter, bStart); 688 else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) && 689 (pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15)) 690 SetOFDMContinuousTx(pAdapter, bStart); 691 /* ADC turn on [bit24-21] adc port0 ~ port1 */ 692 if (!bStart) 693 r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA, 694 r8712_bb_reg_read(pAdapter, 695 rRx_Wait_CCCA) | 0x01E00000); 696} 697 698void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter) 699{ 700 u32 i, phyrx_set = 0; 701 702 for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) { 703 phyrx_set = 0; 704 phyrx_set |= (i << 28); /*select*/ 705 phyrx_set |= 0x08000000; /* set counter to zero*/ 706 r8712_write32(pAdapter, RXERR_RPT, phyrx_set); 707 } 708} 709 710static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit) 711{ 712 /*selection*/ 713 u32 phyrx_set = 0, count = 0; 714 u32 SelectBit; 715 716 SelectBit = selbit << 28; 717 phyrx_set |= (SelectBit & 0xF0000000); 718 r8712_write32(pAdapter, RXERR_RPT, phyrx_set); 719 /*Read packet count*/ 720 count = r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount; 721 return count; 722} 723 724u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter) 725{ 726 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; 727 728 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT); 729 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT); 730 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT); 731 return OFDM_cnt + CCK_cnt + HT_cnt; 732} 733 734u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter) 735{ 736 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; 737 738 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT); 739 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT); 740 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT); 741 return OFDM_cnt + CCK_cnt + HT_cnt; 742} 743