rtl871x_mp_phy_regdef.h revision 2865d42c78a9121caad52cb02d1fbb7f5cdbc4ef
1/***************************************************************************** 2 * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. 3 * 4 * Module: __INC_HAL8192SPHYREG_H 5 * 6 * 7 * Note: 1. Define PMAC/BB register map 8 * 2. Define RF register map 9 * 3. PMAC/BB register bit mask. 10 * 4. RF reg bit mask. 11 * 5. Other BB/RF relative definition. 12 * 13 * 14 * Export: Constants, macro, functions(API), global variables(None). 15 * 16 * Abbrev: 17 * 18 * History: 19 * Data Who Remark 20 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. 21 * 2. Reorganize code architecture. 22 * 09/25/2008 MH 1. Add RL6052 register definition 23 * 24 *****************************************************************************/ 25#ifndef __RTL871X_MP_PHY_REGDEF_H 26#define __RTL871X_MP_PHY_REGDEF_H 27 28 29/*--------------------------Define Parameters-------------------------------*/ 30 31/*============================================================ 32 * 8192S Regsiter offset definition 33 *============================================================ 34 * 35 * 36 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 37 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 38 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 39 * 3. RF register 0x00-2E 40 * 4. Bit Mask for BB/RF register 41 * 5. Other defintion for BB/RF R/W 42 * 43 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 44 * 1. Page1(0x100) 45 */ 46#define rPMAC_Reset 0x100 47#define rPMAC_TxStart 0x104 48#define rPMAC_TxLegacySIG 0x108 49#define rPMAC_TxHTSIG1 0x10c 50#define rPMAC_TxHTSIG2 0x110 51#define rPMAC_PHYDebug 0x114 52#define rPMAC_TxPacketNum 0x118 53#define rPMAC_TxIdle 0x11c 54#define rPMAC_TxMACHeader0 0x120 55#define rPMAC_TxMACHeader1 0x124 56#define rPMAC_TxMACHeader2 0x128 57#define rPMAC_TxMACHeader3 0x12c 58#define rPMAC_TxMACHeader4 0x130 59#define rPMAC_TxMACHeader5 0x134 60#define rPMAC_TxDataType 0x138 61#define rPMAC_TxRandomSeed 0x13c 62#define rPMAC_CCKPLCPPreamble 0x140 63#define rPMAC_CCKPLCPHeader 0x144 64#define rPMAC_CCKCRC16 0x148 65#define rPMAC_OFDMRxCRC32OK 0x170 66#define rPMAC_OFDMRxCRC32Er 0x174 67#define rPMAC_OFDMRxParityEr 0x178 68#define rPMAC_OFDMRxCRC8Er 0x17c 69#define rPMAC_CCKCRxRC16Er 0x180 70#define rPMAC_CCKCRxRC32Er 0x184 71#define rPMAC_CCKCRxRC32OK 0x188 72#define rPMAC_TxStatus 0x18c 73 74/* 75 * 2. Page2(0x200) 76 * 77 * The following two definition are only used for USB interface. 78 *#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. 79 *#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. 80 * 81 * 82 * 3. Page8(0x800) 83 */ 84#define rFPGA0_RFMOD 0x800 /*RF mode & CCK TxSC RF 85 * BW Setting?? */ 86#define rFPGA0_TxInfo 0x804 /* Status report?? */ 87#define rFPGA0_PSDFunction 0x808 88#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 89#define rFPGA0_RFTiming1 0x810 /* Useless now */ 90#define rFPGA0_RFTiming2 0x814 91#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 92#define rFPGA0_XA_HSSIParameter2 0x824 93#define rFPGA0_XB_HSSIParameter1 0x828 94#define rFPGA0_XB_HSSIParameter2 0x82c 95#define rFPGA0_XC_HSSIParameter1 0x830 96#define rFPGA0_XC_HSSIParameter2 0x834 97#define rFPGA0_XD_HSSIParameter1 0x838 98#define rFPGA0_XD_HSSIParameter2 0x83c 99#define rFPGA0_XA_LSSIParameter 0x840 100#define rFPGA0_XB_LSSIParameter 0x844 101#define rFPGA0_XC_LSSIParameter 0x848 102#define rFPGA0_XD_LSSIParameter 0x84c 103 104#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 105#define rFPGA0_RFSleepUpParameter 0x854 106 107#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 108#define rFPGA0_XCD_SwitchControl 0x85c 109 110#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 111#define rFPGA0_XB_RFInterfaceOE 0x864 112#define rFPGA0_XC_RFInterfaceOE 0x868 113#define rFPGA0_XD_RFInterfaceOE 0x86c 114#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Ctrl */ 115#define rFPGA0_XCD_RFInterfaceSW 0x874 116 117#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 118#define rFPGA0_XCD_RFParameter 0x87c 119 120#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting 121 * RF-R/W protection 122 * for parameter4?? */ 123#define rFPGA0_AnalogParameter2 0x884 124#define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 125#define rFPGA0_AnalogParameter4 0x88c 126 127#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 128#define rFPGA0_XB_LSSIReadBack 0x8a4 129#define rFPGA0_XC_LSSIReadBack 0x8a8 130#define rFPGA0_XD_LSSIReadBack 0x8ac 131 132#define rFPGA0_PSDReport 0x8b4 /* Useless now */ 133#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ 134#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 135 136/* 137 * 4. Page9(0x900) 138 */ 139#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ 140 141#define rFPGA1_TxBlock 0x904 /* Useless now */ 142#define rFPGA1_DebugSelect 0x908 /* Useless now */ 143#define rFPGA1_TxInfo 0x90c /* Useless now */ 144 145/* 146 * 5. PageA(0xA00) 147 * 148 * Set Control channel to upper or lower. 149 * These settings are required only for 40MHz */ 150#define rCCK0_System 0xa00 151 152#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ 153#define rCCK0_CCA 0xa08 /* Disable init gain now */ 154 155#define rCCK0_RxAGC1 0xa0c 156/* AGC default value, saturation level 157 * Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. 158 * Not the same as 90 series */ 159#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 160 161#define rCCK0_RxHP 0xa14 162 163#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel 164 * estimation threshold */ 165#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 166 167#define rCCK0_TxFilter1 0xa20 168#define rCCK0_TxFilter2 0xa24 169#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 170#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f 171 * channel report */ 172#define rCCK0_TRSSIReport 0xa50 173#define rCCK0_RxReport 0xa54 /* 0xa57 */ 174#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 175#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 176 177/* 178 * 6. PageC(0xC00) 179 */ 180#define rOFDM0_LSTF 0xc00 181#define rOFDM0_TRxPathEnable 0xc04 182#define rOFDM0_TRMuxPar 0xc08 183#define rOFDM0_TRSWIsolation 0xc0c 184 185/*RxIQ DC offset, Rx digital filter, DC notch filter */ 186#define rOFDM0_XARxAFE 0xc10 187#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 188#define rOFDM0_XBRxAFE 0xc18 189#define rOFDM0_XBRxIQImbalance 0xc1c 190#define rOFDM0_XCRxAFE 0xc20 191#define rOFDM0_XCRxIQImbalance 0xc24 192#define rOFDM0_XDRxAFE 0xc28 193#define rOFDM0_XDRxIQImbalance 0xc2c 194 195#define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD DM tune 196 * init gain */ 197#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 198#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 199#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & 200 * Short-GI */ 201 202#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 203#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 204#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 205#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 206 207#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 208#define rOFDM0_XAAGCCore2 0xc54 209#define rOFDM0_XBAGCCore1 0xc58 210#define rOFDM0_XBAGCCore2 0xc5c 211#define rOFDM0_XCAGCCore1 0xc60 212#define rOFDM0_XCAGCCore2 0xc64 213#define rOFDM0_XDAGCCore1 0xc68 214#define rOFDM0_XDAGCCore2 0xc6c 215#define rOFDM0_AGCParameter1 0xc70 216#define rOFDM0_AGCParameter2 0xc74 217#define rOFDM0_AGCRSSITable 0xc78 218#define rOFDM0_HTSTFAGC 0xc7c 219 220#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 221#define rOFDM0_XATxAFE 0xc84 222#define rOFDM0_XBTxIQImbalance 0xc88 223#define rOFDM0_XBTxAFE 0xc8c 224#define rOFDM0_XCTxIQImbalance 0xc90 225#define rOFDM0_XCTxAFE 0xc94 226#define rOFDM0_XDTxIQImbalance 0xc98 227#define rOFDM0_XDTxAFE 0xc9c 228 229#define rOFDM0_RxHPParameter 0xce0 230#define rOFDM0_TxPseudoNoiseWgt 0xce4 231#define rOFDM0_FrameSync 0xcf0 232#define rOFDM0_DFSReport 0xcf4 233#define rOFDM0_TxCoeff1 0xca4 234#define rOFDM0_TxCoeff2 0xca8 235#define rOFDM0_TxCoeff3 0xcac 236#define rOFDM0_TxCoeff4 0xcb0 237#define rOFDM0_TxCoeff5 0xcb4 238#define rOFDM0_TxCoeff6 0xcb8 239 240/* 241 * 7. PageD(0xD00) 242 */ 243#define rOFDM1_LSTF 0xd00 244#define rOFDM1_TRxPathEnable 0xd04 245 246#define rOFDM1_CFO 0xd08 /* No setting now */ 247#define rOFDM1_CSI1 0xd10 248#define rOFDM1_SBD 0xd14 249#define rOFDM1_CSI2 0xd18 250#define rOFDM1_CFOTracking 0xd2c 251#define rOFDM1_TRxMesaure1 0xd34 252#define rOFDM1_IntfDet 0xd3c 253#define rOFDM1_PseudoNoiseStateAB 0xd50 254#define rOFDM1_PseudoNoiseStateCD 0xd54 255#define rOFDM1_RxPseudoNoiseWgt 0xd58 256 257#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 258#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 259#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 260#define rOFDM_ShortCFOAB 0xdac /* No setting now */ 261#define rOFDM_ShortCFOCD 0xdb0 262#define rOFDM_LongCFOAB 0xdb4 263#define rOFDM_LongCFOCD 0xdb8 264#define rOFDM_TailCFOAB 0xdbc 265#define rOFDM_TailCFOCD 0xdc0 266#define rOFDM_PWMeasure1 0xdc4 267#define rOFDM_PWMeasure2 0xdc8 268#define rOFDM_BWReport 0xdcc 269#define rOFDM_AGCReport 0xdd0 270#define rOFDM_RxSNR 0xdd4 271#define rOFDM_RxEVMCSI 0xdd8 272#define rOFDM_SIGReport 0xddc 273 274/* 275 * 8. PageE(0xE00) 276 */ 277#define rTxAGC_Rate18_06 0xe00 278#define rTxAGC_Rate54_24 0xe04 279#define rTxAGC_CCK_Mcs32 0xe08 280#define rTxAGC_Mcs03_Mcs00 0xe10 281#define rTxAGC_Mcs07_Mcs04 0xe14 282#define rTxAGC_Mcs11_Mcs08 0xe18 283#define rTxAGC_Mcs15_Mcs12 0xe1c 284 285/* Analog- control in RX_WAIT_CCA : REG: EE0 286 * [Analog- Power & Control Register] */ 287#define rRx_Wait_CCCA 0xe70 288#define rAnapar_Ctrl_BB 0xee0 289 290/* 291 * 7. RF Register 0x00-0x2E (RF 8256) 292 * RF-0222D 0x00-3F 293 * 294 * Zebra1 295 */ 296#define rZebra1_HSSIEnable 0x0 /* Useless now */ 297#define rZebra1_TRxEnable1 0x1 298#define rZebra1_TRxEnable2 0x2 299#define rZebra1_AGC 0x4 300#define rZebra1_ChargePump 0x5 301#define rZebra1_Channel 0x7 /* RF channel switch */ 302#define rZebra1_TxGain 0x8 /* Useless now */ 303#define rZebra1_TxLPF 0x9 304#define rZebra1_RxLPF 0xb 305#define rZebra1_RxHPFCorner 0xc 306 307/* Zebra4 */ 308#define rGlobalCtrl 0 /* Useless now */ 309#define rRTL8256_TxLPF 19 310#define rRTL8256_RxLPF 11 311 312/* RTL8258 */ 313#define rRTL8258_TxLPF 0x11 /* Useless now */ 314#define rRTL8258_RxLPF 0x13 315#define rRTL8258_RSSILPF 0xa 316 317/* RL6052 Register definition */ 318#define RF_AC 0x00 319#define RF_IQADJ_G1 0x01 320#define RF_IQADJ_G2 0x02 321#define RF_POW_TRSW 0x05 322 323#define RF_GAIN_RX 0x06 324#define RF_GAIN_TX 0x07 325 326#define RF_TXM_IDAC 0x08 327#define RF_BS_IQGEN 0x0F 328 329#define RF_MODE1 0x10 330#define RF_MODE2 0x11 331 332#define RF_RX_AGC_HP 0x12 333#define RF_TX_AGC 0x13 334#define RF_BIAS 0x14 335#define RF_IPA 0x15 336#define RF_POW_ABILITY 0x17 337#define RF_MODE_AG 0x18 338#define rRfChannel 0x18 /* RF channel and BW switch */ 339#define RF_CHNLBW 0x18 /* RF channel and BW switch */ 340#define RF_TOP 0x19 341#define RF_RX_G1 0x1A 342#define RF_RX_G2 0x1B 343#define RF_RX_BB2 0x1C 344#define RF_RX_BB1 0x1D 345 346#define RF_RCK1 0x1E 347#define RF_RCK2 0x1F 348 349#define RF_TX_G1 0x20 350#define RF_TX_G2 0x21 351#define RF_TX_G3 0x22 352 353#define RF_TX_BB1 0x23 354#define RF_T_METER 0x24 355 356#define RF_SYN_G1 0x25 /* RF TX Power control */ 357#define RF_SYN_G2 0x26 /* RF TX Power control */ 358#define RF_SYN_G3 0x27 /* RF TX Power control */ 359#define RF_SYN_G4 0x28 /* RF TX Power control */ 360#define RF_SYN_G5 0x29 /* RF TX Power control */ 361#define RF_SYN_G6 0x2A /* RF TX Power control */ 362#define RF_SYN_G7 0x2B /* RF TX Power control */ 363#define RF_SYN_G8 0x2C /* RF TX Power control */ 364 365#define RF_RCK_OS 0x30 /* RF TX PA control */ 366 367#define RF_TXPA_G1 0x31 /* RF TX PA control */ 368#define RF_TXPA_G2 0x32 /* RF TX PA control */ 369#define RF_TXPA_G3 0x33 /* RF TX PA control */ 370 371/* 372 * Bit Mask 373 * 374 * 1. Page1(0x100) */ 375#define bBBResetB 0x100 /* Useless now? */ 376#define bGlobalResetB 0x200 377#define bOFDMTxStart 0x4 378#define bCCKTxStart 0x8 379#define bCRC32Debug 0x100 380#define bPMACLoopback 0x10 381#define bTxLSIG 0xffffff 382#define bOFDMTxRate 0xf 383#define bOFDMTxReserved 0x10 384#define bOFDMTxLength 0x1ffe0 385#define bOFDMTxParity 0x20000 386#define bTxHTSIG1 0xffffff 387#define bTxHTMCSRate 0x7f 388#define bTxHTBW 0x80 389#define bTxHTLength 0xffff00 390#define bTxHTSIG2 0xffffff 391#define bTxHTSmoothing 0x1 392#define bTxHTSounding 0x2 393#define bTxHTReserved 0x4 394#define bTxHTAggreation 0x8 395#define bTxHTSTBC 0x30 396#define bTxHTAdvanceCoding 0x40 397#define bTxHTShortGI 0x80 398#define bTxHTNumberHT_LTF 0x300 399#define bTxHTCRC8 0x3fc00 400#define bCounterReset 0x10000 401#define bNumOfOFDMTx 0xffff 402#define bNumOfCCKTx 0xffff0000 403#define bTxIdleInterval 0xffff 404#define bOFDMService 0xffff0000 405#define bTxMACHeader 0xffffffff 406#define bTxDataInit 0xff 407#define bTxHTMode 0x100 408#define bTxDataType 0x30000 409#define bTxRandomSeed 0xffffffff 410#define bCCKTxPreamble 0x1 411#define bCCKTxSFD 0xffff0000 412#define bCCKTxSIG 0xff 413#define bCCKTxService 0xff00 414#define bCCKLengthExt 0x8000 415#define bCCKTxLength 0xffff0000 416#define bCCKTxCRC16 0xffff 417#define bCCKTxStatus 0x1 418#define bOFDMTxStatus 0x2 419#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && \ 420 (_Offset <= 0xfff)) 421 422/* 2. Page8(0x800) */ 423#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 424#define bJapanMode 0x2 425#define bCCKTxSC 0x30 426#define bCCKEn 0x1000000 427#define bOFDMEn 0x2000000 428 429#define bOFDMRxADCPhase 0x10000 /* Useless now */ 430#define bOFDMTxDACPhase 0x40000 431#define bXATxAGC 0x3f 432#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 433#define bXCTxAGC 0xf000 434#define bXDTxAGC 0xf0000 435 436#define bPAStart 0xf0000000 /* Useless now */ 437#define bTRStart 0x00f00000 438#define bRFStart 0x0000f000 439#define bBBStart 0x000000f0 440#define bBBCCKStart 0x0000000f 441#define bPAEnd 0xf /* Reg0x814 */ 442#define bTREnd 0x0f000000 443#define bRFEnd 0x000f0000 444#define bCCAMask 0x000000f0 /* T2R */ 445#define bR2RCCAMask 0x00000f00 446#define bHSSI_R2TDelay 0xf8000000 447#define bHSSI_T2RDelay 0xf80000 448#define bContTxHSSI 0x400 /* change gain at continue Tx */ 449#define bIGFromCCK 0x200 450#define bAGCAddress 0x3f 451#define bRxHPTx 0x7000 452#define bRxHPT2R 0x38000 453#define bRxHPCCKIni 0xc0000 454#define bAGCTxCode 0xc00000 455#define bAGCRxCode 0x300000 456#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParm1 */ 457#define b3WireAddressLength 0x400 458#define b3WireRFPowerDown 0x1 /* Useless now */ 459#define b5GPAPEPolarity 0x40000000 460#define b2GPAPEPolarity 0x80000000 461#define bRFSW_TxDefaultAnt 0x3 462#define bRFSW_TxOptionAnt 0x30 463#define bRFSW_RxDefaultAnt 0x300 464#define bRFSW_RxOptionAnt 0x3000 465#define bRFSI_3WireData 0x1 466#define bRFSI_3WireClock 0x2 467#define bRFSI_3WireLoad 0x4 468#define bRFSI_3WireRW 0x8 469#define bRFSI_3Wire 0xf 470#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 471#define bRFSI_TRSW 0x20 /* Useless now */ 472#define bRFSI_TRSWB 0x40 473#define bRFSI_ANTSW 0x100 474#define bRFSI_ANTSWB 0x200 475#define bRFSI_PAPE 0x400 476#define bRFSI_PAPE5G 0x800 477#define bBandSelect 0x1 478#define bHTSIG2_GI 0x80 479#define bHTSIG2_Smoothing 0x01 480#define bHTSIG2_Sounding 0x02 481#define bHTSIG2_Aggreaton 0x08 482#define bHTSIG2_STBC 0x30 483#define bHTSIG2_AdvCoding 0x40 484#define bHTSIG2_NumOfHTLTF 0x300 485#define bHTSIG2_CRC8 0x3fc 486#define bHTSIG1_MCS 0x7f 487#define bHTSIG1_BandWidth 0x80 488#define bHTSIG1_HTLength 0xffff 489#define bLSIG_Rate 0xf 490#define bLSIG_Reserved 0x10 491#define bLSIG_Length 0x1fffe 492#define bLSIG_Parity 0x20 493#define bCCKRxPhase 0x4 494#define bLSSIReadAddress 0x7f800000 /* T65 RF */ 495#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 496#define bLSSIReadBackData 0xfffff /* T65 RF */ 497#define bLSSIReadOKFlag 0x1000 /* Useless now */ 498#define bCCKSampleRate 0x8 /*0: 44MHz, 1:88MHz*/ 499#define bRegulator0Standby 0x1 500#define bRegulatorPLLStandby 0x2 501#define bRegulator1Standby 0x4 502#define bPLLPowerUp 0x8 503#define bDPLLPowerUp 0x10 504#define bDA10PowerUp 0x20 505#define bAD7PowerUp 0x200 506#define bDA6PowerUp 0x2000 507#define bXtalPowerUp 0x4000 508#define b40MDClkPowerUP 0x8000 509#define bDA6DebugMode 0x20000 510#define bDA6Swing 0x380000 511 512/* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 513#define bADClkPhase 0x4000000 514 515#define b80MClkDelay 0x18000000 /* Useless */ 516#define bAFEWatchDogEnable 0x20000000 517 518/* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 519#define bXtalCap01 0xc0000000 520#define bXtalCap23 0x3 521#define bXtalCap92x 0x0f000000 522#define bXtalCap 0x0f000000 523#define bIntDifClkEnable 0x400 /* Useless */ 524#define bExtSigClkEnable 0x800 525#define bBandgapMbiasPowerUp 0x10000 526#define bAD11SHGain 0xc0000 527#define bAD11InputRange 0x700000 528#define bAD11OPCurrent 0x3800000 529#define bIPathLoopback 0x4000000 530#define bQPathLoopback 0x8000000 531#define bAFELoopback 0x10000000 532#define bDA10Swing 0x7e0 533#define bDA10Reverse 0x800 534#define bDAClkSource 0x1000 535#define bAD7InputRange 0x6000 536#define bAD7Gain 0x38000 537#define bAD7OutputCMMode 0x40000 538#define bAD7InputCMMode 0x380000 539#define bAD7Current 0xc00000 540#define bRegulatorAdjust 0x7000000 541#define bAD11PowerUpAtTx 0x1 542#define bDA10PSAtTx 0x10 543#define bAD11PowerUpAtRx 0x100 544#define bDA10PSAtRx 0x1000 545#define bCCKRxAGCFormat 0x200 546#define bPSDFFTSamplepPoint 0xc000 547#define bPSDAverageNum 0x3000 548#define bIQPathControl 0xc00 549#define bPSDFreq 0x3ff 550#define bPSDAntennaPath 0x30 551#define bPSDIQSwitch 0x40 552#define bPSDRxTrigger 0x400000 553#define bPSDTxTrigger 0x80000000 554#define bPSDSineToneScale 0x7f000000 555#define bPSDReport 0xffff 556 557/* 3. Page9(0x900) */ 558#define bOFDMTxSC 0x30000000 /* Useless */ 559#define bCCKTxOn 0x1 560#define bOFDMTxOn 0x2 561#define bDebugPage 0xfff /* reset debug page and HWord, LWord */ 562#define bDebugItem 0xff /* reset debug page and LWord */ 563#define bAntL 0x10 564#define bAntNonHT 0x100 565#define bAntHT1 0x1000 566#define bAntHT2 0x10000 567#define bAntHT1S1 0x100000 568#define bAntNonHTS1 0x1000000 569 570/* 4. PageA(0xA00) */ 571#define bCCKBBMode 0x3 /* Useless */ 572#define bCCKTxPowerSaving 0x80 573#define bCCKRxPowerSaving 0x40 574 575#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch*/ 576#define bCCKScramble 0x8 /* Useless */ 577#define bCCKAntDiversity 0x8000 578#define bCCKCarrierRecovery 0x4000 579#define bCCKTxRate 0x3000 580#define bCCKDCCancel 0x0800 581#define bCCKISICancel 0x0400 582#define bCCKMatchFilter 0x0200 583#define bCCKEqualizer 0x0100 584#define bCCKPreambleDetect 0x800000 585#define bCCKFastFalseCCA 0x400000 586#define bCCKChEstStart 0x300000 587#define bCCKCCACount 0x080000 588#define bCCKcs_lim 0x070000 589#define bCCKBistMode 0x80000000 590#define bCCKCCAMask 0x40000000 591#define bCCKTxDACPhase 0x4 592#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 593#define bCCKr_cp_mode0 0x0100 594#define bCCKTxDCOffset 0xf0 595#define bCCKRxDCOffset 0xf 596#define bCCKCCAMode 0xc000 597#define bCCKFalseCS_lim 0x3f00 598#define bCCKCS_ratio 0xc00000 599#define bCCKCorgBit_sel 0x300000 600#define bCCKPD_lim 0x0f0000 601#define bCCKNewCCA 0x80000000 602#define bCCKRxHPofIG 0x8000 603#define bCCKRxIG 0x7f00 604#define bCCKLNAPolarity 0x800000 605#define bCCKRx1stGain 0x7f0000 606#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 607#define bCCKRxAGCSatLevel 0x1f000000 608#define bCCKRxAGCSatCount 0xe0 609#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 610#define bCCKFixedRxAGC 0x8000 611#define bCCKAntennaPolarity 0x2000 612#define bCCKTxFilterType 0x0c00 613#define bCCKRxAGCReportType 0x0300 614#define bCCKRxDAGCEn 0x80000000 615#define bCCKRxDAGCPeriod 0x20000000 616#define bCCKRxDAGCSatLevel 0x1f000000 617#define bCCKTimingRecovery 0x800000 618#define bCCKTxC0 0x3f0000 619#define bCCKTxC1 0x3f000000 620#define bCCKTxC2 0x3f 621#define bCCKTxC3 0x3f00 622#define bCCKTxC4 0x3f0000 623#define bCCKTxC5 0x3f000000 624#define bCCKTxC6 0x3f 625#define bCCKTxC7 0x3f00 626#define bCCKDebugPort 0xff0000 627#define bCCKDACDebug 0x0f000000 628#define bCCKFalseAlarmEnable 0x8000 629#define bCCKFalseAlarmRead 0x4000 630#define bCCKTRSSI 0x7f 631#define bCCKRxAGCReport 0xfe 632#define bCCKRxReport_AntSel 0x80000000 633#define bCCKRxReport_MFOff 0x40000000 634#define bCCKRxRxReport_SQLoss 0x20000000 635#define bCCKRxReport_Pktloss 0x10000000 636#define bCCKRxReport_Lockedbit 0x08000000 637#define bCCKRxReport_RateError 0x04000000 638#define bCCKRxReport_RxRate 0x03000000 639#define bCCKRxFACounterLower 0xff 640#define bCCKRxFACounterUpper 0xff000000 641#define bCCKRxHPAGCStart 0xe000 642#define bCCKRxHPAGCFinal 0x1c00 643#define bCCKRxFalseAlarmEnable 0x8000 644#define bCCKFACounterFreeze 0x4000 645#define bCCKTxPathSel 0x10000000 646#define bCCKDefaultRxPath 0xc000000 647#define bCCKOptionRxPath 0x3000000 648 649/* 5. PageC(0xC00) */ 650#define bNumOfSTF 0x3 /* Useless */ 651#define bShift_L 0xc0 652#define bGI_TH 0xc 653#define bRxPathA 0x1 654#define bRxPathB 0x2 655#define bRxPathC 0x4 656#define bRxPathD 0x8 657#define bTxPathA 0x1 658#define bTxPathB 0x2 659#define bTxPathC 0x4 660#define bTxPathD 0x8 661#define bTRSSIFreq 0x200 662#define bADCBackoff 0x3000 663#define bDFIRBackoff 0xc000 664#define bTRSSILatchPhase 0x10000 665#define bRxIDCOffset 0xff 666#define bRxQDCOffset 0xff00 667#define bRxDFIRMode 0x1800000 668#define bRxDCNFType 0xe000000 669#define bRXIQImb_A 0x3ff 670#define bRXIQImb_B 0xfc00 671#define bRXIQImb_C 0x3f0000 672#define bRXIQImb_D 0xffc00000 673#define bDC_dc_Notch 0x60000 674#define bRxNBINotch 0x1f000000 675#define bPD_TH 0xf 676#define bPD_TH_Opt2 0xc000 677#define bPWED_TH 0x700 678#define bIfMF_Win_L 0x800 679#define bPD_Option 0x1000 680#define bMF_Win_L 0xe000 681#define bBW_Search_L 0x30000 682#define bwin_enh_L 0xc0000 683#define bBW_TH 0x700000 684#define bED_TH2 0x3800000 685#define bBW_option 0x4000000 686#define bRatio_TH 0x18000000 687#define bWindow_L 0xe0000000 688#define bSBD_Option 0x1 689#define bFrame_TH 0x1c 690#define bFS_Option 0x60 691#define bDC_Slope_check 0x80 692#define bFGuard_Counter_DC_L 0xe00 693#define bFrame_Weight_Short 0x7000 694#define bSub_Tune 0xe00000 695#define bFrame_DC_Length 0xe000000 696#define bSBD_start_offset 0x30000000 697#define bFrame_TH_2 0x7 698#define bFrame_GI2_TH 0x38 699#define bGI2_Sync_en 0x40 700#define bSarch_Short_Early 0x300 701#define bSarch_Short_Late 0xc00 702#define bSarch_GI2_Late 0x70000 703#define bCFOAntSum 0x1 704#define bCFOAcc 0x2 705#define bCFOStartOffset 0xc 706#define bCFOLookBack 0x70 707#define bCFOSumWeight 0x80 708#define bDAGCEnable 0x10000 709#define bTXIQImb_A 0x3ff 710#define bTXIQImb_B 0xfc00 711#define bTXIQImb_C 0x3f0000 712#define bTXIQImb_D 0xffc00000 713#define bTxIDCOffset 0xff 714#define bTxQDCOffset 0xff00 715#define bTxDFIRMode 0x10000 716#define bTxPesudoNoiseOn 0x4000000 717#define bTxPesudoNoise_A 0xff 718#define bTxPesudoNoise_B 0xff00 719#define bTxPesudoNoise_C 0xff0000 720#define bTxPesudoNoise_D 0xff000000 721#define bCCADropOption 0x20000 722#define bCCADropThres 0xfff00000 723#define bEDCCA_H 0xf 724#define bEDCCA_L 0xf0 725#define bLambda_ED 0x300 726#define bRxInitialGain 0x7f 727#define bRxAntDivEn 0x80 728#define bRxAGCAddressForLNA 0x7f00 729#define bRxHighPowerFlow 0x8000 730#define bRxAGCFreezeThres 0xc0000 731#define bRxFreezeStep_AGC1 0x300000 732#define bRxFreezeStep_AGC2 0xc00000 733#define bRxFreezeStep_AGC3 0x3000000 734#define bRxFreezeStep_AGC0 0xc000000 735#define bRxRssi_Cmp_En 0x10000000 736#define bRxQuickAGCEn 0x20000000 737#define bRxAGCFreezeThresMode 0x40000000 738#define bRxOverFlowCheckType 0x80000000 739#define bRxAGCShift 0x7f 740#define bTRSW_Tri_Only 0x80 741#define bPowerThres 0x300 742#define bRxAGCEn 0x1 743#define bRxAGCTogetherEn 0x2 744#define bRxAGCMin 0x4 745#define bRxHP_Ini 0x7 746#define bRxHP_TRLNA 0x70 747#define bRxHP_RSSI 0x700 748#define bRxHP_BBP1 0x7000 749#define bRxHP_BBP2 0x70000 750#define bRxHP_BBP3 0x700000 751#define bRSSI_H 0x7f0000 /* the threshold for high power */ 752#define bRSSI_Gen 0x7f000000 /* the threshold for ant divers */ 753#define bRxSettle_TRSW 0x7 754#define bRxSettle_LNA 0x38 755#define bRxSettle_RSSI 0x1c0 756#define bRxSettle_BBP 0xe00 757#define bRxSettle_RxHP 0x7000 758#define bRxSettle_AntSW_RSSI 0x38000 759#define bRxSettle_AntSW 0xc0000 760#define bRxProcessTime_DAGC 0x300000 761#define bRxSettle_HSSI 0x400000 762#define bRxProcessTime_BBPPW 0x800000 763#define bRxAntennaPowerShift 0x3000000 764#define bRSSITableSelect 0xc000000 765#define bRxHP_Final 0x7000000 766#define bRxHTSettle_BBP 0x7 767#define bRxHTSettle_HSSI 0x8 768#define bRxHTSettle_RxHP 0x70 769#define bRxHTSettle_BBPPW 0x80 770#define bRxHTSettle_Idle 0x300 771#define bRxHTSettle_Reserved 0x1c00 772#define bRxHTRxHPEn 0x8000 773#define bRxHTAGCFreezeThres 0x30000 774#define bRxHTAGCTogetherEn 0x40000 775#define bRxHTAGCMin 0x80000 776#define bRxHTAGCEn 0x100000 777#define bRxHTDAGCEn 0x200000 778#define bRxHTRxHP_BBP 0x1c00000 779#define bRxHTRxHP_Final 0xe0000000 780#define bRxPWRatioTH 0x3 781#define bRxPWRatioEn 0x4 782#define bRxMFHold 0x3800 783#define bRxPD_Delay_TH1 0x38 784#define bRxPD_Delay_TH2 0x1c0 785#define bRxPD_DC_COUNT_MAX 0x600 786#define bRxPD_Delay_TH 0x8000 787#define bRxProcess_Delay 0xf0000 788#define bRxSearchrange_GI2_Early 0x700000 789#define bRxFrame_Guard_Counter_L 0x3800000 790#define bRxSGI_Guard_L 0xc000000 791#define bRxSGI_Search_L 0x30000000 792#define bRxSGI_TH 0xc0000000 793#define bDFSCnt0 0xff 794#define bDFSCnt1 0xff00 795#define bDFSFlag 0xf0000 796#define bMFWeightSum 0x300000 797#define bMinIdxTH 0x7f000000 798#define bDAFormat 0x40000 799#define bTxChEmuEnable 0x01000000 800#define bTRSWIsolation_A 0x7f 801#define bTRSWIsolation_B 0x7f00 802#define bTRSWIsolation_C 0x7f0000 803#define bTRSWIsolation_D 0x7f000000 804#define bExtLNAGain 0x7c00 805 806/* 6. PageE(0xE00) */ 807#define bSTBCEn 0x4 /* Useless */ 808#define bAntennaMapping 0x10 809#define bNss 0x20 810#define bCFOAntSumD 0x200 811#define bPHYCounterReset 0x8000000 812#define bCFOReportGet 0x4000000 813#define bOFDMContinueTx 0x10000000 814#define bOFDMSingleCarrier 0x20000000 815#define bOFDMSingleTone 0x40000000 816#define bHTDetect 0x100 817#define bCFOEn 0x10000 818#define bCFOValue 0xfff00000 819#define bSigTone_Re 0x3f 820#define bSigTone_Im 0x7f00 821#define bCounter_CCA 0xffff 822#define bCounter_ParityFail 0xffff0000 823#define bCounter_RateIllegal 0xffff 824#define bCounter_CRC8Fail 0xffff0000 825#define bCounter_MCSNoSupport 0xffff 826#define bCounter_FastSync 0xffff 827#define bShortCFO 0xfff 828#define bShortCFOTLength 12 /* total */ 829#define bShortCFOFLength 11 /* fraction */ 830#define bLongCFO 0x7ff 831#define bLongCFOTLength 11 832#define bLongCFOFLength 11 833#define bTailCFO 0x1fff 834#define bTailCFOTLength 13 835#define bTailCFOFLength 12 836#define bmax_en_pwdB 0xffff 837#define bCC_power_dB 0xffff0000 838#define bnoise_pwdB 0xffff 839#define bPowerMeasTLength 10 840#define bPowerMeasFLength 3 841#define bRx_HT_BW 0x1 842#define bRxSC 0x6 843#define bRx_HT 0x8 844#define bNB_intf_det_on 0x1 845#define bIntf_win_len_cfg 0x30 846#define bNB_Intf_TH_cfg 0x1c0 847#define bRFGain 0x3f 848#define bTableSel 0x40 849#define bTRSW 0x80 850#define bRxSNR_A 0xff 851#define bRxSNR_B 0xff00 852#define bRxSNR_C 0xff0000 853#define bRxSNR_D 0xff000000 854#define bSNREVMTLength 8 855#define bSNREVMFLength 1 856#define bCSI1st 0xff 857#define bCSI2nd 0xff00 858#define bRxEVM1st 0xff0000 859#define bRxEVM2nd 0xff000000 860#define bSIGEVM 0xff 861#define bPWDB 0xff00 862#define bSGIEN 0x10000 863 864#define bSFactorQAM1 0xf /* Useless */ 865#define bSFactorQAM2 0xf0 866#define bSFactorQAM3 0xf00 867#define bSFactorQAM4 0xf000 868#define bSFactorQAM5 0xf0000 869#define bSFactorQAM6 0xf0000 870#define bSFactorQAM7 0xf00000 871#define bSFactorQAM8 0xf000000 872#define bSFactorQAM9 0xf0000000 873#define bCSIScheme 0x100000 874 875#define bNoiseLvlTopSet 0x3 /* Useless */ 876#define bChSmooth 0x4 877#define bChSmoothCfg1 0x38 878#define bChSmoothCfg2 0x1c0 879#define bChSmoothCfg3 0xe00 880#define bChSmoothCfg4 0x7000 881#define bMRCMode 0x800000 882#define bTHEVMCfg 0x7000000 883 884#define bLoopFitType 0x1 /* Useless */ 885#define bUpdCFO 0x40 886#define bUpdCFOOffData 0x80 887#define bAdvUpdCFO 0x100 888#define bAdvTimeCtrl 0x800 889#define bUpdClko 0x1000 890#define bFC 0x6000 891#define bTrackingMode 0x8000 892#define bPhCmpEnable 0x10000 893#define bUpdClkoLTF 0x20000 894#define bComChCFO 0x40000 895#define bCSIEstiMode 0x80000 896#define bAdvUpdEqz 0x100000 897#define bUChCfg 0x7000000 898#define bUpdEqz 0x8000000 899 900#define bTxAGCRate18_06 0x7f7f7f7f /* Useless */ 901#define bTxAGCRate54_24 0x7f7f7f7f 902#define bTxAGCRateMCS32 0x7f 903#define bTxAGCRateCCK 0x7f00 904#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 905#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 906#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 907#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 908 909/* Rx Pseduo noise */ 910#define bRxPesudoNoiseOn 0x20000000 /* Useless */ 911#define bRxPesudoNoise_A 0xff 912#define bRxPesudoNoise_B 0xff00 913#define bRxPesudoNoise_C 0xff0000 914#define bRxPesudoNoise_D 0xff000000 915#define bPesudoNoiseState_A 0xffff 916#define bPesudoNoiseState_B 0xffff0000 917#define bPesudoNoiseState_C 0xffff 918#define bPesudoNoiseState_D 0xffff0000 919 920/* 7. RF Register 921 * Zebra1 */ 922#define bZebra1_HSSIEnable 0x8 /* Useless */ 923#define bZebra1_TRxControl 0xc00 924#define bZebra1_TRxGainSetting 0x07f 925#define bZebra1_RxCorner 0xc00 926#define bZebra1_TxChargePump 0x38 927#define bZebra1_RxChargePump 0x7 928#define bZebra1_ChannelNum 0xf80 929#define bZebra1_TxLPFBW 0x400 930#define bZebra1_RxLPFBW 0x600 931 932/*Zebra4 */ 933#define bRTL8256RegModeCtrl1 0x100 /* Useless */ 934#define bRTL8256RegModeCtrl0 0x40 935#define bRTL8256_TxLPFBW 0x18 936#define bRTL8256_RxLPFBW 0x600 937 938/* RTL8258 */ 939#define bRTL8258_TxLPFBW 0xc /* Useless */ 940#define bRTL8258_RxLPFBW 0xc00 941#define bRTL8258_RSSILPFBW 0xc0 942 943/* 944 * Other Definition 945 */ 946 947/* byte endable for sb_write */ 948#define bByte0 0x1 /* Useless */ 949#define bByte1 0x2 950#define bByte2 0x4 951#define bByte3 0x8 952#define bWord0 0x3 953#define bWord1 0xc 954#define bDWord 0xf 955 956/* for PutRegsetting & GetRegSetting BitMask */ 957#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 958#define bMaskByte1 0xff00 959#define bMaskByte2 0xff0000 960#define bMaskByte3 0xff000000 961#define bMaskHWord 0xffff0000 962#define bMaskLWord 0x0000ffff 963#define bMaskDWord 0xffffffff 964 965/* for PutRFRegsetting & GetRFRegSetting BitMask */ 966#define bRFRegOffsetMask 0xfffff 967#define bEnable 0x1 /* Useless */ 968#define bDisable 0x0 969 970#define LeftAntenna 0x0 /* Useless */ 971#define RightAntenna 0x1 972 973#define tCheckTxStatus 500 /* 500ms Useless */ 974#define tUpdateRxCounter 100 /* 100ms */ 975 976#define rateCCK 0 /* Useless */ 977#define rateOFDM 1 978#define rateHT 2 979 980/* define Register-End */ 981#define bPMAC_End 0x1ff /* Useless */ 982#define bFPGAPHY0_End 0x8ff 983#define bFPGAPHY1_End 0x9ff 984#define bCCKPHY0_End 0xaff 985#define bOFDMPHY0_End 0xcff 986#define bOFDMPHY1_End 0xdff 987 988#define bPMACControl 0x0 /* Useless */ 989#define bWMACControl 0x1 990#define bWNICControl 0x2 991 992#define ANTENNA_A 0x1 /* Useless */ 993#define ANTENNA_B 0x2 994#define ANTENNA_AB 0x3 /* ANTENNA_A |ANTENNA_B */ 995 996#define ANTENNA_C 0x4 997#define ANTENNA_D 0x8 998 999 1000/* accept all physical address */ 1001#define RCR_AAP BIT(0) 1002#define RCR_APM BIT(1) /* accept physical match */ 1003#define RCR_AM BIT(2) /* accept multicast */ 1004#define RCR_AB BIT(3) /* accept broadcast */ 1005#define RCR_ACRC32 BIT(5) /* accept error packet */ 1006#define RCR_9356SEL BIT(6) 1007#define RCR_AICV BIT(12) /* Accept ICV error packet */ 1008#define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) /* Rx FIFO threshold */ 1009#define RCR_ADF BIT(18) /* Accept Data(frame type) frame */ 1010#define RCR_ACF BIT(19) /* Accept control frame */ 1011#define RCR_AMF BIT(20) /* Accept management frame */ 1012#define RCR_ADD3 BIT(21) 1013#define RCR_APWRMGT BIT(22) /* Accept power management packet */ 1014#define RCR_CBSSID BIT(23) /* Accept BSSID match packet */ 1015#define RCR_ENMARP BIT(28) /* enable mac auto reset phy */ 1016#define RCR_EnCS1 BIT(29) /* enable carrier sense method 1 */ 1017#define RCR_EnCS2 BIT(30) /* enable carrier sense method 2 */ 1018/* Rx Early mode is performed for packet size greater than 1536 */ 1019#define RCR_OnlyErlPkt BIT(31) 1020 1021/*--------------------------Define Parameters-------------------------------*/ 1022 1023 1024#endif /*__INC_HAL8192SPHYREG_H */ 1025 1026