odm.h revision 91a2916a82f326c9836bc2d3e2dad5f3b5405836
1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 17#ifndef __HALDMOUTSRC_H__ 18#define __HALDMOUTSRC_H__ 19 20/* */ 21/* Definition */ 22/* */ 23/* */ 24/* 2011/09/22 MH Define all team supprt ability. */ 25/* */ 26 27/* */ 28/* 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */ 29/* */ 30/* define DM_ODM_SUPPORT_AP 0 */ 31/* define DM_ODM_SUPPORT_ADSL 0 */ 32/* define DM_ODM_SUPPORT_CE 0 */ 33/* define DM_ODM_SUPPORT_MP 1 */ 34 35#define TP_MODE 0 36#define RSSI_MODE 1 37#define TRAFFIC_LOW 0 38#define TRAFFIC_HIGH 1 39 40 41/* */ 42/* 3 Tx Power Tracking */ 43/* 3============================================================ */ 44#define DPK_DELTA_MAPPING_NUM 13 45#define index_mapping_HP_NUM 15 46 47 48/* */ 49/* 3 PSD Handler */ 50/* 3============================================================ */ 51 52#define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 53#define MODE_40M 0 /* 0:20M, 1:40M */ 54#define PSD_TH2 3 55#define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 56#define SIR_STEP_SIZE 3 57#define Smooth_Size_1 5 58#define Smooth_TH_1 3 59#define Smooth_Size_2 10 60#define Smooth_TH_2 4 61#define Smooth_Size_3 20 62#define Smooth_TH_3 4 63#define Smooth_Step_Size 5 64#define Adaptive_SIR 1 65#define PSD_RESCAN 4 66#define PSD_SCAN_INTERVAL 700 /* ms */ 67 68/* 8723A High Power IGI Setting */ 69#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 70#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 71#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 72 73/* LPS define */ 74#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */ 75#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */ 76#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */ 77#define RSSI_OFFSET_DIG 0x05; 78 79/* ANT Test */ 80#define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 81#define ANTTESTA 0x01 /* Ant A will be Testing */ 82#define ANTTESTB 0x02 /* Ant B will be testing */ 83 84 85/* */ 86/* structure and define */ 87/* */ 88 89struct dig_t { 90 u8 Dig_Enable_Flag; 91 u8 Dig_Ext_Port_Stage; 92 93 int RssiLowThresh; 94 int RssiHighThresh; 95 96 u32 FALowThresh; 97 u32 FAHighThresh; 98 99 u8 CurSTAConnectState; 100 u8 PreSTAConnectState; 101 u8 CurMultiSTAConnectState; 102 103 u8 PreIGValue; 104 u8 CurIGValue; 105 u8 BackupIGValue; 106 107 s8 BackoffVal; 108 s8 BackoffVal_range_max; 109 s8 BackoffVal_range_min; 110 u8 rx_gain_range_max; 111 u8 rx_gain_range_min; 112 u8 Rssi_val_min; 113 114 u8 PreCCK_CCAThres; 115 u8 CurCCK_CCAThres; 116 u8 PreCCKPDState; 117 u8 CurCCKPDState; 118 119 u8 LargeFAHit; 120 u8 ForbiddenIGI; 121 u32 Recover_cnt; 122 123 u8 DIG_Dynamic_MIN_0; 124 u8 DIG_Dynamic_MIN_1; 125 bool bMediaConnect_0; 126 bool bMediaConnect_1; 127 128 u32 AntDiv_RSSI_max; 129 u32 RSSI_max; 130}; 131 132struct dynamic_pwr_sav { 133 u8 PreCCAState; 134 u8 CurCCAState; 135 136 u8 PreRFState; 137 u8 CurRFState; 138 139 int Rssi_val_min; 140 141 u8 initialize; 142 u32 Reg874,RegC70,Reg85C,RegA74; 143}; 144 145struct false_alarm_stats { 146 u32 Cnt_Parity_Fail; 147 u32 Cnt_Rate_Illegal; 148 u32 Cnt_Crc8_fail; 149 u32 Cnt_Mcs_fail; 150 u32 Cnt_Ofdm_fail; 151 u32 Cnt_Cck_fail; 152 u32 Cnt_all; 153 u32 Cnt_Fast_Fsync; 154 u32 Cnt_SB_Search_fail; 155 u32 Cnt_OFDM_CCA; 156 u32 Cnt_CCK_CCA; 157 u32 Cnt_CCA_all; 158 u32 Cnt_BW_USC; /* Gary */ 159 u32 Cnt_BW_LSC; /* Gary */ 160}; 161 162struct pri_cca { 163 u8 PriCCA_flag; 164 u8 intf_flag; 165 u8 intf_type; 166 u8 DupRTS_flag; 167 u8 Monitor_flag; 168}; 169 170struct rx_hp { 171 u8 RXHP_flag; 172 u8 PSD_func_trigger; 173 u8 PSD_bitmap_RXHP[80]; 174 u8 Pre_IGI; 175 u8 Cur_IGI; 176 u8 Pre_pw_th; 177 u8 Cur_pw_th; 178 bool First_time_enter; 179 bool RXHP_enable; 180 u8 TP_Mode; 181}; 182 183#define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 184#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 185 186/* This indicates two different the steps. */ 187/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 188/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 189/* with original RSSI to determine if it is necessary to switch antenna. */ 190#define SWAW_STEP_PEAK 0 191#define SWAW_STEP_DETERMINE 1 192 193#define TP_MODE 0 194#define RSSI_MODE 1 195#define TRAFFIC_LOW 0 196#define TRAFFIC_HIGH 1 197 198struct sw_ant_sw { 199 u8 try_flag; 200 s32 PreRSSI; 201 u8 CurAntenna; 202 u8 PreAntenna; 203 u8 RSSI_Trying; 204 u8 TestMode; 205 u8 bTriggerAntennaSwitch; 206 u8 SelectAntennaMap; 207 u8 RSSI_target; 208 209 /* Before link Antenna Switch check */ 210 u8 SWAS_NoLink_State; 211 u32 SWAS_NoLink_BK_Reg860; 212 bool ANTA_ON; /* To indicate Ant A is or not */ 213 bool ANTB_ON; /* To indicate Ant B is on or not */ 214 215 s32 RSSI_sum_A; 216 s32 RSSI_sum_B; 217 s32 RSSI_cnt_A; 218 s32 RSSI_cnt_B; 219 220 u64 lastTxOkCnt; 221 u64 lastRxOkCnt; 222 u64 TXByteCnt_A; 223 u64 TXByteCnt_B; 224 u64 RXByteCnt_A; 225 u64 RXByteCnt_B; 226 u8 TrafficLoad; 227}; 228 229struct edca_turbo { 230 bool bCurrentTurboEDCA; 231 bool bIsCurRDLState; 232 u32 prv_traffic_idx; /* edca turbo */ 233}; 234 235struct odm_rate_adapt { 236 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 237 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 238 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 239 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 240 u32 LastRATR; /* RATR Register Content */ 241}; 242 243#define IQK_MAC_REG_NUM 4 244#define IQK_ADDA_REG_NUM 16 245#define IQK_BB_REG_NUM_MAX 10 246#define IQK_BB_REG_NUM 9 247#define HP_THERMAL_NUM 8 248 249#define AVG_THERMAL_NUM 8 250#define IQK_Matrix_REG_NUM 8 251#define IQK_Matrix_Settings_NUM 1+24+21 252 253#define DM_Type_ByFW 0 254#define DM_Type_ByDriver 1 255 256/* Declare for common info */ 257 258struct odm_phy_dbg_info { 259 /* ODM Write,debug info */ 260 s8 RxSNRdB[RF_PATH_MAX]; 261 u64 NumQryPhyStatus; 262 u64 NumQryPhyStatusCCK; 263 u64 NumQryPhyStatusOFDM; 264 /* Others */ 265 s32 RxEVM[RF_PATH_MAX]; 266 267}; 268 269struct odm_packet_info { 270 u8 Rate; 271 u8 StationID; 272 bool bPacketMatchBSSID; 273 bool bPacketToSelf; 274 bool bPacketBeacon; 275}; 276 277 278enum { 279 /* BB Team */ 280 ODM_DIG = 0x00000001, 281 ODM_HIGH_POWER = 0x00000002, 282 ODM_CCK_CCA_TH = 0x00000004, 283 ODM_FA_STATISTICS = 0x00000008, 284 ODM_RAMASK = 0x00000010, 285 ODM_RSSI_MONITOR = 0x00000020, 286 ODM_SW_ANTDIV = 0x00000040, 287 ODM_HW_ANTDIV = 0x00000080, 288 ODM_BB_PWRSV = 0x00000100, 289 ODM_2TPATHDIV = 0x00000200, 290 ODM_1TPATHDIV = 0x00000400, 291 ODM_PSD2AFH = 0x00000800 292}; 293 294/* */ 295/* 2011/10/20 MH Define Common info enum for all team. */ 296/* */ 297 298enum odm_cmninfo { 299 /* Fixed value: */ 300 /* */ 301 302 ODM_CMNINFO_PLATFORM = 0, 303 ODM_CMNINFO_INTERFACE, /* enum odm_interface_def */ 304 ODM_CMNINFO_MP_TEST_CHIP, 305 ODM_CMNINFO_IC_TYPE, /* enum odm_ic_type_def */ 306 ODM_CMNINFO_CUT_VER, /* enum odm_cut_version */ 307 ODM_CMNINFO_FAB_VER, /* enum odm_fab_version */ 308 ODM_CMNINFO_RF_TYPE, /* enum rf_path_def or enum odm_rf_type? */ 309 ODM_CMNINFO_BOARD_TYPE, /* enum odm_board_type */ 310 ODM_CMNINFO_EXT_LNA, /* true */ 311 ODM_CMNINFO_EXT_PA, 312 ODM_CMNINFO_EXT_TRSW, 313 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 314 ODM_CMNINFO_BINHCT_TEST, 315 ODM_CMNINFO_BWIFI_TEST, 316 ODM_CMNINFO_SMART_CONCURRENT, 317 318 319 /* */ 320 /* Dynamic value: */ 321 /* */ 322 ODM_CMNINFO_BW, /* enum odm_band_width */ 323 ODM_CMNINFO_CHNL, 324 325 ODM_CMNINFO_SCAN, 326 ODM_CMNINFO_POWER_SAVING, 327 ODM_CMNINFO_MP_MODE, 328 329 ODM_CMNINFO_WIFI_DIRECT, 330 ODM_CMNINFO_WIFI_DISPLAY, 331 ODM_CMNINFO_LINK, 332 ODM_CMNINFO_RSSI_MIN, 333 ODM_CMNINFO_DBG_COMP, /* u64 */ 334 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 335 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 336 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 337 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 338 ODM_CMNINFO_BT_DISABLED, 339 ODM_CMNINFO_BT_OPERATION, 340 ODM_CMNINFO_BT_DIG, 341 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */ 342 ODM_CMNINFO_BT_DISABLE_EDCA, 343 344 /* */ 345 /* Dynamic ptr array hook itms. */ 346 /* */ 347 ODM_CMNINFO_STA_STATUS, 348 ODM_CMNINFO_PHY_STATUS, 349 ODM_CMNINFO_MAC_STATUS, 350 351 ODM_CMNINFO_MAX, 352}; 353 354/* Define ODM support ability. ODM_CMNINFO_ABILITY */ 355enum { 356 /* BB ODM section BIT 0-15 */ 357 ODM_BB_DIG = BIT(0), 358 ODM_BB_RA_MASK = BIT(1), 359 ODM_BB_DYNAMIC_TXPWR = BIT(2), 360 ODM_BB_FA_CNT = BIT(3), 361 ODM_BB_RSSI_MONITOR = BIT(4), 362 ODM_BB_CCK_PD = BIT(5), 363 ODM_BB_ANT_DIV = BIT(6), 364 ODM_BB_PWR_SAVE = BIT(7), 365 ODM_BB_PWR_TRAIN = BIT(8), 366 ODM_BB_RATE_ADAPTIVE = BIT(9), 367 ODM_BB_PATH_DIV = BIT(10), 368 ODM_BB_PSD = BIT(11), 369 ODM_BB_RXHP = BIT(12), 370 371 /* MAC DM section BIT 16-23 */ 372 ODM_MAC_EDCA_TURBO = BIT(16), 373 ODM_MAC_EARLY_MODE = BIT(17), 374 375 /* RF ODM section BIT 24-31 */ 376 ODM_RF_TX_PWR_TRACK = BIT(24), 377 ODM_RF_RX_GAIN_TRACK = BIT(25), 378 ODM_RF_CALIBRATION = BIT(26), 379 380}; 381 382/* ODM_CMNINFO_INTERFACE */ 383enum odm_interface_def { 384 ODM_ITRF_PCIE = 0x1, 385 ODM_ITRF_USB = 0x2, 386 ODM_ITRF_SDIO = 0x4, 387 ODM_ITRF_ALL = 0x7, 388}; 389 390/* ODM_CMNINFO_IC_TYPE */ 391enum odm_ic_type_def { 392 ODM_RTL8192S = BIT(0), 393 ODM_RTL8192C = BIT(1), 394 ODM_RTL8192D = BIT(2), 395 ODM_RTL8723A = BIT(3), 396 ODM_RTL8188E = BIT(4), 397 ODM_RTL8812 = BIT(5), 398 ODM_RTL8821 = BIT(6), 399}; 400 401/* ODM_CMNINFO_CUT_VER */ 402enum odm_cut_version { 403 ODM_CUT_A = 1, 404 ODM_CUT_B = 2, 405 ODM_CUT_C = 3, 406 ODM_CUT_D = 4, 407 ODM_CUT_E = 5, 408 ODM_CUT_F = 6, 409 ODM_CUT_TEST = 7, 410}; 411 412/* ODM_CMNINFO_FAB_VER */ 413enum odm_fab_version { 414 ODM_TSMC = 0, 415 ODM_UMC = 1, 416}; 417 418/* ODM_CMNINFO_RF_TYPE */ 419/* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 420enum rf_path_def { 421 ODM_RF_TX_A = BIT(0), 422 ODM_RF_TX_B = BIT(1), 423 ODM_RF_TX_C = BIT(2), 424 ODM_RF_TX_D = BIT(3), 425 ODM_RF_RX_A = BIT(4), 426 ODM_RF_RX_B = BIT(5), 427 ODM_RF_RX_C = BIT(6), 428 ODM_RF_RX_D = BIT(7), 429}; 430 431 432enum odm_rf_type { 433 ODM_1T1R = 0, 434 ODM_1T2R = 1, 435 ODM_2T2R = 2, 436 ODM_2T3R = 3, 437 ODM_2T4R = 4, 438 ODM_3T3R = 5, 439 ODM_3T4R = 6, 440 ODM_4T4R = 7, 441}; 442 443/* ODM Dynamic common info value definition */ 444 445enum odm_mac_phy_mode { 446 ODM_SMSP = 0, 447 ODM_DMSP = 1, 448 ODM_DMDP = 2, 449}; 450 451 452enum odm_bt_coexist { 453 ODM_BT_BUSY = 1, 454 ODM_BT_ON = 2, 455 ODM_BT_OFF = 3, 456 ODM_BT_NONE = 4, 457}; 458 459/* ODM_CMNINFO_OP_MODE */ 460enum odm_operation_mode { 461 ODM_NO_LINK = BIT(0), 462 ODM_LINK = BIT(1), 463 ODM_SCAN = BIT(2), 464 ODM_POWERSAVE = BIT(3), 465 ODM_AP_MODE = BIT(4), 466 ODM_CLIENT_MODE = BIT(5), 467 ODM_AD_HOC = BIT(6), 468 ODM_WIFI_DIRECT = BIT(7), 469 ODM_WIFI_DISPLAY = BIT(8), 470}; 471 472/* ODM_CMNINFO_WM_MODE */ 473enum odm_wireless_mode { 474 ODM_WM_UNKNOW = 0x0, 475 ODM_WM_B = BIT(0), 476 ODM_WM_G = BIT(1), 477 ODM_WM_A = BIT(2), 478 ODM_WM_N24G = BIT(3), 479 ODM_WM_N5G = BIT(4), 480 ODM_WM_AUTO = BIT(5), 481 ODM_WM_AC = BIT(6), 482}; 483 484/* ODM_CMNINFO_BAND */ 485enum odm_band_type { 486 ODM_BAND_2_4G = BIT(0), 487 ODM_BAND_5G = BIT(1), 488 489}; 490 491/* ODM_CMNINFO_SEC_CHNL_OFFSET */ 492enum odm_sec_chnl_offset { 493 ODM_DONT_CARE = 0, 494 ODM_BELOW = 1, 495 ODM_ABOVE = 2 496}; 497 498/* ODM_CMNINFO_BW */ 499enum odm_band_width { 500 ODM_BW20M = 0, 501 ODM_BW40M = 1, 502 ODM_BW80M = 2, 503 ODM_BW160M = 3, 504 ODM_BW10M = 4, 505}; 506 507/* ODM_CMNINFO_CHNL */ 508 509/* ODM_CMNINFO_BOARD_TYPE */ 510enum odm_board_type { 511 ODM_BOARD_NORMAL = 0, 512 ODM_BOARD_HIGHPWR = 1, 513 ODM_BOARD_MINICARD = 2, 514 ODM_BOARD_SLIM = 3, 515 ODM_BOARD_COMBO = 4, 516 517}; 518 519/* ODM_CMNINFO_ONE_PATH_CCA */ 520enum odm_cca_path { 521 ODM_CCA_2R = 0, 522 ODM_CCA_1R_A = 1, 523 ODM_CCA_1R_B = 2, 524}; 525 526struct iqk_matrix_regs_set { 527 bool bIQKDone; 528 s32 Value[1][IQK_Matrix_REG_NUM]; 529}; 530 531struct odm_rf_cal_t { 532 /* for tx power tracking */ 533 534 u32 RegA24; /* for TempCCK */ 535 s32 RegE94; 536 s32 RegE9C; 537 s32 RegEB4; 538 s32 RegEBC; 539 540 /* u8 bTXPowerTracking; */ 541 u8 TXPowercount; 542 bool bTXPowerTrackingInit; 543 bool bTXPowerTracking; 544 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 545 u8 TM_Trigger; 546 u8 InternalPA5G[2]; /* pathA / pathB */ 547 548 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 549 u8 ThermalValue; 550 u8 ThermalValue_LCK; 551 u8 ThermalValue_IQK; 552 u8 ThermalValue_DPK; 553 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 554 u8 ThermalValue_AVG_index; 555 u8 ThermalValue_RxGain; 556 u8 ThermalValue_Crystal; 557 u8 ThermalValue_DPKstore; 558 u8 ThermalValue_DPKtrack; 559 bool TxPowerTrackingInProgress; 560 bool bDPKenable; 561 562 bool bReloadtxpowerindex; 563 u8 bRfPiEnable; 564 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 565 566 u8 bCCKinCH14; 567 u8 CCK_index; 568 u8 OFDM_index[2]; 569 bool bDoneTxpower; 570 571 u8 ThermalValue_HP[HP_THERMAL_NUM]; 572 u8 ThermalValue_HP_index; 573 struct iqk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 574 575 u8 Delta_IQK; 576 u8 Delta_LCK; 577 578 /* for IQK */ 579 u32 RegC04; 580 u32 Reg874; 581 u32 RegC08; 582 u32 RegB68; 583 u32 RegB6C; 584 u32 Reg870; 585 u32 Reg860; 586 u32 Reg864; 587 588 bool bIQKInitialized; 589 bool bLCKInProgress; 590 bool bAntennaDetected; 591 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 592 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 593 u32 IQK_BB_backup_recover[9]; 594 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 595 596 /* for APK */ 597 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 598 u8 bAPKdone; 599 u8 bAPKThermalMeterIgnore; 600 u8 bDPdone; 601 u8 bDPPathAOK; 602 u8 bDPPathBOK; 603}; 604 605/* ODM Dynamic common info value definition */ 606struct odm_fat_t { 607 u8 Bssid[6]; 608 u8 antsel_rx_keep_0; 609 u8 antsel_rx_keep_1; 610 u8 antsel_rx_keep_2; 611 u32 antSumRSSI[7]; 612 u32 antRSSIcnt[7]; 613 u32 antAveRSSI[7]; 614 u8 FAT_State; 615 u32 TrainIdx; 616 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 617 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 618 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 619 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 620 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 621 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 622 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 623 u8 RxIdleAnt; 624 bool bBecomeLinked; 625}; 626 627enum fat_state { 628 FAT_NORMAL_STATE = 0, 629 FAT_TRAINING_STATE = 1, 630}; 631 632enum ant_dif_type { 633 NO_ANTDIV = 0xFF, 634 CG_TRX_HW_ANTDIV = 0x01, 635 CGCS_RX_HW_ANTDIV = 0x02, 636 FIXED_HW_ANTDIV = 0x03, 637 CG_TRX_SMART_ANTDIV = 0x04, 638 CGCS_RX_SW_ANTDIV = 0x05, 639}; 640 641/* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 642struct dm_odm_t { 643 /* */ 644 /* Add for different team use temporarily */ 645 /* */ 646 struct rtw_adapter *Adapter; /* For CE/NIC team */ 647 648 u64 DebugComponents; 649 u32 DebugLevel; 650 651/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 652 bool bCckHighPower; 653 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 654 u8 ControlChannel; 655/* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 656 657/* 1 COMMON INFORMATION */ 658 659 /* Init Value */ 660/* HOOK BEFORE REG INIT----------- */ 661 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K */ 662 u32 SupportAbility; 663 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */ 664 u8 SupportInterface; 665 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 666 u32 SupportICType; 667 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 668 u8 CutVersion; 669 /* Fab Version TSMC/UMC = 0/1 */ 670 u8 FabVersion; 671 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 672 u8 RFType; 673 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 674 u8 BoardType; 675 /* with external LNA NO/Yes = 0/1 */ 676 u8 ExtLNA; 677 /* with external PA NO/Yes = 0/1 */ 678 u8 ExtPA; 679 /* with external TRSW NO/Yes = 0/1 */ 680 u8 ExtTRSW; 681 u8 PatchID; /* Customer ID */ 682 bool bInHctTest; 683 bool bWIFITest; 684 685 bool bDualMacSmartConcurrent; 686 u32 BK_SupportAbility; 687 u8 AntDivType; 688/* HOOK BEFORE REG INIT----------- */ 689 690 /* */ 691 /* Dynamic Value */ 692 /* */ 693/* POINTER REFERENCE----------- */ 694 695 u8 u8_temp; 696 bool bool_temp; 697 struct rtw_adapter *PADAPTER_temp; 698 699 /* BW info 20M/40M/80M = 0/1/2 */ 700 u8 *pBandWidth; 701 /* Central channel location Ch1/Ch2/.... */ 702 u8 *pChannel; /* central channel number */ 703 /* Common info for Status */ 704 bool *pbScanInProcess; 705 bool *pbPowerSaving; 706/* POINTER REFERENCE----------- */ 707 /* */ 708/* CALL BY VALUE------------- */ 709 bool bWIFI_Direct; 710 bool bWIFI_Display; 711 bool bLinked; 712 u8 RSSI_Min; 713 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 714 bool bIsMPChip; 715 bool bOneEntryOnly; 716 /* Common info for BTDM */ 717 bool bBtDisabled; /* BT is disabled */ 718 bool bBtHsOperation; /* BT HS mode is under progress */ 719 u8 btHsDigVal; /* use BT rssi to decide the DIG value */ 720 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 721 bool bBtBusy; /* BT is busy. */ 722/* CALL BY VALUE------------- */ 723 724 /* 2 Define STA info. */ 725 /* _ODM_STA_INFO */ 726 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 727 struct sta_info * pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 728 729 /* */ 730 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 731 /* We need to colelct all support abilit to a proper area. */ 732 /* */ 733 bool RaSupport88E; 734 735 /* Define ........... */ 736 737 /* Latest packet phy info (ODM write) */ 738 struct odm_phy_dbg_info PhyDbgInfo; 739 /* PHY_INFO_88E PhyInfo; */ 740 741 /* Latest packet phy info (ODM write) */ 742 /* MAC_INFO_88E MacInfo; */ 743 744 /* Different Team independt structure?? */ 745 746 /* */ 747 /* TX_RTP_CMN TX_retrpo; */ 748 /* TX_RTP_88E TX_retrpo; */ 749 /* TX_RTP_8195 TX_retrpo; */ 750 751 /* */ 752 /* ODM Structure */ 753 /* */ 754 struct odm_fat_t DM_FatTable; 755 struct dig_t DM_DigTable; 756 struct dynamic_pwr_sav DM_PSTable; 757 struct pri_cca DM_PriCCA; 758 struct rx_hp DM_RXHP_Table; 759 struct false_alarm_stats FalseAlmCnt; 760 struct false_alarm_stats FlaseAlmCntBuddyAdapter; 761 struct sw_ant_sw DM_SWAT_Table; 762 bool RSSI_test; 763 764 struct edca_turbo DM_EDCA_Table; 765 u32 WMMEDCA_BE; 766 /* Copy from SD4 structure */ 767 /* */ 768 /* ================================================== */ 769 /* */ 770 771 /* PSD */ 772 bool bUserAssignLevel; 773 u8 RSSI_BT; /* come from BT */ 774 bool bPSDinProcess; 775 776 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 777 u8 bUseRAMask; 778 779 struct odm_rate_adapt RateAdaptive; 780 781 782 struct odm_rf_cal_t RFCalibrateInfo; 783 784 /* */ 785 /* TX power tracking */ 786 /* */ 787 u8 BbSwingIdxOfdm; 788 u8 BbSwingIdxOfdmCurrent; 789 u8 BbSwingIdxOfdmBase; 790 bool BbSwingFlagOfdm; 791 u8 BbSwingIdxCck; 792 u8 BbSwingIdxCckCurrent; 793 u8 BbSwingIdxCckBase; 794 bool BbSwingFlagCck; 795 /* */ 796 /* ODM system resource. */ 797 /* */ 798}; /* DM_Dynamic_Mechanism_Structure */ 799 800enum odm_rf_content { 801 odm_radioa_txt = 0x1000, 802 odm_radiob_txt = 0x1001, 803 odm_radioc_txt = 0x1002, 804 odm_radiod_txt = 0x1003 805}; 806 807/* Status code */ 808enum rt_status { 809 RT_STATUS_SUCCESS, 810 RT_STATUS_FAILURE, 811 RT_STATUS_PENDING, 812 RT_STATUS_RESOURCE, 813 RT_STATUS_INVALID_CONTEXT, 814 RT_STATUS_INVALID_PARAMETER, 815 RT_STATUS_NOT_SUPPORT, 816 RT_STATUS_OS_API_FAILED, 817}; 818 819/* include "odm_function.h" */ 820 821/* 3=========================================================== */ 822/* 3 DIG */ 823/* 3=========================================================== */ 824 825enum dm_dig_op { 826 DIG_TYPE_THRESH_HIGH = 0, 827 DIG_TYPE_THRESH_LOW = 1, 828 DIG_TYPE_BACKOFF = 2, 829 DIG_TYPE_RX_GAIN_MIN = 3, 830 DIG_TYPE_RX_GAIN_MAX = 4, 831 DIG_TYPE_ENABLE = 5, 832 DIG_TYPE_DISABLE = 6, 833 DIG_OP_TYPE_MAX 834}; 835 836#define DM_DIG_THRESH_HIGH 40 837#define DM_DIG_THRESH_LOW 35 838 839#define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */ 840 841 842#define DM_FALSEALARM_THRESH_LOW 400 843#define DM_FALSEALARM_THRESH_HIGH 1000 844 845#define DM_DIG_MAX_NIC 0x4e 846#define DM_DIG_MIN_NIC 0x1e 847 848#define DM_DIG_MAX_AP 0x32 849#define DM_DIG_MIN_AP 0x20 850 851#define DM_DIG_MAX_NIC_HP 0x46 852#define DM_DIG_MIN_NIC_HP 0x2e 853 854#define DM_DIG_MAX_AP_HP 0x42 855#define DM_DIG_MIN_AP_HP 0x30 856 857/* vivi 92c&92d has different definition, 20110504 */ 858/* this is for 92c */ 859#define DM_DIG_FA_TH0 0x200 860#define DM_DIG_FA_TH1 0x300 861#define DM_DIG_FA_TH2 0x400 862/* this is for 92d */ 863#define DM_DIG_FA_TH0_92D 0x100 864#define DM_DIG_FA_TH1_92D 0x400 865#define DM_DIG_FA_TH2_92D 0x600 866 867#define DM_DIG_BACKOFF_MAX 12 868#define DM_DIG_BACKOFF_MIN -4 869#define DM_DIG_BACKOFF_DEFAULT 10 870 871/* 3=========================================================== */ 872/* 3 AGC RX High Power Mode */ 873/* 3=========================================================== */ 874#define LNA_Low_Gain_1 0x64 875#define LNA_Low_Gain_2 0x5A 876#define LNA_Low_Gain_3 0x58 877 878#define FA_RXHP_TH1 5000 879#define FA_RXHP_TH2 1500 880#define FA_RXHP_TH3 800 881#define FA_RXHP_TH4 600 882#define FA_RXHP_TH5 500 883 884/* 3=========================================================== */ 885/* 3 EDCA */ 886/* 3=========================================================== */ 887 888/* 3=========================================================== */ 889/* 3 Dynamic Tx Power */ 890/* 3=========================================================== */ 891/* Dynamic Tx Power Control Threshold */ 892#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 893#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 894#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F 895 896#define TxHighPwrLevel_Normal 0 897#define TxHighPwrLevel_Level1 1 898#define TxHighPwrLevel_Level2 2 899#define TxHighPwrLevel_BT1 3 900#define TxHighPwrLevel_BT2 4 901#define TxHighPwrLevel_15 5 902#define TxHighPwrLevel_35 6 903#define TxHighPwrLevel_50 7 904#define TxHighPwrLevel_70 8 905#define TxHighPwrLevel_100 9 906 907/* 3=========================================================== */ 908/* 3 Rate Adaptive */ 909/* 3=========================================================== */ 910#define DM_RATR_STA_INIT 0 911#define DM_RATR_STA_HIGH 1 912#define DM_RATR_STA_MIDDLE 2 913#define DM_RATR_STA_LOW 3 914 915/* 3=========================================================== */ 916/* 3 BB Power Save */ 917/* 3=========================================================== */ 918 919 920enum dm_1r_cca { 921 CCA_1R =0, 922 CCA_2R = 1, 923 CCA_MAX = 2, 924}; 925 926enum dm_rf_def { 927 RF_Save =0, 928 RF_Normal = 1, 929 RF_MAX = 2, 930}; 931 932/* 3=========================================================== */ 933/* 3 Antenna Diversity */ 934/* 3=========================================================== */ 935enum dm_swas { 936 Antenna_A = 1, 937 Antenna_B = 2, 938 Antenna_MAX = 3, 939}; 940 941/* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 942#define MAX_ANTENNA_DETECTION_CNT 10 943 944/* */ 945/* Extern Global Variables. */ 946/* */ 947#define OFDM_TABLE_SIZE_92C 37 948#define OFDM_TABLE_SIZE_92D 43 949#define CCK_TABLE_SIZE 33 950 951extern u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D]; 952extern u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8]; 953extern u8 CCKSwingTable_Ch1423A [CCK_TABLE_SIZE][8]; 954 955 956 957/* 20100514 Joseph: Add definition for antenna switching test after link. */ 958/* This indicates two different the steps. */ 959/* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 960/* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 961/* with original RSSI to determine if it is necessary to switch antenna. */ 962#define SWAW_STEP_PEAK 0 963#define SWAW_STEP_DETERMINE 1 964 965void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm, u8 CurrentIGI); 966void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres); 967 968void ODM_SetAntenna(struct dm_odm_t *pDM_Odm, u8 Antenna); 969 970 971#define dm_RF_Saving ODM_RF_Saving23a 972void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal); 973 974#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink 975void ODM_SwAntDivRestAfterLink(struct dm_odm_t *pDM_Odm); 976 977#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck23a 978void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm); 979 980bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate, 981 u8 *pRATRState); 982 983 984#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 985void ODM_SwAntDivChkPerPktRssi(struct dm_odm_t *pDM_Odm, u8 StationID, 986 struct phy_info *pPhyInfo); 987 988u32 ConvertTo_dB23a(u32 Value); 989 990u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd); 991 992void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm); 993 994u32 ODM_Get_Rate_Bitmap23a(struct dm_odm_t *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level); 995 996 997void ODM23a_DMInit(struct dm_odm_t *pDM_Odm); 998 999struct hal_data_8723a; 1000void ODM_DMWatchdog23a(struct hal_data_8723a *pHalData); 1001 1002void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u32 Value); 1003 1004void ODM23a_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, void *pValue); 1005 1006void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u16 Index, void *pValue); 1007 1008void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 1009 1010void ODM_ResetIQKResult(struct dm_odm_t *pDM_Odm); 1011 1012void ODM_AntselStatistics_88C(struct dm_odm_t *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate); 1013 1014void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm); 1015 1016bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode); 1017 1018void odm_dtc(struct dm_odm_t *pDM_Odm); 1019 1020#endif 1021