12f3517418dc0684a32318f2c5b53257416448b1eBryan Wu/* 2ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang * Blackfin On-Chip Sport Emulated UART Driver 32f3517418dc0684a32318f2c5b53257416448b1eBryan Wu * 4ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang * Copyright 2006-2008 Analog Devices Inc. 52f3517418dc0684a32318f2c5b53257416448b1eBryan Wu * 6ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang * Enter bugs at http://blackfin.uclinux.org/ 72f3517418dc0684a32318f2c5b53257416448b1eBryan Wu * 8ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang * Licensed under the GPL-2 or later. 92f3517418dc0684a32318f2c5b53257416448b1eBryan Wu */ 102f3517418dc0684a32318f2c5b53257416448b1eBryan Wu 11ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang/* 12ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang * This driver and the hardware supported are in term of EE-191 of ADI. 13631dd1a885b6d7e9f6f51b4e5b311c2bb04c323cJustin P. Mattock * http://www.analog.com/static/imported-files/application_notes/EE191.pdf 14ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang * This application note describe how to implement a UART on a Sharc DSP, 15ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang * but this driver is implemented on Blackfin Processor. 16ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang * Transmit Frame Sync is not used by this driver to transfer data out. 17ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang */ 18ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang 19ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang#ifndef _BFIN_SPORT_UART_H 20ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang#define _BFIN_SPORT_UART_H 212f3517418dc0684a32318f2c5b53257416448b1eBryan Wu 222f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_TCR1 0x00 /* Transmit Configuration 1 Register */ 232f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_TCR2 0x04 /* Transmit Configuration 2 Register */ 242f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_TCLKDIV 0x08 /* Transmit Serial Clock Divider Register */ 252f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_TFSDIV 0x0C /* Transmit Frame Sync Divider Register */ 262f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_TX 0x10 /* Transmit Data Register */ 272f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_RX 0x18 /* Receive Data Register */ 282f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_RCR1 0x20 /* Receive Configuration 1 Register */ 292f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_RCR2 0x24 /* Receive Configuration 2 Register */ 302f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_RCLKDIV 0x28 /* Receive Serial Clock Divider Register */ 312f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_RFSDIV 0x2c /* Receive Frame Sync Divider Register */ 322f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define OFFSET_STAT 0x30 /* Status Register */ 332f3517418dc0684a32318f2c5b53257416448b1eBryan Wu 342f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_TCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR1)) 352f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_TCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_TCR2)) 362f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_TCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV)) 372f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_TFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_TFSDIV)) 382f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_TX(sport) bfin_read16(((sport)->port.membase + OFFSET_TX)) 392f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_RX(sport) bfin_read16(((sport)->port.membase + OFFSET_RX)) 40a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang/* 41a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang * If another interrupt fires while doing a 32-bit read from RX FIFO, 42a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang * a fake RX underflow error will be generated. So disable interrupts 43a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang * to prevent interruption while reading the FIFO. 44a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang */ 45a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang#define SPORT_GET_RX32(sport) \ 46a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang({ \ 47a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang unsigned int __ret; \ 4807143eaefd025098089edee7047714f6604a4a21Sonic Zhang unsigned long flags; \ 49a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang if (ANOMALY_05000473) \ 5007143eaefd025098089edee7047714f6604a4a21Sonic Zhang local_irq_save(flags); \ 51a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang __ret = bfin_read32((sport)->port.membase + OFFSET_RX); \ 52a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang if (ANOMALY_05000473) \ 5307143eaefd025098089edee7047714f6604a4a21Sonic Zhang local_irq_restore(flags); \ 54a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang __ret; \ 55a5a420d207df40226afbf828c12bd9b4c6e058efSonic Zhang}) 562f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_RCR1(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR1)) 572f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_RCR2(sport) bfin_read16(((sport)->port.membase + OFFSET_RCR2)) 582f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_RCLKDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV)) 592f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_RFSDIV(sport) bfin_read16(((sport)->port.membase + OFFSET_RFSDIV)) 602f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_GET_STAT(sport) bfin_read16(((sport)->port.membase + OFFSET_STAT)) 612f3517418dc0684a32318f2c5b53257416448b1eBryan Wu 622f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_TCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR1), v) 632f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_TCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCR2), v) 642f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_TCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v) 652f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_TFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v) 662f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_TX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_TX), v) 672f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_RX(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RX), v) 682f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_RCR1(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR1), v) 692f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_RCR2(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCR2), v) 702f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_RCLKDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v) 712f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_RFSDIV(sport, v) bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v) 722f3517418dc0684a32318f2c5b53257416448b1eBryan Wu#define SPORT_PUT_STAT(sport, v) bfin_write16(((sport)->port.membase + OFFSET_STAT), v) 73ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang 74ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang#define SPORT_TX_FIFO_SIZE 8 75ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang 761f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang#define SPORT_UART_GET_CTS(x) gpio_get_value(x->cts_pin) 771f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang#define SPORT_UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1) 781f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang#define SPORT_UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0) 791f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang 801f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang#if defined(CONFIG_SERIAL_BFIN_SPORT0_UART_CTSRTS) \ 811f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang || defined(CONFIG_SERIAL_BFIN_SPORT1_UART_CTSRTS) \ 821f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang || defined(CONFIG_SERIAL_BFIN_SPORT2_UART_CTSRTS) \ 831f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang || defined(CONFIG_SERIAL_BFIN_SPORT3_UART_CTSRTS) 841f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang# define CONFIG_SERIAL_BFIN_SPORT_CTSRTS 851f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang#endif 861f7d1c85df5b63359e7f7e3fbd1509c1cdd6414fSonic Zhang 87ccf68e59e93181df9353c0cc721459d18ff200b6sonic zhang#endif /* _BFIN_SPORT_UART_H */ 88