cpm_uart_core.c revision 227434f8986c3827a1faedd1feb437acd6285315
1/*
2 *  Driver for CPM (SCC/SMC) serial ports; core driver
3 *
4 *  Based on arch/ppc/cpm2_io/uart.c by Dan Malek
5 *  Based on ppc8xx.c by Thomas Gleixner
6 *  Based on drivers/serial/amba.c by Russell King
7 *
8 *  Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
9 *              Pantelis Antoniou (panto@intracom.gr) (CPM1)
10 *
11 *  Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
12 *            (C) 2004 Intracom, S.A.
13 *            (C) 2005-2006 MontaVista Software, Inc.
14 *		Vitaly Bordug <vbordug@ru.mvista.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
29 *
30 */
31
32#include <linux/module.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/serial.h>
38#include <linux/console.h>
39#include <linux/sysrq.h>
40#include <linux/device.h>
41#include <linux/bootmem.h>
42#include <linux/dma-mapping.h>
43#include <linux/fs_uart_pd.h>
44#include <linux/of_platform.h>
45#include <linux/gpio.h>
46#include <linux/of_gpio.h>
47#include <linux/clk.h>
48
49#include <asm/io.h>
50#include <asm/irq.h>
51#include <asm/delay.h>
52#include <asm/fs_pd.h>
53#include <asm/udbg.h>
54
55#if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
56#define SUPPORT_SYSRQ
57#endif
58
59#include <linux/serial_core.h>
60#include <linux/kernel.h>
61
62#include "cpm_uart.h"
63
64
65/**************************************************************/
66
67static int  cpm_uart_tx_pump(struct uart_port *port);
68static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
69static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
70static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
71
72/**************************************************************/
73
74#define HW_BUF_SPD_THRESHOLD    2400
75
76/*
77 * Check, if transmit buffers are processed
78*/
79static unsigned int cpm_uart_tx_empty(struct uart_port *port)
80{
81	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
82	cbd_t __iomem *bdp = pinfo->tx_bd_base;
83	int ret = 0;
84
85	while (1) {
86		if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
87			break;
88
89		if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
90			ret = TIOCSER_TEMT;
91			break;
92		}
93		bdp++;
94	}
95
96	pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
97
98	return ret;
99}
100
101static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
102{
103	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
104
105	if (pinfo->gpios[GPIO_RTS] >= 0)
106		gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
107
108	if (pinfo->gpios[GPIO_DTR] >= 0)
109		gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
110}
111
112static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
113{
114	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
115	unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
116
117	if (pinfo->gpios[GPIO_CTS] >= 0) {
118		if (gpio_get_value(pinfo->gpios[GPIO_CTS]))
119			mctrl &= ~TIOCM_CTS;
120	}
121
122	if (pinfo->gpios[GPIO_DSR] >= 0) {
123		if (gpio_get_value(pinfo->gpios[GPIO_DSR]))
124			mctrl &= ~TIOCM_DSR;
125	}
126
127	if (pinfo->gpios[GPIO_DCD] >= 0) {
128		if (gpio_get_value(pinfo->gpios[GPIO_DCD]))
129			mctrl &= ~TIOCM_CAR;
130	}
131
132	if (pinfo->gpios[GPIO_RI] >= 0) {
133		if (!gpio_get_value(pinfo->gpios[GPIO_RI]))
134			mctrl |= TIOCM_RNG;
135	}
136
137	return mctrl;
138}
139
140/*
141 * Stop transmitter
142 */
143static void cpm_uart_stop_tx(struct uart_port *port)
144{
145	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
146	smc_t __iomem *smcp = pinfo->smcp;
147	scc_t __iomem *sccp = pinfo->sccp;
148
149	pr_debug("CPM uart[%d]:stop tx\n", port->line);
150
151	if (IS_SMC(pinfo))
152		clrbits8(&smcp->smc_smcm, SMCM_TX);
153	else
154		clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
155}
156
157/*
158 * Start transmitter
159 */
160static void cpm_uart_start_tx(struct uart_port *port)
161{
162	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
163	smc_t __iomem *smcp = pinfo->smcp;
164	scc_t __iomem *sccp = pinfo->sccp;
165
166	pr_debug("CPM uart[%d]:start tx\n", port->line);
167
168	if (IS_SMC(pinfo)) {
169		if (in_8(&smcp->smc_smcm) & SMCM_TX)
170			return;
171	} else {
172		if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
173			return;
174	}
175
176	if (cpm_uart_tx_pump(port) != 0) {
177		if (IS_SMC(pinfo)) {
178			setbits8(&smcp->smc_smcm, SMCM_TX);
179		} else {
180			setbits16(&sccp->scc_sccm, UART_SCCM_TX);
181		}
182	}
183}
184
185/*
186 * Stop receiver
187 */
188static void cpm_uart_stop_rx(struct uart_port *port)
189{
190	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
191	smc_t __iomem *smcp = pinfo->smcp;
192	scc_t __iomem *sccp = pinfo->sccp;
193
194	pr_debug("CPM uart[%d]:stop rx\n", port->line);
195
196	if (IS_SMC(pinfo))
197		clrbits8(&smcp->smc_smcm, SMCM_RX);
198	else
199		clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
200}
201
202/*
203 * Enable Modem status interrupts
204 */
205static void cpm_uart_enable_ms(struct uart_port *port)
206{
207	pr_debug("CPM uart[%d]:enable ms\n", port->line);
208}
209
210/*
211 * Generate a break.
212 */
213static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
214{
215	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
216
217	pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
218		break_state);
219
220	if (break_state)
221		cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
222	else
223		cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
224}
225
226/*
227 * Transmit characters, refill buffer descriptor, if possible
228 */
229static void cpm_uart_int_tx(struct uart_port *port)
230{
231	pr_debug("CPM uart[%d]:TX INT\n", port->line);
232
233	cpm_uart_tx_pump(port);
234}
235
236#ifdef CONFIG_CONSOLE_POLL
237static int serial_polled;
238#endif
239
240/*
241 * Receive characters
242 */
243static void cpm_uart_int_rx(struct uart_port *port)
244{
245	int i;
246	unsigned char ch;
247	u8 *cp;
248	struct tty_port *tport = &port->state->port;
249	struct tty_struct *tty = tport->tty;
250	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
251	cbd_t __iomem *bdp;
252	u16 status;
253	unsigned int flg;
254
255	pr_debug("CPM uart[%d]:RX INT\n", port->line);
256
257	/* Just loop through the closed BDs and copy the characters into
258	 * the buffer.
259	 */
260	bdp = pinfo->rx_cur;
261	for (;;) {
262#ifdef CONFIG_CONSOLE_POLL
263		if (unlikely(serial_polled)) {
264			serial_polled = 0;
265			return;
266		}
267#endif
268		/* get status */
269		status = in_be16(&bdp->cbd_sc);
270		/* If this one is empty, return happy */
271		if (status & BD_SC_EMPTY)
272			break;
273
274		/* get number of characters, and check spce in flip-buffer */
275		i = in_be16(&bdp->cbd_datlen);
276
277		/* If we have not enough room in tty flip buffer, then we try
278		 * later, which will be the next rx-interrupt or a timeout
279		 */
280		if (tty_buffer_request_room(tport, i) < i) {
281			printk(KERN_WARNING "No room in flip buffer\n");
282			return;
283		}
284
285		/* get pointer */
286		cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
287
288		/* loop through the buffer */
289		while (i-- > 0) {
290			ch = *cp++;
291			port->icount.rx++;
292			flg = TTY_NORMAL;
293
294			if (status &
295			    (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
296				goto handle_error;
297			if (uart_handle_sysrq_char(port, ch))
298				continue;
299#ifdef CONFIG_CONSOLE_POLL
300			if (unlikely(serial_polled)) {
301				serial_polled = 0;
302				return;
303			}
304#endif
305		      error_return:
306			tty_insert_flip_char(tty, ch, flg);
307
308		}		/* End while (i--) */
309
310		/* This BD is ready to be used again. Clear status. get next */
311		clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
312		                        BD_SC_OV | BD_SC_ID);
313		setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
314
315		if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
316			bdp = pinfo->rx_bd_base;
317		else
318			bdp++;
319
320	} /* End for (;;) */
321
322	/* Write back buffer pointer */
323	pinfo->rx_cur = bdp;
324
325	/* activate BH processing */
326	tty_flip_buffer_push(tty);
327
328	return;
329
330	/* Error processing */
331
332      handle_error:
333	/* Statistics */
334	if (status & BD_SC_BR)
335		port->icount.brk++;
336	if (status & BD_SC_PR)
337		port->icount.parity++;
338	if (status & BD_SC_FR)
339		port->icount.frame++;
340	if (status & BD_SC_OV)
341		port->icount.overrun++;
342
343	/* Mask out ignored conditions */
344	status &= port->read_status_mask;
345
346	/* Handle the remaining ones */
347	if (status & BD_SC_BR)
348		flg = TTY_BREAK;
349	else if (status & BD_SC_PR)
350		flg = TTY_PARITY;
351	else if (status & BD_SC_FR)
352		flg = TTY_FRAME;
353
354	/* overrun does not affect the current character ! */
355	if (status & BD_SC_OV) {
356		ch = 0;
357		flg = TTY_OVERRUN;
358		/* We skip this buffer */
359		/* CHECK: Is really nothing senseful there */
360		/* ASSUMPTION: it contains nothing valid */
361		i = 0;
362	}
363#ifdef SUPPORT_SYSRQ
364	port->sysrq = 0;
365#endif
366	goto error_return;
367}
368
369/*
370 * Asynchron mode interrupt handler
371 */
372static irqreturn_t cpm_uart_int(int irq, void *data)
373{
374	u8 events;
375	struct uart_port *port = data;
376	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
377	smc_t __iomem *smcp = pinfo->smcp;
378	scc_t __iomem *sccp = pinfo->sccp;
379
380	pr_debug("CPM uart[%d]:IRQ\n", port->line);
381
382	if (IS_SMC(pinfo)) {
383		events = in_8(&smcp->smc_smce);
384		out_8(&smcp->smc_smce, events);
385		if (events & SMCM_BRKE)
386			uart_handle_break(port);
387		if (events & SMCM_RX)
388			cpm_uart_int_rx(port);
389		if (events & SMCM_TX)
390			cpm_uart_int_tx(port);
391	} else {
392		events = in_be16(&sccp->scc_scce);
393		out_be16(&sccp->scc_scce, events);
394		if (events & UART_SCCM_BRKE)
395			uart_handle_break(port);
396		if (events & UART_SCCM_RX)
397			cpm_uart_int_rx(port);
398		if (events & UART_SCCM_TX)
399			cpm_uart_int_tx(port);
400	}
401	return (events) ? IRQ_HANDLED : IRQ_NONE;
402}
403
404static int cpm_uart_startup(struct uart_port *port)
405{
406	int retval;
407	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
408
409	pr_debug("CPM uart[%d]:startup\n", port->line);
410
411	/* If the port is not the console, make sure rx is disabled. */
412	if (!(pinfo->flags & FLAG_CONSOLE)) {
413		/* Disable UART rx */
414		if (IS_SMC(pinfo)) {
415			clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
416			clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
417		} else {
418			clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
419			clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
420		}
421		cpm_uart_initbd(pinfo);
422		cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
423	}
424	/* Install interrupt handler. */
425	retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
426	if (retval)
427		return retval;
428
429	/* Startup rx-int */
430	if (IS_SMC(pinfo)) {
431		setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
432		setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
433	} else {
434		setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
435		setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
436	}
437
438	return 0;
439}
440
441inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
442{
443	set_current_state(TASK_UNINTERRUPTIBLE);
444	schedule_timeout(pinfo->wait_closing);
445}
446
447/*
448 * Shutdown the uart
449 */
450static void cpm_uart_shutdown(struct uart_port *port)
451{
452	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
453
454	pr_debug("CPM uart[%d]:shutdown\n", port->line);
455
456	/* free interrupt handler */
457	free_irq(port->irq, port);
458
459	/* If the port is not the console, disable Rx and Tx. */
460	if (!(pinfo->flags & FLAG_CONSOLE)) {
461		/* Wait for all the BDs marked sent */
462		while(!cpm_uart_tx_empty(port)) {
463			set_current_state(TASK_UNINTERRUPTIBLE);
464			schedule_timeout(2);
465		}
466
467		if (pinfo->wait_closing)
468			cpm_uart_wait_until_send(pinfo);
469
470		/* Stop uarts */
471		if (IS_SMC(pinfo)) {
472			smc_t __iomem *smcp = pinfo->smcp;
473			clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
474			clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
475		} else {
476			scc_t __iomem *sccp = pinfo->sccp;
477			clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
478			clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
479		}
480
481		/* Shut them really down and reinit buffer descriptors */
482		if (IS_SMC(pinfo)) {
483			out_be16(&pinfo->smcup->smc_brkcr, 0);
484			cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
485		} else {
486			out_be16(&pinfo->sccup->scc_brkcr, 0);
487			cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
488		}
489
490		cpm_uart_initbd(pinfo);
491	}
492}
493
494static void cpm_uart_set_termios(struct uart_port *port,
495                                 struct ktermios *termios,
496                                 struct ktermios *old)
497{
498	int baud;
499	unsigned long flags;
500	u16 cval, scval, prev_mode;
501	int bits, sbits;
502	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
503	smc_t __iomem *smcp = pinfo->smcp;
504	scc_t __iomem *sccp = pinfo->sccp;
505	int maxidl;
506
507	pr_debug("CPM uart[%d]:set_termios\n", port->line);
508
509	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
510	if (baud < HW_BUF_SPD_THRESHOLD ||
511	    (pinfo->port.state && pinfo->port.state->port.tty->low_latency))
512		pinfo->rx_fifosize = 1;
513	else
514		pinfo->rx_fifosize = RX_BUF_SIZE;
515
516	/* MAXIDL is the timeout after which a receive buffer is closed
517	 * when not full if no more characters are received.
518	 * We calculate it from the baudrate so that the duration is
519	 * always the same at standard rates: about 4ms.
520	 */
521	maxidl = baud / 2400;
522	if (maxidl < 1)
523		maxidl = 1;
524	if (maxidl > 0x10)
525		maxidl = 0x10;
526
527	/* Character length programmed into the mode register is the
528	 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
529	 * 1 or 2 stop bits, minus 1.
530	 * The value 'bits' counts this for us.
531	 */
532	cval = 0;
533	scval = 0;
534
535	/* byte size */
536	switch (termios->c_cflag & CSIZE) {
537	case CS5:
538		bits = 5;
539		break;
540	case CS6:
541		bits = 6;
542		break;
543	case CS7:
544		bits = 7;
545		break;
546	case CS8:
547		bits = 8;
548		break;
549		/* Never happens, but GCC is too dumb to figure it out */
550	default:
551		bits = 8;
552		break;
553	}
554	sbits = bits - 5;
555
556	if (termios->c_cflag & CSTOPB) {
557		cval |= SMCMR_SL;	/* Two stops */
558		scval |= SCU_PSMR_SL;
559		bits++;
560	}
561
562	if (termios->c_cflag & PARENB) {
563		cval |= SMCMR_PEN;
564		scval |= SCU_PSMR_PEN;
565		bits++;
566		if (!(termios->c_cflag & PARODD)) {
567			cval |= SMCMR_PM_EVEN;
568			scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
569		}
570	}
571
572	/*
573	 * Update the timeout
574	 */
575	uart_update_timeout(port, termios->c_cflag, baud);
576
577	/*
578	 * Set up parity check flag
579	 */
580#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
581
582	port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
583	if (termios->c_iflag & INPCK)
584		port->read_status_mask |= BD_SC_FR | BD_SC_PR;
585	if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
586		port->read_status_mask |= BD_SC_BR;
587
588	/*
589	 * Characters to ignore
590	 */
591	port->ignore_status_mask = 0;
592	if (termios->c_iflag & IGNPAR)
593		port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
594	if (termios->c_iflag & IGNBRK) {
595		port->ignore_status_mask |= BD_SC_BR;
596		/*
597		 * If we're ignore parity and break indicators, ignore
598		 * overruns too.  (For real raw support).
599		 */
600		if (termios->c_iflag & IGNPAR)
601			port->ignore_status_mask |= BD_SC_OV;
602	}
603	/*
604	 * !!! ignore all characters if CREAD is not set
605	 */
606	if ((termios->c_cflag & CREAD) == 0)
607		port->read_status_mask &= ~BD_SC_EMPTY;
608
609	spin_lock_irqsave(&port->lock, flags);
610
611	/* Start bit has not been added (so don't, because we would just
612	 * subtract it later), and we need to add one for the number of
613	 * stops bits (there is always at least one).
614	 */
615	bits++;
616	if (IS_SMC(pinfo)) {
617		/*
618		 * MRBLR can be changed while an SMC/SCC is operating only
619		 * if it is done in a single bus cycle with one 16-bit move
620		 * (not two 8-bit bus cycles back-to-back). This occurs when
621		 * the cp shifts control to the next RxBD, so the change does
622		 * not take effect immediately. To guarantee the exact RxBD
623		 * on which the change occurs, change MRBLR only while the
624		 * SMC/SCC receiver is disabled.
625		 */
626		out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
627		out_be16(&pinfo->smcup->smc_maxidl, maxidl);
628
629		/* Set the mode register.  We want to keep a copy of the
630		 * enables, because we want to put them back if they were
631		 * present.
632		 */
633		prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
634		/* Output in *one* operation, so we don't interrupt RX/TX if they
635		 * were already enabled. */
636		out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
637		    SMCMR_SM_UART | prev_mode);
638	} else {
639		out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
640		out_be16(&pinfo->sccup->scc_maxidl, maxidl);
641		out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
642	}
643
644	if (pinfo->clk)
645		clk_set_rate(pinfo->clk, baud);
646	else
647		cpm_set_brg(pinfo->brg - 1, baud);
648	spin_unlock_irqrestore(&port->lock, flags);
649}
650
651static const char *cpm_uart_type(struct uart_port *port)
652{
653	pr_debug("CPM uart[%d]:uart_type\n", port->line);
654
655	return port->type == PORT_CPM ? "CPM UART" : NULL;
656}
657
658/*
659 * verify the new serial_struct (for TIOCSSERIAL).
660 */
661static int cpm_uart_verify_port(struct uart_port *port,
662				struct serial_struct *ser)
663{
664	int ret = 0;
665
666	pr_debug("CPM uart[%d]:verify_port\n", port->line);
667
668	if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
669		ret = -EINVAL;
670	if (ser->irq < 0 || ser->irq >= nr_irqs)
671		ret = -EINVAL;
672	if (ser->baud_base < 9600)
673		ret = -EINVAL;
674	return ret;
675}
676
677/*
678 * Transmit characters, refill buffer descriptor, if possible
679 */
680static int cpm_uart_tx_pump(struct uart_port *port)
681{
682	cbd_t __iomem *bdp;
683	u8 *p;
684	int count;
685	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
686	struct circ_buf *xmit = &port->state->xmit;
687
688	/* Handle xon/xoff */
689	if (port->x_char) {
690		/* Pick next descriptor and fill from buffer */
691		bdp = pinfo->tx_cur;
692
693		p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
694
695		*p++ = port->x_char;
696
697		out_be16(&bdp->cbd_datlen, 1);
698		setbits16(&bdp->cbd_sc, BD_SC_READY);
699		/* Get next BD. */
700		if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
701			bdp = pinfo->tx_bd_base;
702		else
703			bdp++;
704		pinfo->tx_cur = bdp;
705
706		port->icount.tx++;
707		port->x_char = 0;
708		return 1;
709	}
710
711	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
712		cpm_uart_stop_tx(port);
713		return 0;
714	}
715
716	/* Pick next descriptor and fill from buffer */
717	bdp = pinfo->tx_cur;
718
719	while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
720	       xmit->tail != xmit->head) {
721		count = 0;
722		p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
723		while (count < pinfo->tx_fifosize) {
724			*p++ = xmit->buf[xmit->tail];
725			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
726			port->icount.tx++;
727			count++;
728			if (xmit->head == xmit->tail)
729				break;
730		}
731		out_be16(&bdp->cbd_datlen, count);
732		setbits16(&bdp->cbd_sc, BD_SC_READY);
733		/* Get next BD. */
734		if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
735			bdp = pinfo->tx_bd_base;
736		else
737			bdp++;
738	}
739	pinfo->tx_cur = bdp;
740
741	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
742		uart_write_wakeup(port);
743
744	if (uart_circ_empty(xmit)) {
745		cpm_uart_stop_tx(port);
746		return 0;
747	}
748
749	return 1;
750}
751
752/*
753 * init buffer descriptors
754 */
755static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
756{
757	int i;
758	u8 *mem_addr;
759	cbd_t __iomem *bdp;
760
761	pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
762
763	/* Set the physical address of the host memory
764	 * buffers in the buffer descriptors, and the
765	 * virtual address for us to work with.
766	 */
767	mem_addr = pinfo->mem_addr;
768	bdp = pinfo->rx_cur = pinfo->rx_bd_base;
769	for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
770		out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
771		out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
772		mem_addr += pinfo->rx_fifosize;
773	}
774
775	out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
776	out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
777
778	/* Set the physical address of the host memory
779	 * buffers in the buffer descriptors, and the
780	 * virtual address for us to work with.
781	 */
782	mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
783	bdp = pinfo->tx_cur = pinfo->tx_bd_base;
784	for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
785		out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
786		out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
787		mem_addr += pinfo->tx_fifosize;
788	}
789
790	out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
791	out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
792}
793
794static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
795{
796	scc_t __iomem *scp;
797	scc_uart_t __iomem *sup;
798
799	pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
800
801	scp = pinfo->sccp;
802	sup = pinfo->sccup;
803
804	/* Store address */
805	out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
806	         (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
807	out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
808	         (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
809
810	/* Set up the uart parameters in the
811	 * parameter ram.
812	 */
813
814	cpm_set_scc_fcr(sup);
815
816	out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
817	out_be16(&sup->scc_maxidl, 0x10);
818	out_be16(&sup->scc_brkcr, 1);
819	out_be16(&sup->scc_parec, 0);
820	out_be16(&sup->scc_frmec, 0);
821	out_be16(&sup->scc_nosec, 0);
822	out_be16(&sup->scc_brkec, 0);
823	out_be16(&sup->scc_uaddr1, 0);
824	out_be16(&sup->scc_uaddr2, 0);
825	out_be16(&sup->scc_toseq, 0);
826	out_be16(&sup->scc_char1, 0x8000);
827	out_be16(&sup->scc_char2, 0x8000);
828	out_be16(&sup->scc_char3, 0x8000);
829	out_be16(&sup->scc_char4, 0x8000);
830	out_be16(&sup->scc_char5, 0x8000);
831	out_be16(&sup->scc_char6, 0x8000);
832	out_be16(&sup->scc_char7, 0x8000);
833	out_be16(&sup->scc_char8, 0x8000);
834	out_be16(&sup->scc_rccm, 0xc0ff);
835
836	/* Send the CPM an initialize command.
837	 */
838	cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
839
840	/* Set UART mode, 8 bit, no parity, one stop.
841	 * Enable receive and transmit.
842	 */
843	out_be32(&scp->scc_gsmrh, 0);
844	out_be32(&scp->scc_gsmrl,
845	         SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
846
847	/* Enable rx interrupts  and clear all pending events.  */
848	out_be16(&scp->scc_sccm, 0);
849	out_be16(&scp->scc_scce, 0xffff);
850	out_be16(&scp->scc_dsr, 0x7e7e);
851	out_be16(&scp->scc_psmr, 0x3000);
852
853	setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
854}
855
856static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
857{
858	smc_t __iomem *sp;
859	smc_uart_t __iomem *up;
860
861	pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
862
863	sp = pinfo->smcp;
864	up = pinfo->smcup;
865
866	/* Store address */
867	out_be16(&pinfo->smcup->smc_rbase,
868	         (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
869	out_be16(&pinfo->smcup->smc_tbase,
870	         (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
871
872/*
873 *  In case SMC1 is being relocated...
874 */
875#if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
876	out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
877	out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
878	out_be32(&up->smc_rstate, 0);
879	out_be32(&up->smc_tstate, 0);
880	out_be16(&up->smc_brkcr, 1);              /* number of break chars */
881	out_be16(&up->smc_brkec, 0);
882#endif
883
884	/* Set up the uart parameters in the
885	 * parameter ram.
886	 */
887	cpm_set_smc_fcr(up);
888
889	/* Using idle character time requires some additional tuning.  */
890	out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
891	out_be16(&up->smc_maxidl, 0x10);
892	out_be16(&up->smc_brklen, 0);
893	out_be16(&up->smc_brkec, 0);
894	out_be16(&up->smc_brkcr, 1);
895
896	cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
897
898	/* Set UART mode, 8 bit, no parity, one stop.
899	 * Enable receive and transmit.
900	 */
901	out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
902
903	/* Enable only rx interrupts clear all pending events. */
904	out_8(&sp->smc_smcm, 0);
905	out_8(&sp->smc_smce, 0xff);
906
907	setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
908}
909
910/*
911 * Initialize port. This is called from early_console stuff
912 * so we have to be careful here !
913 */
914static int cpm_uart_request_port(struct uart_port *port)
915{
916	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
917	int ret;
918
919	pr_debug("CPM uart[%d]:request port\n", port->line);
920
921	if (pinfo->flags & FLAG_CONSOLE)
922		return 0;
923
924	if (IS_SMC(pinfo)) {
925		clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
926		clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
927	} else {
928		clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
929		clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
930	}
931
932	ret = cpm_uart_allocbuf(pinfo, 0);
933
934	if (ret)
935		return ret;
936
937	cpm_uart_initbd(pinfo);
938	if (IS_SMC(pinfo))
939		cpm_uart_init_smc(pinfo);
940	else
941		cpm_uart_init_scc(pinfo);
942
943	return 0;
944}
945
946static void cpm_uart_release_port(struct uart_port *port)
947{
948	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
949
950	if (!(pinfo->flags & FLAG_CONSOLE))
951		cpm_uart_freebuf(pinfo);
952}
953
954/*
955 * Configure/autoconfigure the port.
956 */
957static void cpm_uart_config_port(struct uart_port *port, int flags)
958{
959	pr_debug("CPM uart[%d]:config_port\n", port->line);
960
961	if (flags & UART_CONFIG_TYPE) {
962		port->type = PORT_CPM;
963		cpm_uart_request_port(port);
964	}
965}
966
967#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
968/*
969 * Write a string to the serial port
970 * Note that this is called with interrupts already disabled
971 */
972static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
973		const char *string, u_int count)
974{
975	unsigned int i;
976	cbd_t __iomem *bdp, *bdbase;
977	unsigned char *cpm_outp_addr;
978
979	/* Get the address of the host memory buffer.
980	 */
981	bdp = pinfo->tx_cur;
982	bdbase = pinfo->tx_bd_base;
983
984	/*
985	 * Now, do each character.  This is not as bad as it looks
986	 * since this is a holding FIFO and not a transmitting FIFO.
987	 * We could add the complexity of filling the entire transmit
988	 * buffer, but we would just wait longer between accesses......
989	 */
990	for (i = 0; i < count; i++, string++) {
991		/* Wait for transmitter fifo to empty.
992		 * Ready indicates output is ready, and xmt is doing
993		 * that, not that it is ready for us to send.
994		 */
995		while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
996			;
997
998		/* Send the character out.
999		 * If the buffer address is in the CPM DPRAM, don't
1000		 * convert it.
1001		 */
1002		cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
1003					pinfo);
1004		*cpm_outp_addr = *string;
1005
1006		out_be16(&bdp->cbd_datlen, 1);
1007		setbits16(&bdp->cbd_sc, BD_SC_READY);
1008
1009		if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1010			bdp = bdbase;
1011		else
1012			bdp++;
1013
1014		/* if a LF, also do CR... */
1015		if (*string == 10) {
1016			while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1017				;
1018
1019			cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
1020						pinfo);
1021			*cpm_outp_addr = 13;
1022
1023			out_be16(&bdp->cbd_datlen, 1);
1024			setbits16(&bdp->cbd_sc, BD_SC_READY);
1025
1026			if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1027				bdp = bdbase;
1028			else
1029				bdp++;
1030		}
1031	}
1032
1033	/*
1034	 * Finally, Wait for transmitter & holding register to empty
1035	 *  and restore the IER
1036	 */
1037	while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1038		;
1039
1040	pinfo->tx_cur = bdp;
1041}
1042#endif
1043
1044#ifdef CONFIG_CONSOLE_POLL
1045/* Serial polling routines for writing and reading from the uart while
1046 * in an interrupt or debug context.
1047 */
1048
1049#define GDB_BUF_SIZE	512	/* power of 2, please */
1050
1051static char poll_buf[GDB_BUF_SIZE];
1052static char *pollp;
1053static int poll_chars;
1054
1055static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1056{
1057	u_char		c, *cp;
1058	volatile cbd_t	*bdp;
1059	int		i;
1060
1061	/* Get the address of the host memory buffer.
1062	 */
1063	bdp = pinfo->rx_cur;
1064	while (bdp->cbd_sc & BD_SC_EMPTY)
1065		;
1066
1067	/* If the buffer address is in the CPM DPRAM, don't
1068	 * convert it.
1069	 */
1070	cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1071
1072	if (obuf) {
1073		i = c = bdp->cbd_datlen;
1074		while (i-- > 0)
1075			*obuf++ = *cp++;
1076	} else
1077		c = *cp;
1078	bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1079	bdp->cbd_sc |= BD_SC_EMPTY;
1080
1081	if (bdp->cbd_sc & BD_SC_WRAP)
1082		bdp = pinfo->rx_bd_base;
1083	else
1084		bdp++;
1085	pinfo->rx_cur = (cbd_t *)bdp;
1086
1087	return (int)c;
1088}
1089
1090static int cpm_get_poll_char(struct uart_port *port)
1091{
1092	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
1093
1094	if (!serial_polled) {
1095		serial_polled = 1;
1096		poll_chars = 0;
1097	}
1098	if (poll_chars <= 0) {
1099		poll_chars = poll_wait_key(poll_buf, pinfo);
1100		pollp = poll_buf;
1101	}
1102	poll_chars--;
1103	return *pollp++;
1104}
1105
1106static void cpm_put_poll_char(struct uart_port *port,
1107			 unsigned char c)
1108{
1109	struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
1110	static char ch[2];
1111
1112	ch[0] = (char)c;
1113	cpm_uart_early_write(pinfo, ch, 1);
1114}
1115#endif /* CONFIG_CONSOLE_POLL */
1116
1117static struct uart_ops cpm_uart_pops = {
1118	.tx_empty	= cpm_uart_tx_empty,
1119	.set_mctrl	= cpm_uart_set_mctrl,
1120	.get_mctrl	= cpm_uart_get_mctrl,
1121	.stop_tx	= cpm_uart_stop_tx,
1122	.start_tx	= cpm_uart_start_tx,
1123	.stop_rx	= cpm_uart_stop_rx,
1124	.enable_ms	= cpm_uart_enable_ms,
1125	.break_ctl	= cpm_uart_break_ctl,
1126	.startup	= cpm_uart_startup,
1127	.shutdown	= cpm_uart_shutdown,
1128	.set_termios	= cpm_uart_set_termios,
1129	.type		= cpm_uart_type,
1130	.release_port	= cpm_uart_release_port,
1131	.request_port	= cpm_uart_request_port,
1132	.config_port	= cpm_uart_config_port,
1133	.verify_port	= cpm_uart_verify_port,
1134#ifdef CONFIG_CONSOLE_POLL
1135	.poll_get_char = cpm_get_poll_char,
1136	.poll_put_char = cpm_put_poll_char,
1137#endif
1138};
1139
1140struct uart_cpm_port cpm_uart_ports[UART_NR];
1141
1142static int cpm_uart_init_port(struct device_node *np,
1143                              struct uart_cpm_port *pinfo)
1144{
1145	const u32 *data;
1146	void __iomem *mem, *pram;
1147	int len;
1148	int ret;
1149	int i;
1150
1151	data = of_get_property(np, "clock", NULL);
1152	if (data) {
1153		struct clk *clk = clk_get(NULL, (const char*)data);
1154		if (!IS_ERR(clk))
1155			pinfo->clk = clk;
1156	}
1157	if (!pinfo->clk) {
1158		data = of_get_property(np, "fsl,cpm-brg", &len);
1159		if (!data || len != 4) {
1160			printk(KERN_ERR "CPM UART %s has no/invalid "
1161			                "fsl,cpm-brg property.\n", np->name);
1162			return -EINVAL;
1163		}
1164		pinfo->brg = *data;
1165	}
1166
1167	data = of_get_property(np, "fsl,cpm-command", &len);
1168	if (!data || len != 4) {
1169		printk(KERN_ERR "CPM UART %s has no/invalid "
1170		                "fsl,cpm-command property.\n", np->name);
1171		return -EINVAL;
1172	}
1173	pinfo->command = *data;
1174
1175	mem = of_iomap(np, 0);
1176	if (!mem)
1177		return -ENOMEM;
1178
1179	if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1180	    of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1181		pinfo->sccp = mem;
1182		pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1183	} else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1184	           of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1185		pinfo->flags |= FLAG_SMC;
1186		pinfo->smcp = mem;
1187		pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1188	} else {
1189		ret = -ENODEV;
1190		goto out_mem;
1191	}
1192
1193	if (!pram) {
1194		ret = -ENOMEM;
1195		goto out_mem;
1196	}
1197
1198	pinfo->tx_nrfifos = TX_NUM_FIFO;
1199	pinfo->tx_fifosize = TX_BUF_SIZE;
1200	pinfo->rx_nrfifos = RX_NUM_FIFO;
1201	pinfo->rx_fifosize = RX_BUF_SIZE;
1202
1203	pinfo->port.uartclk = ppc_proc_freq;
1204	pinfo->port.mapbase = (unsigned long)mem;
1205	pinfo->port.type = PORT_CPM;
1206	pinfo->port.ops = &cpm_uart_pops,
1207	pinfo->port.iotype = UPIO_MEM;
1208	pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1209	spin_lock_init(&pinfo->port.lock);
1210
1211	pinfo->port.irq = of_irq_to_resource(np, 0, NULL);
1212	if (pinfo->port.irq == NO_IRQ) {
1213		ret = -EINVAL;
1214		goto out_pram;
1215	}
1216
1217	for (i = 0; i < NUM_GPIOS; i++)
1218		pinfo->gpios[i] = of_get_gpio(np, i);
1219
1220#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1221	udbg_putc = NULL;
1222#endif
1223
1224	return cpm_uart_request_port(&pinfo->port);
1225
1226out_pram:
1227	cpm_uart_unmap_pram(pinfo, pram);
1228out_mem:
1229	iounmap(mem);
1230	return ret;
1231}
1232
1233#ifdef CONFIG_SERIAL_CPM_CONSOLE
1234/*
1235 *	Print a string to the serial port trying not to disturb
1236 *	any possible real use of the port...
1237 *
1238 *	Note that this is called with interrupts already disabled
1239 */
1240static void cpm_uart_console_write(struct console *co, const char *s,
1241				   u_int count)
1242{
1243	struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1244	unsigned long flags;
1245	int nolock = oops_in_progress;
1246
1247	if (unlikely(nolock)) {
1248		local_irq_save(flags);
1249	} else {
1250		spin_lock_irqsave(&pinfo->port.lock, flags);
1251	}
1252
1253	cpm_uart_early_write(pinfo, s, count);
1254
1255	if (unlikely(nolock)) {
1256		local_irq_restore(flags);
1257	} else {
1258		spin_unlock_irqrestore(&pinfo->port.lock, flags);
1259	}
1260}
1261
1262
1263static int __init cpm_uart_console_setup(struct console *co, char *options)
1264{
1265	int baud = 38400;
1266	int bits = 8;
1267	int parity = 'n';
1268	int flow = 'n';
1269	int ret;
1270	struct uart_cpm_port *pinfo;
1271	struct uart_port *port;
1272
1273	struct device_node *np = NULL;
1274	int i = 0;
1275
1276	if (co->index >= UART_NR) {
1277		printk(KERN_ERR "cpm_uart: console index %d too high\n",
1278		       co->index);
1279		return -ENODEV;
1280	}
1281
1282	do {
1283		np = of_find_node_by_type(np, "serial");
1284		if (!np)
1285			return -ENODEV;
1286
1287		if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1288		    !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1289		    !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1290		    !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1291			i--;
1292	} while (i++ != co->index);
1293
1294	pinfo = &cpm_uart_ports[co->index];
1295
1296	pinfo->flags |= FLAG_CONSOLE;
1297	port = &pinfo->port;
1298
1299	ret = cpm_uart_init_port(np, pinfo);
1300	of_node_put(np);
1301	if (ret)
1302		return ret;
1303
1304	if (options) {
1305		uart_parse_options(options, &baud, &parity, &bits, &flow);
1306	} else {
1307		if ((baud = uart_baudrate()) == -1)
1308			baud = 9600;
1309	}
1310
1311	if (IS_SMC(pinfo)) {
1312		out_be16(&pinfo->smcup->smc_brkcr, 0);
1313		cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1314		clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1315		clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1316	} else {
1317		out_be16(&pinfo->sccup->scc_brkcr, 0);
1318		cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1319		clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1320		clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1321	}
1322
1323	ret = cpm_uart_allocbuf(pinfo, 1);
1324
1325	if (ret)
1326		return ret;
1327
1328	cpm_uart_initbd(pinfo);
1329
1330	if (IS_SMC(pinfo))
1331		cpm_uart_init_smc(pinfo);
1332	else
1333		cpm_uart_init_scc(pinfo);
1334
1335	uart_set_options(port, co, baud, parity, bits, flow);
1336	cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1337
1338	return 0;
1339}
1340
1341static struct uart_driver cpm_reg;
1342static struct console cpm_scc_uart_console = {
1343	.name		= "ttyCPM",
1344	.write		= cpm_uart_console_write,
1345	.device		= uart_console_device,
1346	.setup		= cpm_uart_console_setup,
1347	.flags		= CON_PRINTBUFFER,
1348	.index		= -1,
1349	.data		= &cpm_reg,
1350};
1351
1352static int __init cpm_uart_console_init(void)
1353{
1354	register_console(&cpm_scc_uart_console);
1355	return 0;
1356}
1357
1358console_initcall(cpm_uart_console_init);
1359
1360#define CPM_UART_CONSOLE	&cpm_scc_uart_console
1361#else
1362#define CPM_UART_CONSOLE	NULL
1363#endif
1364
1365static struct uart_driver cpm_reg = {
1366	.owner		= THIS_MODULE,
1367	.driver_name	= "ttyCPM",
1368	.dev_name	= "ttyCPM",
1369	.major		= SERIAL_CPM_MAJOR,
1370	.minor		= SERIAL_CPM_MINOR,
1371	.cons		= CPM_UART_CONSOLE,
1372	.nr		= UART_NR,
1373};
1374
1375static int probe_index;
1376
1377static int cpm_uart_probe(struct platform_device *ofdev)
1378{
1379	int index = probe_index++;
1380	struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1381	int ret;
1382
1383	pinfo->port.line = index;
1384
1385	if (index >= UART_NR)
1386		return -ENODEV;
1387
1388	dev_set_drvdata(&ofdev->dev, pinfo);
1389
1390	/* initialize the device pointer for the port */
1391	pinfo->port.dev = &ofdev->dev;
1392
1393	ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1394	if (ret)
1395		return ret;
1396
1397	return uart_add_one_port(&cpm_reg, &pinfo->port);
1398}
1399
1400static int cpm_uart_remove(struct platform_device *ofdev)
1401{
1402	struct uart_cpm_port *pinfo = dev_get_drvdata(&ofdev->dev);
1403	return uart_remove_one_port(&cpm_reg, &pinfo->port);
1404}
1405
1406static struct of_device_id cpm_uart_match[] = {
1407	{
1408		.compatible = "fsl,cpm1-smc-uart",
1409	},
1410	{
1411		.compatible = "fsl,cpm1-scc-uart",
1412	},
1413	{
1414		.compatible = "fsl,cpm2-smc-uart",
1415	},
1416	{
1417		.compatible = "fsl,cpm2-scc-uart",
1418	},
1419	{}
1420};
1421
1422static struct platform_driver cpm_uart_driver = {
1423	.driver = {
1424		.name = "cpm_uart",
1425		.owner = THIS_MODULE,
1426		.of_match_table = cpm_uart_match,
1427	},
1428	.probe = cpm_uart_probe,
1429	.remove = cpm_uart_remove,
1430 };
1431
1432static int __init cpm_uart_init(void)
1433{
1434	int ret = uart_register_driver(&cpm_reg);
1435	if (ret)
1436		return ret;
1437
1438	ret = platform_driver_register(&cpm_uart_driver);
1439	if (ret)
1440		uart_unregister_driver(&cpm_reg);
1441
1442	return ret;
1443}
1444
1445static void __exit cpm_uart_exit(void)
1446{
1447	platform_driver_unregister(&cpm_uart_driver);
1448	uart_unregister_driver(&cpm_reg);
1449}
1450
1451module_init(cpm_uart_init);
1452module_exit(cpm_uart_exit);
1453
1454MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1455MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1456MODULE_LICENSE("GPL");
1457MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
1458