cpm_uart_core.c revision 2e124b4a390ca85325fae75764bef92f0547fa25
1/* 2 * Driver for CPM (SCC/SMC) serial ports; core driver 3 * 4 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek 5 * Based on ppc8xx.c by Thomas Gleixner 6 * Based on drivers/serial/amba.c by Russell King 7 * 8 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) 9 * Pantelis Antoniou (panto@intracom.gr) (CPM1) 10 * 11 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. 12 * (C) 2004 Intracom, S.A. 13 * (C) 2005-2006 MontaVista Software, Inc. 14 * Vitaly Bordug <vbordug@ru.mvista.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 29 * 30 */ 31 32#include <linux/module.h> 33#include <linux/tty.h> 34#include <linux/tty_flip.h> 35#include <linux/ioport.h> 36#include <linux/init.h> 37#include <linux/serial.h> 38#include <linux/console.h> 39#include <linux/sysrq.h> 40#include <linux/device.h> 41#include <linux/bootmem.h> 42#include <linux/dma-mapping.h> 43#include <linux/fs_uart_pd.h> 44#include <linux/of_platform.h> 45#include <linux/gpio.h> 46#include <linux/of_gpio.h> 47#include <linux/clk.h> 48 49#include <asm/io.h> 50#include <asm/irq.h> 51#include <asm/delay.h> 52#include <asm/fs_pd.h> 53#include <asm/udbg.h> 54 55#if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 56#define SUPPORT_SYSRQ 57#endif 58 59#include <linux/serial_core.h> 60#include <linux/kernel.h> 61 62#include "cpm_uart.h" 63 64 65/**************************************************************/ 66 67static int cpm_uart_tx_pump(struct uart_port *port); 68static void cpm_uart_init_smc(struct uart_cpm_port *pinfo); 69static void cpm_uart_init_scc(struct uart_cpm_port *pinfo); 70static void cpm_uart_initbd(struct uart_cpm_port *pinfo); 71 72/**************************************************************/ 73 74#define HW_BUF_SPD_THRESHOLD 2400 75 76/* 77 * Check, if transmit buffers are processed 78*/ 79static unsigned int cpm_uart_tx_empty(struct uart_port *port) 80{ 81 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 82 cbd_t __iomem *bdp = pinfo->tx_bd_base; 83 int ret = 0; 84 85 while (1) { 86 if (in_be16(&bdp->cbd_sc) & BD_SC_READY) 87 break; 88 89 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { 90 ret = TIOCSER_TEMT; 91 break; 92 } 93 bdp++; 94 } 95 96 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); 97 98 return ret; 99} 100 101static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 102{ 103 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 104 105 if (pinfo->gpios[GPIO_RTS] >= 0) 106 gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); 107 108 if (pinfo->gpios[GPIO_DTR] >= 0) 109 gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR)); 110} 111 112static unsigned int cpm_uart_get_mctrl(struct uart_port *port) 113{ 114 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 115 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 116 117 if (pinfo->gpios[GPIO_CTS] >= 0) { 118 if (gpio_get_value(pinfo->gpios[GPIO_CTS])) 119 mctrl &= ~TIOCM_CTS; 120 } 121 122 if (pinfo->gpios[GPIO_DSR] >= 0) { 123 if (gpio_get_value(pinfo->gpios[GPIO_DSR])) 124 mctrl &= ~TIOCM_DSR; 125 } 126 127 if (pinfo->gpios[GPIO_DCD] >= 0) { 128 if (gpio_get_value(pinfo->gpios[GPIO_DCD])) 129 mctrl &= ~TIOCM_CAR; 130 } 131 132 if (pinfo->gpios[GPIO_RI] >= 0) { 133 if (!gpio_get_value(pinfo->gpios[GPIO_RI])) 134 mctrl |= TIOCM_RNG; 135 } 136 137 return mctrl; 138} 139 140/* 141 * Stop transmitter 142 */ 143static void cpm_uart_stop_tx(struct uart_port *port) 144{ 145 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 146 smc_t __iomem *smcp = pinfo->smcp; 147 scc_t __iomem *sccp = pinfo->sccp; 148 149 pr_debug("CPM uart[%d]:stop tx\n", port->line); 150 151 if (IS_SMC(pinfo)) 152 clrbits8(&smcp->smc_smcm, SMCM_TX); 153 else 154 clrbits16(&sccp->scc_sccm, UART_SCCM_TX); 155} 156 157/* 158 * Start transmitter 159 */ 160static void cpm_uart_start_tx(struct uart_port *port) 161{ 162 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 163 smc_t __iomem *smcp = pinfo->smcp; 164 scc_t __iomem *sccp = pinfo->sccp; 165 166 pr_debug("CPM uart[%d]:start tx\n", port->line); 167 168 if (IS_SMC(pinfo)) { 169 if (in_8(&smcp->smc_smcm) & SMCM_TX) 170 return; 171 } else { 172 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) 173 return; 174 } 175 176 if (cpm_uart_tx_pump(port) != 0) { 177 if (IS_SMC(pinfo)) { 178 setbits8(&smcp->smc_smcm, SMCM_TX); 179 } else { 180 setbits16(&sccp->scc_sccm, UART_SCCM_TX); 181 } 182 } 183} 184 185/* 186 * Stop receiver 187 */ 188static void cpm_uart_stop_rx(struct uart_port *port) 189{ 190 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 191 smc_t __iomem *smcp = pinfo->smcp; 192 scc_t __iomem *sccp = pinfo->sccp; 193 194 pr_debug("CPM uart[%d]:stop rx\n", port->line); 195 196 if (IS_SMC(pinfo)) 197 clrbits8(&smcp->smc_smcm, SMCM_RX); 198 else 199 clrbits16(&sccp->scc_sccm, UART_SCCM_RX); 200} 201 202/* 203 * Enable Modem status interrupts 204 */ 205static void cpm_uart_enable_ms(struct uart_port *port) 206{ 207 pr_debug("CPM uart[%d]:enable ms\n", port->line); 208} 209 210/* 211 * Generate a break. 212 */ 213static void cpm_uart_break_ctl(struct uart_port *port, int break_state) 214{ 215 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 216 217 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, 218 break_state); 219 220 if (break_state) 221 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 222 else 223 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 224} 225 226/* 227 * Transmit characters, refill buffer descriptor, if possible 228 */ 229static void cpm_uart_int_tx(struct uart_port *port) 230{ 231 pr_debug("CPM uart[%d]:TX INT\n", port->line); 232 233 cpm_uart_tx_pump(port); 234} 235 236#ifdef CONFIG_CONSOLE_POLL 237static int serial_polled; 238#endif 239 240/* 241 * Receive characters 242 */ 243static void cpm_uart_int_rx(struct uart_port *port) 244{ 245 int i; 246 unsigned char ch; 247 u8 *cp; 248 struct tty_port *tport = &port->state->port; 249 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 250 cbd_t __iomem *bdp; 251 u16 status; 252 unsigned int flg; 253 254 pr_debug("CPM uart[%d]:RX INT\n", port->line); 255 256 /* Just loop through the closed BDs and copy the characters into 257 * the buffer. 258 */ 259 bdp = pinfo->rx_cur; 260 for (;;) { 261#ifdef CONFIG_CONSOLE_POLL 262 if (unlikely(serial_polled)) { 263 serial_polled = 0; 264 return; 265 } 266#endif 267 /* get status */ 268 status = in_be16(&bdp->cbd_sc); 269 /* If this one is empty, return happy */ 270 if (status & BD_SC_EMPTY) 271 break; 272 273 /* get number of characters, and check spce in flip-buffer */ 274 i = in_be16(&bdp->cbd_datlen); 275 276 /* If we have not enough room in tty flip buffer, then we try 277 * later, which will be the next rx-interrupt or a timeout 278 */ 279 if (tty_buffer_request_room(tport, i) < i) { 280 printk(KERN_WARNING "No room in flip buffer\n"); 281 return; 282 } 283 284 /* get pointer */ 285 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 286 287 /* loop through the buffer */ 288 while (i-- > 0) { 289 ch = *cp++; 290 port->icount.rx++; 291 flg = TTY_NORMAL; 292 293 if (status & 294 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) 295 goto handle_error; 296 if (uart_handle_sysrq_char(port, ch)) 297 continue; 298#ifdef CONFIG_CONSOLE_POLL 299 if (unlikely(serial_polled)) { 300 serial_polled = 0; 301 return; 302 } 303#endif 304 error_return: 305 tty_insert_flip_char(tport, ch, flg); 306 307 } /* End while (i--) */ 308 309 /* This BD is ready to be used again. Clear status. get next */ 310 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | 311 BD_SC_OV | BD_SC_ID); 312 setbits16(&bdp->cbd_sc, BD_SC_EMPTY); 313 314 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 315 bdp = pinfo->rx_bd_base; 316 else 317 bdp++; 318 319 } /* End for (;;) */ 320 321 /* Write back buffer pointer */ 322 pinfo->rx_cur = bdp; 323 324 /* activate BH processing */ 325 tty_flip_buffer_push(tport); 326 327 return; 328 329 /* Error processing */ 330 331 handle_error: 332 /* Statistics */ 333 if (status & BD_SC_BR) 334 port->icount.brk++; 335 if (status & BD_SC_PR) 336 port->icount.parity++; 337 if (status & BD_SC_FR) 338 port->icount.frame++; 339 if (status & BD_SC_OV) 340 port->icount.overrun++; 341 342 /* Mask out ignored conditions */ 343 status &= port->read_status_mask; 344 345 /* Handle the remaining ones */ 346 if (status & BD_SC_BR) 347 flg = TTY_BREAK; 348 else if (status & BD_SC_PR) 349 flg = TTY_PARITY; 350 else if (status & BD_SC_FR) 351 flg = TTY_FRAME; 352 353 /* overrun does not affect the current character ! */ 354 if (status & BD_SC_OV) { 355 ch = 0; 356 flg = TTY_OVERRUN; 357 /* We skip this buffer */ 358 /* CHECK: Is really nothing senseful there */ 359 /* ASSUMPTION: it contains nothing valid */ 360 i = 0; 361 } 362#ifdef SUPPORT_SYSRQ 363 port->sysrq = 0; 364#endif 365 goto error_return; 366} 367 368/* 369 * Asynchron mode interrupt handler 370 */ 371static irqreturn_t cpm_uart_int(int irq, void *data) 372{ 373 u8 events; 374 struct uart_port *port = data; 375 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 376 smc_t __iomem *smcp = pinfo->smcp; 377 scc_t __iomem *sccp = pinfo->sccp; 378 379 pr_debug("CPM uart[%d]:IRQ\n", port->line); 380 381 if (IS_SMC(pinfo)) { 382 events = in_8(&smcp->smc_smce); 383 out_8(&smcp->smc_smce, events); 384 if (events & SMCM_BRKE) 385 uart_handle_break(port); 386 if (events & SMCM_RX) 387 cpm_uart_int_rx(port); 388 if (events & SMCM_TX) 389 cpm_uart_int_tx(port); 390 } else { 391 events = in_be16(&sccp->scc_scce); 392 out_be16(&sccp->scc_scce, events); 393 if (events & UART_SCCM_BRKE) 394 uart_handle_break(port); 395 if (events & UART_SCCM_RX) 396 cpm_uart_int_rx(port); 397 if (events & UART_SCCM_TX) 398 cpm_uart_int_tx(port); 399 } 400 return (events) ? IRQ_HANDLED : IRQ_NONE; 401} 402 403static int cpm_uart_startup(struct uart_port *port) 404{ 405 int retval; 406 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 407 408 pr_debug("CPM uart[%d]:startup\n", port->line); 409 410 /* If the port is not the console, make sure rx is disabled. */ 411 if (!(pinfo->flags & FLAG_CONSOLE)) { 412 /* Disable UART rx */ 413 if (IS_SMC(pinfo)) { 414 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN); 415 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 416 } else { 417 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR); 418 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 419 } 420 cpm_uart_initbd(pinfo); 421 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 422 } 423 /* Install interrupt handler. */ 424 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); 425 if (retval) 426 return retval; 427 428 /* Startup rx-int */ 429 if (IS_SMC(pinfo)) { 430 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 431 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); 432 } else { 433 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 434 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); 435 } 436 437 return 0; 438} 439 440inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) 441{ 442 set_current_state(TASK_UNINTERRUPTIBLE); 443 schedule_timeout(pinfo->wait_closing); 444} 445 446/* 447 * Shutdown the uart 448 */ 449static void cpm_uart_shutdown(struct uart_port *port) 450{ 451 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 452 453 pr_debug("CPM uart[%d]:shutdown\n", port->line); 454 455 /* free interrupt handler */ 456 free_irq(port->irq, port); 457 458 /* If the port is not the console, disable Rx and Tx. */ 459 if (!(pinfo->flags & FLAG_CONSOLE)) { 460 /* Wait for all the BDs marked sent */ 461 while(!cpm_uart_tx_empty(port)) { 462 set_current_state(TASK_UNINTERRUPTIBLE); 463 schedule_timeout(2); 464 } 465 466 if (pinfo->wait_closing) 467 cpm_uart_wait_until_send(pinfo); 468 469 /* Stop uarts */ 470 if (IS_SMC(pinfo)) { 471 smc_t __iomem *smcp = pinfo->smcp; 472 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 473 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); 474 } else { 475 scc_t __iomem *sccp = pinfo->sccp; 476 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 477 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 478 } 479 480 /* Shut them really down and reinit buffer descriptors */ 481 if (IS_SMC(pinfo)) { 482 out_be16(&pinfo->smcup->smc_brkcr, 0); 483 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 484 } else { 485 out_be16(&pinfo->sccup->scc_brkcr, 0); 486 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 487 } 488 489 cpm_uart_initbd(pinfo); 490 } 491} 492 493static void cpm_uart_set_termios(struct uart_port *port, 494 struct ktermios *termios, 495 struct ktermios *old) 496{ 497 int baud; 498 unsigned long flags; 499 u16 cval, scval, prev_mode; 500 int bits, sbits; 501 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 502 smc_t __iomem *smcp = pinfo->smcp; 503 scc_t __iomem *sccp = pinfo->sccp; 504 int maxidl; 505 506 pr_debug("CPM uart[%d]:set_termios\n", port->line); 507 508 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 509 if (baud < HW_BUF_SPD_THRESHOLD || 510 (pinfo->port.state && pinfo->port.state->port.low_latency)) 511 pinfo->rx_fifosize = 1; 512 else 513 pinfo->rx_fifosize = RX_BUF_SIZE; 514 515 /* MAXIDL is the timeout after which a receive buffer is closed 516 * when not full if no more characters are received. 517 * We calculate it from the baudrate so that the duration is 518 * always the same at standard rates: about 4ms. 519 */ 520 maxidl = baud / 2400; 521 if (maxidl < 1) 522 maxidl = 1; 523 if (maxidl > 0x10) 524 maxidl = 0x10; 525 526 /* Character length programmed into the mode register is the 527 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, 528 * 1 or 2 stop bits, minus 1. 529 * The value 'bits' counts this for us. 530 */ 531 cval = 0; 532 scval = 0; 533 534 /* byte size */ 535 switch (termios->c_cflag & CSIZE) { 536 case CS5: 537 bits = 5; 538 break; 539 case CS6: 540 bits = 6; 541 break; 542 case CS7: 543 bits = 7; 544 break; 545 case CS8: 546 bits = 8; 547 break; 548 /* Never happens, but GCC is too dumb to figure it out */ 549 default: 550 bits = 8; 551 break; 552 } 553 sbits = bits - 5; 554 555 if (termios->c_cflag & CSTOPB) { 556 cval |= SMCMR_SL; /* Two stops */ 557 scval |= SCU_PSMR_SL; 558 bits++; 559 } 560 561 if (termios->c_cflag & PARENB) { 562 cval |= SMCMR_PEN; 563 scval |= SCU_PSMR_PEN; 564 bits++; 565 if (!(termios->c_cflag & PARODD)) { 566 cval |= SMCMR_PM_EVEN; 567 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); 568 } 569 } 570 571 /* 572 * Update the timeout 573 */ 574 uart_update_timeout(port, termios->c_cflag, baud); 575 576 /* 577 * Set up parity check flag 578 */ 579#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) 580 581 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); 582 if (termios->c_iflag & INPCK) 583 port->read_status_mask |= BD_SC_FR | BD_SC_PR; 584 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) 585 port->read_status_mask |= BD_SC_BR; 586 587 /* 588 * Characters to ignore 589 */ 590 port->ignore_status_mask = 0; 591 if (termios->c_iflag & IGNPAR) 592 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; 593 if (termios->c_iflag & IGNBRK) { 594 port->ignore_status_mask |= BD_SC_BR; 595 /* 596 * If we're ignore parity and break indicators, ignore 597 * overruns too. (For real raw support). 598 */ 599 if (termios->c_iflag & IGNPAR) 600 port->ignore_status_mask |= BD_SC_OV; 601 } 602 /* 603 * !!! ignore all characters if CREAD is not set 604 */ 605 if ((termios->c_cflag & CREAD) == 0) 606 port->read_status_mask &= ~BD_SC_EMPTY; 607 608 spin_lock_irqsave(&port->lock, flags); 609 610 /* Start bit has not been added (so don't, because we would just 611 * subtract it later), and we need to add one for the number of 612 * stops bits (there is always at least one). 613 */ 614 bits++; 615 if (IS_SMC(pinfo)) { 616 /* 617 * MRBLR can be changed while an SMC/SCC is operating only 618 * if it is done in a single bus cycle with one 16-bit move 619 * (not two 8-bit bus cycles back-to-back). This occurs when 620 * the cp shifts control to the next RxBD, so the change does 621 * not take effect immediately. To guarantee the exact RxBD 622 * on which the change occurs, change MRBLR only while the 623 * SMC/SCC receiver is disabled. 624 */ 625 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize); 626 out_be16(&pinfo->smcup->smc_maxidl, maxidl); 627 628 /* Set the mode register. We want to keep a copy of the 629 * enables, because we want to put them back if they were 630 * present. 631 */ 632 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN); 633 /* Output in *one* operation, so we don't interrupt RX/TX if they 634 * were already enabled. */ 635 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval | 636 SMCMR_SM_UART | prev_mode); 637 } else { 638 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 639 out_be16(&pinfo->sccup->scc_maxidl, maxidl); 640 out_be16(&sccp->scc_psmr, (sbits << 12) | scval); 641 } 642 643 if (pinfo->clk) 644 clk_set_rate(pinfo->clk, baud); 645 else 646 cpm_set_brg(pinfo->brg - 1, baud); 647 spin_unlock_irqrestore(&port->lock, flags); 648} 649 650static const char *cpm_uart_type(struct uart_port *port) 651{ 652 pr_debug("CPM uart[%d]:uart_type\n", port->line); 653 654 return port->type == PORT_CPM ? "CPM UART" : NULL; 655} 656 657/* 658 * verify the new serial_struct (for TIOCSSERIAL). 659 */ 660static int cpm_uart_verify_port(struct uart_port *port, 661 struct serial_struct *ser) 662{ 663 int ret = 0; 664 665 pr_debug("CPM uart[%d]:verify_port\n", port->line); 666 667 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) 668 ret = -EINVAL; 669 if (ser->irq < 0 || ser->irq >= nr_irqs) 670 ret = -EINVAL; 671 if (ser->baud_base < 9600) 672 ret = -EINVAL; 673 return ret; 674} 675 676/* 677 * Transmit characters, refill buffer descriptor, if possible 678 */ 679static int cpm_uart_tx_pump(struct uart_port *port) 680{ 681 cbd_t __iomem *bdp; 682 u8 *p; 683 int count; 684 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 685 struct circ_buf *xmit = &port->state->xmit; 686 687 /* Handle xon/xoff */ 688 if (port->x_char) { 689 /* Pick next descriptor and fill from buffer */ 690 bdp = pinfo->tx_cur; 691 692 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 693 694 *p++ = port->x_char; 695 696 out_be16(&bdp->cbd_datlen, 1); 697 setbits16(&bdp->cbd_sc, BD_SC_READY); 698 /* Get next BD. */ 699 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 700 bdp = pinfo->tx_bd_base; 701 else 702 bdp++; 703 pinfo->tx_cur = bdp; 704 705 port->icount.tx++; 706 port->x_char = 0; 707 return 1; 708 } 709 710 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 711 cpm_uart_stop_tx(port); 712 return 0; 713 } 714 715 /* Pick next descriptor and fill from buffer */ 716 bdp = pinfo->tx_cur; 717 718 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && 719 xmit->tail != xmit->head) { 720 count = 0; 721 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 722 while (count < pinfo->tx_fifosize) { 723 *p++ = xmit->buf[xmit->tail]; 724 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 725 port->icount.tx++; 726 count++; 727 if (xmit->head == xmit->tail) 728 break; 729 } 730 out_be16(&bdp->cbd_datlen, count); 731 setbits16(&bdp->cbd_sc, BD_SC_READY); 732 /* Get next BD. */ 733 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 734 bdp = pinfo->tx_bd_base; 735 else 736 bdp++; 737 } 738 pinfo->tx_cur = bdp; 739 740 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 741 uart_write_wakeup(port); 742 743 if (uart_circ_empty(xmit)) { 744 cpm_uart_stop_tx(port); 745 return 0; 746 } 747 748 return 1; 749} 750 751/* 752 * init buffer descriptors 753 */ 754static void cpm_uart_initbd(struct uart_cpm_port *pinfo) 755{ 756 int i; 757 u8 *mem_addr; 758 cbd_t __iomem *bdp; 759 760 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); 761 762 /* Set the physical address of the host memory 763 * buffers in the buffer descriptors, and the 764 * virtual address for us to work with. 765 */ 766 mem_addr = pinfo->mem_addr; 767 bdp = pinfo->rx_cur = pinfo->rx_bd_base; 768 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { 769 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 770 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); 771 mem_addr += pinfo->rx_fifosize; 772 } 773 774 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 775 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); 776 777 /* Set the physical address of the host memory 778 * buffers in the buffer descriptors, and the 779 * virtual address for us to work with. 780 */ 781 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); 782 bdp = pinfo->tx_cur = pinfo->tx_bd_base; 783 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { 784 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 785 out_be16(&bdp->cbd_sc, BD_SC_INTRPT); 786 mem_addr += pinfo->tx_fifosize; 787 } 788 789 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 790 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); 791} 792 793static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) 794{ 795 scc_t __iomem *scp; 796 scc_uart_t __iomem *sup; 797 798 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); 799 800 scp = pinfo->sccp; 801 sup = pinfo->sccup; 802 803 /* Store address */ 804 out_be16(&pinfo->sccup->scc_genscc.scc_rbase, 805 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 806 out_be16(&pinfo->sccup->scc_genscc.scc_tbase, 807 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 808 809 /* Set up the uart parameters in the 810 * parameter ram. 811 */ 812 813 cpm_set_scc_fcr(sup); 814 815 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 816 out_be16(&sup->scc_maxidl, 0x10); 817 out_be16(&sup->scc_brkcr, 1); 818 out_be16(&sup->scc_parec, 0); 819 out_be16(&sup->scc_frmec, 0); 820 out_be16(&sup->scc_nosec, 0); 821 out_be16(&sup->scc_brkec, 0); 822 out_be16(&sup->scc_uaddr1, 0); 823 out_be16(&sup->scc_uaddr2, 0); 824 out_be16(&sup->scc_toseq, 0); 825 out_be16(&sup->scc_char1, 0x8000); 826 out_be16(&sup->scc_char2, 0x8000); 827 out_be16(&sup->scc_char3, 0x8000); 828 out_be16(&sup->scc_char4, 0x8000); 829 out_be16(&sup->scc_char5, 0x8000); 830 out_be16(&sup->scc_char6, 0x8000); 831 out_be16(&sup->scc_char7, 0x8000); 832 out_be16(&sup->scc_char8, 0x8000); 833 out_be16(&sup->scc_rccm, 0xc0ff); 834 835 /* Send the CPM an initialize command. 836 */ 837 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 838 839 /* Set UART mode, 8 bit, no parity, one stop. 840 * Enable receive and transmit. 841 */ 842 out_be32(&scp->scc_gsmrh, 0); 843 out_be32(&scp->scc_gsmrl, 844 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); 845 846 /* Enable rx interrupts and clear all pending events. */ 847 out_be16(&scp->scc_sccm, 0); 848 out_be16(&scp->scc_scce, 0xffff); 849 out_be16(&scp->scc_dsr, 0x7e7e); 850 out_be16(&scp->scc_psmr, 0x3000); 851 852 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 853} 854 855static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) 856{ 857 smc_t __iomem *sp; 858 smc_uart_t __iomem *up; 859 860 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); 861 862 sp = pinfo->smcp; 863 up = pinfo->smcup; 864 865 /* Store address */ 866 out_be16(&pinfo->smcup->smc_rbase, 867 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 868 out_be16(&pinfo->smcup->smc_tbase, 869 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 870 871/* 872 * In case SMC1 is being relocated... 873 */ 874#if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH) 875 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); 876 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); 877 out_be32(&up->smc_rstate, 0); 878 out_be32(&up->smc_tstate, 0); 879 out_be16(&up->smc_brkcr, 1); /* number of break chars */ 880 out_be16(&up->smc_brkec, 0); 881#endif 882 883 /* Set up the uart parameters in the 884 * parameter ram. 885 */ 886 cpm_set_smc_fcr(up); 887 888 /* Using idle character time requires some additional tuning. */ 889 out_be16(&up->smc_mrblr, pinfo->rx_fifosize); 890 out_be16(&up->smc_maxidl, 0x10); 891 out_be16(&up->smc_brklen, 0); 892 out_be16(&up->smc_brkec, 0); 893 out_be16(&up->smc_brkcr, 1); 894 895 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 896 897 /* Set UART mode, 8 bit, no parity, one stop. 898 * Enable receive and transmit. 899 */ 900 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); 901 902 /* Enable only rx interrupts clear all pending events. */ 903 out_8(&sp->smc_smcm, 0); 904 out_8(&sp->smc_smce, 0xff); 905 906 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 907} 908 909/* 910 * Initialize port. This is called from early_console stuff 911 * so we have to be careful here ! 912 */ 913static int cpm_uart_request_port(struct uart_port *port) 914{ 915 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 916 int ret; 917 918 pr_debug("CPM uart[%d]:request port\n", port->line); 919 920 if (pinfo->flags & FLAG_CONSOLE) 921 return 0; 922 923 if (IS_SMC(pinfo)) { 924 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 925 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 926 } else { 927 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 928 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 929 } 930 931 ret = cpm_uart_allocbuf(pinfo, 0); 932 933 if (ret) 934 return ret; 935 936 cpm_uart_initbd(pinfo); 937 if (IS_SMC(pinfo)) 938 cpm_uart_init_smc(pinfo); 939 else 940 cpm_uart_init_scc(pinfo); 941 942 return 0; 943} 944 945static void cpm_uart_release_port(struct uart_port *port) 946{ 947 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 948 949 if (!(pinfo->flags & FLAG_CONSOLE)) 950 cpm_uart_freebuf(pinfo); 951} 952 953/* 954 * Configure/autoconfigure the port. 955 */ 956static void cpm_uart_config_port(struct uart_port *port, int flags) 957{ 958 pr_debug("CPM uart[%d]:config_port\n", port->line); 959 960 if (flags & UART_CONFIG_TYPE) { 961 port->type = PORT_CPM; 962 cpm_uart_request_port(port); 963 } 964} 965 966#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE) 967/* 968 * Write a string to the serial port 969 * Note that this is called with interrupts already disabled 970 */ 971static void cpm_uart_early_write(struct uart_cpm_port *pinfo, 972 const char *string, u_int count) 973{ 974 unsigned int i; 975 cbd_t __iomem *bdp, *bdbase; 976 unsigned char *cpm_outp_addr; 977 978 /* Get the address of the host memory buffer. 979 */ 980 bdp = pinfo->tx_cur; 981 bdbase = pinfo->tx_bd_base; 982 983 /* 984 * Now, do each character. This is not as bad as it looks 985 * since this is a holding FIFO and not a transmitting FIFO. 986 * We could add the complexity of filling the entire transmit 987 * buffer, but we would just wait longer between accesses...... 988 */ 989 for (i = 0; i < count; i++, string++) { 990 /* Wait for transmitter fifo to empty. 991 * Ready indicates output is ready, and xmt is doing 992 * that, not that it is ready for us to send. 993 */ 994 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 995 ; 996 997 /* Send the character out. 998 * If the buffer address is in the CPM DPRAM, don't 999 * convert it. 1000 */ 1001 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1002 pinfo); 1003 *cpm_outp_addr = *string; 1004 1005 out_be16(&bdp->cbd_datlen, 1); 1006 setbits16(&bdp->cbd_sc, BD_SC_READY); 1007 1008 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1009 bdp = bdbase; 1010 else 1011 bdp++; 1012 1013 /* if a LF, also do CR... */ 1014 if (*string == 10) { 1015 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1016 ; 1017 1018 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1019 pinfo); 1020 *cpm_outp_addr = 13; 1021 1022 out_be16(&bdp->cbd_datlen, 1); 1023 setbits16(&bdp->cbd_sc, BD_SC_READY); 1024 1025 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1026 bdp = bdbase; 1027 else 1028 bdp++; 1029 } 1030 } 1031 1032 /* 1033 * Finally, Wait for transmitter & holding register to empty 1034 * and restore the IER 1035 */ 1036 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1037 ; 1038 1039 pinfo->tx_cur = bdp; 1040} 1041#endif 1042 1043#ifdef CONFIG_CONSOLE_POLL 1044/* Serial polling routines for writing and reading from the uart while 1045 * in an interrupt or debug context. 1046 */ 1047 1048#define GDB_BUF_SIZE 512 /* power of 2, please */ 1049 1050static char poll_buf[GDB_BUF_SIZE]; 1051static char *pollp; 1052static int poll_chars; 1053 1054static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo) 1055{ 1056 u_char c, *cp; 1057 volatile cbd_t *bdp; 1058 int i; 1059 1060 /* Get the address of the host memory buffer. 1061 */ 1062 bdp = pinfo->rx_cur; 1063 while (bdp->cbd_sc & BD_SC_EMPTY) 1064 ; 1065 1066 /* If the buffer address is in the CPM DPRAM, don't 1067 * convert it. 1068 */ 1069 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); 1070 1071 if (obuf) { 1072 i = c = bdp->cbd_datlen; 1073 while (i-- > 0) 1074 *obuf++ = *cp++; 1075 } else 1076 c = *cp; 1077 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); 1078 bdp->cbd_sc |= BD_SC_EMPTY; 1079 1080 if (bdp->cbd_sc & BD_SC_WRAP) 1081 bdp = pinfo->rx_bd_base; 1082 else 1083 bdp++; 1084 pinfo->rx_cur = (cbd_t *)bdp; 1085 1086 return (int)c; 1087} 1088 1089static int cpm_get_poll_char(struct uart_port *port) 1090{ 1091 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 1092 1093 if (!serial_polled) { 1094 serial_polled = 1; 1095 poll_chars = 0; 1096 } 1097 if (poll_chars <= 0) { 1098 poll_chars = poll_wait_key(poll_buf, pinfo); 1099 pollp = poll_buf; 1100 } 1101 poll_chars--; 1102 return *pollp++; 1103} 1104 1105static void cpm_put_poll_char(struct uart_port *port, 1106 unsigned char c) 1107{ 1108 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 1109 static char ch[2]; 1110 1111 ch[0] = (char)c; 1112 cpm_uart_early_write(pinfo, ch, 1); 1113} 1114#endif /* CONFIG_CONSOLE_POLL */ 1115 1116static struct uart_ops cpm_uart_pops = { 1117 .tx_empty = cpm_uart_tx_empty, 1118 .set_mctrl = cpm_uart_set_mctrl, 1119 .get_mctrl = cpm_uart_get_mctrl, 1120 .stop_tx = cpm_uart_stop_tx, 1121 .start_tx = cpm_uart_start_tx, 1122 .stop_rx = cpm_uart_stop_rx, 1123 .enable_ms = cpm_uart_enable_ms, 1124 .break_ctl = cpm_uart_break_ctl, 1125 .startup = cpm_uart_startup, 1126 .shutdown = cpm_uart_shutdown, 1127 .set_termios = cpm_uart_set_termios, 1128 .type = cpm_uart_type, 1129 .release_port = cpm_uart_release_port, 1130 .request_port = cpm_uart_request_port, 1131 .config_port = cpm_uart_config_port, 1132 .verify_port = cpm_uart_verify_port, 1133#ifdef CONFIG_CONSOLE_POLL 1134 .poll_get_char = cpm_get_poll_char, 1135 .poll_put_char = cpm_put_poll_char, 1136#endif 1137}; 1138 1139struct uart_cpm_port cpm_uart_ports[UART_NR]; 1140 1141static int cpm_uart_init_port(struct device_node *np, 1142 struct uart_cpm_port *pinfo) 1143{ 1144 const u32 *data; 1145 void __iomem *mem, *pram; 1146 int len; 1147 int ret; 1148 int i; 1149 1150 data = of_get_property(np, "clock", NULL); 1151 if (data) { 1152 struct clk *clk = clk_get(NULL, (const char*)data); 1153 if (!IS_ERR(clk)) 1154 pinfo->clk = clk; 1155 } 1156 if (!pinfo->clk) { 1157 data = of_get_property(np, "fsl,cpm-brg", &len); 1158 if (!data || len != 4) { 1159 printk(KERN_ERR "CPM UART %s has no/invalid " 1160 "fsl,cpm-brg property.\n", np->name); 1161 return -EINVAL; 1162 } 1163 pinfo->brg = *data; 1164 } 1165 1166 data = of_get_property(np, "fsl,cpm-command", &len); 1167 if (!data || len != 4) { 1168 printk(KERN_ERR "CPM UART %s has no/invalid " 1169 "fsl,cpm-command property.\n", np->name); 1170 return -EINVAL; 1171 } 1172 pinfo->command = *data; 1173 1174 mem = of_iomap(np, 0); 1175 if (!mem) 1176 return -ENOMEM; 1177 1178 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || 1179 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { 1180 pinfo->sccp = mem; 1181 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); 1182 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || 1183 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { 1184 pinfo->flags |= FLAG_SMC; 1185 pinfo->smcp = mem; 1186 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); 1187 } else { 1188 ret = -ENODEV; 1189 goto out_mem; 1190 } 1191 1192 if (!pram) { 1193 ret = -ENOMEM; 1194 goto out_mem; 1195 } 1196 1197 pinfo->tx_nrfifos = TX_NUM_FIFO; 1198 pinfo->tx_fifosize = TX_BUF_SIZE; 1199 pinfo->rx_nrfifos = RX_NUM_FIFO; 1200 pinfo->rx_fifosize = RX_BUF_SIZE; 1201 1202 pinfo->port.uartclk = ppc_proc_freq; 1203 pinfo->port.mapbase = (unsigned long)mem; 1204 pinfo->port.type = PORT_CPM; 1205 pinfo->port.ops = &cpm_uart_pops, 1206 pinfo->port.iotype = UPIO_MEM; 1207 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; 1208 spin_lock_init(&pinfo->port.lock); 1209 1210 pinfo->port.irq = of_irq_to_resource(np, 0, NULL); 1211 if (pinfo->port.irq == NO_IRQ) { 1212 ret = -EINVAL; 1213 goto out_pram; 1214 } 1215 1216 for (i = 0; i < NUM_GPIOS; i++) 1217 pinfo->gpios[i] = of_get_gpio(np, i); 1218 1219#ifdef CONFIG_PPC_EARLY_DEBUG_CPM 1220 udbg_putc = NULL; 1221#endif 1222 1223 return cpm_uart_request_port(&pinfo->port); 1224 1225out_pram: 1226 cpm_uart_unmap_pram(pinfo, pram); 1227out_mem: 1228 iounmap(mem); 1229 return ret; 1230} 1231 1232#ifdef CONFIG_SERIAL_CPM_CONSOLE 1233/* 1234 * Print a string to the serial port trying not to disturb 1235 * any possible real use of the port... 1236 * 1237 * Note that this is called with interrupts already disabled 1238 */ 1239static void cpm_uart_console_write(struct console *co, const char *s, 1240 u_int count) 1241{ 1242 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; 1243 unsigned long flags; 1244 int nolock = oops_in_progress; 1245 1246 if (unlikely(nolock)) { 1247 local_irq_save(flags); 1248 } else { 1249 spin_lock_irqsave(&pinfo->port.lock, flags); 1250 } 1251 1252 cpm_uart_early_write(pinfo, s, count); 1253 1254 if (unlikely(nolock)) { 1255 local_irq_restore(flags); 1256 } else { 1257 spin_unlock_irqrestore(&pinfo->port.lock, flags); 1258 } 1259} 1260 1261 1262static int __init cpm_uart_console_setup(struct console *co, char *options) 1263{ 1264 int baud = 38400; 1265 int bits = 8; 1266 int parity = 'n'; 1267 int flow = 'n'; 1268 int ret; 1269 struct uart_cpm_port *pinfo; 1270 struct uart_port *port; 1271 1272 struct device_node *np = NULL; 1273 int i = 0; 1274 1275 if (co->index >= UART_NR) { 1276 printk(KERN_ERR "cpm_uart: console index %d too high\n", 1277 co->index); 1278 return -ENODEV; 1279 } 1280 1281 do { 1282 np = of_find_node_by_type(np, "serial"); 1283 if (!np) 1284 return -ENODEV; 1285 1286 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && 1287 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && 1288 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && 1289 !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) 1290 i--; 1291 } while (i++ != co->index); 1292 1293 pinfo = &cpm_uart_ports[co->index]; 1294 1295 pinfo->flags |= FLAG_CONSOLE; 1296 port = &pinfo->port; 1297 1298 ret = cpm_uart_init_port(np, pinfo); 1299 of_node_put(np); 1300 if (ret) 1301 return ret; 1302 1303 if (options) { 1304 uart_parse_options(options, &baud, &parity, &bits, &flow); 1305 } else { 1306 if ((baud = uart_baudrate()) == -1) 1307 baud = 9600; 1308 } 1309 1310 if (IS_SMC(pinfo)) { 1311 out_be16(&pinfo->smcup->smc_brkcr, 0); 1312 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 1313 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 1314 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 1315 } else { 1316 out_be16(&pinfo->sccup->scc_brkcr, 0); 1317 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 1318 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 1319 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 1320 } 1321 1322 ret = cpm_uart_allocbuf(pinfo, 1); 1323 1324 if (ret) 1325 return ret; 1326 1327 cpm_uart_initbd(pinfo); 1328 1329 if (IS_SMC(pinfo)) 1330 cpm_uart_init_smc(pinfo); 1331 else 1332 cpm_uart_init_scc(pinfo); 1333 1334 uart_set_options(port, co, baud, parity, bits, flow); 1335 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 1336 1337 return 0; 1338} 1339 1340static struct uart_driver cpm_reg; 1341static struct console cpm_scc_uart_console = { 1342 .name = "ttyCPM", 1343 .write = cpm_uart_console_write, 1344 .device = uart_console_device, 1345 .setup = cpm_uart_console_setup, 1346 .flags = CON_PRINTBUFFER, 1347 .index = -1, 1348 .data = &cpm_reg, 1349}; 1350 1351static int __init cpm_uart_console_init(void) 1352{ 1353 register_console(&cpm_scc_uart_console); 1354 return 0; 1355} 1356 1357console_initcall(cpm_uart_console_init); 1358 1359#define CPM_UART_CONSOLE &cpm_scc_uart_console 1360#else 1361#define CPM_UART_CONSOLE NULL 1362#endif 1363 1364static struct uart_driver cpm_reg = { 1365 .owner = THIS_MODULE, 1366 .driver_name = "ttyCPM", 1367 .dev_name = "ttyCPM", 1368 .major = SERIAL_CPM_MAJOR, 1369 .minor = SERIAL_CPM_MINOR, 1370 .cons = CPM_UART_CONSOLE, 1371 .nr = UART_NR, 1372}; 1373 1374static int probe_index; 1375 1376static int cpm_uart_probe(struct platform_device *ofdev) 1377{ 1378 int index = probe_index++; 1379 struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; 1380 int ret; 1381 1382 pinfo->port.line = index; 1383 1384 if (index >= UART_NR) 1385 return -ENODEV; 1386 1387 dev_set_drvdata(&ofdev->dev, pinfo); 1388 1389 /* initialize the device pointer for the port */ 1390 pinfo->port.dev = &ofdev->dev; 1391 1392 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo); 1393 if (ret) 1394 return ret; 1395 1396 return uart_add_one_port(&cpm_reg, &pinfo->port); 1397} 1398 1399static int cpm_uart_remove(struct platform_device *ofdev) 1400{ 1401 struct uart_cpm_port *pinfo = dev_get_drvdata(&ofdev->dev); 1402 return uart_remove_one_port(&cpm_reg, &pinfo->port); 1403} 1404 1405static struct of_device_id cpm_uart_match[] = { 1406 { 1407 .compatible = "fsl,cpm1-smc-uart", 1408 }, 1409 { 1410 .compatible = "fsl,cpm1-scc-uart", 1411 }, 1412 { 1413 .compatible = "fsl,cpm2-smc-uart", 1414 }, 1415 { 1416 .compatible = "fsl,cpm2-scc-uart", 1417 }, 1418 {} 1419}; 1420 1421static struct platform_driver cpm_uart_driver = { 1422 .driver = { 1423 .name = "cpm_uart", 1424 .owner = THIS_MODULE, 1425 .of_match_table = cpm_uart_match, 1426 }, 1427 .probe = cpm_uart_probe, 1428 .remove = cpm_uart_remove, 1429 }; 1430 1431static int __init cpm_uart_init(void) 1432{ 1433 int ret = uart_register_driver(&cpm_reg); 1434 if (ret) 1435 return ret; 1436 1437 ret = platform_driver_register(&cpm_uart_driver); 1438 if (ret) 1439 uart_unregister_driver(&cpm_reg); 1440 1441 return ret; 1442} 1443 1444static void __exit cpm_uart_exit(void) 1445{ 1446 platform_driver_unregister(&cpm_uart_driver); 1447 uart_unregister_driver(&cpm_reg); 1448} 1449 1450module_init(cpm_uart_init); 1451module_exit(cpm_uart_exit); 1452 1453MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); 1454MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); 1455MODULE_LICENSE("GPL"); 1456MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); 1457