cpm_uart_core.c revision fbbb9d9646f04768d0176f75e7fc93d29457b5db
1/* 2 * Driver for CPM (SCC/SMC) serial ports; core driver 3 * 4 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek 5 * Based on ppc8xx.c by Thomas Gleixner 6 * Based on drivers/serial/amba.c by Russell King 7 * 8 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) 9 * Pantelis Antoniou (panto@intracom.gr) (CPM1) 10 * 11 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. 12 * (C) 2004 Intracom, S.A. 13 * (C) 2005-2006 MontaVista Software, Inc. 14 * Vitaly Bordug <vbordug@ru.mvista.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 29 * 30 */ 31 32#include <linux/module.h> 33#include <linux/tty.h> 34#include <linux/tty_flip.h> 35#include <linux/ioport.h> 36#include <linux/init.h> 37#include <linux/serial.h> 38#include <linux/console.h> 39#include <linux/sysrq.h> 40#include <linux/device.h> 41#include <linux/bootmem.h> 42#include <linux/dma-mapping.h> 43#include <linux/fs_uart_pd.h> 44#include <linux/of_platform.h> 45#include <linux/gpio.h> 46#include <linux/of_gpio.h> 47#include <linux/clk.h> 48 49#include <asm/io.h> 50#include <asm/irq.h> 51#include <asm/delay.h> 52#include <asm/fs_pd.h> 53#include <asm/udbg.h> 54 55#if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 56#define SUPPORT_SYSRQ 57#endif 58 59#include <linux/serial_core.h> 60#include <linux/kernel.h> 61 62#include "cpm_uart.h" 63 64 65/**************************************************************/ 66 67static int cpm_uart_tx_pump(struct uart_port *port); 68static void cpm_uart_init_smc(struct uart_cpm_port *pinfo); 69static void cpm_uart_init_scc(struct uart_cpm_port *pinfo); 70static void cpm_uart_initbd(struct uart_cpm_port *pinfo); 71 72/**************************************************************/ 73 74#define HW_BUF_SPD_THRESHOLD 2400 75 76/* 77 * Check, if transmit buffers are processed 78*/ 79static unsigned int cpm_uart_tx_empty(struct uart_port *port) 80{ 81 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 82 cbd_t __iomem *bdp = pinfo->tx_bd_base; 83 int ret = 0; 84 85 while (1) { 86 if (in_be16(&bdp->cbd_sc) & BD_SC_READY) 87 break; 88 89 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { 90 ret = TIOCSER_TEMT; 91 break; 92 } 93 bdp++; 94 } 95 96 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); 97 98 return ret; 99} 100 101static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 102{ 103 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 104 105 if (pinfo->gpios[GPIO_RTS] >= 0) 106 gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); 107 108 if (pinfo->gpios[GPIO_DTR] >= 0) 109 gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR)); 110} 111 112static unsigned int cpm_uart_get_mctrl(struct uart_port *port) 113{ 114 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 115 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 116 117 if (pinfo->gpios[GPIO_CTS] >= 0) { 118 if (gpio_get_value(pinfo->gpios[GPIO_CTS])) 119 mctrl &= ~TIOCM_CTS; 120 } 121 122 if (pinfo->gpios[GPIO_DSR] >= 0) { 123 if (gpio_get_value(pinfo->gpios[GPIO_DSR])) 124 mctrl &= ~TIOCM_DSR; 125 } 126 127 if (pinfo->gpios[GPIO_DCD] >= 0) { 128 if (gpio_get_value(pinfo->gpios[GPIO_DCD])) 129 mctrl &= ~TIOCM_CAR; 130 } 131 132 if (pinfo->gpios[GPIO_RI] >= 0) { 133 if (!gpio_get_value(pinfo->gpios[GPIO_RI])) 134 mctrl |= TIOCM_RNG; 135 } 136 137 return mctrl; 138} 139 140/* 141 * Stop transmitter 142 */ 143static void cpm_uart_stop_tx(struct uart_port *port) 144{ 145 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 146 smc_t __iomem *smcp = pinfo->smcp; 147 scc_t __iomem *sccp = pinfo->sccp; 148 149 pr_debug("CPM uart[%d]:stop tx\n", port->line); 150 151 if (IS_SMC(pinfo)) 152 clrbits8(&smcp->smc_smcm, SMCM_TX); 153 else 154 clrbits16(&sccp->scc_sccm, UART_SCCM_TX); 155} 156 157/* 158 * Start transmitter 159 */ 160static void cpm_uart_start_tx(struct uart_port *port) 161{ 162 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 163 smc_t __iomem *smcp = pinfo->smcp; 164 scc_t __iomem *sccp = pinfo->sccp; 165 166 pr_debug("CPM uart[%d]:start tx\n", port->line); 167 168 if (IS_SMC(pinfo)) { 169 if (in_8(&smcp->smc_smcm) & SMCM_TX) 170 return; 171 } else { 172 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) 173 return; 174 } 175 176 if (cpm_uart_tx_pump(port) != 0) { 177 if (IS_SMC(pinfo)) { 178 setbits8(&smcp->smc_smcm, SMCM_TX); 179 } else { 180 setbits16(&sccp->scc_sccm, UART_SCCM_TX); 181 } 182 } 183} 184 185/* 186 * Stop receiver 187 */ 188static void cpm_uart_stop_rx(struct uart_port *port) 189{ 190 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 191 smc_t __iomem *smcp = pinfo->smcp; 192 scc_t __iomem *sccp = pinfo->sccp; 193 194 pr_debug("CPM uart[%d]:stop rx\n", port->line); 195 196 if (IS_SMC(pinfo)) 197 clrbits8(&smcp->smc_smcm, SMCM_RX); 198 else 199 clrbits16(&sccp->scc_sccm, UART_SCCM_RX); 200} 201 202/* 203 * Enable Modem status interrupts 204 */ 205static void cpm_uart_enable_ms(struct uart_port *port) 206{ 207 pr_debug("CPM uart[%d]:enable ms\n", port->line); 208} 209 210/* 211 * Generate a break. 212 */ 213static void cpm_uart_break_ctl(struct uart_port *port, int break_state) 214{ 215 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 216 217 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, 218 break_state); 219 220 if (break_state) 221 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 222 else 223 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 224} 225 226/* 227 * Transmit characters, refill buffer descriptor, if possible 228 */ 229static void cpm_uart_int_tx(struct uart_port *port) 230{ 231 pr_debug("CPM uart[%d]:TX INT\n", port->line); 232 233 cpm_uart_tx_pump(port); 234} 235 236#ifdef CONFIG_CONSOLE_POLL 237static int serial_polled; 238#endif 239 240/* 241 * Receive characters 242 */ 243static void cpm_uart_int_rx(struct uart_port *port) 244{ 245 int i; 246 unsigned char ch; 247 u8 *cp; 248 struct tty_struct *tty = port->state->port.tty; 249 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 250 cbd_t __iomem *bdp; 251 u16 status; 252 unsigned int flg; 253 254 pr_debug("CPM uart[%d]:RX INT\n", port->line); 255 256 /* Just loop through the closed BDs and copy the characters into 257 * the buffer. 258 */ 259 bdp = pinfo->rx_cur; 260 for (;;) { 261#ifdef CONFIG_CONSOLE_POLL 262 if (unlikely(serial_polled)) { 263 serial_polled = 0; 264 return; 265 } 266#endif 267 /* get status */ 268 status = in_be16(&bdp->cbd_sc); 269 /* If this one is empty, return happy */ 270 if (status & BD_SC_EMPTY) 271 break; 272 273 /* get number of characters, and check spce in flip-buffer */ 274 i = in_be16(&bdp->cbd_datlen); 275 276 /* If we have not enough room in tty flip buffer, then we try 277 * later, which will be the next rx-interrupt or a timeout 278 */ 279 if(tty_buffer_request_room(tty, i) < i) { 280 printk(KERN_WARNING "No room in flip buffer\n"); 281 return; 282 } 283 284 /* get pointer */ 285 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 286 287 /* loop through the buffer */ 288 while (i-- > 0) { 289 ch = *cp++; 290 port->icount.rx++; 291 flg = TTY_NORMAL; 292 293 if (status & 294 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) 295 goto handle_error; 296 if (uart_handle_sysrq_char(port, ch)) 297 continue; 298#ifdef CONFIG_CONSOLE_POLL 299 if (unlikely(serial_polled)) { 300 serial_polled = 0; 301 return; 302 } 303#endif 304 error_return: 305 tty_insert_flip_char(tty, ch, flg); 306 307 } /* End while (i--) */ 308 309 /* This BD is ready to be used again. Clear status. get next */ 310 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | 311 BD_SC_OV | BD_SC_ID); 312 setbits16(&bdp->cbd_sc, BD_SC_EMPTY); 313 314 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 315 bdp = pinfo->rx_bd_base; 316 else 317 bdp++; 318 319 } /* End for (;;) */ 320 321 /* Write back buffer pointer */ 322 pinfo->rx_cur = bdp; 323 324 /* activate BH processing */ 325 tty_flip_buffer_push(tty); 326 327 return; 328 329 /* Error processing */ 330 331 handle_error: 332 /* Statistics */ 333 if (status & BD_SC_BR) 334 port->icount.brk++; 335 if (status & BD_SC_PR) 336 port->icount.parity++; 337 if (status & BD_SC_FR) 338 port->icount.frame++; 339 if (status & BD_SC_OV) 340 port->icount.overrun++; 341 342 /* Mask out ignored conditions */ 343 status &= port->read_status_mask; 344 345 /* Handle the remaining ones */ 346 if (status & BD_SC_BR) 347 flg = TTY_BREAK; 348 else if (status & BD_SC_PR) 349 flg = TTY_PARITY; 350 else if (status & BD_SC_FR) 351 flg = TTY_FRAME; 352 353 /* overrun does not affect the current character ! */ 354 if (status & BD_SC_OV) { 355 ch = 0; 356 flg = TTY_OVERRUN; 357 /* We skip this buffer */ 358 /* CHECK: Is really nothing senseful there */ 359 /* ASSUMPTION: it contains nothing valid */ 360 i = 0; 361 } 362#ifdef SUPPORT_SYSRQ 363 port->sysrq = 0; 364#endif 365 goto error_return; 366} 367 368/* 369 * Asynchron mode interrupt handler 370 */ 371static irqreturn_t cpm_uart_int(int irq, void *data) 372{ 373 u8 events; 374 struct uart_port *port = data; 375 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 376 smc_t __iomem *smcp = pinfo->smcp; 377 scc_t __iomem *sccp = pinfo->sccp; 378 379 pr_debug("CPM uart[%d]:IRQ\n", port->line); 380 381 if (IS_SMC(pinfo)) { 382 events = in_8(&smcp->smc_smce); 383 out_8(&smcp->smc_smce, events); 384 if (events & SMCM_BRKE) 385 uart_handle_break(port); 386 if (events & SMCM_RX) 387 cpm_uart_int_rx(port); 388 if (events & SMCM_TX) 389 cpm_uart_int_tx(port); 390 } else { 391 events = in_be16(&sccp->scc_scce); 392 out_be16(&sccp->scc_scce, events); 393 if (events & UART_SCCM_BRKE) 394 uart_handle_break(port); 395 if (events & UART_SCCM_RX) 396 cpm_uart_int_rx(port); 397 if (events & UART_SCCM_TX) 398 cpm_uart_int_tx(port); 399 } 400 return (events) ? IRQ_HANDLED : IRQ_NONE; 401} 402 403static int cpm_uart_startup(struct uart_port *port) 404{ 405 int retval; 406 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 407 408 pr_debug("CPM uart[%d]:startup\n", port->line); 409 410 /* If the port is not the console, make sure rx is disabled. */ 411 if (!(pinfo->flags & FLAG_CONSOLE)) { 412 /* Disable UART rx */ 413 if (IS_SMC(pinfo)) { 414 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN); 415 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 416 } else { 417 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR); 418 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 419 } 420 cpm_uart_initbd(pinfo); 421 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 422 } 423 /* Install interrupt handler. */ 424 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); 425 if (retval) 426 return retval; 427 428 /* Startup rx-int */ 429 if (IS_SMC(pinfo)) { 430 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 431 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); 432 } else { 433 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 434 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); 435 } 436 437 return 0; 438} 439 440inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) 441{ 442 set_current_state(TASK_UNINTERRUPTIBLE); 443 schedule_timeout(pinfo->wait_closing); 444} 445 446/* 447 * Shutdown the uart 448 */ 449static void cpm_uart_shutdown(struct uart_port *port) 450{ 451 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 452 453 pr_debug("CPM uart[%d]:shutdown\n", port->line); 454 455 /* free interrupt handler */ 456 free_irq(port->irq, port); 457 458 /* If the port is not the console, disable Rx and Tx. */ 459 if (!(pinfo->flags & FLAG_CONSOLE)) { 460 /* Wait for all the BDs marked sent */ 461 while(!cpm_uart_tx_empty(port)) { 462 set_current_state(TASK_UNINTERRUPTIBLE); 463 schedule_timeout(2); 464 } 465 466 if (pinfo->wait_closing) 467 cpm_uart_wait_until_send(pinfo); 468 469 /* Stop uarts */ 470 if (IS_SMC(pinfo)) { 471 smc_t __iomem *smcp = pinfo->smcp; 472 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 473 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); 474 } else { 475 scc_t __iomem *sccp = pinfo->sccp; 476 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 477 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 478 } 479 480 /* Shut them really down and reinit buffer descriptors */ 481 if (IS_SMC(pinfo)) { 482 out_be16(&pinfo->smcup->smc_brkcr, 0); 483 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 484 } else { 485 out_be16(&pinfo->sccup->scc_brkcr, 0); 486 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 487 } 488 489 cpm_uart_initbd(pinfo); 490 } 491} 492 493static void cpm_uart_set_termios(struct uart_port *port, 494 struct ktermios *termios, 495 struct ktermios *old) 496{ 497 int baud; 498 unsigned long flags; 499 u16 cval, scval, prev_mode; 500 int bits, sbits; 501 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 502 smc_t __iomem *smcp = pinfo->smcp; 503 scc_t __iomem *sccp = pinfo->sccp; 504 505 pr_debug("CPM uart[%d]:set_termios\n", port->line); 506 507 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 508 if (baud < HW_BUF_SPD_THRESHOLD || 509 (pinfo->port.state && pinfo->port.state->port.tty->low_latency)) 510 pinfo->rx_fifosize = 1; 511 else 512 pinfo->rx_fifosize = RX_BUF_SIZE; 513 514 /* Character length programmed into the mode register is the 515 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, 516 * 1 or 2 stop bits, minus 1. 517 * The value 'bits' counts this for us. 518 */ 519 cval = 0; 520 scval = 0; 521 522 /* byte size */ 523 switch (termios->c_cflag & CSIZE) { 524 case CS5: 525 bits = 5; 526 break; 527 case CS6: 528 bits = 6; 529 break; 530 case CS7: 531 bits = 7; 532 break; 533 case CS8: 534 bits = 8; 535 break; 536 /* Never happens, but GCC is too dumb to figure it out */ 537 default: 538 bits = 8; 539 break; 540 } 541 sbits = bits - 5; 542 543 if (termios->c_cflag & CSTOPB) { 544 cval |= SMCMR_SL; /* Two stops */ 545 scval |= SCU_PSMR_SL; 546 bits++; 547 } 548 549 if (termios->c_cflag & PARENB) { 550 cval |= SMCMR_PEN; 551 scval |= SCU_PSMR_PEN; 552 bits++; 553 if (!(termios->c_cflag & PARODD)) { 554 cval |= SMCMR_PM_EVEN; 555 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); 556 } 557 } 558 559 /* 560 * Update the timeout 561 */ 562 uart_update_timeout(port, termios->c_cflag, baud); 563 564 /* 565 * Set up parity check flag 566 */ 567#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) 568 569 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); 570 if (termios->c_iflag & INPCK) 571 port->read_status_mask |= BD_SC_FR | BD_SC_PR; 572 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) 573 port->read_status_mask |= BD_SC_BR; 574 575 /* 576 * Characters to ignore 577 */ 578 port->ignore_status_mask = 0; 579 if (termios->c_iflag & IGNPAR) 580 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; 581 if (termios->c_iflag & IGNBRK) { 582 port->ignore_status_mask |= BD_SC_BR; 583 /* 584 * If we're ignore parity and break indicators, ignore 585 * overruns too. (For real raw support). 586 */ 587 if (termios->c_iflag & IGNPAR) 588 port->ignore_status_mask |= BD_SC_OV; 589 } 590 /* 591 * !!! ignore all characters if CREAD is not set 592 */ 593 if ((termios->c_cflag & CREAD) == 0) 594 port->read_status_mask &= ~BD_SC_EMPTY; 595 596 spin_lock_irqsave(&port->lock, flags); 597 598 /* Start bit has not been added (so don't, because we would just 599 * subtract it later), and we need to add one for the number of 600 * stops bits (there is always at least one). 601 */ 602 bits++; 603 if (IS_SMC(pinfo)) { 604 /* 605 * MRBLR can be changed while an SMC/SCC is operating only 606 * if it is done in a single bus cycle with one 16-bit move 607 * (not two 8-bit bus cycles back-to-back). This occurs when 608 * the cp shifts control to the next RxBD, so the change does 609 * not take effect immediately. To guarantee the exact RxBD 610 * on which the change occurs, change MRBLR only while the 611 * SMC/SCC receiver is disabled. 612 */ 613 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize); 614 615 /* Set the mode register. We want to keep a copy of the 616 * enables, because we want to put them back if they were 617 * present. 618 */ 619 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN); 620 /* Output in *one* operation, so we don't interrupt RX/TX if they 621 * were already enabled. */ 622 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval | 623 SMCMR_SM_UART | prev_mode); 624 } else { 625 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 626 out_be16(&sccp->scc_psmr, (sbits << 12) | scval); 627 } 628 629 if (pinfo->clk) 630 clk_set_rate(pinfo->clk, baud); 631 else 632 cpm_set_brg(pinfo->brg - 1, baud); 633 spin_unlock_irqrestore(&port->lock, flags); 634} 635 636static const char *cpm_uart_type(struct uart_port *port) 637{ 638 pr_debug("CPM uart[%d]:uart_type\n", port->line); 639 640 return port->type == PORT_CPM ? "CPM UART" : NULL; 641} 642 643/* 644 * verify the new serial_struct (for TIOCSSERIAL). 645 */ 646static int cpm_uart_verify_port(struct uart_port *port, 647 struct serial_struct *ser) 648{ 649 int ret = 0; 650 651 pr_debug("CPM uart[%d]:verify_port\n", port->line); 652 653 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) 654 ret = -EINVAL; 655 if (ser->irq < 0 || ser->irq >= nr_irqs) 656 ret = -EINVAL; 657 if (ser->baud_base < 9600) 658 ret = -EINVAL; 659 return ret; 660} 661 662/* 663 * Transmit characters, refill buffer descriptor, if possible 664 */ 665static int cpm_uart_tx_pump(struct uart_port *port) 666{ 667 cbd_t __iomem *bdp; 668 u8 *p; 669 int count; 670 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 671 struct circ_buf *xmit = &port->state->xmit; 672 673 /* Handle xon/xoff */ 674 if (port->x_char) { 675 /* Pick next descriptor and fill from buffer */ 676 bdp = pinfo->tx_cur; 677 678 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 679 680 *p++ = port->x_char; 681 682 out_be16(&bdp->cbd_datlen, 1); 683 setbits16(&bdp->cbd_sc, BD_SC_READY); 684 /* Get next BD. */ 685 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 686 bdp = pinfo->tx_bd_base; 687 else 688 bdp++; 689 pinfo->tx_cur = bdp; 690 691 port->icount.tx++; 692 port->x_char = 0; 693 return 1; 694 } 695 696 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 697 cpm_uart_stop_tx(port); 698 return 0; 699 } 700 701 /* Pick next descriptor and fill from buffer */ 702 bdp = pinfo->tx_cur; 703 704 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && 705 xmit->tail != xmit->head) { 706 count = 0; 707 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 708 while (count < pinfo->tx_fifosize) { 709 *p++ = xmit->buf[xmit->tail]; 710 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 711 port->icount.tx++; 712 count++; 713 if (xmit->head == xmit->tail) 714 break; 715 } 716 out_be16(&bdp->cbd_datlen, count); 717 setbits16(&bdp->cbd_sc, BD_SC_READY); 718 /* Get next BD. */ 719 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 720 bdp = pinfo->tx_bd_base; 721 else 722 bdp++; 723 } 724 pinfo->tx_cur = bdp; 725 726 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 727 uart_write_wakeup(port); 728 729 if (uart_circ_empty(xmit)) { 730 cpm_uart_stop_tx(port); 731 return 0; 732 } 733 734 return 1; 735} 736 737/* 738 * init buffer descriptors 739 */ 740static void cpm_uart_initbd(struct uart_cpm_port *pinfo) 741{ 742 int i; 743 u8 *mem_addr; 744 cbd_t __iomem *bdp; 745 746 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); 747 748 /* Set the physical address of the host memory 749 * buffers in the buffer descriptors, and the 750 * virtual address for us to work with. 751 */ 752 mem_addr = pinfo->mem_addr; 753 bdp = pinfo->rx_cur = pinfo->rx_bd_base; 754 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { 755 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 756 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); 757 mem_addr += pinfo->rx_fifosize; 758 } 759 760 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 761 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); 762 763 /* Set the physical address of the host memory 764 * buffers in the buffer descriptors, and the 765 * virtual address for us to work with. 766 */ 767 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); 768 bdp = pinfo->tx_cur = pinfo->tx_bd_base; 769 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { 770 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 771 out_be16(&bdp->cbd_sc, BD_SC_INTRPT); 772 mem_addr += pinfo->tx_fifosize; 773 } 774 775 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 776 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); 777} 778 779static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) 780{ 781 scc_t __iomem *scp; 782 scc_uart_t __iomem *sup; 783 784 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); 785 786 scp = pinfo->sccp; 787 sup = pinfo->sccup; 788 789 /* Store address */ 790 out_be16(&pinfo->sccup->scc_genscc.scc_rbase, 791 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 792 out_be16(&pinfo->sccup->scc_genscc.scc_tbase, 793 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 794 795 /* Set up the uart parameters in the 796 * parameter ram. 797 */ 798 799 cpm_set_scc_fcr(sup); 800 801 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 802 out_be16(&sup->scc_maxidl, 0x10); 803 out_be16(&sup->scc_brkcr, 1); 804 out_be16(&sup->scc_parec, 0); 805 out_be16(&sup->scc_frmec, 0); 806 out_be16(&sup->scc_nosec, 0); 807 out_be16(&sup->scc_brkec, 0); 808 out_be16(&sup->scc_uaddr1, 0); 809 out_be16(&sup->scc_uaddr2, 0); 810 out_be16(&sup->scc_toseq, 0); 811 out_be16(&sup->scc_char1, 0x8000); 812 out_be16(&sup->scc_char2, 0x8000); 813 out_be16(&sup->scc_char3, 0x8000); 814 out_be16(&sup->scc_char4, 0x8000); 815 out_be16(&sup->scc_char5, 0x8000); 816 out_be16(&sup->scc_char6, 0x8000); 817 out_be16(&sup->scc_char7, 0x8000); 818 out_be16(&sup->scc_char8, 0x8000); 819 out_be16(&sup->scc_rccm, 0xc0ff); 820 821 /* Send the CPM an initialize command. 822 */ 823 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 824 825 /* Set UART mode, 8 bit, no parity, one stop. 826 * Enable receive and transmit. 827 */ 828 out_be32(&scp->scc_gsmrh, 0); 829 out_be32(&scp->scc_gsmrl, 830 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); 831 832 /* Enable rx interrupts and clear all pending events. */ 833 out_be16(&scp->scc_sccm, 0); 834 out_be16(&scp->scc_scce, 0xffff); 835 out_be16(&scp->scc_dsr, 0x7e7e); 836 out_be16(&scp->scc_psmr, 0x3000); 837 838 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 839} 840 841static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) 842{ 843 smc_t __iomem *sp; 844 smc_uart_t __iomem *up; 845 846 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); 847 848 sp = pinfo->smcp; 849 up = pinfo->smcup; 850 851 /* Store address */ 852 out_be16(&pinfo->smcup->smc_rbase, 853 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 854 out_be16(&pinfo->smcup->smc_tbase, 855 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 856 857/* 858 * In case SMC1 is being relocated... 859 */ 860#if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH) 861 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); 862 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); 863 out_be32(&up->smc_rstate, 0); 864 out_be32(&up->smc_tstate, 0); 865 out_be16(&up->smc_brkcr, 1); /* number of break chars */ 866 out_be16(&up->smc_brkec, 0); 867#endif 868 869 /* Set up the uart parameters in the 870 * parameter ram. 871 */ 872 cpm_set_smc_fcr(up); 873 874 /* Using idle character time requires some additional tuning. */ 875 out_be16(&up->smc_mrblr, pinfo->rx_fifosize); 876 out_be16(&up->smc_maxidl, 0x10); 877 out_be16(&up->smc_brklen, 0); 878 out_be16(&up->smc_brkec, 0); 879 out_be16(&up->smc_brkcr, 1); 880 881 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 882 883 /* Set UART mode, 8 bit, no parity, one stop. 884 * Enable receive and transmit. 885 */ 886 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); 887 888 /* Enable only rx interrupts clear all pending events. */ 889 out_8(&sp->smc_smcm, 0); 890 out_8(&sp->smc_smce, 0xff); 891 892 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 893} 894 895/* 896 * Initialize port. This is called from early_console stuff 897 * so we have to be careful here ! 898 */ 899static int cpm_uart_request_port(struct uart_port *port) 900{ 901 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 902 int ret; 903 904 pr_debug("CPM uart[%d]:request port\n", port->line); 905 906 if (pinfo->flags & FLAG_CONSOLE) 907 return 0; 908 909 if (IS_SMC(pinfo)) { 910 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 911 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 912 } else { 913 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 914 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 915 } 916 917 ret = cpm_uart_allocbuf(pinfo, 0); 918 919 if (ret) 920 return ret; 921 922 cpm_uart_initbd(pinfo); 923 if (IS_SMC(pinfo)) 924 cpm_uart_init_smc(pinfo); 925 else 926 cpm_uart_init_scc(pinfo); 927 928 return 0; 929} 930 931static void cpm_uart_release_port(struct uart_port *port) 932{ 933 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 934 935 if (!(pinfo->flags & FLAG_CONSOLE)) 936 cpm_uart_freebuf(pinfo); 937} 938 939/* 940 * Configure/autoconfigure the port. 941 */ 942static void cpm_uart_config_port(struct uart_port *port, int flags) 943{ 944 pr_debug("CPM uart[%d]:config_port\n", port->line); 945 946 if (flags & UART_CONFIG_TYPE) { 947 port->type = PORT_CPM; 948 cpm_uart_request_port(port); 949 } 950} 951 952#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE) 953/* 954 * Write a string to the serial port 955 * Note that this is called with interrupts already disabled 956 */ 957static void cpm_uart_early_write(struct uart_cpm_port *pinfo, 958 const char *string, u_int count) 959{ 960 unsigned int i; 961 cbd_t __iomem *bdp, *bdbase; 962 unsigned char *cpm_outp_addr; 963 964 /* Get the address of the host memory buffer. 965 */ 966 bdp = pinfo->tx_cur; 967 bdbase = pinfo->tx_bd_base; 968 969 /* 970 * Now, do each character. This is not as bad as it looks 971 * since this is a holding FIFO and not a transmitting FIFO. 972 * We could add the complexity of filling the entire transmit 973 * buffer, but we would just wait longer between accesses...... 974 */ 975 for (i = 0; i < count; i++, string++) { 976 /* Wait for transmitter fifo to empty. 977 * Ready indicates output is ready, and xmt is doing 978 * that, not that it is ready for us to send. 979 */ 980 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 981 ; 982 983 /* Send the character out. 984 * If the buffer address is in the CPM DPRAM, don't 985 * convert it. 986 */ 987 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 988 pinfo); 989 *cpm_outp_addr = *string; 990 991 out_be16(&bdp->cbd_datlen, 1); 992 setbits16(&bdp->cbd_sc, BD_SC_READY); 993 994 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 995 bdp = bdbase; 996 else 997 bdp++; 998 999 /* if a LF, also do CR... */ 1000 if (*string == 10) { 1001 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1002 ; 1003 1004 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1005 pinfo); 1006 *cpm_outp_addr = 13; 1007 1008 out_be16(&bdp->cbd_datlen, 1); 1009 setbits16(&bdp->cbd_sc, BD_SC_READY); 1010 1011 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1012 bdp = bdbase; 1013 else 1014 bdp++; 1015 } 1016 } 1017 1018 /* 1019 * Finally, Wait for transmitter & holding register to empty 1020 * and restore the IER 1021 */ 1022 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1023 ; 1024 1025 pinfo->tx_cur = bdp; 1026} 1027#endif 1028 1029#ifdef CONFIG_CONSOLE_POLL 1030/* Serial polling routines for writing and reading from the uart while 1031 * in an interrupt or debug context. 1032 */ 1033 1034#define GDB_BUF_SIZE 512 /* power of 2, please */ 1035 1036static char poll_buf[GDB_BUF_SIZE]; 1037static char *pollp; 1038static int poll_chars; 1039 1040static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo) 1041{ 1042 u_char c, *cp; 1043 volatile cbd_t *bdp; 1044 int i; 1045 1046 /* Get the address of the host memory buffer. 1047 */ 1048 bdp = pinfo->rx_cur; 1049 while (bdp->cbd_sc & BD_SC_EMPTY) 1050 ; 1051 1052 /* If the buffer address is in the CPM DPRAM, don't 1053 * convert it. 1054 */ 1055 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); 1056 1057 if (obuf) { 1058 i = c = bdp->cbd_datlen; 1059 while (i-- > 0) 1060 *obuf++ = *cp++; 1061 } else 1062 c = *cp; 1063 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); 1064 bdp->cbd_sc |= BD_SC_EMPTY; 1065 1066 if (bdp->cbd_sc & BD_SC_WRAP) 1067 bdp = pinfo->rx_bd_base; 1068 else 1069 bdp++; 1070 pinfo->rx_cur = (cbd_t *)bdp; 1071 1072 return (int)c; 1073} 1074 1075static int cpm_get_poll_char(struct uart_port *port) 1076{ 1077 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 1078 1079 if (!serial_polled) { 1080 serial_polled = 1; 1081 poll_chars = 0; 1082 } 1083 if (poll_chars <= 0) { 1084 poll_chars = poll_wait_key(poll_buf, pinfo); 1085 pollp = poll_buf; 1086 } 1087 poll_chars--; 1088 return *pollp++; 1089} 1090 1091static void cpm_put_poll_char(struct uart_port *port, 1092 unsigned char c) 1093{ 1094 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 1095 static char ch[2]; 1096 1097 ch[0] = (char)c; 1098 cpm_uart_early_write(pinfo, ch, 1); 1099} 1100#endif /* CONFIG_CONSOLE_POLL */ 1101 1102static struct uart_ops cpm_uart_pops = { 1103 .tx_empty = cpm_uart_tx_empty, 1104 .set_mctrl = cpm_uart_set_mctrl, 1105 .get_mctrl = cpm_uart_get_mctrl, 1106 .stop_tx = cpm_uart_stop_tx, 1107 .start_tx = cpm_uart_start_tx, 1108 .stop_rx = cpm_uart_stop_rx, 1109 .enable_ms = cpm_uart_enable_ms, 1110 .break_ctl = cpm_uart_break_ctl, 1111 .startup = cpm_uart_startup, 1112 .shutdown = cpm_uart_shutdown, 1113 .set_termios = cpm_uart_set_termios, 1114 .type = cpm_uart_type, 1115 .release_port = cpm_uart_release_port, 1116 .request_port = cpm_uart_request_port, 1117 .config_port = cpm_uart_config_port, 1118 .verify_port = cpm_uart_verify_port, 1119#ifdef CONFIG_CONSOLE_POLL 1120 .poll_get_char = cpm_get_poll_char, 1121 .poll_put_char = cpm_put_poll_char, 1122#endif 1123}; 1124 1125struct uart_cpm_port cpm_uart_ports[UART_NR]; 1126 1127static int cpm_uart_init_port(struct device_node *np, 1128 struct uart_cpm_port *pinfo) 1129{ 1130 const u32 *data; 1131 void __iomem *mem, *pram; 1132 int len; 1133 int ret; 1134 int i; 1135 1136 data = of_get_property(np, "clock", NULL); 1137 if (data) { 1138 struct clk *clk = clk_get(NULL, (const char*)data); 1139 if (!IS_ERR(clk)) 1140 pinfo->clk = clk; 1141 } 1142 if (!pinfo->clk) { 1143 data = of_get_property(np, "fsl,cpm-brg", &len); 1144 if (!data || len != 4) { 1145 printk(KERN_ERR "CPM UART %s has no/invalid " 1146 "fsl,cpm-brg property.\n", np->name); 1147 return -EINVAL; 1148 } 1149 pinfo->brg = *data; 1150 } 1151 1152 data = of_get_property(np, "fsl,cpm-command", &len); 1153 if (!data || len != 4) { 1154 printk(KERN_ERR "CPM UART %s has no/invalid " 1155 "fsl,cpm-command property.\n", np->name); 1156 return -EINVAL; 1157 } 1158 pinfo->command = *data; 1159 1160 mem = of_iomap(np, 0); 1161 if (!mem) 1162 return -ENOMEM; 1163 1164 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || 1165 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { 1166 pinfo->sccp = mem; 1167 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); 1168 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || 1169 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { 1170 pinfo->flags |= FLAG_SMC; 1171 pinfo->smcp = mem; 1172 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); 1173 } else { 1174 ret = -ENODEV; 1175 goto out_mem; 1176 } 1177 1178 if (!pram) { 1179 ret = -ENOMEM; 1180 goto out_mem; 1181 } 1182 1183 pinfo->tx_nrfifos = TX_NUM_FIFO; 1184 pinfo->tx_fifosize = TX_BUF_SIZE; 1185 pinfo->rx_nrfifos = RX_NUM_FIFO; 1186 pinfo->rx_fifosize = RX_BUF_SIZE; 1187 1188 pinfo->port.uartclk = ppc_proc_freq; 1189 pinfo->port.mapbase = (unsigned long)mem; 1190 pinfo->port.type = PORT_CPM; 1191 pinfo->port.ops = &cpm_uart_pops, 1192 pinfo->port.iotype = UPIO_MEM; 1193 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; 1194 spin_lock_init(&pinfo->port.lock); 1195 1196 pinfo->port.irq = of_irq_to_resource(np, 0, NULL); 1197 if (pinfo->port.irq == NO_IRQ) { 1198 ret = -EINVAL; 1199 goto out_pram; 1200 } 1201 1202 for (i = 0; i < NUM_GPIOS; i++) 1203 pinfo->gpios[i] = of_get_gpio(np, i); 1204 1205#ifdef CONFIG_PPC_EARLY_DEBUG_CPM 1206 udbg_putc = NULL; 1207#endif 1208 1209 return cpm_uart_request_port(&pinfo->port); 1210 1211out_pram: 1212 cpm_uart_unmap_pram(pinfo, pram); 1213out_mem: 1214 iounmap(mem); 1215 return ret; 1216} 1217 1218#ifdef CONFIG_SERIAL_CPM_CONSOLE 1219/* 1220 * Print a string to the serial port trying not to disturb 1221 * any possible real use of the port... 1222 * 1223 * Note that this is called with interrupts already disabled 1224 */ 1225static void cpm_uart_console_write(struct console *co, const char *s, 1226 u_int count) 1227{ 1228 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; 1229 unsigned long flags; 1230 int nolock = oops_in_progress; 1231 1232 if (unlikely(nolock)) { 1233 local_irq_save(flags); 1234 } else { 1235 spin_lock_irqsave(&pinfo->port.lock, flags); 1236 } 1237 1238 cpm_uart_early_write(pinfo, s, count); 1239 1240 if (unlikely(nolock)) { 1241 local_irq_restore(flags); 1242 } else { 1243 spin_unlock_irqrestore(&pinfo->port.lock, flags); 1244 } 1245} 1246 1247 1248static int __init cpm_uart_console_setup(struct console *co, char *options) 1249{ 1250 int baud = 38400; 1251 int bits = 8; 1252 int parity = 'n'; 1253 int flow = 'n'; 1254 int ret; 1255 struct uart_cpm_port *pinfo; 1256 struct uart_port *port; 1257 1258 struct device_node *np = NULL; 1259 int i = 0; 1260 1261 if (co->index >= UART_NR) { 1262 printk(KERN_ERR "cpm_uart: console index %d too high\n", 1263 co->index); 1264 return -ENODEV; 1265 } 1266 1267 do { 1268 np = of_find_node_by_type(np, "serial"); 1269 if (!np) 1270 return -ENODEV; 1271 1272 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && 1273 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && 1274 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && 1275 !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) 1276 i--; 1277 } while (i++ != co->index); 1278 1279 pinfo = &cpm_uart_ports[co->index]; 1280 1281 pinfo->flags |= FLAG_CONSOLE; 1282 port = &pinfo->port; 1283 1284 ret = cpm_uart_init_port(np, pinfo); 1285 of_node_put(np); 1286 if (ret) 1287 return ret; 1288 1289 if (options) { 1290 uart_parse_options(options, &baud, &parity, &bits, &flow); 1291 } else { 1292 if ((baud = uart_baudrate()) == -1) 1293 baud = 9600; 1294 } 1295 1296 if (IS_SMC(pinfo)) { 1297 out_be16(&pinfo->smcup->smc_brkcr, 0); 1298 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 1299 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 1300 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 1301 } else { 1302 out_be16(&pinfo->sccup->scc_brkcr, 0); 1303 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 1304 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 1305 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 1306 } 1307 1308 ret = cpm_uart_allocbuf(pinfo, 1); 1309 1310 if (ret) 1311 return ret; 1312 1313 cpm_uart_initbd(pinfo); 1314 1315 if (IS_SMC(pinfo)) 1316 cpm_uart_init_smc(pinfo); 1317 else 1318 cpm_uart_init_scc(pinfo); 1319 1320 uart_set_options(port, co, baud, parity, bits, flow); 1321 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 1322 1323 return 0; 1324} 1325 1326static struct uart_driver cpm_reg; 1327static struct console cpm_scc_uart_console = { 1328 .name = "ttyCPM", 1329 .write = cpm_uart_console_write, 1330 .device = uart_console_device, 1331 .setup = cpm_uart_console_setup, 1332 .flags = CON_PRINTBUFFER, 1333 .index = -1, 1334 .data = &cpm_reg, 1335}; 1336 1337static int __init cpm_uart_console_init(void) 1338{ 1339 register_console(&cpm_scc_uart_console); 1340 return 0; 1341} 1342 1343console_initcall(cpm_uart_console_init); 1344 1345#define CPM_UART_CONSOLE &cpm_scc_uart_console 1346#else 1347#define CPM_UART_CONSOLE NULL 1348#endif 1349 1350static struct uart_driver cpm_reg = { 1351 .owner = THIS_MODULE, 1352 .driver_name = "ttyCPM", 1353 .dev_name = "ttyCPM", 1354 .major = SERIAL_CPM_MAJOR, 1355 .minor = SERIAL_CPM_MINOR, 1356 .cons = CPM_UART_CONSOLE, 1357 .nr = UART_NR, 1358}; 1359 1360static int probe_index; 1361 1362static int __devinit cpm_uart_probe(struct platform_device *ofdev) 1363{ 1364 int index = probe_index++; 1365 struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; 1366 int ret; 1367 1368 pinfo->port.line = index; 1369 1370 if (index >= UART_NR) 1371 return -ENODEV; 1372 1373 dev_set_drvdata(&ofdev->dev, pinfo); 1374 1375 /* initialize the device pointer for the port */ 1376 pinfo->port.dev = &ofdev->dev; 1377 1378 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo); 1379 if (ret) 1380 return ret; 1381 1382 return uart_add_one_port(&cpm_reg, &pinfo->port); 1383} 1384 1385static int __devexit cpm_uart_remove(struct platform_device *ofdev) 1386{ 1387 struct uart_cpm_port *pinfo = dev_get_drvdata(&ofdev->dev); 1388 return uart_remove_one_port(&cpm_reg, &pinfo->port); 1389} 1390 1391static struct of_device_id cpm_uart_match[] = { 1392 { 1393 .compatible = "fsl,cpm1-smc-uart", 1394 }, 1395 { 1396 .compatible = "fsl,cpm1-scc-uart", 1397 }, 1398 { 1399 .compatible = "fsl,cpm2-smc-uart", 1400 }, 1401 { 1402 .compatible = "fsl,cpm2-scc-uart", 1403 }, 1404 {} 1405}; 1406 1407static struct platform_driver cpm_uart_driver = { 1408 .driver = { 1409 .name = "cpm_uart", 1410 .owner = THIS_MODULE, 1411 .of_match_table = cpm_uart_match, 1412 }, 1413 .probe = cpm_uart_probe, 1414 .remove = cpm_uart_remove, 1415 }; 1416 1417static int __init cpm_uart_init(void) 1418{ 1419 int ret = uart_register_driver(&cpm_reg); 1420 if (ret) 1421 return ret; 1422 1423 ret = platform_driver_register(&cpm_uart_driver); 1424 if (ret) 1425 uart_unregister_driver(&cpm_reg); 1426 1427 return ret; 1428} 1429 1430static void __exit cpm_uart_exit(void) 1431{ 1432 platform_driver_unregister(&cpm_uart_driver); 1433 uart_unregister_driver(&cpm_reg); 1434} 1435 1436module_init(cpm_uart_init); 1437module_exit(cpm_uart_exit); 1438 1439MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); 1440MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); 1441MODULE_LICENSE("GPL"); 1442MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); 1443