gadget.c revision 08f0d96670c53898b4154e7945e77cdd966003f7
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <linux/kernel.h> 40#include <linux/delay.h> 41#include <linux/slab.h> 42#include <linux/spinlock.h> 43#include <linux/platform_device.h> 44#include <linux/pm_runtime.h> 45#include <linux/interrupt.h> 46#include <linux/io.h> 47#include <linux/list.h> 48#include <linux/dma-mapping.h> 49 50#include <linux/usb/ch9.h> 51#include <linux/usb/gadget.h> 52 53#include "core.h" 54#include "gadget.h" 55#include "io.h" 56 57/** 58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 59 * @dwc: pointer to our context structure 60 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 61 * 62 * Caller should take care of locking. This function will 63 * return 0 on success or -EINVAL if wrong Test Selector 64 * is passed 65 */ 66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 67{ 68 u32 reg; 69 70 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 71 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 72 73 switch (mode) { 74 case TEST_J: 75 case TEST_K: 76 case TEST_SE0_NAK: 77 case TEST_PACKET: 78 case TEST_FORCE_EN: 79 reg |= mode << 1; 80 break; 81 default: 82 return -EINVAL; 83 } 84 85 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 86 87 return 0; 88} 89 90/** 91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 92 * @dwc: pointer to our context structure 93 * @state: the state to put link into 94 * 95 * Caller should take care of locking. This function will 96 * return 0 on success or -ETIMEDOUT. 97 */ 98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 99{ 100 int retries = 10000; 101 u32 reg; 102 103 /* 104 * Wait until device controller is ready. Only applies to 1.94a and 105 * later RTL. 106 */ 107 if (dwc->revision >= DWC3_REVISION_194A) { 108 while (--retries) { 109 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 110 if (reg & DWC3_DSTS_DCNRD) 111 udelay(5); 112 else 113 break; 114 } 115 116 if (retries <= 0) 117 return -ETIMEDOUT; 118 } 119 120 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 122 123 /* set requested state */ 124 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 125 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 126 127 /* 128 * The following code is racy when called from dwc3_gadget_wakeup, 129 * and is not needed, at least on newer versions 130 */ 131 if (dwc->revision >= DWC3_REVISION_194A) 132 return 0; 133 134 /* wait for a change in DSTS */ 135 retries = 10000; 136 while (--retries) { 137 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 138 139 if (DWC3_DSTS_USBLNKST(reg) == state) 140 return 0; 141 142 udelay(5); 143 } 144 145 dev_vdbg(dwc->dev, "link state change request timed out\n"); 146 147 return -ETIMEDOUT; 148} 149 150/** 151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 152 * @dwc: pointer to our context structure 153 * 154 * This function will a best effort FIFO allocation in order 155 * to improve FIFO usage and throughput, while still allowing 156 * us to enable as many endpoints as possible. 157 * 158 * Keep in mind that this operation will be highly dependent 159 * on the configured size for RAM1 - which contains TxFifo -, 160 * the amount of endpoints enabled on coreConsultant tool, and 161 * the width of the Master Bus. 162 * 163 * In the ideal world, we would always be able to satisfy the 164 * following equation: 165 * 166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 168 * 169 * Unfortunately, due to many variables that's not always the case. 170 */ 171int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 172{ 173 int last_fifo_depth = 0; 174 int ram1_depth; 175 int fifo_size; 176 int mdwidth; 177 int num; 178 179 if (!dwc->needs_fifo_resize) 180 return 0; 181 182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 184 185 /* MDWIDTH is represented in bits, we need it in bytes */ 186 mdwidth >>= 3; 187 188 /* 189 * FIXME For now we will only allocate 1 wMaxPacketSize space 190 * for each enabled endpoint, later patches will come to 191 * improve this algorithm so that we better use the internal 192 * FIFO space 193 */ 194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { 195 struct dwc3_ep *dep = dwc->eps[num]; 196 int fifo_number = dep->number >> 1; 197 int mult = 1; 198 int tmp; 199 200 if (!(dep->number & 1)) 201 continue; 202 203 if (!(dep->flags & DWC3_EP_ENABLED)) 204 continue; 205 206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) 207 || usb_endpoint_xfer_isoc(dep->endpoint.desc)) 208 mult = 3; 209 210 /* 211 * REVISIT: the following assumes we will always have enough 212 * space available on the FIFO RAM for all possible use cases. 213 * Make sure that's true somehow and change FIFO allocation 214 * accordingly. 215 * 216 * If we have Bulk or Isochronous endpoints, we want 217 * them to be able to be very, very fast. So we're giving 218 * those endpoints a fifo_size which is enough for 3 full 219 * packets 220 */ 221 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 222 tmp += mdwidth; 223 224 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 225 226 fifo_size |= (last_fifo_depth << 16); 227 228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 229 dep->name, last_fifo_depth, fifo_size & 0xffff); 230 231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), 232 fifo_size); 233 234 last_fifo_depth += (fifo_size & 0xffff); 235 } 236 237 return 0; 238} 239 240void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 241 int status) 242{ 243 struct dwc3 *dwc = dep->dwc; 244 245 if (req->queued) { 246 if (req->request.num_mapped_sgs) 247 dep->busy_slot += req->request.num_mapped_sgs; 248 else 249 dep->busy_slot++; 250 251 /* 252 * Skip LINK TRB. We can't use req->trb and check for 253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just 254 * completed (not the LINK TRB). 255 */ 256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 257 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 258 dep->busy_slot++; 259 } 260 list_del(&req->list); 261 req->trb = NULL; 262 263 if (req->request.status == -EINPROGRESS) 264 req->request.status = status; 265 266 usb_gadget_unmap_request(&dwc->gadget, &req->request, 267 req->direction); 268 269 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 270 req, dep->name, req->request.actual, 271 req->request.length, status); 272 273 spin_unlock(&dwc->lock); 274 req->request.complete(&dep->endpoint, &req->request); 275 spin_lock(&dwc->lock); 276} 277 278static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 279{ 280 switch (cmd) { 281 case DWC3_DEPCMD_DEPSTARTCFG: 282 return "Start New Configuration"; 283 case DWC3_DEPCMD_ENDTRANSFER: 284 return "End Transfer"; 285 case DWC3_DEPCMD_UPDATETRANSFER: 286 return "Update Transfer"; 287 case DWC3_DEPCMD_STARTTRANSFER: 288 return "Start Transfer"; 289 case DWC3_DEPCMD_CLEARSTALL: 290 return "Clear Stall"; 291 case DWC3_DEPCMD_SETSTALL: 292 return "Set Stall"; 293 case DWC3_DEPCMD_GETEPSTATE: 294 return "Get Endpoint State"; 295 case DWC3_DEPCMD_SETTRANSFRESOURCE: 296 return "Set Endpoint Transfer Resource"; 297 case DWC3_DEPCMD_SETEPCONFIG: 298 return "Set Endpoint Configuration"; 299 default: 300 return "UNKNOWN command"; 301 } 302} 303 304int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) 305{ 306 u32 timeout = 500; 307 u32 reg; 308 309 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 310 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 311 312 do { 313 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 314 if (!(reg & DWC3_DGCMD_CMDACT)) { 315 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 316 DWC3_DGCMD_STATUS(reg)); 317 return 0; 318 } 319 320 /* 321 * We can't sleep here, because it's also called from 322 * interrupt context. 323 */ 324 timeout--; 325 if (!timeout) 326 return -ETIMEDOUT; 327 udelay(1); 328 } while (1); 329} 330 331int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 332 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 333{ 334 struct dwc3_ep *dep = dwc->eps[ep]; 335 u32 timeout = 500; 336 u32 reg; 337 338 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 339 dep->name, 340 dwc3_gadget_ep_cmd_string(cmd), params->param0, 341 params->param1, params->param2); 342 343 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 346 347 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 348 do { 349 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 350 if (!(reg & DWC3_DEPCMD_CMDACT)) { 351 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 352 DWC3_DEPCMD_STATUS(reg)); 353 return 0; 354 } 355 356 /* 357 * We can't sleep here, because it is also called from 358 * interrupt context. 359 */ 360 timeout--; 361 if (!timeout) 362 return -ETIMEDOUT; 363 364 udelay(1); 365 } while (1); 366} 367 368static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 369 struct dwc3_trb *trb) 370{ 371 u32 offset = (char *) trb - (char *) dep->trb_pool; 372 373 return dep->trb_pool_dma + offset; 374} 375 376static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 377{ 378 struct dwc3 *dwc = dep->dwc; 379 380 if (dep->trb_pool) 381 return 0; 382 383 if (dep->number == 0 || dep->number == 1) 384 return 0; 385 386 dep->trb_pool = dma_alloc_coherent(dwc->dev, 387 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 388 &dep->trb_pool_dma, GFP_KERNEL); 389 if (!dep->trb_pool) { 390 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 391 dep->name); 392 return -ENOMEM; 393 } 394 395 return 0; 396} 397 398static void dwc3_free_trb_pool(struct dwc3_ep *dep) 399{ 400 struct dwc3 *dwc = dep->dwc; 401 402 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 403 dep->trb_pool, dep->trb_pool_dma); 404 405 dep->trb_pool = NULL; 406 dep->trb_pool_dma = 0; 407} 408 409static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 410{ 411 struct dwc3_gadget_ep_cmd_params params; 412 u32 cmd; 413 414 memset(¶ms, 0x00, sizeof(params)); 415 416 if (dep->number != 1) { 417 cmd = DWC3_DEPCMD_DEPSTARTCFG; 418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 419 if (dep->number > 1) { 420 if (dwc->start_config_issued) 421 return 0; 422 dwc->start_config_issued = true; 423 cmd |= DWC3_DEPCMD_PARAM(2); 424 } 425 426 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 427 } 428 429 return 0; 430} 431 432static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 433 const struct usb_endpoint_descriptor *desc, 434 const struct usb_ss_ep_comp_descriptor *comp_desc) 435{ 436 struct dwc3_gadget_ep_cmd_params params; 437 438 memset(¶ms, 0x00, sizeof(params)); 439 440 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 441 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) 442 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst); 443 444 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 445 | DWC3_DEPCFG_XFER_NOT_READY_EN; 446 447 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 448 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 449 | DWC3_DEPCFG_STREAM_EVENT_EN; 450 dep->stream_capable = true; 451 } 452 453 if (usb_endpoint_xfer_isoc(desc)) 454 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 455 456 /* 457 * We are doing 1:1 mapping for endpoints, meaning 458 * Physical Endpoints 2 maps to Logical Endpoint 2 and 459 * so on. We consider the direction bit as part of the physical 460 * endpoint number. So USB endpoint 0x81 is 0x03. 461 */ 462 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 463 464 /* 465 * We must use the lower 16 TX FIFOs even though 466 * HW might have more 467 */ 468 if (dep->direction) 469 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 470 471 if (desc->bInterval) { 472 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 473 dep->interval = 1 << (desc->bInterval - 1); 474 } 475 476 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 477 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 478} 479 480static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 481{ 482 struct dwc3_gadget_ep_cmd_params params; 483 484 memset(¶ms, 0x00, sizeof(params)); 485 486 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 487 488 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 489 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 490} 491 492/** 493 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 494 * @dep: endpoint to be initialized 495 * @desc: USB Endpoint Descriptor 496 * 497 * Caller should take care of locking 498 */ 499static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 500 const struct usb_endpoint_descriptor *desc, 501 const struct usb_ss_ep_comp_descriptor *comp_desc) 502{ 503 struct dwc3 *dwc = dep->dwc; 504 u32 reg; 505 int ret = -ENOMEM; 506 507 if (!(dep->flags & DWC3_EP_ENABLED)) { 508 ret = dwc3_gadget_start_config(dwc, dep); 509 if (ret) 510 return ret; 511 } 512 513 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc); 514 if (ret) 515 return ret; 516 517 if (!(dep->flags & DWC3_EP_ENABLED)) { 518 struct dwc3_trb *trb_st_hw; 519 struct dwc3_trb *trb_link; 520 521 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 522 if (ret) 523 return ret; 524 525 dep->endpoint.desc = desc; 526 dep->comp_desc = comp_desc; 527 dep->type = usb_endpoint_type(desc); 528 dep->flags |= DWC3_EP_ENABLED; 529 530 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 531 reg |= DWC3_DALEPENA_EP(dep->number); 532 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 533 534 if (!usb_endpoint_xfer_isoc(desc)) 535 return 0; 536 537 memset(&trb_link, 0, sizeof(trb_link)); 538 539 /* Link TRB for ISOC. The HWO bit is never reset */ 540 trb_st_hw = &dep->trb_pool[0]; 541 542 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 543 544 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 545 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 546 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 547 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 548 } 549 550 return 0; 551} 552 553static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); 554static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 555{ 556 struct dwc3_request *req; 557 558 if (!list_empty(&dep->req_queued)) { 559 dwc3_stop_active_transfer(dwc, dep->number); 560 561 /* 562 * NOTICE: We are violating what the Databook says about the 563 * EndTransfer command. Ideally we would _always_ wait for the 564 * EndTransfer Command Completion IRQ, but that's causing too 565 * much trouble synchronizing between us and gadget driver. 566 * 567 * We have discussed this with the IP Provider and it was 568 * suggested to giveback all requests here, but give HW some 569 * extra time to synchronize with the interconnect. We're using 570 * an arbitraty 100us delay for that. 571 * 572 * Note also that a similar handling was tested by Synopsys 573 * (thanks a lot Paul) and nothing bad has come out of it. 574 * In short, what we're doing is: 575 * 576 * - Issue EndTransfer WITH CMDIOC bit set 577 * - Wait 100us 578 * - giveback all requests to gadget driver 579 */ 580 udelay(100); 581 582 while (!list_empty(&dep->req_queued)) { 583 req = next_request(&dep->req_queued); 584 585 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 586 } 587 } 588 589 while (!list_empty(&dep->request_list)) { 590 req = next_request(&dep->request_list); 591 592 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 593 } 594} 595 596/** 597 * __dwc3_gadget_ep_disable - Disables a HW endpoint 598 * @dep: the endpoint to disable 599 * 600 * This function also removes requests which are currently processed ny the 601 * hardware and those which are not yet scheduled. 602 * Caller should take care of locking. 603 */ 604static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 605{ 606 struct dwc3 *dwc = dep->dwc; 607 u32 reg; 608 609 dwc3_remove_requests(dwc, dep); 610 611 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 612 reg &= ~DWC3_DALEPENA_EP(dep->number); 613 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 614 615 dep->stream_capable = false; 616 dep->endpoint.desc = NULL; 617 dep->comp_desc = NULL; 618 dep->type = 0; 619 dep->flags = 0; 620 621 return 0; 622} 623 624/* -------------------------------------------------------------------------- */ 625 626static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 627 const struct usb_endpoint_descriptor *desc) 628{ 629 return -EINVAL; 630} 631 632static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 633{ 634 return -EINVAL; 635} 636 637/* -------------------------------------------------------------------------- */ 638 639static int dwc3_gadget_ep_enable(struct usb_ep *ep, 640 const struct usb_endpoint_descriptor *desc) 641{ 642 struct dwc3_ep *dep; 643 struct dwc3 *dwc; 644 unsigned long flags; 645 int ret; 646 647 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 648 pr_debug("dwc3: invalid parameters\n"); 649 return -EINVAL; 650 } 651 652 if (!desc->wMaxPacketSize) { 653 pr_debug("dwc3: missing wMaxPacketSize\n"); 654 return -EINVAL; 655 } 656 657 dep = to_dwc3_ep(ep); 658 dwc = dep->dwc; 659 660 switch (usb_endpoint_type(desc)) { 661 case USB_ENDPOINT_XFER_CONTROL: 662 strlcat(dep->name, "-control", sizeof(dep->name)); 663 break; 664 case USB_ENDPOINT_XFER_ISOC: 665 strlcat(dep->name, "-isoc", sizeof(dep->name)); 666 break; 667 case USB_ENDPOINT_XFER_BULK: 668 strlcat(dep->name, "-bulk", sizeof(dep->name)); 669 break; 670 case USB_ENDPOINT_XFER_INT: 671 strlcat(dep->name, "-int", sizeof(dep->name)); 672 break; 673 default: 674 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 675 } 676 677 if (dep->flags & DWC3_EP_ENABLED) { 678 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 679 dep->name); 680 return 0; 681 } 682 683 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 684 685 spin_lock_irqsave(&dwc->lock, flags); 686 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc); 687 spin_unlock_irqrestore(&dwc->lock, flags); 688 689 return ret; 690} 691 692static int dwc3_gadget_ep_disable(struct usb_ep *ep) 693{ 694 struct dwc3_ep *dep; 695 struct dwc3 *dwc; 696 unsigned long flags; 697 int ret; 698 699 if (!ep) { 700 pr_debug("dwc3: invalid parameters\n"); 701 return -EINVAL; 702 } 703 704 dep = to_dwc3_ep(ep); 705 dwc = dep->dwc; 706 707 if (!(dep->flags & DWC3_EP_ENABLED)) { 708 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 709 dep->name); 710 return 0; 711 } 712 713 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 714 dep->number >> 1, 715 (dep->number & 1) ? "in" : "out"); 716 717 spin_lock_irqsave(&dwc->lock, flags); 718 ret = __dwc3_gadget_ep_disable(dep); 719 spin_unlock_irqrestore(&dwc->lock, flags); 720 721 return ret; 722} 723 724static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 725 gfp_t gfp_flags) 726{ 727 struct dwc3_request *req; 728 struct dwc3_ep *dep = to_dwc3_ep(ep); 729 struct dwc3 *dwc = dep->dwc; 730 731 req = kzalloc(sizeof(*req), gfp_flags); 732 if (!req) { 733 dev_err(dwc->dev, "not enough memory\n"); 734 return NULL; 735 } 736 737 req->epnum = dep->number; 738 req->dep = dep; 739 740 return &req->request; 741} 742 743static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 744 struct usb_request *request) 745{ 746 struct dwc3_request *req = to_dwc3_request(request); 747 748 kfree(req); 749} 750 751/** 752 * dwc3_prepare_one_trb - setup one TRB from one request 753 * @dep: endpoint for which this request is prepared 754 * @req: dwc3_request pointer 755 */ 756static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 757 struct dwc3_request *req, dma_addr_t dma, 758 unsigned length, unsigned last, unsigned chain) 759{ 760 struct dwc3 *dwc = dep->dwc; 761 struct dwc3_trb *trb; 762 763 unsigned int cur_slot; 764 765 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 766 dep->name, req, (unsigned long long) dma, 767 length, last ? " last" : "", 768 chain ? " chain" : ""); 769 770 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 771 cur_slot = dep->free_slot; 772 dep->free_slot++; 773 774 /* Skip the LINK-TRB on ISOC */ 775 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 776 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 777 return; 778 779 if (!req->trb) { 780 dwc3_gadget_move_request_queued(req); 781 req->trb = trb; 782 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 783 } 784 785 trb->size = DWC3_TRB_SIZE_LENGTH(length); 786 trb->bpl = lower_32_bits(dma); 787 trb->bph = upper_32_bits(dma); 788 789 switch (usb_endpoint_type(dep->endpoint.desc)) { 790 case USB_ENDPOINT_XFER_CONTROL: 791 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 792 break; 793 794 case USB_ENDPOINT_XFER_ISOC: 795 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 796 797 if (!req->request.no_interrupt) 798 trb->ctrl |= DWC3_TRB_CTRL_IOC; 799 break; 800 801 case USB_ENDPOINT_XFER_BULK: 802 case USB_ENDPOINT_XFER_INT: 803 trb->ctrl = DWC3_TRBCTL_NORMAL; 804 break; 805 default: 806 /* 807 * This is only possible with faulty memory because we 808 * checked it already :) 809 */ 810 BUG(); 811 } 812 813 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 814 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 815 trb->ctrl |= DWC3_TRB_CTRL_CSP; 816 } else { 817 if (chain) 818 trb->ctrl |= DWC3_TRB_CTRL_CHN; 819 820 if (last) 821 trb->ctrl |= DWC3_TRB_CTRL_LST; 822 } 823 824 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 825 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); 826 827 trb->ctrl |= DWC3_TRB_CTRL_HWO; 828} 829 830/* 831 * dwc3_prepare_trbs - setup TRBs from requests 832 * @dep: endpoint for which requests are being prepared 833 * @starting: true if the endpoint is idle and no requests are queued. 834 * 835 * The function goes through the requests list and sets up TRBs for the 836 * transfers. The function returns once there are no more TRBs available or 837 * it runs out of requests. 838 */ 839static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 840{ 841 struct dwc3_request *req, *n; 842 u32 trbs_left; 843 u32 max; 844 unsigned int last_one = 0; 845 846 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 847 848 /* the first request must not be queued */ 849 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 850 851 /* Can't wrap around on a non-isoc EP since there's no link TRB */ 852 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 853 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); 854 if (trbs_left > max) 855 trbs_left = max; 856 } 857 858 /* 859 * If busy & slot are equal than it is either full or empty. If we are 860 * starting to process requests then we are empty. Otherwise we are 861 * full and don't do anything 862 */ 863 if (!trbs_left) { 864 if (!starting) 865 return; 866 trbs_left = DWC3_TRB_NUM; 867 /* 868 * In case we start from scratch, we queue the ISOC requests 869 * starting from slot 1. This is done because we use ring 870 * buffer and have no LST bit to stop us. Instead, we place 871 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt 872 * after the first request so we start at slot 1 and have 873 * 7 requests proceed before we hit the first IOC. 874 * Other transfer types don't use the ring buffer and are 875 * processed from the first TRB until the last one. Since we 876 * don't wrap around we have to start at the beginning. 877 */ 878 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 879 dep->busy_slot = 1; 880 dep->free_slot = 1; 881 } else { 882 dep->busy_slot = 0; 883 dep->free_slot = 0; 884 } 885 } 886 887 /* The last TRB is a link TRB, not used for xfer */ 888 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) 889 return; 890 891 list_for_each_entry_safe(req, n, &dep->request_list, list) { 892 unsigned length; 893 dma_addr_t dma; 894 895 if (req->request.num_mapped_sgs > 0) { 896 struct usb_request *request = &req->request; 897 struct scatterlist *sg = request->sg; 898 struct scatterlist *s; 899 int i; 900 901 for_each_sg(sg, s, request->num_mapped_sgs, i) { 902 unsigned chain = true; 903 904 length = sg_dma_len(s); 905 dma = sg_dma_address(s); 906 907 if (i == (request->num_mapped_sgs - 1) || 908 sg_is_last(s)) { 909 last_one = true; 910 chain = false; 911 } 912 913 trbs_left--; 914 if (!trbs_left) 915 last_one = true; 916 917 if (last_one) 918 chain = false; 919 920 dwc3_prepare_one_trb(dep, req, dma, length, 921 last_one, chain); 922 923 if (last_one) 924 break; 925 } 926 } else { 927 dma = req->request.dma; 928 length = req->request.length; 929 trbs_left--; 930 931 if (!trbs_left) 932 last_one = 1; 933 934 /* Is this the last request? */ 935 if (list_is_last(&req->list, &dep->request_list)) 936 last_one = 1; 937 938 dwc3_prepare_one_trb(dep, req, dma, length, 939 last_one, false); 940 941 if (last_one) 942 break; 943 } 944 } 945} 946 947static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 948 int start_new) 949{ 950 struct dwc3_gadget_ep_cmd_params params; 951 struct dwc3_request *req; 952 struct dwc3 *dwc = dep->dwc; 953 int ret; 954 u32 cmd; 955 956 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 957 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 958 return -EBUSY; 959 } 960 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 961 962 /* 963 * If we are getting here after a short-out-packet we don't enqueue any 964 * new requests as we try to set the IOC bit only on the last request. 965 */ 966 if (start_new) { 967 if (list_empty(&dep->req_queued)) 968 dwc3_prepare_trbs(dep, start_new); 969 970 /* req points to the first request which will be sent */ 971 req = next_request(&dep->req_queued); 972 } else { 973 dwc3_prepare_trbs(dep, start_new); 974 975 /* 976 * req points to the first request where HWO changed from 0 to 1 977 */ 978 req = next_request(&dep->req_queued); 979 } 980 if (!req) { 981 dep->flags |= DWC3_EP_PENDING_REQUEST; 982 return 0; 983 } 984 985 memset(¶ms, 0, sizeof(params)); 986 params.param0 = upper_32_bits(req->trb_dma); 987 params.param1 = lower_32_bits(req->trb_dma); 988 989 if (start_new) 990 cmd = DWC3_DEPCMD_STARTTRANSFER; 991 else 992 cmd = DWC3_DEPCMD_UPDATETRANSFER; 993 994 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 995 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 996 if (ret < 0) { 997 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 998 999 /* 1000 * FIXME we need to iterate over the list of requests 1001 * here and stop, unmap, free and del each of the linked 1002 * requests instead of what we do now. 1003 */ 1004 usb_gadget_unmap_request(&dwc->gadget, &req->request, 1005 req->direction); 1006 list_del(&req->list); 1007 return ret; 1008 } 1009 1010 dep->flags |= DWC3_EP_BUSY; 1011 1012 if (start_new) { 1013 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 1014 dep->number); 1015 WARN_ON_ONCE(!dep->resource_index); 1016 } 1017 1018 return 0; 1019} 1020 1021static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, 1022 struct dwc3_ep *dep, u32 cur_uf) 1023{ 1024 u32 uf; 1025 1026 if (list_empty(&dep->request_list)) { 1027 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1028 dep->name); 1029 return; 1030 } 1031 1032 /* 4 micro frames in the future */ 1033 uf = cur_uf + dep->interval * 4; 1034 1035 __dwc3_gadget_kick_transfer(dep, uf, 1); 1036} 1037 1038static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1039 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1040{ 1041 u32 cur_uf, mask; 1042 1043 mask = ~(dep->interval - 1); 1044 cur_uf = event->parameters & mask; 1045 1046 __dwc3_gadget_start_isoc(dwc, dep, cur_uf); 1047} 1048 1049static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 1050{ 1051 struct dwc3 *dwc = dep->dwc; 1052 int ret; 1053 1054 req->request.actual = 0; 1055 req->request.status = -EINPROGRESS; 1056 req->direction = dep->direction; 1057 req->epnum = dep->number; 1058 1059 /* 1060 * We only add to our list of requests now and 1061 * start consuming the list once we get XferNotReady 1062 * IRQ. 1063 * 1064 * That way, we avoid doing anything that we don't need 1065 * to do now and defer it until the point we receive a 1066 * particular token from the Host side. 1067 * 1068 * This will also avoid Host cancelling URBs due to too 1069 * many NAKs. 1070 */ 1071 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1072 dep->direction); 1073 if (ret) 1074 return ret; 1075 1076 list_add_tail(&req->list, &dep->request_list); 1077 1078 /* 1079 * There are a few special cases: 1080 * 1081 * 1. XferNotReady with empty list of requests. We need to kick the 1082 * transfer here in that situation, otherwise we will be NAKing 1083 * forever. If we get XferNotReady before gadget driver has a 1084 * chance to queue a request, we will ACK the IRQ but won't be 1085 * able to receive the data until the next request is queued. 1086 * The following code is handling exactly that. 1087 * 1088 */ 1089 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1090 int ret; 1091 1092 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1093 if (ret && ret != -EBUSY) { 1094 struct dwc3 *dwc = dep->dwc; 1095 1096 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1097 dep->name); 1098 } 1099 } 1100 1101 /* 1102 * 2. XferInProgress on Isoc EP with an active transfer. We need to 1103 * kick the transfer here after queuing a request, otherwise the 1104 * core may not see the modified TRB(s). 1105 */ 1106 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1107 (dep->flags & DWC3_EP_BUSY)) { 1108 WARN_ON_ONCE(!dep->resource_index); 1109 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, 1110 false); 1111 if (ret && ret != -EBUSY) { 1112 struct dwc3 *dwc = dep->dwc; 1113 1114 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1115 dep->name); 1116 } 1117 } 1118 1119 /* 1120 * 3. Missed ISOC Handling. We need to start isoc transfer on the saved 1121 * uframe number. 1122 */ 1123 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1124 (dep->flags & DWC3_EP_MISSED_ISOC)) { 1125 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf); 1126 dep->flags &= ~DWC3_EP_MISSED_ISOC; 1127 } 1128 1129 return 0; 1130} 1131 1132static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1133 gfp_t gfp_flags) 1134{ 1135 struct dwc3_request *req = to_dwc3_request(request); 1136 struct dwc3_ep *dep = to_dwc3_ep(ep); 1137 struct dwc3 *dwc = dep->dwc; 1138 1139 unsigned long flags; 1140 1141 int ret; 1142 1143 if (!dep->endpoint.desc) { 1144 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1145 request, ep->name); 1146 return -ESHUTDOWN; 1147 } 1148 1149 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1150 request, ep->name, request->length); 1151 1152 spin_lock_irqsave(&dwc->lock, flags); 1153 ret = __dwc3_gadget_ep_queue(dep, req); 1154 spin_unlock_irqrestore(&dwc->lock, flags); 1155 1156 return ret; 1157} 1158 1159static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1160 struct usb_request *request) 1161{ 1162 struct dwc3_request *req = to_dwc3_request(request); 1163 struct dwc3_request *r = NULL; 1164 1165 struct dwc3_ep *dep = to_dwc3_ep(ep); 1166 struct dwc3 *dwc = dep->dwc; 1167 1168 unsigned long flags; 1169 int ret = 0; 1170 1171 spin_lock_irqsave(&dwc->lock, flags); 1172 1173 list_for_each_entry(r, &dep->request_list, list) { 1174 if (r == req) 1175 break; 1176 } 1177 1178 if (r != req) { 1179 list_for_each_entry(r, &dep->req_queued, list) { 1180 if (r == req) 1181 break; 1182 } 1183 if (r == req) { 1184 /* wait until it is processed */ 1185 dwc3_stop_active_transfer(dwc, dep->number); 1186 goto out0; 1187 } 1188 dev_err(dwc->dev, "request %p was not queued to %s\n", 1189 request, ep->name); 1190 ret = -EINVAL; 1191 goto out0; 1192 } 1193 1194 /* giveback the request */ 1195 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1196 1197out0: 1198 spin_unlock_irqrestore(&dwc->lock, flags); 1199 1200 return ret; 1201} 1202 1203int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1204{ 1205 struct dwc3_gadget_ep_cmd_params params; 1206 struct dwc3 *dwc = dep->dwc; 1207 int ret; 1208 1209 memset(¶ms, 0x00, sizeof(params)); 1210 1211 if (value) { 1212 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1213 DWC3_DEPCMD_SETSTALL, ¶ms); 1214 if (ret) 1215 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1216 value ? "set" : "clear", 1217 dep->name); 1218 else 1219 dep->flags |= DWC3_EP_STALL; 1220 } else { 1221 if (dep->flags & DWC3_EP_WEDGE) 1222 return 0; 1223 1224 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1225 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1226 if (ret) 1227 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1228 value ? "set" : "clear", 1229 dep->name); 1230 else 1231 dep->flags &= ~DWC3_EP_STALL; 1232 } 1233 1234 return ret; 1235} 1236 1237static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1238{ 1239 struct dwc3_ep *dep = to_dwc3_ep(ep); 1240 struct dwc3 *dwc = dep->dwc; 1241 1242 unsigned long flags; 1243 1244 int ret; 1245 1246 spin_lock_irqsave(&dwc->lock, flags); 1247 1248 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1249 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1250 ret = -EINVAL; 1251 goto out; 1252 } 1253 1254 ret = __dwc3_gadget_ep_set_halt(dep, value); 1255out: 1256 spin_unlock_irqrestore(&dwc->lock, flags); 1257 1258 return ret; 1259} 1260 1261static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1262{ 1263 struct dwc3_ep *dep = to_dwc3_ep(ep); 1264 struct dwc3 *dwc = dep->dwc; 1265 unsigned long flags; 1266 1267 spin_lock_irqsave(&dwc->lock, flags); 1268 dep->flags |= DWC3_EP_WEDGE; 1269 spin_unlock_irqrestore(&dwc->lock, flags); 1270 1271 if (dep->number == 0 || dep->number == 1) 1272 return dwc3_gadget_ep0_set_halt(ep, 1); 1273 else 1274 return dwc3_gadget_ep_set_halt(ep, 1); 1275} 1276 1277/* -------------------------------------------------------------------------- */ 1278 1279static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1280 .bLength = USB_DT_ENDPOINT_SIZE, 1281 .bDescriptorType = USB_DT_ENDPOINT, 1282 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1283}; 1284 1285static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1286 .enable = dwc3_gadget_ep0_enable, 1287 .disable = dwc3_gadget_ep0_disable, 1288 .alloc_request = dwc3_gadget_ep_alloc_request, 1289 .free_request = dwc3_gadget_ep_free_request, 1290 .queue = dwc3_gadget_ep0_queue, 1291 .dequeue = dwc3_gadget_ep_dequeue, 1292 .set_halt = dwc3_gadget_ep0_set_halt, 1293 .set_wedge = dwc3_gadget_ep_set_wedge, 1294}; 1295 1296static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1297 .enable = dwc3_gadget_ep_enable, 1298 .disable = dwc3_gadget_ep_disable, 1299 .alloc_request = dwc3_gadget_ep_alloc_request, 1300 .free_request = dwc3_gadget_ep_free_request, 1301 .queue = dwc3_gadget_ep_queue, 1302 .dequeue = dwc3_gadget_ep_dequeue, 1303 .set_halt = dwc3_gadget_ep_set_halt, 1304 .set_wedge = dwc3_gadget_ep_set_wedge, 1305}; 1306 1307/* -------------------------------------------------------------------------- */ 1308 1309static int dwc3_gadget_get_frame(struct usb_gadget *g) 1310{ 1311 struct dwc3 *dwc = gadget_to_dwc(g); 1312 u32 reg; 1313 1314 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1315 return DWC3_DSTS_SOFFN(reg); 1316} 1317 1318static int dwc3_gadget_wakeup(struct usb_gadget *g) 1319{ 1320 struct dwc3 *dwc = gadget_to_dwc(g); 1321 1322 unsigned long timeout; 1323 unsigned long flags; 1324 1325 u32 reg; 1326 1327 int ret = 0; 1328 1329 u8 link_state; 1330 u8 speed; 1331 1332 spin_lock_irqsave(&dwc->lock, flags); 1333 1334 /* 1335 * According to the Databook Remote wakeup request should 1336 * be issued only when the device is in early suspend state. 1337 * 1338 * We can check that via USB Link State bits in DSTS register. 1339 */ 1340 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1341 1342 speed = reg & DWC3_DSTS_CONNECTSPD; 1343 if (speed == DWC3_DSTS_SUPERSPEED) { 1344 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1345 ret = -EINVAL; 1346 goto out; 1347 } 1348 1349 link_state = DWC3_DSTS_USBLNKST(reg); 1350 1351 switch (link_state) { 1352 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1353 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1354 break; 1355 default: 1356 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1357 link_state); 1358 ret = -EINVAL; 1359 goto out; 1360 } 1361 1362 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1363 if (ret < 0) { 1364 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1365 goto out; 1366 } 1367 1368 /* Recent versions do this automatically */ 1369 if (dwc->revision < DWC3_REVISION_194A) { 1370 /* write zeroes to Link Change Request */ 1371 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1372 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1373 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1374 } 1375 1376 /* poll until Link State changes to ON */ 1377 timeout = jiffies + msecs_to_jiffies(100); 1378 1379 while (!time_after(jiffies, timeout)) { 1380 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1381 1382 /* in HS, means ON */ 1383 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1384 break; 1385 } 1386 1387 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1388 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1389 ret = -EINVAL; 1390 } 1391 1392out: 1393 spin_unlock_irqrestore(&dwc->lock, flags); 1394 1395 return ret; 1396} 1397 1398static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1399 int is_selfpowered) 1400{ 1401 struct dwc3 *dwc = gadget_to_dwc(g); 1402 unsigned long flags; 1403 1404 spin_lock_irqsave(&dwc->lock, flags); 1405 dwc->is_selfpowered = !!is_selfpowered; 1406 spin_unlock_irqrestore(&dwc->lock, flags); 1407 1408 return 0; 1409} 1410 1411static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) 1412{ 1413 u32 reg; 1414 u32 timeout = 500; 1415 1416 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1417 if (is_on) { 1418 if (dwc->revision <= DWC3_REVISION_187A) { 1419 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1420 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1421 } 1422 1423 if (dwc->revision >= DWC3_REVISION_194A) 1424 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1425 reg |= DWC3_DCTL_RUN_STOP; 1426 } else { 1427 reg &= ~DWC3_DCTL_RUN_STOP; 1428 } 1429 1430 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1431 1432 do { 1433 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1434 if (is_on) { 1435 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1436 break; 1437 } else { 1438 if (reg & DWC3_DSTS_DEVCTRLHLT) 1439 break; 1440 } 1441 timeout--; 1442 if (!timeout) 1443 break; 1444 udelay(1); 1445 } while (1); 1446 1447 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1448 dwc->gadget_driver 1449 ? dwc->gadget_driver->function : "no-function", 1450 is_on ? "connect" : "disconnect"); 1451} 1452 1453static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1454{ 1455 struct dwc3 *dwc = gadget_to_dwc(g); 1456 unsigned long flags; 1457 1458 is_on = !!is_on; 1459 1460 spin_lock_irqsave(&dwc->lock, flags); 1461 dwc3_gadget_run_stop(dwc, is_on); 1462 spin_unlock_irqrestore(&dwc->lock, flags); 1463 1464 return 0; 1465} 1466 1467static int dwc3_gadget_start(struct usb_gadget *g, 1468 struct usb_gadget_driver *driver) 1469{ 1470 struct dwc3 *dwc = gadget_to_dwc(g); 1471 struct dwc3_ep *dep; 1472 unsigned long flags; 1473 int ret = 0; 1474 u32 reg; 1475 1476 spin_lock_irqsave(&dwc->lock, flags); 1477 1478 if (dwc->gadget_driver) { 1479 dev_err(dwc->dev, "%s is already bound to %s\n", 1480 dwc->gadget.name, 1481 dwc->gadget_driver->driver.name); 1482 ret = -EBUSY; 1483 goto err0; 1484 } 1485 1486 dwc->gadget_driver = driver; 1487 dwc->gadget.dev.driver = &driver->driver; 1488 1489 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1490 reg &= ~(DWC3_DCFG_SPEED_MASK); 1491 1492 /** 1493 * WORKAROUND: DWC3 revision < 2.20a have an issue 1494 * which would cause metastability state on Run/Stop 1495 * bit if we try to force the IP to USB2-only mode. 1496 * 1497 * Because of that, we cannot configure the IP to any 1498 * speed other than the SuperSpeed 1499 * 1500 * Refers to: 1501 * 1502 * STAR#9000525659: Clock Domain Crossing on DCTL in 1503 * USB 2.0 Mode 1504 */ 1505 if (dwc->revision < DWC3_REVISION_220A) 1506 reg |= DWC3_DCFG_SUPERSPEED; 1507 else 1508 reg |= dwc->maximum_speed; 1509 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1510 1511 dwc->start_config_issued = false; 1512 1513 /* Start with SuperSpeed Default */ 1514 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1515 1516 dep = dwc->eps[0]; 1517 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1518 if (ret) { 1519 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1520 goto err0; 1521 } 1522 1523 dep = dwc->eps[1]; 1524 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1525 if (ret) { 1526 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1527 goto err1; 1528 } 1529 1530 /* begin to receive SETUP packets */ 1531 dwc->ep0state = EP0_SETUP_PHASE; 1532 dwc3_ep0_out_start(dwc); 1533 1534 spin_unlock_irqrestore(&dwc->lock, flags); 1535 1536 return 0; 1537 1538err1: 1539 __dwc3_gadget_ep_disable(dwc->eps[0]); 1540 1541err0: 1542 spin_unlock_irqrestore(&dwc->lock, flags); 1543 1544 return ret; 1545} 1546 1547static int dwc3_gadget_stop(struct usb_gadget *g, 1548 struct usb_gadget_driver *driver) 1549{ 1550 struct dwc3 *dwc = gadget_to_dwc(g); 1551 unsigned long flags; 1552 1553 spin_lock_irqsave(&dwc->lock, flags); 1554 1555 __dwc3_gadget_ep_disable(dwc->eps[0]); 1556 __dwc3_gadget_ep_disable(dwc->eps[1]); 1557 1558 dwc->gadget_driver = NULL; 1559 dwc->gadget.dev.driver = NULL; 1560 1561 spin_unlock_irqrestore(&dwc->lock, flags); 1562 1563 return 0; 1564} 1565 1566static const struct usb_gadget_ops dwc3_gadget_ops = { 1567 .get_frame = dwc3_gadget_get_frame, 1568 .wakeup = dwc3_gadget_wakeup, 1569 .set_selfpowered = dwc3_gadget_set_selfpowered, 1570 .pullup = dwc3_gadget_pullup, 1571 .udc_start = dwc3_gadget_start, 1572 .udc_stop = dwc3_gadget_stop, 1573}; 1574 1575/* -------------------------------------------------------------------------- */ 1576 1577static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1578{ 1579 struct dwc3_ep *dep; 1580 u8 epnum; 1581 1582 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1583 1584 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1585 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1586 if (!dep) { 1587 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1588 epnum); 1589 return -ENOMEM; 1590 } 1591 1592 dep->dwc = dwc; 1593 dep->number = epnum; 1594 dwc->eps[epnum] = dep; 1595 1596 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1597 (epnum & 1) ? "in" : "out"); 1598 dep->endpoint.name = dep->name; 1599 dep->direction = (epnum & 1); 1600 1601 if (epnum == 0 || epnum == 1) { 1602 dep->endpoint.maxpacket = 512; 1603 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1604 if (!epnum) 1605 dwc->gadget.ep0 = &dep->endpoint; 1606 } else { 1607 int ret; 1608 1609 dep->endpoint.maxpacket = 1024; 1610 dep->endpoint.max_streams = 15; 1611 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1612 list_add_tail(&dep->endpoint.ep_list, 1613 &dwc->gadget.ep_list); 1614 1615 ret = dwc3_alloc_trb_pool(dep); 1616 if (ret) 1617 return ret; 1618 } 1619 1620 INIT_LIST_HEAD(&dep->request_list); 1621 INIT_LIST_HEAD(&dep->req_queued); 1622 } 1623 1624 return 0; 1625} 1626 1627static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1628{ 1629 struct dwc3_ep *dep; 1630 u8 epnum; 1631 1632 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1633 dep = dwc->eps[epnum]; 1634 dwc3_free_trb_pool(dep); 1635 1636 if (epnum != 0 && epnum != 1) 1637 list_del(&dep->endpoint.ep_list); 1638 1639 kfree(dep); 1640 } 1641} 1642 1643static void dwc3_gadget_release(struct device *dev) 1644{ 1645 dev_dbg(dev, "%s\n", __func__); 1646} 1647 1648/* -------------------------------------------------------------------------- */ 1649static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1650 const struct dwc3_event_depevt *event, int status) 1651{ 1652 struct dwc3_request *req; 1653 struct dwc3_trb *trb; 1654 unsigned int count; 1655 unsigned int s_pkt = 0; 1656 unsigned int trb_status; 1657 1658 do { 1659 req = next_request(&dep->req_queued); 1660 if (!req) { 1661 WARN_ON_ONCE(1); 1662 return 1; 1663 } 1664 1665 trb = req->trb; 1666 1667 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 1668 /* 1669 * We continue despite the error. There is not much we 1670 * can do. If we don't clean it up we loop forever. If 1671 * we skip the TRB then it gets overwritten after a 1672 * while since we use them in a ring buffer. A BUG() 1673 * would help. Lets hope that if this occurs, someone 1674 * fixes the root cause instead of looking away :) 1675 */ 1676 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1677 dep->name, req->trb); 1678 count = trb->size & DWC3_TRB_SIZE_MASK; 1679 1680 if (dep->direction) { 1681 if (count) { 1682 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); 1683 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { 1684 dev_dbg(dwc->dev, "incomplete IN transfer %s\n", 1685 dep->name); 1686 dep->current_uf = event->parameters & 1687 ~(dep->interval - 1); 1688 dep->flags |= DWC3_EP_MISSED_ISOC; 1689 } else { 1690 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1691 dep->name); 1692 status = -ECONNRESET; 1693 } 1694 } 1695 } else { 1696 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1697 s_pkt = 1; 1698 } 1699 1700 /* 1701 * We assume here we will always receive the entire data block 1702 * which we should receive. Meaning, if we program RX to 1703 * receive 4K but we receive only 2K, we assume that's all we 1704 * should receive and we simply bounce the request back to the 1705 * gadget driver for further processing. 1706 */ 1707 req->request.actual += req->request.length - count; 1708 dwc3_gadget_giveback(dep, req, status); 1709 if (s_pkt) 1710 break; 1711 if ((event->status & DEPEVT_STATUS_LST) && 1712 (trb->ctrl & (DWC3_TRB_CTRL_LST | 1713 DWC3_TRB_CTRL_HWO))) 1714 break; 1715 if ((event->status & DEPEVT_STATUS_IOC) && 1716 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1717 break; 1718 } while (1); 1719 1720 if ((event->status & DEPEVT_STATUS_IOC) && 1721 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1722 return 0; 1723 return 1; 1724} 1725 1726static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1727 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1728 int start_new) 1729{ 1730 unsigned status = 0; 1731 int clean_busy; 1732 1733 if (event->status & DEPEVT_STATUS_BUSERR) 1734 status = -ECONNRESET; 1735 1736 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1737 if (clean_busy) 1738 dep->flags &= ~DWC3_EP_BUSY; 1739 1740 /* 1741 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1742 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1743 */ 1744 if (dwc->revision < DWC3_REVISION_183A) { 1745 u32 reg; 1746 int i; 1747 1748 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1749 struct dwc3_ep *dep = dwc->eps[i]; 1750 1751 if (!(dep->flags & DWC3_EP_ENABLED)) 1752 continue; 1753 1754 if (!list_empty(&dep->req_queued)) 1755 return; 1756 } 1757 1758 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1759 reg |= dwc->u1u2; 1760 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1761 1762 dwc->u1u2 = 0; 1763 } 1764} 1765 1766static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1767 const struct dwc3_event_depevt *event) 1768{ 1769 struct dwc3_ep *dep; 1770 u8 epnum = event->endpoint_number; 1771 1772 dep = dwc->eps[epnum]; 1773 1774 if (!(dep->flags & DWC3_EP_ENABLED)) 1775 return; 1776 1777 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1778 dwc3_ep_event_string(event->endpoint_event)); 1779 1780 if (epnum == 0 || epnum == 1) { 1781 dwc3_ep0_interrupt(dwc, event); 1782 return; 1783 } 1784 1785 switch (event->endpoint_event) { 1786 case DWC3_DEPEVT_XFERCOMPLETE: 1787 dep->resource_index = 0; 1788 1789 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1790 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1791 dep->name); 1792 return; 1793 } 1794 1795 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1796 break; 1797 case DWC3_DEPEVT_XFERINPROGRESS: 1798 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1799 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1800 dep->name); 1801 return; 1802 } 1803 1804 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1805 break; 1806 case DWC3_DEPEVT_XFERNOTREADY: 1807 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1808 dwc3_gadget_start_isoc(dwc, dep, event); 1809 } else { 1810 int ret; 1811 1812 dev_vdbg(dwc->dev, "%s: reason %s\n", 1813 dep->name, event->status & 1814 DEPEVT_STATUS_TRANSFER_ACTIVE 1815 ? "Transfer Active" 1816 : "Transfer Not Active"); 1817 1818 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1819 if (!ret || ret == -EBUSY) 1820 return; 1821 1822 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1823 dep->name); 1824 } 1825 1826 break; 1827 case DWC3_DEPEVT_STREAMEVT: 1828 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { 1829 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1830 dep->name); 1831 return; 1832 } 1833 1834 switch (event->status) { 1835 case DEPEVT_STREAMEVT_FOUND: 1836 dev_vdbg(dwc->dev, "Stream %d found and started\n", 1837 event->parameters); 1838 1839 break; 1840 case DEPEVT_STREAMEVT_NOTFOUND: 1841 /* FALLTHROUGH */ 1842 default: 1843 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 1844 } 1845 break; 1846 case DWC3_DEPEVT_RXTXFIFOEVT: 1847 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 1848 break; 1849 case DWC3_DEPEVT_EPCMDCMPLT: 1850 dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); 1851 break; 1852 } 1853} 1854 1855static void dwc3_disconnect_gadget(struct dwc3 *dwc) 1856{ 1857 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 1858 spin_unlock(&dwc->lock); 1859 dwc->gadget_driver->disconnect(&dwc->gadget); 1860 spin_lock(&dwc->lock); 1861 } 1862} 1863 1864static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) 1865{ 1866 struct dwc3_ep *dep; 1867 struct dwc3_gadget_ep_cmd_params params; 1868 u32 cmd; 1869 int ret; 1870 1871 dep = dwc->eps[epnum]; 1872 1873 if (!dep->resource_index) 1874 return; 1875 1876 cmd = DWC3_DEPCMD_ENDTRANSFER; 1877 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; 1878 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1879 memset(¶ms, 0, sizeof(params)); 1880 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1881 WARN_ON_ONCE(ret); 1882 dep->resource_index = 0; 1883} 1884 1885static void dwc3_stop_active_transfers(struct dwc3 *dwc) 1886{ 1887 u32 epnum; 1888 1889 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1890 struct dwc3_ep *dep; 1891 1892 dep = dwc->eps[epnum]; 1893 if (!(dep->flags & DWC3_EP_ENABLED)) 1894 continue; 1895 1896 dwc3_remove_requests(dwc, dep); 1897 } 1898} 1899 1900static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 1901{ 1902 u32 epnum; 1903 1904 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1905 struct dwc3_ep *dep; 1906 struct dwc3_gadget_ep_cmd_params params; 1907 int ret; 1908 1909 dep = dwc->eps[epnum]; 1910 1911 if (!(dep->flags & DWC3_EP_STALL)) 1912 continue; 1913 1914 dep->flags &= ~DWC3_EP_STALL; 1915 1916 memset(¶ms, 0, sizeof(params)); 1917 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1918 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1919 WARN_ON_ONCE(ret); 1920 } 1921} 1922 1923static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 1924{ 1925 int reg; 1926 1927 dev_vdbg(dwc->dev, "%s\n", __func__); 1928 1929 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1930 reg &= ~DWC3_DCTL_INITU1ENA; 1931 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1932 1933 reg &= ~DWC3_DCTL_INITU2ENA; 1934 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1935 1936 dwc3_disconnect_gadget(dwc); 1937 dwc->start_config_issued = false; 1938 1939 dwc->gadget.speed = USB_SPEED_UNKNOWN; 1940 dwc->setup_packet_pending = false; 1941} 1942 1943static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend) 1944{ 1945 u32 reg; 1946 1947 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1948 1949 if (suspend) 1950 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1951 else 1952 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 1953 1954 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1955} 1956 1957static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend) 1958{ 1959 u32 reg; 1960 1961 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1962 1963 if (suspend) 1964 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1965 else 1966 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1967 1968 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1969} 1970 1971static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 1972{ 1973 u32 reg; 1974 1975 dev_vdbg(dwc->dev, "%s\n", __func__); 1976 1977 /* 1978 * WORKAROUND: DWC3 revisions <1.88a have an issue which 1979 * would cause a missing Disconnect Event if there's a 1980 * pending Setup Packet in the FIFO. 1981 * 1982 * There's no suggested workaround on the official Bug 1983 * report, which states that "unless the driver/application 1984 * is doing any special handling of a disconnect event, 1985 * there is no functional issue". 1986 * 1987 * Unfortunately, it turns out that we _do_ some special 1988 * handling of a disconnect event, namely complete all 1989 * pending transfers, notify gadget driver of the 1990 * disconnection, and so on. 1991 * 1992 * Our suggested workaround is to follow the Disconnect 1993 * Event steps here, instead, based on a setup_packet_pending 1994 * flag. Such flag gets set whenever we have a XferNotReady 1995 * event on EP0 and gets cleared on XferComplete for the 1996 * same endpoint. 1997 * 1998 * Refers to: 1999 * 2000 * STAR#9000466709: RTL: Device : Disconnect event not 2001 * generated if setup packet pending in FIFO 2002 */ 2003 if (dwc->revision < DWC3_REVISION_188A) { 2004 if (dwc->setup_packet_pending) 2005 dwc3_gadget_disconnect_interrupt(dwc); 2006 } 2007 2008 /* after reset -> Default State */ 2009 dwc->dev_state = DWC3_DEFAULT_STATE; 2010 2011 /* Recent versions support automatic phy suspend and don't need this */ 2012 if (dwc->revision < DWC3_REVISION_194A) { 2013 /* Resume PHYs */ 2014 dwc3_gadget_usb2_phy_suspend(dwc, false); 2015 dwc3_gadget_usb3_phy_suspend(dwc, false); 2016 } 2017 2018 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 2019 dwc3_disconnect_gadget(dwc); 2020 2021 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2022 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2023 reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA); 2024 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 2025 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2026 dwc->test_mode = false; 2027 2028 dwc3_stop_active_transfers(dwc); 2029 dwc3_clear_stall_all_ep(dwc); 2030 dwc->start_config_issued = false; 2031 2032 /* Reset device address to zero */ 2033 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2034 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2035 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2036} 2037 2038static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 2039{ 2040 u32 reg; 2041 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 2042 2043 /* 2044 * We change the clock only at SS but I dunno why I would want to do 2045 * this. Maybe it becomes part of the power saving plan. 2046 */ 2047 2048 if (speed != DWC3_DSTS_SUPERSPEED) 2049 return; 2050 2051 /* 2052 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2053 * each time on Connect Done. 2054 */ 2055 if (!usb30_clock) 2056 return; 2057 2058 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 2059 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 2060 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 2061} 2062 2063static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed) 2064{ 2065 switch (speed) { 2066 case USB_SPEED_SUPER: 2067 dwc3_gadget_usb2_phy_suspend(dwc, true); 2068 break; 2069 case USB_SPEED_HIGH: 2070 case USB_SPEED_FULL: 2071 case USB_SPEED_LOW: 2072 dwc3_gadget_usb3_phy_suspend(dwc, true); 2073 break; 2074 } 2075} 2076 2077static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2078{ 2079 struct dwc3_gadget_ep_cmd_params params; 2080 struct dwc3_ep *dep; 2081 int ret; 2082 u32 reg; 2083 u8 speed; 2084 2085 dev_vdbg(dwc->dev, "%s\n", __func__); 2086 2087 memset(¶ms, 0x00, sizeof(params)); 2088 2089 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2090 speed = reg & DWC3_DSTS_CONNECTSPD; 2091 dwc->speed = speed; 2092 2093 dwc3_update_ram_clk_sel(dwc, speed); 2094 2095 switch (speed) { 2096 case DWC3_DCFG_SUPERSPEED: 2097 /* 2098 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2099 * would cause a missing USB3 Reset event. 2100 * 2101 * In such situations, we should force a USB3 Reset 2102 * event by calling our dwc3_gadget_reset_interrupt() 2103 * routine. 2104 * 2105 * Refers to: 2106 * 2107 * STAR#9000483510: RTL: SS : USB3 reset event may 2108 * not be generated always when the link enters poll 2109 */ 2110 if (dwc->revision < DWC3_REVISION_190A) 2111 dwc3_gadget_reset_interrupt(dwc); 2112 2113 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2114 dwc->gadget.ep0->maxpacket = 512; 2115 dwc->gadget.speed = USB_SPEED_SUPER; 2116 break; 2117 case DWC3_DCFG_HIGHSPEED: 2118 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2119 dwc->gadget.ep0->maxpacket = 64; 2120 dwc->gadget.speed = USB_SPEED_HIGH; 2121 break; 2122 case DWC3_DCFG_FULLSPEED2: 2123 case DWC3_DCFG_FULLSPEED1: 2124 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2125 dwc->gadget.ep0->maxpacket = 64; 2126 dwc->gadget.speed = USB_SPEED_FULL; 2127 break; 2128 case DWC3_DCFG_LOWSPEED: 2129 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2130 dwc->gadget.ep0->maxpacket = 8; 2131 dwc->gadget.speed = USB_SPEED_LOW; 2132 break; 2133 } 2134 2135 /* Recent versions support automatic phy suspend and don't need this */ 2136 if (dwc->revision < DWC3_REVISION_194A) { 2137 /* Suspend unneeded PHY */ 2138 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed); 2139 } 2140 2141 dep = dwc->eps[0]; 2142 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 2143 if (ret) { 2144 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2145 return; 2146 } 2147 2148 dep = dwc->eps[1]; 2149 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 2150 if (ret) { 2151 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2152 return; 2153 } 2154 2155 /* 2156 * Configure PHY via GUSB3PIPECTLn if required. 2157 * 2158 * Update GTXFIFOSIZn 2159 * 2160 * In both cases reset values should be sufficient. 2161 */ 2162} 2163 2164static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2165{ 2166 dev_vdbg(dwc->dev, "%s\n", __func__); 2167 2168 /* 2169 * TODO take core out of low power mode when that's 2170 * implemented. 2171 */ 2172 2173 dwc->gadget_driver->resume(&dwc->gadget); 2174} 2175 2176static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2177 unsigned int evtinfo) 2178{ 2179 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2180 2181 /* 2182 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2183 * on the link partner, the USB session might do multiple entry/exit 2184 * of low power states before a transfer takes place. 2185 * 2186 * Due to this problem, we might experience lower throughput. The 2187 * suggested workaround is to disable DCTL[12:9] bits if we're 2188 * transitioning from U1/U2 to U0 and enable those bits again 2189 * after a transfer completes and there are no pending transfers 2190 * on any of the enabled endpoints. 2191 * 2192 * This is the first half of that workaround. 2193 * 2194 * Refers to: 2195 * 2196 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2197 * core send LGO_Ux entering U0 2198 */ 2199 if (dwc->revision < DWC3_REVISION_183A) { 2200 if (next == DWC3_LINK_STATE_U0) { 2201 u32 u1u2; 2202 u32 reg; 2203 2204 switch (dwc->link_state) { 2205 case DWC3_LINK_STATE_U1: 2206 case DWC3_LINK_STATE_U2: 2207 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2208 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2209 | DWC3_DCTL_ACCEPTU2ENA 2210 | DWC3_DCTL_INITU1ENA 2211 | DWC3_DCTL_ACCEPTU1ENA); 2212 2213 if (!dwc->u1u2) 2214 dwc->u1u2 = reg & u1u2; 2215 2216 reg &= ~u1u2; 2217 2218 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2219 break; 2220 default: 2221 /* do nothing */ 2222 break; 2223 } 2224 } 2225 } 2226 2227 dwc->link_state = next; 2228 2229 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 2230} 2231 2232static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2233 const struct dwc3_event_devt *event) 2234{ 2235 switch (event->type) { 2236 case DWC3_DEVICE_EVENT_DISCONNECT: 2237 dwc3_gadget_disconnect_interrupt(dwc); 2238 break; 2239 case DWC3_DEVICE_EVENT_RESET: 2240 dwc3_gadget_reset_interrupt(dwc); 2241 break; 2242 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2243 dwc3_gadget_conndone_interrupt(dwc); 2244 break; 2245 case DWC3_DEVICE_EVENT_WAKEUP: 2246 dwc3_gadget_wakeup_interrupt(dwc); 2247 break; 2248 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2249 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2250 break; 2251 case DWC3_DEVICE_EVENT_EOPF: 2252 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2253 break; 2254 case DWC3_DEVICE_EVENT_SOF: 2255 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2256 break; 2257 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2258 dev_vdbg(dwc->dev, "Erratic Error\n"); 2259 break; 2260 case DWC3_DEVICE_EVENT_CMD_CMPL: 2261 dev_vdbg(dwc->dev, "Command Complete\n"); 2262 break; 2263 case DWC3_DEVICE_EVENT_OVERFLOW: 2264 dev_vdbg(dwc->dev, "Overflow\n"); 2265 break; 2266 default: 2267 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2268 } 2269} 2270 2271static void dwc3_process_event_entry(struct dwc3 *dwc, 2272 const union dwc3_event *event) 2273{ 2274 /* Endpoint IRQ, handle it and return early */ 2275 if (event->type.is_devspec == 0) { 2276 /* depevt */ 2277 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2278 } 2279 2280 switch (event->type.type) { 2281 case DWC3_EVENT_TYPE_DEV: 2282 dwc3_gadget_interrupt(dwc, &event->devt); 2283 break; 2284 /* REVISIT what to do with Carkit and I2C events ? */ 2285 default: 2286 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2287 } 2288} 2289 2290static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2291{ 2292 struct dwc3_event_buffer *evt; 2293 int left; 2294 u32 count; 2295 2296 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2297 count &= DWC3_GEVNTCOUNT_MASK; 2298 if (!count) 2299 return IRQ_NONE; 2300 2301 evt = dwc->ev_buffs[buf]; 2302 left = count; 2303 2304 while (left > 0) { 2305 union dwc3_event event; 2306 2307 event.raw = *(u32 *) (evt->buf + evt->lpos); 2308 2309 dwc3_process_event_entry(dwc, &event); 2310 /* 2311 * XXX we wrap around correctly to the next entry as almost all 2312 * entries are 4 bytes in size. There is one entry which has 12 2313 * bytes which is a regular entry followed by 8 bytes data. ATM 2314 * I don't know how things are organized if were get next to the 2315 * a boundary so I worry about that once we try to handle that. 2316 */ 2317 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2318 left -= 4; 2319 2320 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2321 } 2322 2323 return IRQ_HANDLED; 2324} 2325 2326static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2327{ 2328 struct dwc3 *dwc = _dwc; 2329 int i; 2330 irqreturn_t ret = IRQ_NONE; 2331 2332 spin_lock(&dwc->lock); 2333 2334 for (i = 0; i < dwc->num_event_buffers; i++) { 2335 irqreturn_t status; 2336 2337 status = dwc3_process_event_buf(dwc, i); 2338 if (status == IRQ_HANDLED) 2339 ret = status; 2340 } 2341 2342 spin_unlock(&dwc->lock); 2343 2344 return ret; 2345} 2346 2347/** 2348 * dwc3_gadget_init - Initializes gadget related registers 2349 * @dwc: pointer to our controller context structure 2350 * 2351 * Returns 0 on success otherwise negative errno. 2352 */ 2353int __devinit dwc3_gadget_init(struct dwc3 *dwc) 2354{ 2355 u32 reg; 2356 int ret; 2357 int irq; 2358 2359 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2360 &dwc->ctrl_req_addr, GFP_KERNEL); 2361 if (!dwc->ctrl_req) { 2362 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2363 ret = -ENOMEM; 2364 goto err0; 2365 } 2366 2367 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2368 &dwc->ep0_trb_addr, GFP_KERNEL); 2369 if (!dwc->ep0_trb) { 2370 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2371 ret = -ENOMEM; 2372 goto err1; 2373 } 2374 2375 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); 2376 if (!dwc->setup_buf) { 2377 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2378 ret = -ENOMEM; 2379 goto err2; 2380 } 2381 2382 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2383 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, 2384 GFP_KERNEL); 2385 if (!dwc->ep0_bounce) { 2386 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2387 ret = -ENOMEM; 2388 goto err3; 2389 } 2390 2391 dev_set_name(&dwc->gadget.dev, "gadget"); 2392 2393 dwc->gadget.ops = &dwc3_gadget_ops; 2394 dwc->gadget.max_speed = USB_SPEED_SUPER; 2395 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2396 dwc->gadget.dev.parent = dwc->dev; 2397 dwc->gadget.sg_supported = true; 2398 2399 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); 2400 2401 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; 2402 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; 2403 dwc->gadget.dev.release = dwc3_gadget_release; 2404 dwc->gadget.name = "dwc3-gadget"; 2405 2406 /* 2407 * REVISIT: Here we should clear all pending IRQs to be 2408 * sure we're starting from a well known location. 2409 */ 2410 2411 ret = dwc3_gadget_init_endpoints(dwc); 2412 if (ret) 2413 goto err4; 2414 2415 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2416 2417 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, 2418 "dwc3", dwc); 2419 if (ret) { 2420 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 2421 irq, ret); 2422 goto err5; 2423 } 2424 2425 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2426 reg |= DWC3_DCFG_LPM_CAP; 2427 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2428 2429 /* Enable all but Start and End of Frame IRQs */ 2430 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 2431 DWC3_DEVTEN_EVNTOVERFLOWEN | 2432 DWC3_DEVTEN_CMDCMPLTEN | 2433 DWC3_DEVTEN_ERRTICERREN | 2434 DWC3_DEVTEN_WKUPEVTEN | 2435 DWC3_DEVTEN_ULSTCNGEN | 2436 DWC3_DEVTEN_CONNECTDONEEN | 2437 DWC3_DEVTEN_USBRSTEN | 2438 DWC3_DEVTEN_DISCONNEVTEN); 2439 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 2440 2441 /* Enable USB2 LPM and automatic phy suspend only on recent versions */ 2442 if (dwc->revision >= DWC3_REVISION_194A) { 2443 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2444 reg |= DWC3_DCFG_LPM_CAP; 2445 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2446 2447 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2448 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2449 2450 /* TODO: This should be configurable */ 2451 reg |= DWC3_DCTL_HIRD_THRES(31); 2452 2453 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2454 2455 dwc3_gadget_usb2_phy_suspend(dwc, false); 2456 dwc3_gadget_usb3_phy_suspend(dwc, false); 2457 } 2458 2459 ret = device_register(&dwc->gadget.dev); 2460 if (ret) { 2461 dev_err(dwc->dev, "failed to register gadget device\n"); 2462 put_device(&dwc->gadget.dev); 2463 goto err6; 2464 } 2465 2466 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2467 if (ret) { 2468 dev_err(dwc->dev, "failed to register udc\n"); 2469 goto err7; 2470 } 2471 2472 return 0; 2473 2474err7: 2475 device_unregister(&dwc->gadget.dev); 2476 2477err6: 2478 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2479 free_irq(irq, dwc); 2480 2481err5: 2482 dwc3_gadget_free_endpoints(dwc); 2483 2484err4: 2485 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2486 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2487 2488err3: 2489 kfree(dwc->setup_buf); 2490 2491err2: 2492 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2493 dwc->ep0_trb, dwc->ep0_trb_addr); 2494 2495err1: 2496 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2497 dwc->ctrl_req, dwc->ctrl_req_addr); 2498 2499err0: 2500 return ret; 2501} 2502 2503void dwc3_gadget_exit(struct dwc3 *dwc) 2504{ 2505 int irq; 2506 2507 usb_del_gadget_udc(&dwc->gadget); 2508 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2509 2510 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2511 free_irq(irq, dwc); 2512 2513 dwc3_gadget_free_endpoints(dwc); 2514 2515 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2516 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2517 2518 kfree(dwc->setup_buf); 2519 2520 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2521 dwc->ep0_trb, dwc->ep0_trb_addr); 2522 2523 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2524 dwc->ctrl_req, dwc->ctrl_req_addr); 2525 2526 device_unregister(&dwc->gadget.dev); 2527} 2528