gadget.c revision 0b7836a9eb32f626ffd3fe3045e8c618cb8ed965
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * All rights reserved. 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The names of the above-listed copyright holders may not be used 20 * to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * ALTERNATIVELY, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2, as published by the Free 25 * Software Foundation. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#include <linux/kernel.h> 41#include <linux/delay.h> 42#include <linux/slab.h> 43#include <linux/spinlock.h> 44#include <linux/platform_device.h> 45#include <linux/pm_runtime.h> 46#include <linux/interrupt.h> 47#include <linux/io.h> 48#include <linux/list.h> 49#include <linux/dma-mapping.h> 50 51#include <linux/usb/ch9.h> 52#include <linux/usb/gadget.h> 53 54#include "core.h" 55#include "gadget.h" 56#include "io.h" 57 58#define DMA_ADDR_INVALID (~(dma_addr_t)0) 59 60void dwc3_map_buffer_to_dma(struct dwc3_request *req) 61{ 62 struct dwc3 *dwc = req->dep->dwc; 63 64 if (req->request.dma == DMA_ADDR_INVALID) { 65 req->request.dma = dma_map_single(dwc->dev, req->request.buf, 66 req->request.length, req->direction 67 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 68 req->mapped = true; 69 } else { 70 dma_sync_single_for_device(dwc->dev, req->request.dma, 71 req->request.length, req->direction 72 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 73 req->mapped = false; 74 } 75} 76 77void dwc3_unmap_buffer_from_dma(struct dwc3_request *req) 78{ 79 struct dwc3 *dwc = req->dep->dwc; 80 81 if (req->mapped) { 82 dma_unmap_single(dwc->dev, req->request.dma, 83 req->request.length, req->direction 84 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 85 req->mapped = 0; 86 req->request.dma = DMA_ADDR_INVALID; 87 } else { 88 dma_sync_single_for_cpu(dwc->dev, req->request.dma, 89 req->request.length, req->direction 90 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 91 } 92} 93 94void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 95 int status) 96{ 97 struct dwc3 *dwc = dep->dwc; 98 99 if (req->queued) { 100 dep->busy_slot++; 101 /* 102 * Skip LINK TRB. We can't use req->trb and check for 103 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just 104 * completed (not the LINK TRB). 105 */ 106 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 107 usb_endpoint_xfer_isoc(dep->desc)) 108 dep->busy_slot++; 109 } 110 list_del(&req->list); 111 112 if (req->request.status == -EINPROGRESS) 113 req->request.status = status; 114 115 dwc3_unmap_buffer_from_dma(req); 116 117 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 118 req, dep->name, req->request.actual, 119 req->request.length, status); 120 121 spin_unlock(&dwc->lock); 122 req->request.complete(&req->dep->endpoint, &req->request); 123 spin_lock(&dwc->lock); 124} 125 126static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 127{ 128 switch (cmd) { 129 case DWC3_DEPCMD_DEPSTARTCFG: 130 return "Start New Configuration"; 131 case DWC3_DEPCMD_ENDTRANSFER: 132 return "End Transfer"; 133 case DWC3_DEPCMD_UPDATETRANSFER: 134 return "Update Transfer"; 135 case DWC3_DEPCMD_STARTTRANSFER: 136 return "Start Transfer"; 137 case DWC3_DEPCMD_CLEARSTALL: 138 return "Clear Stall"; 139 case DWC3_DEPCMD_SETSTALL: 140 return "Set Stall"; 141 case DWC3_DEPCMD_GETSEQNUMBER: 142 return "Get Data Sequence Number"; 143 case DWC3_DEPCMD_SETTRANSFRESOURCE: 144 return "Set Endpoint Transfer Resource"; 145 case DWC3_DEPCMD_SETEPCONFIG: 146 return "Set Endpoint Configuration"; 147 default: 148 return "UNKNOWN command"; 149 } 150} 151 152int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 153 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 154{ 155 struct dwc3_ep *dep = dwc->eps[ep]; 156 u32 timeout = 500; 157 u32 reg; 158 159 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 160 dep->name, 161 dwc3_gadget_ep_cmd_string(cmd), params->param0.raw, 162 params->param1.raw, params->param2.raw); 163 164 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0.raw); 165 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1.raw); 166 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2.raw); 167 168 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 169 do { 170 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 171 if (!(reg & DWC3_DEPCMD_CMDACT)) { 172 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 173 DWC3_DEPCMD_STATUS(reg)); 174 return 0; 175 } 176 177 /* 178 * We can't sleep here, because it is also called from 179 * interrupt context. 180 */ 181 timeout--; 182 if (!timeout) 183 return -ETIMEDOUT; 184 185 udelay(1); 186 } while (1); 187} 188 189static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 190 struct dwc3_trb_hw *trb) 191{ 192 u32 offset = trb - dep->trb_pool; 193 194 return dep->trb_pool_dma + offset; 195} 196 197static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 198{ 199 struct dwc3 *dwc = dep->dwc; 200 201 if (dep->trb_pool) 202 return 0; 203 204 if (dep->number == 0 || dep->number == 1) 205 return 0; 206 207 dep->trb_pool = dma_alloc_coherent(dwc->dev, 208 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 209 &dep->trb_pool_dma, GFP_KERNEL); 210 if (!dep->trb_pool) { 211 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 212 dep->name); 213 return -ENOMEM; 214 } 215 216 return 0; 217} 218 219static void dwc3_free_trb_pool(struct dwc3_ep *dep) 220{ 221 struct dwc3 *dwc = dep->dwc; 222 223 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 224 dep->trb_pool, dep->trb_pool_dma); 225 226 dep->trb_pool = NULL; 227 dep->trb_pool_dma = 0; 228} 229 230static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 231{ 232 struct dwc3_gadget_ep_cmd_params params; 233 u32 cmd; 234 235 memset(¶ms, 0x00, sizeof(params)); 236 237 if (dep->number != 1) { 238 cmd = DWC3_DEPCMD_DEPSTARTCFG; 239 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 240 if (dep->number > 1) 241 cmd |= DWC3_DEPCMD_PARAM(2); 242 243 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 244 } 245 246 return 0; 247} 248 249static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 250 const struct usb_endpoint_descriptor *desc) 251{ 252 struct dwc3_gadget_ep_cmd_params params; 253 254 memset(¶ms, 0x00, sizeof(params)); 255 256 params.param0.depcfg.ep_type = usb_endpoint_type(desc); 257 params.param0.depcfg.max_packet_size = usb_endpoint_maxp(desc); 258 259 params.param1.depcfg.xfer_complete_enable = true; 260 params.param1.depcfg.xfer_not_ready_enable = true; 261 262 if (usb_endpoint_xfer_isoc(desc)) 263 params.param1.depcfg.xfer_in_progress_enable = true; 264 265 /* 266 * We are doing 1:1 mapping for endpoints, meaning 267 * Physical Endpoints 2 maps to Logical Endpoint 2 and 268 * so on. We consider the direction bit as part of the physical 269 * endpoint number. So USB endpoint 0x81 is 0x03. 270 */ 271 params.param1.depcfg.ep_number = dep->number; 272 273 /* 274 * We must use the lower 16 TX FIFOs even though 275 * HW might have more 276 */ 277 if (dep->direction) 278 params.param0.depcfg.fifo_number = dep->number >> 1; 279 280 if (desc->bInterval) { 281 params.param1.depcfg.binterval_m1 = desc->bInterval - 1; 282 dep->interval = 1 << (desc->bInterval - 1); 283 } 284 285 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 286 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 287} 288 289static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 290{ 291 struct dwc3_gadget_ep_cmd_params params; 292 293 memset(¶ms, 0x00, sizeof(params)); 294 295 params.param0.depxfercfg.number_xfer_resources = 1; 296 297 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 298 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 299} 300 301/** 302 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 303 * @dep: endpoint to be initialized 304 * @desc: USB Endpoint Descriptor 305 * 306 * Caller should take care of locking 307 */ 308static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 309 const struct usb_endpoint_descriptor *desc) 310{ 311 struct dwc3 *dwc = dep->dwc; 312 u32 reg; 313 int ret = -ENOMEM; 314 315 if (!(dep->flags & DWC3_EP_ENABLED)) { 316 ret = dwc3_gadget_start_config(dwc, dep); 317 if (ret) 318 return ret; 319 } 320 321 ret = dwc3_gadget_set_ep_config(dwc, dep, desc); 322 if (ret) 323 return ret; 324 325 if (!(dep->flags & DWC3_EP_ENABLED)) { 326 struct dwc3_trb_hw *trb_st_hw; 327 struct dwc3_trb_hw *trb_link_hw; 328 struct dwc3_trb trb_link; 329 330 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 331 if (ret) 332 return ret; 333 334 dep->desc = desc; 335 dep->type = usb_endpoint_type(desc); 336 dep->flags |= DWC3_EP_ENABLED; 337 338 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 339 reg |= DWC3_DALEPENA_EP(dep->number); 340 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 341 342 if (!usb_endpoint_xfer_isoc(desc)) 343 return 0; 344 345 memset(&trb_link, 0, sizeof(trb_link)); 346 347 /* Link TRB for ISOC. The HWO but is never reset */ 348 trb_st_hw = &dep->trb_pool[0]; 349 350 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw); 351 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB; 352 trb_link.hwo = true; 353 354 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1]; 355 dwc3_trb_to_hw(&trb_link, trb_link_hw); 356 } 357 358 return 0; 359} 360 361static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); 362static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 363{ 364 struct dwc3_request *req; 365 366 if (!list_empty(&dep->req_queued)) 367 dwc3_stop_active_transfer(dwc, dep->number); 368 369 while (!list_empty(&dep->request_list)) { 370 req = next_request(&dep->request_list); 371 372 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 373 } 374} 375 376/** 377 * __dwc3_gadget_ep_disable - Disables a HW endpoint 378 * @dep: the endpoint to disable 379 * 380 * This function also removes requests which are currently processed ny the 381 * hardware and those which are not yet scheduled. 382 * Caller should take care of locking. 383 */ 384static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 385{ 386 struct dwc3 *dwc = dep->dwc; 387 u32 reg; 388 389 dep->flags &= ~DWC3_EP_ENABLED; 390 dwc3_remove_requests(dwc, dep); 391 392 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 393 reg &= ~DWC3_DALEPENA_EP(dep->number); 394 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 395 396 dep->desc = NULL; 397 dep->type = 0; 398 399 return 0; 400} 401 402/* -------------------------------------------------------------------------- */ 403 404static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 405 const struct usb_endpoint_descriptor *desc) 406{ 407 return -EINVAL; 408} 409 410static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 411{ 412 return -EINVAL; 413} 414 415/* -------------------------------------------------------------------------- */ 416 417static int dwc3_gadget_ep_enable(struct usb_ep *ep, 418 const struct usb_endpoint_descriptor *desc) 419{ 420 struct dwc3_ep *dep; 421 struct dwc3 *dwc; 422 unsigned long flags; 423 int ret; 424 425 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 426 pr_debug("dwc3: invalid parameters\n"); 427 return -EINVAL; 428 } 429 430 if (!desc->wMaxPacketSize) { 431 pr_debug("dwc3: missing wMaxPacketSize\n"); 432 return -EINVAL; 433 } 434 435 dep = to_dwc3_ep(ep); 436 dwc = dep->dwc; 437 438 switch (usb_endpoint_type(desc)) { 439 case USB_ENDPOINT_XFER_CONTROL: 440 strncat(dep->name, "-control", sizeof(dep->name)); 441 break; 442 case USB_ENDPOINT_XFER_ISOC: 443 strncat(dep->name, "-isoc", sizeof(dep->name)); 444 break; 445 case USB_ENDPOINT_XFER_BULK: 446 strncat(dep->name, "-bulk", sizeof(dep->name)); 447 break; 448 case USB_ENDPOINT_XFER_INT: 449 strncat(dep->name, "-int", sizeof(dep->name)); 450 break; 451 default: 452 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 453 } 454 455 if (dep->flags & DWC3_EP_ENABLED) { 456 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 457 dep->name); 458 return 0; 459 } 460 461 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 462 463 spin_lock_irqsave(&dwc->lock, flags); 464 ret = __dwc3_gadget_ep_enable(dep, desc); 465 spin_unlock_irqrestore(&dwc->lock, flags); 466 467 return ret; 468} 469 470static int dwc3_gadget_ep_disable(struct usb_ep *ep) 471{ 472 struct dwc3_ep *dep; 473 struct dwc3 *dwc; 474 unsigned long flags; 475 int ret; 476 477 if (!ep) { 478 pr_debug("dwc3: invalid parameters\n"); 479 return -EINVAL; 480 } 481 482 dep = to_dwc3_ep(ep); 483 dwc = dep->dwc; 484 485 if (!(dep->flags & DWC3_EP_ENABLED)) { 486 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 487 dep->name); 488 return 0; 489 } 490 491 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 492 dep->number >> 1, 493 (dep->number & 1) ? "in" : "out"); 494 495 spin_lock_irqsave(&dwc->lock, flags); 496 ret = __dwc3_gadget_ep_disable(dep); 497 spin_unlock_irqrestore(&dwc->lock, flags); 498 499 return ret; 500} 501 502static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 503 gfp_t gfp_flags) 504{ 505 struct dwc3_request *req; 506 struct dwc3_ep *dep = to_dwc3_ep(ep); 507 struct dwc3 *dwc = dep->dwc; 508 509 req = kzalloc(sizeof(*req), gfp_flags); 510 if (!req) { 511 dev_err(dwc->dev, "not enough memory\n"); 512 return NULL; 513 } 514 515 req->epnum = dep->number; 516 req->dep = dep; 517 req->request.dma = DMA_ADDR_INVALID; 518 519 return &req->request; 520} 521 522static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 523 struct usb_request *request) 524{ 525 struct dwc3_request *req = to_dwc3_request(request); 526 527 kfree(req); 528} 529 530/* 531 * dwc3_prepare_trbs - setup TRBs from requests 532 * @dep: endpoint for which requests are being prepared 533 * @starting: true if the endpoint is idle and no requests are queued. 534 * 535 * The functions goes through the requests list and setups TRBs for the 536 * transfers. The functions returns once there are not more TRBs available or 537 * it run out of requests. 538 */ 539static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep, 540 bool starting) 541{ 542 struct dwc3_request *req, *n, *ret = NULL; 543 struct dwc3_trb_hw *trb_hw; 544 struct dwc3_trb trb; 545 u32 trbs_left; 546 547 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 548 549 /* the first request must not be queued */ 550 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 551 /* 552 * if busy & slot are equal than it is either full or empty. If we are 553 * starting to proceed requests then we are empty. Otherwise we ar 554 * full and don't do anything 555 */ 556 if (!trbs_left) { 557 if (!starting) 558 return NULL; 559 trbs_left = DWC3_TRB_NUM; 560 /* 561 * In case we start from scratch, we queue the ISOC requests 562 * starting from slot 1. This is done because we use ring 563 * buffer and have no LST bit to stop us. Instead, we place 564 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt 565 * after the first request so we start at slot 1 and have 566 * 7 requests proceed before we hit the first IOC. 567 * Other transfer types don't use the ring buffer and are 568 * processed from the first TRB until the last one. Since we 569 * don't wrap around we have to start at the beginning. 570 */ 571 if (usb_endpoint_xfer_isoc(dep->desc)) { 572 dep->busy_slot = 1; 573 dep->free_slot = 1; 574 } else { 575 dep->busy_slot = 0; 576 dep->free_slot = 0; 577 } 578 } 579 580 /* The last TRB is a link TRB, not used for xfer */ 581 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc)) 582 return NULL; 583 584 list_for_each_entry_safe(req, n, &dep->request_list, list) { 585 unsigned int last_one = 0; 586 unsigned int cur_slot; 587 588 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 589 cur_slot = dep->free_slot; 590 dep->free_slot++; 591 592 /* Skip the LINK-TRB on ISOC */ 593 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 594 usb_endpoint_xfer_isoc(dep->desc)) 595 continue; 596 597 dwc3_gadget_move_request_queued(req); 598 memset(&trb, 0, sizeof(trb)); 599 trbs_left--; 600 601 /* Is our TRB pool empty? */ 602 if (!trbs_left) 603 last_one = 1; 604 /* Is this the last request? */ 605 if (list_empty(&dep->request_list)) 606 last_one = 1; 607 608 /* 609 * FIXME we shouldn't need to set LST bit always but we are 610 * facing some weird problem with the Hardware where it doesn't 611 * complete even though it has been previously started. 612 * 613 * While we're debugging the problem, as a workaround to 614 * multiple TRBs handling, use only one TRB at a time. 615 */ 616 last_one = 1; 617 618 req->trb = trb_hw; 619 if (!ret) 620 ret = req; 621 622 trb.bplh = req->request.dma; 623 624 if (usb_endpoint_xfer_isoc(dep->desc)) { 625 trb.isp_imi = true; 626 trb.csp = true; 627 } else { 628 trb.lst = last_one; 629 } 630 631 switch (usb_endpoint_type(dep->desc)) { 632 case USB_ENDPOINT_XFER_CONTROL: 633 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP; 634 break; 635 636 case USB_ENDPOINT_XFER_ISOC: 637 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 638 639 /* IOC every DWC3_TRB_NUM / 4 so we can refill */ 640 if (!(cur_slot % (DWC3_TRB_NUM / 4))) 641 trb.ioc = last_one; 642 break; 643 644 case USB_ENDPOINT_XFER_BULK: 645 case USB_ENDPOINT_XFER_INT: 646 trb.trbctl = DWC3_TRBCTL_NORMAL; 647 break; 648 default: 649 /* 650 * This is only possible with faulty memory because we 651 * checked it already :) 652 */ 653 BUG(); 654 } 655 656 trb.length = req->request.length; 657 trb.hwo = true; 658 659 dwc3_trb_to_hw(&trb, trb_hw); 660 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw); 661 662 if (last_one) 663 break; 664 } 665 666 return ret; 667} 668 669static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 670 int start_new) 671{ 672 struct dwc3_gadget_ep_cmd_params params; 673 struct dwc3_request *req; 674 struct dwc3 *dwc = dep->dwc; 675 int ret; 676 u32 cmd; 677 678 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 679 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 680 return -EBUSY; 681 } 682 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 683 684 /* 685 * If we are getting here after a short-out-packet we don't enqueue any 686 * new requests as we try to set the IOC bit only on the last request. 687 */ 688 if (start_new) { 689 if (list_empty(&dep->req_queued)) 690 dwc3_prepare_trbs(dep, start_new); 691 692 /* req points to the first request which will be sent */ 693 req = next_request(&dep->req_queued); 694 } else { 695 /* 696 * req points to the first request where HWO changed 697 * from 0 to 1 698 */ 699 req = dwc3_prepare_trbs(dep, start_new); 700 } 701 if (!req) { 702 dep->flags |= DWC3_EP_PENDING_REQUEST; 703 return 0; 704 } 705 706 memset(¶ms, 0, sizeof(params)); 707 params.param0.depstrtxfer.transfer_desc_addr_high = 708 upper_32_bits(req->trb_dma); 709 params.param1.depstrtxfer.transfer_desc_addr_low = 710 lower_32_bits(req->trb_dma); 711 712 if (start_new) 713 cmd = DWC3_DEPCMD_STARTTRANSFER; 714 else 715 cmd = DWC3_DEPCMD_UPDATETRANSFER; 716 717 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 718 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 719 if (ret < 0) { 720 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 721 722 /* 723 * FIXME we need to iterate over the list of requests 724 * here and stop, unmap, free and del each of the linked 725 * requests instead of we do now. 726 */ 727 dwc3_unmap_buffer_from_dma(req); 728 list_del(&req->list); 729 return ret; 730 } 731 732 dep->flags |= DWC3_EP_BUSY; 733 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, 734 dep->number); 735 if (!dep->res_trans_idx) 736 printk_once(KERN_ERR "%s() res_trans_idx is invalid\n", __func__); 737 return 0; 738} 739 740static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 741{ 742 req->request.actual = 0; 743 req->request.status = -EINPROGRESS; 744 req->direction = dep->direction; 745 req->epnum = dep->number; 746 747 /* 748 * We only add to our list of requests now and 749 * start consuming the list once we get XferNotReady 750 * IRQ. 751 * 752 * That way, we avoid doing anything that we don't need 753 * to do now and defer it until the point we receive a 754 * particular token from the Host side. 755 * 756 * This will also avoid Host cancelling URBs due to too 757 * many NACKs. 758 */ 759 dwc3_map_buffer_to_dma(req); 760 list_add_tail(&req->list, &dep->request_list); 761 762 /* 763 * There is one special case: XferNotReady with 764 * empty list of requests. We need to kick the 765 * transfer here in that situation, otherwise 766 * we will be NAKing forever. 767 * 768 * If we get XferNotReady before gadget driver 769 * has a chance to queue a request, we will ACK 770 * the IRQ but won't be able to receive the data 771 * until the next request is queued. The following 772 * code is handling exactly that. 773 */ 774 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 775 int ret; 776 int start_trans; 777 778 start_trans = 1; 779 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 780 dep->flags & DWC3_EP_BUSY) 781 start_trans = 0; 782 783 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans); 784 if (ret && ret != -EBUSY) { 785 struct dwc3 *dwc = dep->dwc; 786 787 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 788 dep->name); 789 } 790 }; 791 792 return 0; 793} 794 795static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 796 gfp_t gfp_flags) 797{ 798 struct dwc3_request *req = to_dwc3_request(request); 799 struct dwc3_ep *dep = to_dwc3_ep(ep); 800 struct dwc3 *dwc = dep->dwc; 801 802 unsigned long flags; 803 804 int ret; 805 806 if (!dep->desc) { 807 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 808 request, ep->name); 809 return -ESHUTDOWN; 810 } 811 812 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 813 request, ep->name, request->length); 814 815 spin_lock_irqsave(&dwc->lock, flags); 816 ret = __dwc3_gadget_ep_queue(dep, req); 817 spin_unlock_irqrestore(&dwc->lock, flags); 818 819 return ret; 820} 821 822static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 823 struct usb_request *request) 824{ 825 struct dwc3_request *req = to_dwc3_request(request); 826 struct dwc3_request *r = NULL; 827 828 struct dwc3_ep *dep = to_dwc3_ep(ep); 829 struct dwc3 *dwc = dep->dwc; 830 831 unsigned long flags; 832 int ret = 0; 833 834 spin_lock_irqsave(&dwc->lock, flags); 835 836 list_for_each_entry(r, &dep->request_list, list) { 837 if (r == req) 838 break; 839 } 840 841 if (r != req) { 842 list_for_each_entry(r, &dep->req_queued, list) { 843 if (r == req) 844 break; 845 } 846 if (r == req) { 847 /* wait until it is processed */ 848 dwc3_stop_active_transfer(dwc, dep->number); 849 goto out0; 850 } 851 dev_err(dwc->dev, "request %p was not queued to %s\n", 852 request, ep->name); 853 ret = -EINVAL; 854 goto out0; 855 } 856 857 /* giveback the request */ 858 dwc3_gadget_giveback(dep, req, -ECONNRESET); 859 860out0: 861 spin_unlock_irqrestore(&dwc->lock, flags); 862 863 return ret; 864} 865 866int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 867{ 868 struct dwc3_gadget_ep_cmd_params params; 869 struct dwc3 *dwc = dep->dwc; 870 int ret; 871 872 memset(¶ms, 0x00, sizeof(params)); 873 874 if (value) { 875 if (dep->number == 0 || dep->number == 1) { 876 /* 877 * Whenever EP0 is stalled, we will restart 878 * the state machine, thus moving back to 879 * Setup Phase 880 */ 881 dwc->ep0state = EP0_SETUP_PHASE; 882 } 883 884 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 885 DWC3_DEPCMD_SETSTALL, ¶ms); 886 if (ret) 887 dev_err(dwc->dev, "failed to %s STALL on %s\n", 888 value ? "set" : "clear", 889 dep->name); 890 else 891 dep->flags |= DWC3_EP_STALL; 892 } else { 893 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 894 DWC3_DEPCMD_CLEARSTALL, ¶ms); 895 if (ret) 896 dev_err(dwc->dev, "failed to %s STALL on %s\n", 897 value ? "set" : "clear", 898 dep->name); 899 else 900 dep->flags &= ~DWC3_EP_STALL; 901 } 902 return ret; 903} 904 905static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 906{ 907 struct dwc3_ep *dep = to_dwc3_ep(ep); 908 struct dwc3 *dwc = dep->dwc; 909 910 unsigned long flags; 911 912 int ret; 913 914 spin_lock_irqsave(&dwc->lock, flags); 915 916 if (usb_endpoint_xfer_isoc(dep->desc)) { 917 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 918 ret = -EINVAL; 919 goto out; 920 } 921 922 ret = __dwc3_gadget_ep_set_halt(dep, value); 923out: 924 spin_unlock_irqrestore(&dwc->lock, flags); 925 926 return ret; 927} 928 929static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 930{ 931 struct dwc3_ep *dep = to_dwc3_ep(ep); 932 933 dep->flags |= DWC3_EP_WEDGE; 934 935 return usb_ep_set_halt(ep); 936} 937 938/* -------------------------------------------------------------------------- */ 939 940static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 941 .bLength = USB_DT_ENDPOINT_SIZE, 942 .bDescriptorType = USB_DT_ENDPOINT, 943 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 944}; 945 946static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 947 .enable = dwc3_gadget_ep0_enable, 948 .disable = dwc3_gadget_ep0_disable, 949 .alloc_request = dwc3_gadget_ep_alloc_request, 950 .free_request = dwc3_gadget_ep_free_request, 951 .queue = dwc3_gadget_ep0_queue, 952 .dequeue = dwc3_gadget_ep_dequeue, 953 .set_halt = dwc3_gadget_ep_set_halt, 954 .set_wedge = dwc3_gadget_ep_set_wedge, 955}; 956 957static const struct usb_ep_ops dwc3_gadget_ep_ops = { 958 .enable = dwc3_gadget_ep_enable, 959 .disable = dwc3_gadget_ep_disable, 960 .alloc_request = dwc3_gadget_ep_alloc_request, 961 .free_request = dwc3_gadget_ep_free_request, 962 .queue = dwc3_gadget_ep_queue, 963 .dequeue = dwc3_gadget_ep_dequeue, 964 .set_halt = dwc3_gadget_ep_set_halt, 965 .set_wedge = dwc3_gadget_ep_set_wedge, 966}; 967 968/* -------------------------------------------------------------------------- */ 969 970static int dwc3_gadget_get_frame(struct usb_gadget *g) 971{ 972 struct dwc3 *dwc = gadget_to_dwc(g); 973 u32 reg; 974 975 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 976 return DWC3_DSTS_SOFFN(reg); 977} 978 979static int dwc3_gadget_wakeup(struct usb_gadget *g) 980{ 981 struct dwc3 *dwc = gadget_to_dwc(g); 982 983 unsigned long timeout; 984 unsigned long flags; 985 986 u32 reg; 987 988 int ret = 0; 989 990 u8 link_state; 991 u8 speed; 992 993 spin_lock_irqsave(&dwc->lock, flags); 994 995 /* 996 * According to the Databook Remote wakeup request should 997 * be issued only when the device is in early suspend state. 998 * 999 * We can check that via USB Link State bits in DSTS register. 1000 */ 1001 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1002 1003 speed = reg & DWC3_DSTS_CONNECTSPD; 1004 if (speed == DWC3_DSTS_SUPERSPEED) { 1005 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1006 ret = -EINVAL; 1007 goto out; 1008 } 1009 1010 link_state = DWC3_DSTS_USBLNKST(reg); 1011 1012 switch (link_state) { 1013 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1014 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1015 break; 1016 default: 1017 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1018 link_state); 1019 ret = -EINVAL; 1020 goto out; 1021 } 1022 1023 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1024 1025 /* 1026 * Switch link state to Recovery. In HS/FS/LS this means 1027 * RemoteWakeup Request 1028 */ 1029 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY; 1030 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1031 1032 /* wait for at least 2000us */ 1033 usleep_range(2000, 2500); 1034 1035 /* write zeroes to Link Change Request */ 1036 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1037 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1038 1039 /* pool until Link State change to ON */ 1040 timeout = jiffies + msecs_to_jiffies(100); 1041 1042 while (!(time_after(jiffies, timeout))) { 1043 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1044 1045 /* in HS, means ON */ 1046 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1047 break; 1048 } 1049 1050 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1051 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1052 ret = -EINVAL; 1053 } 1054 1055out: 1056 spin_unlock_irqrestore(&dwc->lock, flags); 1057 1058 return ret; 1059} 1060 1061static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1062 int is_selfpowered) 1063{ 1064 struct dwc3 *dwc = gadget_to_dwc(g); 1065 1066 dwc->is_selfpowered = !!is_selfpowered; 1067 1068 return 0; 1069} 1070 1071static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) 1072{ 1073 u32 reg; 1074 u32 timeout = 500; 1075 1076 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1077 if (is_on) 1078 reg |= DWC3_DCTL_RUN_STOP; 1079 else 1080 reg &= ~DWC3_DCTL_RUN_STOP; 1081 1082 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1083 1084 do { 1085 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1086 if (is_on) { 1087 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1088 break; 1089 } else { 1090 if (reg & DWC3_DSTS_DEVCTRLHLT) 1091 break; 1092 } 1093 timeout--; 1094 if (!timeout) 1095 break; 1096 udelay(1); 1097 } while (1); 1098 1099 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1100 dwc->gadget_driver 1101 ? dwc->gadget_driver->function : "no-function", 1102 is_on ? "connect" : "disconnect"); 1103} 1104 1105static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1106{ 1107 struct dwc3 *dwc = gadget_to_dwc(g); 1108 unsigned long flags; 1109 1110 is_on = !!is_on; 1111 1112 spin_lock_irqsave(&dwc->lock, flags); 1113 dwc3_gadget_run_stop(dwc, is_on); 1114 spin_unlock_irqrestore(&dwc->lock, flags); 1115 1116 return 0; 1117} 1118 1119static int dwc3_gadget_start(struct usb_gadget *g, 1120 struct usb_gadget_driver *driver) 1121{ 1122 struct dwc3 *dwc = gadget_to_dwc(g); 1123 struct dwc3_ep *dep; 1124 unsigned long flags; 1125 int ret = 0; 1126 u32 reg; 1127 1128 spin_lock_irqsave(&dwc->lock, flags); 1129 1130 if (dwc->gadget_driver) { 1131 dev_err(dwc->dev, "%s is already bound to %s\n", 1132 dwc->gadget.name, 1133 dwc->gadget_driver->driver.name); 1134 ret = -EBUSY; 1135 goto err0; 1136 } 1137 1138 dwc->gadget_driver = driver; 1139 dwc->gadget.dev.driver = &driver->driver; 1140 1141 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1142 1143 /* 1144 * REVISIT: power down scale might be different 1145 * depending on PHY used, need to pass that via platform_data 1146 */ 1147 reg |= DWC3_GCTL_PWRDNSCALE(0x61a) 1148 | DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_DEVICE); 1149 reg &= ~DWC3_GCTL_DISSCRAMBLE; 1150 1151 /* 1152 * WORKAROUND: DWC3 revisions <1.90a have a bug 1153 * when The device fails to connect at SuperSpeed 1154 * and falls back to high-speed mode which causes 1155 * the device to enter in a Connect/Disconnect loop 1156 */ 1157 if (dwc->revision < DWC3_REVISION_190A) 1158 reg |= DWC3_GCTL_U2RSTECN; 1159 1160 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1161 1162 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1163 reg &= ~(DWC3_DCFG_SPEED_MASK); 1164 reg |= DWC3_DCFG_SUPERSPEED; 1165 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1166 1167 /* Start with SuperSpeed Default */ 1168 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1169 1170 dep = dwc->eps[0]; 1171 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc); 1172 if (ret) { 1173 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1174 goto err0; 1175 } 1176 1177 dep = dwc->eps[1]; 1178 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc); 1179 if (ret) { 1180 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1181 goto err1; 1182 } 1183 1184 /* begin to receive SETUP packets */ 1185 dwc->ep0state = EP0_SETUP_PHASE; 1186 dwc3_ep0_out_start(dwc); 1187 1188 spin_unlock_irqrestore(&dwc->lock, flags); 1189 1190 return 0; 1191 1192err1: 1193 __dwc3_gadget_ep_disable(dwc->eps[0]); 1194 1195err0: 1196 spin_unlock_irqrestore(&dwc->lock, flags); 1197 1198 return ret; 1199} 1200 1201static int dwc3_gadget_stop(struct usb_gadget *g, 1202 struct usb_gadget_driver *driver) 1203{ 1204 struct dwc3 *dwc = gadget_to_dwc(g); 1205 unsigned long flags; 1206 1207 spin_lock_irqsave(&dwc->lock, flags); 1208 1209 __dwc3_gadget_ep_disable(dwc->eps[0]); 1210 __dwc3_gadget_ep_disable(dwc->eps[1]); 1211 1212 dwc->gadget_driver = NULL; 1213 dwc->gadget.dev.driver = NULL; 1214 1215 spin_unlock_irqrestore(&dwc->lock, flags); 1216 1217 return 0; 1218} 1219static const struct usb_gadget_ops dwc3_gadget_ops = { 1220 .get_frame = dwc3_gadget_get_frame, 1221 .wakeup = dwc3_gadget_wakeup, 1222 .set_selfpowered = dwc3_gadget_set_selfpowered, 1223 .pullup = dwc3_gadget_pullup, 1224 .udc_start = dwc3_gadget_start, 1225 .udc_stop = dwc3_gadget_stop, 1226}; 1227 1228/* -------------------------------------------------------------------------- */ 1229 1230static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1231{ 1232 struct dwc3_ep *dep; 1233 u8 epnum; 1234 1235 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1236 1237 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1238 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1239 if (!dep) { 1240 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1241 epnum); 1242 return -ENOMEM; 1243 } 1244 1245 dep->dwc = dwc; 1246 dep->number = epnum; 1247 dwc->eps[epnum] = dep; 1248 1249 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1250 (epnum & 1) ? "in" : "out"); 1251 dep->endpoint.name = dep->name; 1252 dep->direction = (epnum & 1); 1253 1254 if (epnum == 0 || epnum == 1) { 1255 dep->endpoint.maxpacket = 512; 1256 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1257 if (!epnum) 1258 dwc->gadget.ep0 = &dep->endpoint; 1259 } else { 1260 int ret; 1261 1262 dep->endpoint.maxpacket = 1024; 1263 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1264 list_add_tail(&dep->endpoint.ep_list, 1265 &dwc->gadget.ep_list); 1266 1267 ret = dwc3_alloc_trb_pool(dep); 1268 if (ret) { 1269 dev_err(dwc->dev, "%s: failed to allocate TRB pool\n", dep->name); 1270 return ret; 1271 } 1272 } 1273 INIT_LIST_HEAD(&dep->request_list); 1274 INIT_LIST_HEAD(&dep->req_queued); 1275 } 1276 1277 return 0; 1278} 1279 1280static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1281{ 1282 struct dwc3_ep *dep; 1283 u8 epnum; 1284 1285 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1286 dep = dwc->eps[epnum]; 1287 dwc3_free_trb_pool(dep); 1288 1289 if (epnum != 0 && epnum != 1) 1290 list_del(&dep->endpoint.ep_list); 1291 1292 kfree(dep); 1293 } 1294} 1295 1296static void dwc3_gadget_release(struct device *dev) 1297{ 1298 dev_dbg(dev, "%s\n", __func__); 1299} 1300 1301/* -------------------------------------------------------------------------- */ 1302static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1303 const struct dwc3_event_depevt *event, int status) 1304{ 1305 struct dwc3_request *req; 1306 struct dwc3_trb trb; 1307 unsigned int count; 1308 unsigned int s_pkt = 0; 1309 1310 do { 1311 req = next_request(&dep->req_queued); 1312 if (!req) 1313 break; 1314 1315 dwc3_trb_to_nat(req->trb, &trb); 1316 1317 if (trb.hwo && status != -ESHUTDOWN) 1318 /* 1319 * We continue despite the error. There is not much we 1320 * can do. If we don't clean in up we loop for ever. If 1321 * we skip the TRB than it gets overwritten reused after 1322 * a while since we use them in a ring buffer. a BUG() 1323 * would help. Lets hope that if this occures, someone 1324 * fixes the root cause instead of looking away :) 1325 */ 1326 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1327 dep->name, req->trb); 1328 count = trb.length; 1329 1330 if (dep->direction) { 1331 if (count) { 1332 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1333 dep->name); 1334 status = -ECONNRESET; 1335 } 1336 } else { 1337 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1338 s_pkt = 1; 1339 } 1340 1341 /* 1342 * We assume here we will always receive the entire data block 1343 * which we should receive. Meaning, if we program RX to 1344 * receive 4K but we receive only 2K, we assume that's all we 1345 * should receive and we simply bounce the request back to the 1346 * gadget driver for further processing. 1347 */ 1348 req->request.actual += req->request.length - count; 1349 dwc3_gadget_giveback(dep, req, status); 1350 if (s_pkt) 1351 break; 1352 if ((event->status & DEPEVT_STATUS_LST) && trb.lst) 1353 break; 1354 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc) 1355 break; 1356 } while (1); 1357 1358 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc) 1359 return 0; 1360 return 1; 1361} 1362 1363static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1364 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1365 int start_new) 1366{ 1367 unsigned status = 0; 1368 int clean_busy; 1369 1370 if (event->status & DEPEVT_STATUS_BUSERR) 1371 status = -ECONNRESET; 1372 1373 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1374 if (clean_busy) { 1375 dep->flags &= ~DWC3_EP_BUSY; 1376 dep->res_trans_idx = 0; 1377 } 1378} 1379 1380static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1381 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1382{ 1383 u32 uf; 1384 1385 if (list_empty(&dep->request_list)) { 1386 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1387 dep->name); 1388 return; 1389 } 1390 1391 if (event->parameters) { 1392 u32 mask; 1393 1394 mask = ~(dep->interval - 1); 1395 uf = event->parameters & mask; 1396 /* 4 micro frames in the future */ 1397 uf += dep->interval * 4; 1398 } else { 1399 uf = 0; 1400 } 1401 1402 __dwc3_gadget_kick_transfer(dep, uf, 1); 1403} 1404 1405static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep, 1406 const struct dwc3_event_depevt *event) 1407{ 1408 struct dwc3 *dwc = dep->dwc; 1409 struct dwc3_event_depevt mod_ev = *event; 1410 1411 /* 1412 * We were asked to remove one requests. It is possible that this 1413 * request and a few other were started together and have the same 1414 * transfer index. Since we stopped the complete endpoint we don't 1415 * know how many requests were already completed (and not yet) 1416 * reported and how could be done (later). We purge them all until 1417 * the end of the list. 1418 */ 1419 mod_ev.status = DEPEVT_STATUS_LST; 1420 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN); 1421 dep->flags &= ~DWC3_EP_BUSY; 1422 /* pending requets are ignored and are queued on XferNotReady */ 1423} 1424 1425static void dwc3_ep_cmd_compl(struct dwc3_ep *dep, 1426 const struct dwc3_event_depevt *event) 1427{ 1428 u32 param = event->parameters; 1429 u32 cmd_type = (param >> 8) & ((1 << 5) - 1); 1430 1431 switch (cmd_type) { 1432 case DWC3_DEPCMD_ENDTRANSFER: 1433 dwc3_process_ep_cmd_complete(dep, event); 1434 break; 1435 case DWC3_DEPCMD_STARTTRANSFER: 1436 dep->res_trans_idx = param & 0x7f; 1437 break; 1438 default: 1439 printk(KERN_ERR "%s() unknown /unexpected type: %d\n", 1440 __func__, cmd_type); 1441 break; 1442 }; 1443} 1444 1445static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1446 const struct dwc3_event_depevt *event) 1447{ 1448 struct dwc3_ep *dep; 1449 u8 epnum = event->endpoint_number; 1450 1451 dep = dwc->eps[epnum]; 1452 1453 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1454 dwc3_ep_event_string(event->endpoint_event)); 1455 1456 if (epnum == 0 || epnum == 1) { 1457 dwc3_ep0_interrupt(dwc, event); 1458 return; 1459 } 1460 1461 switch (event->endpoint_event) { 1462 case DWC3_DEPEVT_XFERCOMPLETE: 1463 if (usb_endpoint_xfer_isoc(dep->desc)) { 1464 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1465 dep->name); 1466 return; 1467 } 1468 1469 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1470 break; 1471 case DWC3_DEPEVT_XFERINPROGRESS: 1472 if (!usb_endpoint_xfer_isoc(dep->desc)) { 1473 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1474 dep->name); 1475 return; 1476 } 1477 1478 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1479 break; 1480 case DWC3_DEPEVT_XFERNOTREADY: 1481 if (usb_endpoint_xfer_isoc(dep->desc)) { 1482 dwc3_gadget_start_isoc(dwc, dep, event); 1483 } else { 1484 int ret; 1485 1486 dev_vdbg(dwc->dev, "%s: reason %s\n", 1487 dep->name, event->status 1488 ? "Transfer Active" 1489 : "Transfer Not Active"); 1490 1491 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1492 if (!ret || ret == -EBUSY) 1493 return; 1494 1495 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1496 dep->name); 1497 } 1498 1499 break; 1500 case DWC3_DEPEVT_RXTXFIFOEVT: 1501 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 1502 break; 1503 case DWC3_DEPEVT_STREAMEVT: 1504 dev_dbg(dwc->dev, "%s Stream Event\n", dep->name); 1505 break; 1506 case DWC3_DEPEVT_EPCMDCMPLT: 1507 dwc3_ep_cmd_compl(dep, event); 1508 break; 1509 } 1510} 1511 1512static void dwc3_disconnect_gadget(struct dwc3 *dwc) 1513{ 1514 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 1515 spin_unlock(&dwc->lock); 1516 dwc->gadget_driver->disconnect(&dwc->gadget); 1517 spin_lock(&dwc->lock); 1518 } 1519} 1520 1521static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) 1522{ 1523 struct dwc3_ep *dep; 1524 struct dwc3_gadget_ep_cmd_params params; 1525 u32 cmd; 1526 int ret; 1527 1528 dep = dwc->eps[epnum]; 1529 1530 WARN_ON(!dep->res_trans_idx); 1531 if (dep->res_trans_idx) { 1532 cmd = DWC3_DEPCMD_ENDTRANSFER; 1533 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; 1534 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx); 1535 memset(¶ms, 0, sizeof(params)); 1536 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1537 WARN_ON_ONCE(ret); 1538 dep->res_trans_idx = 0; 1539 } 1540} 1541 1542static void dwc3_stop_active_transfers(struct dwc3 *dwc) 1543{ 1544 u32 epnum; 1545 1546 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1547 struct dwc3_ep *dep; 1548 1549 dep = dwc->eps[epnum]; 1550 if (!(dep->flags & DWC3_EP_ENABLED)) 1551 continue; 1552 1553 dwc3_remove_requests(dwc, dep); 1554 } 1555} 1556 1557static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 1558{ 1559 u32 epnum; 1560 1561 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1562 struct dwc3_ep *dep; 1563 struct dwc3_gadget_ep_cmd_params params; 1564 int ret; 1565 1566 dep = dwc->eps[epnum]; 1567 1568 if (!(dep->flags & DWC3_EP_STALL)) 1569 continue; 1570 1571 dep->flags &= ~DWC3_EP_STALL; 1572 1573 memset(¶ms, 0, sizeof(params)); 1574 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1575 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1576 WARN_ON_ONCE(ret); 1577 } 1578} 1579 1580static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 1581{ 1582 dev_vdbg(dwc->dev, "%s\n", __func__); 1583#if 0 1584 XXX 1585 U1/U2 is powersave optimization. Skip it for now. Anyway we need to 1586 enable it before we can disable it. 1587 1588 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1589 reg &= ~DWC3_DCTL_INITU1ENA; 1590 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1591 1592 reg &= ~DWC3_DCTL_INITU2ENA; 1593 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1594#endif 1595 1596 dwc3_stop_active_transfers(dwc); 1597 dwc3_disconnect_gadget(dwc); 1598 1599 dwc->gadget.speed = USB_SPEED_UNKNOWN; 1600} 1601 1602static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on) 1603{ 1604 u32 reg; 1605 1606 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1607 1608 if (on) 1609 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 1610 else 1611 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1612 1613 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1614} 1615 1616static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on) 1617{ 1618 u32 reg; 1619 1620 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1621 1622 if (on) 1623 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1624 else 1625 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1626 1627 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1628} 1629 1630static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 1631{ 1632 u32 reg; 1633 1634 dev_vdbg(dwc->dev, "%s\n", __func__); 1635 1636 /* Enable PHYs */ 1637 dwc3_gadget_usb2_phy_power(dwc, true); 1638 dwc3_gadget_usb3_phy_power(dwc, true); 1639 1640 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 1641 dwc3_disconnect_gadget(dwc); 1642 1643 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1644 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 1645 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1646 1647 dwc3_stop_active_transfers(dwc); 1648 dwc3_clear_stall_all_ep(dwc); 1649 1650 /* Reset device address to zero */ 1651 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1652 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 1653 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1654 1655 /* 1656 * Wait for RxFifo to drain 1657 * 1658 * REVISIT probably shouldn't wait forever. 1659 * In case Hardware ends up in a screwed up 1660 * case, we error out, notify the user and, 1661 * maybe, WARN() or BUG() but leave the rest 1662 * of the kernel working fine. 1663 * 1664 * REVISIT the below is rather CPU intensive, 1665 * maybe we should read and if it doesn't work 1666 * sleep (not busy wait) for a few useconds. 1667 * 1668 * REVISIT why wait until the RXFIFO is empty anyway? 1669 */ 1670 while (!(dwc3_readl(dwc->regs, DWC3_DSTS) 1671 & DWC3_DSTS_RXFIFOEMPTY)) 1672 cpu_relax(); 1673} 1674 1675static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 1676{ 1677 u32 reg; 1678 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 1679 1680 /* 1681 * We change the clock only at SS but I dunno why I would want to do 1682 * this. Maybe it becomes part of the power saving plan. 1683 */ 1684 1685 if (speed != DWC3_DSTS_SUPERSPEED) 1686 return; 1687 1688 /* 1689 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 1690 * each time on Connect Done. 1691 */ 1692 if (!usb30_clock) 1693 return; 1694 1695 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1696 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 1697 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1698} 1699 1700static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed) 1701{ 1702 switch (speed) { 1703 case USB_SPEED_SUPER: 1704 dwc3_gadget_usb2_phy_power(dwc, false); 1705 break; 1706 case USB_SPEED_HIGH: 1707 case USB_SPEED_FULL: 1708 case USB_SPEED_LOW: 1709 dwc3_gadget_usb3_phy_power(dwc, false); 1710 break; 1711 } 1712} 1713 1714static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 1715{ 1716 struct dwc3_gadget_ep_cmd_params params; 1717 struct dwc3_ep *dep; 1718 int ret; 1719 u32 reg; 1720 u8 speed; 1721 1722 dev_vdbg(dwc->dev, "%s\n", __func__); 1723 1724 memset(¶ms, 0x00, sizeof(params)); 1725 1726 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1727 speed = reg & DWC3_DSTS_CONNECTSPD; 1728 dwc->speed = speed; 1729 1730 dwc3_update_ram_clk_sel(dwc, speed); 1731 1732 switch (speed) { 1733 case DWC3_DCFG_SUPERSPEED: 1734 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1735 dwc->gadget.ep0->maxpacket = 512; 1736 dwc->gadget.speed = USB_SPEED_SUPER; 1737 break; 1738 case DWC3_DCFG_HIGHSPEED: 1739 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 1740 dwc->gadget.ep0->maxpacket = 64; 1741 dwc->gadget.speed = USB_SPEED_HIGH; 1742 break; 1743 case DWC3_DCFG_FULLSPEED2: 1744 case DWC3_DCFG_FULLSPEED1: 1745 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 1746 dwc->gadget.ep0->maxpacket = 64; 1747 dwc->gadget.speed = USB_SPEED_FULL; 1748 break; 1749 case DWC3_DCFG_LOWSPEED: 1750 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 1751 dwc->gadget.ep0->maxpacket = 8; 1752 dwc->gadget.speed = USB_SPEED_LOW; 1753 break; 1754 } 1755 1756 /* Disable unneded PHY */ 1757 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed); 1758 1759 dep = dwc->eps[0]; 1760 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc); 1761 if (ret) { 1762 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1763 return; 1764 } 1765 1766 dep = dwc->eps[1]; 1767 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc); 1768 if (ret) { 1769 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1770 return; 1771 } 1772 1773 /* 1774 * Configure PHY via GUSB3PIPECTLn if required. 1775 * 1776 * Update GTXFIFOSIZn 1777 * 1778 * In both cases reset values should be sufficient. 1779 */ 1780} 1781 1782static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 1783{ 1784 dev_vdbg(dwc->dev, "%s\n", __func__); 1785 1786 /* 1787 * TODO take core out of low power mode when that's 1788 * implemented. 1789 */ 1790 1791 dwc->gadget_driver->resume(&dwc->gadget); 1792} 1793 1794static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 1795 unsigned int evtinfo) 1796{ 1797 dev_vdbg(dwc->dev, "%s\n", __func__); 1798 1799 /* The fith bit says SuperSpeed yes or no. */ 1800 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK; 1801} 1802 1803static void dwc3_gadget_interrupt(struct dwc3 *dwc, 1804 const struct dwc3_event_devt *event) 1805{ 1806 switch (event->type) { 1807 case DWC3_DEVICE_EVENT_DISCONNECT: 1808 dwc3_gadget_disconnect_interrupt(dwc); 1809 break; 1810 case DWC3_DEVICE_EVENT_RESET: 1811 dwc3_gadget_reset_interrupt(dwc); 1812 break; 1813 case DWC3_DEVICE_EVENT_CONNECT_DONE: 1814 dwc3_gadget_conndone_interrupt(dwc); 1815 break; 1816 case DWC3_DEVICE_EVENT_WAKEUP: 1817 dwc3_gadget_wakeup_interrupt(dwc); 1818 break; 1819 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 1820 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 1821 break; 1822 case DWC3_DEVICE_EVENT_EOPF: 1823 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 1824 break; 1825 case DWC3_DEVICE_EVENT_SOF: 1826 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 1827 break; 1828 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 1829 dev_vdbg(dwc->dev, "Erratic Error\n"); 1830 break; 1831 case DWC3_DEVICE_EVENT_CMD_CMPL: 1832 dev_vdbg(dwc->dev, "Command Complete\n"); 1833 break; 1834 case DWC3_DEVICE_EVENT_OVERFLOW: 1835 dev_vdbg(dwc->dev, "Overflow\n"); 1836 break; 1837 default: 1838 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 1839 } 1840} 1841 1842static void dwc3_process_event_entry(struct dwc3 *dwc, 1843 const union dwc3_event *event) 1844{ 1845 /* Endpoint IRQ, handle it and return early */ 1846 if (event->type.is_devspec == 0) { 1847 /* depevt */ 1848 return dwc3_endpoint_interrupt(dwc, &event->depevt); 1849 } 1850 1851 switch (event->type.type) { 1852 case DWC3_EVENT_TYPE_DEV: 1853 dwc3_gadget_interrupt(dwc, &event->devt); 1854 break; 1855 /* REVISIT what to do with Carkit and I2C events ? */ 1856 default: 1857 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 1858 } 1859} 1860 1861static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 1862{ 1863 struct dwc3_event_buffer *evt; 1864 int left; 1865 u32 count; 1866 1867 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 1868 count &= DWC3_GEVNTCOUNT_MASK; 1869 if (!count) 1870 return IRQ_NONE; 1871 1872 evt = dwc->ev_buffs[buf]; 1873 left = count; 1874 1875 while (left > 0) { 1876 union dwc3_event event; 1877 1878 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw)); 1879 dwc3_process_event_entry(dwc, &event); 1880 /* 1881 * XXX we wrap around correctly to the next entry as almost all 1882 * entries are 4 bytes in size. There is one entry which has 12 1883 * bytes which is a regular entry followed by 8 bytes data. ATM 1884 * I don't know how things are organized if were get next to the 1885 * a boundary so I worry about that once we try to handle that. 1886 */ 1887 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 1888 left -= 4; 1889 1890 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 1891 } 1892 1893 return IRQ_HANDLED; 1894} 1895 1896static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 1897{ 1898 struct dwc3 *dwc = _dwc; 1899 int i; 1900 irqreturn_t ret = IRQ_NONE; 1901 1902 spin_lock(&dwc->lock); 1903 1904 for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) { 1905 irqreturn_t status; 1906 1907 status = dwc3_process_event_buf(dwc, i); 1908 if (status == IRQ_HANDLED) 1909 ret = status; 1910 } 1911 1912 spin_unlock(&dwc->lock); 1913 1914 return ret; 1915} 1916 1917/** 1918 * dwc3_gadget_init - Initializes gadget related registers 1919 * @dwc: Pointer to out controller context structure 1920 * 1921 * Returns 0 on success otherwise negative errno. 1922 */ 1923int __devinit dwc3_gadget_init(struct dwc3 *dwc) 1924{ 1925 u32 reg; 1926 int ret; 1927 int irq; 1928 1929 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 1930 &dwc->ctrl_req_addr, GFP_KERNEL); 1931 if (!dwc->ctrl_req) { 1932 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 1933 ret = -ENOMEM; 1934 goto err0; 1935 } 1936 1937 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 1938 &dwc->ep0_trb_addr, GFP_KERNEL); 1939 if (!dwc->ep0_trb) { 1940 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 1941 ret = -ENOMEM; 1942 goto err1; 1943 } 1944 1945 dwc->setup_buf = dma_alloc_coherent(dwc->dev, 1946 sizeof(*dwc->setup_buf) * 2, 1947 &dwc->setup_buf_addr, GFP_KERNEL); 1948 if (!dwc->setup_buf) { 1949 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 1950 ret = -ENOMEM; 1951 goto err2; 1952 } 1953 1954 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 1955 512, &dwc->ep0_bounce_addr, GFP_KERNEL); 1956 if (!dwc->ep0_bounce) { 1957 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 1958 ret = -ENOMEM; 1959 goto err3; 1960 } 1961 1962 dev_set_name(&dwc->gadget.dev, "gadget"); 1963 1964 dwc->gadget.ops = &dwc3_gadget_ops; 1965 dwc->gadget.is_dualspeed = true; 1966 dwc->gadget.speed = USB_SPEED_UNKNOWN; 1967 dwc->gadget.dev.parent = dwc->dev; 1968 1969 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); 1970 1971 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; 1972 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; 1973 dwc->gadget.dev.release = dwc3_gadget_release; 1974 dwc->gadget.name = "dwc3-gadget"; 1975 1976 /* 1977 * REVISIT: Here we should clear all pending IRQs to be 1978 * sure we're starting from a well known location. 1979 */ 1980 1981 ret = dwc3_gadget_init_endpoints(dwc); 1982 if (ret) 1983 goto err4; 1984 1985 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1986 1987 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, 1988 "dwc3", dwc); 1989 if (ret) { 1990 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 1991 irq, ret); 1992 goto err5; 1993 } 1994 1995 /* Enable all but Start and End of Frame IRQs */ 1996 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 1997 DWC3_DEVTEN_EVNTOVERFLOWEN | 1998 DWC3_DEVTEN_CMDCMPLTEN | 1999 DWC3_DEVTEN_ERRTICERREN | 2000 DWC3_DEVTEN_WKUPEVTEN | 2001 DWC3_DEVTEN_ULSTCNGEN | 2002 DWC3_DEVTEN_CONNECTDONEEN | 2003 DWC3_DEVTEN_USBRSTEN | 2004 DWC3_DEVTEN_DISCONNEVTEN); 2005 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 2006 2007 ret = device_register(&dwc->gadget.dev); 2008 if (ret) { 2009 dev_err(dwc->dev, "failed to register gadget device\n"); 2010 put_device(&dwc->gadget.dev); 2011 goto err6; 2012 } 2013 2014 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2015 if (ret) { 2016 dev_err(dwc->dev, "failed to register udc\n"); 2017 goto err7; 2018 } 2019 2020 return 0; 2021 2022err7: 2023 device_unregister(&dwc->gadget.dev); 2024 2025err6: 2026 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2027 free_irq(irq, dwc); 2028 2029err5: 2030 dwc3_gadget_free_endpoints(dwc); 2031 2032err4: 2033 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce, 2034 dwc->ep0_bounce_addr); 2035 2036err3: 2037 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2, 2038 dwc->setup_buf, dwc->setup_buf_addr); 2039 2040err2: 2041 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2042 dwc->ep0_trb, dwc->ep0_trb_addr); 2043 2044err1: 2045 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2046 dwc->ctrl_req, dwc->ctrl_req_addr); 2047 2048err0: 2049 return ret; 2050} 2051 2052void dwc3_gadget_exit(struct dwc3 *dwc) 2053{ 2054 int irq; 2055 int i; 2056 2057 usb_del_gadget_udc(&dwc->gadget); 2058 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2059 2060 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2061 free_irq(irq, dwc); 2062 2063 for (i = 0; i < ARRAY_SIZE(dwc->eps); i++) 2064 __dwc3_gadget_ep_disable(dwc->eps[i]); 2065 2066 dwc3_gadget_free_endpoints(dwc); 2067 2068 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce, 2069 dwc->ep0_bounce_addr); 2070 2071 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2, 2072 dwc->setup_buf, dwc->setup_buf_addr); 2073 2074 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2075 dwc->ep0_trb, dwc->ep0_trb_addr); 2076 2077 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2078 dwc->ctrl_req, dwc->ctrl_req_addr); 2079 2080 device_unregister(&dwc->gadget.dev); 2081} 2082