gadget.c revision 2e81c36a00d0eb8ce72faaaec1a1d865617374ae
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <linux/kernel.h> 40#include <linux/delay.h> 41#include <linux/slab.h> 42#include <linux/spinlock.h> 43#include <linux/platform_device.h> 44#include <linux/pm_runtime.h> 45#include <linux/interrupt.h> 46#include <linux/io.h> 47#include <linux/list.h> 48#include <linux/dma-mapping.h> 49 50#include <linux/usb/ch9.h> 51#include <linux/usb/gadget.h> 52 53#include "core.h" 54#include "gadget.h" 55#include "io.h" 56 57#define DMA_ADDR_INVALID (~(dma_addr_t)0) 58 59/** 60 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 61 * @dwc: pointer to our context structure 62 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 63 * 64 * Caller should take care of locking. This function will 65 * return 0 on success or -EINVAL if wrong Test Selector 66 * is passed 67 */ 68int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 69{ 70 u32 reg; 71 72 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 73 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 74 75 switch (mode) { 76 case TEST_J: 77 case TEST_K: 78 case TEST_SE0_NAK: 79 case TEST_PACKET: 80 case TEST_FORCE_EN: 81 reg |= mode << 1; 82 break; 83 default: 84 return -EINVAL; 85 } 86 87 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 88 89 return 0; 90} 91 92/** 93 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 94 * @dwc: pointer to our context structure 95 * @state: the state to put link into 96 * 97 * Caller should take care of locking. This function will 98 * return 0 on success or -EINVAL. 99 */ 100int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 101{ 102 int retries = 100; 103 u32 reg; 104 105 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 106 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 107 108 /* set requested state */ 109 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 110 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 111 112 /* wait for a change in DSTS */ 113 while (--retries) { 114 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 115 116 /* in HS, means ON */ 117 if (DWC3_DSTS_USBLNKST(reg) == state) 118 return 0; 119 120 udelay(500); 121 } 122 123 dev_vdbg(dwc->dev, "link state change request timed out\n"); 124 125 return -ETIMEDOUT; 126} 127 128/** 129 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 130 * @dwc: pointer to our context structure 131 * 132 * This function will a best effort FIFO allocation in order 133 * to improve FIFO usage and throughput, while still allowing 134 * us to enable as many endpoints as possible. 135 * 136 * Keep in mind that this operation will be highly dependent 137 * on the configured size for RAM1 - which contains TxFifo -, 138 * the amount of endpoints enabled on coreConsultant tool, and 139 * the width of the Master Bus. 140 * 141 * In the ideal world, we would always be able to satisfy the 142 * following equation: 143 * 144 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 145 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 146 * 147 * Unfortunately, due to many variables that's not always the case. 148 */ 149int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 150{ 151 int last_fifo_depth = 0; 152 int ram1_depth; 153 int fifo_size; 154 int mdwidth; 155 int num; 156 157 if (!dwc->needs_fifo_resize) 158 return 0; 159 160 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 161 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 162 163 /* MDWIDTH is represented in bits, we need it in bytes */ 164 mdwidth >>= 3; 165 166 /* 167 * FIXME For now we will only allocate 1 wMaxPacketSize space 168 * for each enabled endpoint, later patches will come to 169 * improve this algorithm so that we better use the internal 170 * FIFO space 171 */ 172 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { 173 struct dwc3_ep *dep = dwc->eps[num]; 174 int fifo_number = dep->number >> 1; 175 int mult = 1; 176 int tmp; 177 178 if (!(dep->number & 1)) 179 continue; 180 181 if (!(dep->flags & DWC3_EP_ENABLED)) 182 continue; 183 184 if (usb_endpoint_xfer_bulk(dep->desc) 185 || usb_endpoint_xfer_isoc(dep->desc)) 186 mult = 3; 187 188 /* 189 * REVISIT: the following assumes we will always have enough 190 * space available on the FIFO RAM for all possible use cases. 191 * Make sure that's true somehow and change FIFO allocation 192 * accordingly. 193 * 194 * If we have Bulk or Isochronous endpoints, we want 195 * them to be able to be very, very fast. So we're giving 196 * those endpoints a fifo_size which is enough for 3 full 197 * packets 198 */ 199 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 200 tmp += mdwidth; 201 202 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 203 204 fifo_size |= (last_fifo_depth << 16); 205 206 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 207 dep->name, last_fifo_depth, fifo_size & 0xffff); 208 209 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), 210 fifo_size); 211 212 last_fifo_depth += (fifo_size & 0xffff); 213 } 214 215 return 0; 216} 217 218void dwc3_map_buffer_to_dma(struct dwc3_request *req) 219{ 220 struct dwc3 *dwc = req->dep->dwc; 221 222 if (req->request.length == 0) { 223 /* req->request.dma = dwc->setup_buf_addr; */ 224 return; 225 } 226 227 if (req->request.num_sgs) { 228 int mapped; 229 230 mapped = dma_map_sg(dwc->dev, req->request.sg, 231 req->request.num_sgs, 232 req->direction ? DMA_TO_DEVICE 233 : DMA_FROM_DEVICE); 234 if (mapped < 0) { 235 dev_err(dwc->dev, "failed to map SGs\n"); 236 return; 237 } 238 239 req->request.num_mapped_sgs = mapped; 240 return; 241 } 242 243 if (req->request.dma == DMA_ADDR_INVALID) { 244 req->request.dma = dma_map_single(dwc->dev, req->request.buf, 245 req->request.length, req->direction 246 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 247 req->mapped = true; 248 } 249} 250 251void dwc3_unmap_buffer_from_dma(struct dwc3_request *req) 252{ 253 struct dwc3 *dwc = req->dep->dwc; 254 255 if (req->request.length == 0) { 256 req->request.dma = DMA_ADDR_INVALID; 257 return; 258 } 259 260 if (req->request.num_mapped_sgs) { 261 req->request.dma = DMA_ADDR_INVALID; 262 dma_unmap_sg(dwc->dev, req->request.sg, 263 req->request.num_mapped_sgs, 264 req->direction ? DMA_TO_DEVICE 265 : DMA_FROM_DEVICE); 266 267 req->request.num_mapped_sgs = 0; 268 return; 269 } 270 271 if (req->mapped) { 272 dma_unmap_single(dwc->dev, req->request.dma, 273 req->request.length, req->direction 274 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 275 req->mapped = 0; 276 req->request.dma = DMA_ADDR_INVALID; 277 } 278} 279 280void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 281 int status) 282{ 283 struct dwc3 *dwc = dep->dwc; 284 285 if (req->queued) { 286 if (req->request.num_mapped_sgs) 287 dep->busy_slot += req->request.num_mapped_sgs; 288 else 289 dep->busy_slot++; 290 291 /* 292 * Skip LINK TRB. We can't use req->trb and check for 293 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just 294 * completed (not the LINK TRB). 295 */ 296 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 297 usb_endpoint_xfer_isoc(dep->desc)) 298 dep->busy_slot++; 299 } 300 list_del(&req->list); 301 req->trb = NULL; 302 303 if (req->request.status == -EINPROGRESS) 304 req->request.status = status; 305 306 dwc3_unmap_buffer_from_dma(req); 307 308 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 309 req, dep->name, req->request.actual, 310 req->request.length, status); 311 312 spin_unlock(&dwc->lock); 313 req->request.complete(&req->dep->endpoint, &req->request); 314 spin_lock(&dwc->lock); 315} 316 317static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 318{ 319 switch (cmd) { 320 case DWC3_DEPCMD_DEPSTARTCFG: 321 return "Start New Configuration"; 322 case DWC3_DEPCMD_ENDTRANSFER: 323 return "End Transfer"; 324 case DWC3_DEPCMD_UPDATETRANSFER: 325 return "Update Transfer"; 326 case DWC3_DEPCMD_STARTTRANSFER: 327 return "Start Transfer"; 328 case DWC3_DEPCMD_CLEARSTALL: 329 return "Clear Stall"; 330 case DWC3_DEPCMD_SETSTALL: 331 return "Set Stall"; 332 case DWC3_DEPCMD_GETSEQNUMBER: 333 return "Get Data Sequence Number"; 334 case DWC3_DEPCMD_SETTRANSFRESOURCE: 335 return "Set Endpoint Transfer Resource"; 336 case DWC3_DEPCMD_SETEPCONFIG: 337 return "Set Endpoint Configuration"; 338 default: 339 return "UNKNOWN command"; 340 } 341} 342 343int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 344 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 345{ 346 struct dwc3_ep *dep = dwc->eps[ep]; 347 u32 timeout = 500; 348 u32 reg; 349 350 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 351 dep->name, 352 dwc3_gadget_ep_cmd_string(cmd), params->param0, 353 params->param1, params->param2); 354 355 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 356 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 357 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 358 359 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 360 do { 361 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 362 if (!(reg & DWC3_DEPCMD_CMDACT)) { 363 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 364 DWC3_DEPCMD_STATUS(reg)); 365 return 0; 366 } 367 368 /* 369 * We can't sleep here, because it is also called from 370 * interrupt context. 371 */ 372 timeout--; 373 if (!timeout) 374 return -ETIMEDOUT; 375 376 udelay(1); 377 } while (1); 378} 379 380static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 381 struct dwc3_trb_hw *trb) 382{ 383 u32 offset = (char *) trb - (char *) dep->trb_pool; 384 385 return dep->trb_pool_dma + offset; 386} 387 388static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 389{ 390 struct dwc3 *dwc = dep->dwc; 391 392 if (dep->trb_pool) 393 return 0; 394 395 if (dep->number == 0 || dep->number == 1) 396 return 0; 397 398 dep->trb_pool = dma_alloc_coherent(dwc->dev, 399 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 400 &dep->trb_pool_dma, GFP_KERNEL); 401 if (!dep->trb_pool) { 402 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 403 dep->name); 404 return -ENOMEM; 405 } 406 407 return 0; 408} 409 410static void dwc3_free_trb_pool(struct dwc3_ep *dep) 411{ 412 struct dwc3 *dwc = dep->dwc; 413 414 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 415 dep->trb_pool, dep->trb_pool_dma); 416 417 dep->trb_pool = NULL; 418 dep->trb_pool_dma = 0; 419} 420 421static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 422{ 423 struct dwc3_gadget_ep_cmd_params params; 424 u32 cmd; 425 426 memset(¶ms, 0x00, sizeof(params)); 427 428 if (dep->number != 1) { 429 cmd = DWC3_DEPCMD_DEPSTARTCFG; 430 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 431 if (dep->number > 1) { 432 if (dwc->start_config_issued) 433 return 0; 434 dwc->start_config_issued = true; 435 cmd |= DWC3_DEPCMD_PARAM(2); 436 } 437 438 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 439 } 440 441 return 0; 442} 443 444static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 445 const struct usb_endpoint_descriptor *desc, 446 const struct usb_ss_ep_comp_descriptor *comp_desc) 447{ 448 struct dwc3_gadget_ep_cmd_params params; 449 450 memset(¶ms, 0x00, sizeof(params)); 451 452 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 453 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) 454 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst); 455 456 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 457 | DWC3_DEPCFG_XFER_NOT_READY_EN; 458 459 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 460 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 461 | DWC3_DEPCFG_STREAM_EVENT_EN; 462 dep->stream_capable = true; 463 } 464 465 if (usb_endpoint_xfer_isoc(desc)) 466 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 467 468 /* 469 * We are doing 1:1 mapping for endpoints, meaning 470 * Physical Endpoints 2 maps to Logical Endpoint 2 and 471 * so on. We consider the direction bit as part of the physical 472 * endpoint number. So USB endpoint 0x81 is 0x03. 473 */ 474 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 475 476 /* 477 * We must use the lower 16 TX FIFOs even though 478 * HW might have more 479 */ 480 if (dep->direction) 481 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 482 483 if (desc->bInterval) { 484 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 485 dep->interval = 1 << (desc->bInterval - 1); 486 } 487 488 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 489 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 490} 491 492static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 493{ 494 struct dwc3_gadget_ep_cmd_params params; 495 496 memset(¶ms, 0x00, sizeof(params)); 497 498 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 499 500 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 501 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 502} 503 504/** 505 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 506 * @dep: endpoint to be initialized 507 * @desc: USB Endpoint Descriptor 508 * 509 * Caller should take care of locking 510 */ 511static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 512 const struct usb_endpoint_descriptor *desc, 513 const struct usb_ss_ep_comp_descriptor *comp_desc) 514{ 515 struct dwc3 *dwc = dep->dwc; 516 u32 reg; 517 int ret = -ENOMEM; 518 519 if (!(dep->flags & DWC3_EP_ENABLED)) { 520 ret = dwc3_gadget_start_config(dwc, dep); 521 if (ret) 522 return ret; 523 } 524 525 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc); 526 if (ret) 527 return ret; 528 529 if (!(dep->flags & DWC3_EP_ENABLED)) { 530 struct dwc3_trb_hw *trb_st_hw; 531 struct dwc3_trb_hw *trb_link_hw; 532 struct dwc3_trb trb_link; 533 534 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 535 if (ret) 536 return ret; 537 538 dep->desc = desc; 539 dep->comp_desc = comp_desc; 540 dep->type = usb_endpoint_type(desc); 541 dep->flags |= DWC3_EP_ENABLED; 542 543 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 544 reg |= DWC3_DALEPENA_EP(dep->number); 545 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 546 547 if (!usb_endpoint_xfer_isoc(desc)) 548 return 0; 549 550 memset(&trb_link, 0, sizeof(trb_link)); 551 552 /* Link TRB for ISOC. The HWO but is never reset */ 553 trb_st_hw = &dep->trb_pool[0]; 554 555 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw); 556 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB; 557 trb_link.hwo = true; 558 559 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1]; 560 dwc3_trb_to_hw(&trb_link, trb_link_hw); 561 } 562 563 return 0; 564} 565 566static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); 567static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 568{ 569 struct dwc3_request *req; 570 571 if (!list_empty(&dep->req_queued)) 572 dwc3_stop_active_transfer(dwc, dep->number); 573 574 while (!list_empty(&dep->request_list)) { 575 req = next_request(&dep->request_list); 576 577 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 578 } 579} 580 581/** 582 * __dwc3_gadget_ep_disable - Disables a HW endpoint 583 * @dep: the endpoint to disable 584 * 585 * This function also removes requests which are currently processed ny the 586 * hardware and those which are not yet scheduled. 587 * Caller should take care of locking. 588 */ 589static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 590{ 591 struct dwc3 *dwc = dep->dwc; 592 u32 reg; 593 594 dwc3_remove_requests(dwc, dep); 595 596 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 597 reg &= ~DWC3_DALEPENA_EP(dep->number); 598 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 599 600 dep->stream_capable = false; 601 dep->desc = NULL; 602 dep->comp_desc = NULL; 603 dep->type = 0; 604 dep->flags = 0; 605 606 return 0; 607} 608 609/* -------------------------------------------------------------------------- */ 610 611static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 612 const struct usb_endpoint_descriptor *desc) 613{ 614 return -EINVAL; 615} 616 617static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 618{ 619 return -EINVAL; 620} 621 622/* -------------------------------------------------------------------------- */ 623 624static int dwc3_gadget_ep_enable(struct usb_ep *ep, 625 const struct usb_endpoint_descriptor *desc) 626{ 627 struct dwc3_ep *dep; 628 struct dwc3 *dwc; 629 unsigned long flags; 630 int ret; 631 632 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 633 pr_debug("dwc3: invalid parameters\n"); 634 return -EINVAL; 635 } 636 637 if (!desc->wMaxPacketSize) { 638 pr_debug("dwc3: missing wMaxPacketSize\n"); 639 return -EINVAL; 640 } 641 642 dep = to_dwc3_ep(ep); 643 dwc = dep->dwc; 644 645 switch (usb_endpoint_type(desc)) { 646 case USB_ENDPOINT_XFER_CONTROL: 647 strncat(dep->name, "-control", sizeof(dep->name)); 648 break; 649 case USB_ENDPOINT_XFER_ISOC: 650 strncat(dep->name, "-isoc", sizeof(dep->name)); 651 break; 652 case USB_ENDPOINT_XFER_BULK: 653 strncat(dep->name, "-bulk", sizeof(dep->name)); 654 break; 655 case USB_ENDPOINT_XFER_INT: 656 strncat(dep->name, "-int", sizeof(dep->name)); 657 break; 658 default: 659 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 660 } 661 662 if (dep->flags & DWC3_EP_ENABLED) { 663 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 664 dep->name); 665 return 0; 666 } 667 668 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 669 670 spin_lock_irqsave(&dwc->lock, flags); 671 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc); 672 spin_unlock_irqrestore(&dwc->lock, flags); 673 674 return ret; 675} 676 677static int dwc3_gadget_ep_disable(struct usb_ep *ep) 678{ 679 struct dwc3_ep *dep; 680 struct dwc3 *dwc; 681 unsigned long flags; 682 int ret; 683 684 if (!ep) { 685 pr_debug("dwc3: invalid parameters\n"); 686 return -EINVAL; 687 } 688 689 dep = to_dwc3_ep(ep); 690 dwc = dep->dwc; 691 692 if (!(dep->flags & DWC3_EP_ENABLED)) { 693 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 694 dep->name); 695 return 0; 696 } 697 698 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 699 dep->number >> 1, 700 (dep->number & 1) ? "in" : "out"); 701 702 spin_lock_irqsave(&dwc->lock, flags); 703 ret = __dwc3_gadget_ep_disable(dep); 704 spin_unlock_irqrestore(&dwc->lock, flags); 705 706 return ret; 707} 708 709static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 710 gfp_t gfp_flags) 711{ 712 struct dwc3_request *req; 713 struct dwc3_ep *dep = to_dwc3_ep(ep); 714 struct dwc3 *dwc = dep->dwc; 715 716 req = kzalloc(sizeof(*req), gfp_flags); 717 if (!req) { 718 dev_err(dwc->dev, "not enough memory\n"); 719 return NULL; 720 } 721 722 req->epnum = dep->number; 723 req->dep = dep; 724 req->request.dma = DMA_ADDR_INVALID; 725 726 return &req->request; 727} 728 729static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 730 struct usb_request *request) 731{ 732 struct dwc3_request *req = to_dwc3_request(request); 733 734 kfree(req); 735} 736 737/** 738 * dwc3_prepare_one_trb - setup one TRB from one request 739 * @dep: endpoint for which this request is prepared 740 * @req: dwc3_request pointer 741 */ 742static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 743 struct dwc3_request *req, dma_addr_t dma, 744 unsigned length, unsigned last, unsigned chain) 745{ 746 struct dwc3 *dwc = dep->dwc; 747 struct dwc3_trb_hw *trb_hw; 748 struct dwc3_trb trb; 749 750 unsigned int cur_slot; 751 752 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 753 dep->name, req, (unsigned long long) dma, 754 length, last ? " last" : "", 755 chain ? " chain" : ""); 756 757 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 758 cur_slot = dep->free_slot; 759 dep->free_slot++; 760 761 /* Skip the LINK-TRB on ISOC */ 762 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 763 usb_endpoint_xfer_isoc(dep->desc)) 764 return; 765 766 memset(&trb, 0, sizeof(trb)); 767 if (!req->trb) { 768 dwc3_gadget_move_request_queued(req); 769 req->trb = trb_hw; 770 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw); 771 } 772 773 if (usb_endpoint_xfer_isoc(dep->desc)) { 774 trb.isp_imi = true; 775 trb.csp = true; 776 } else { 777 trb.chn = chain; 778 trb.lst = last; 779 } 780 781 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable) 782 trb.sid_sofn = req->request.stream_id; 783 784 switch (usb_endpoint_type(dep->desc)) { 785 case USB_ENDPOINT_XFER_CONTROL: 786 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP; 787 break; 788 789 case USB_ENDPOINT_XFER_ISOC: 790 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 791 792 /* IOC every DWC3_TRB_NUM / 4 so we can refill */ 793 if (!(cur_slot % (DWC3_TRB_NUM / 4))) 794 trb.ioc = last; 795 break; 796 797 case USB_ENDPOINT_XFER_BULK: 798 case USB_ENDPOINT_XFER_INT: 799 trb.trbctl = DWC3_TRBCTL_NORMAL; 800 break; 801 default: 802 /* 803 * This is only possible with faulty memory because we 804 * checked it already :) 805 */ 806 BUG(); 807 } 808 809 trb.length = length; 810 trb.bplh = dma; 811 trb.hwo = true; 812 813 dwc3_trb_to_hw(&trb, trb_hw); 814} 815 816/* 817 * dwc3_prepare_trbs - setup TRBs from requests 818 * @dep: endpoint for which requests are being prepared 819 * @starting: true if the endpoint is idle and no requests are queued. 820 * 821 * The functions goes through the requests list and setups TRBs for the 822 * transfers. The functions returns once there are not more TRBs available or 823 * it run out of requests. 824 */ 825static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 826{ 827 struct dwc3_request *req, *n; 828 u32 trbs_left; 829 unsigned int last_one = 0; 830 831 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 832 833 /* the first request must not be queued */ 834 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 835 836 /* 837 * if busy & slot are equal than it is either full or empty. If we are 838 * starting to proceed requests then we are empty. Otherwise we ar 839 * full and don't do anything 840 */ 841 if (!trbs_left) { 842 if (!starting) 843 return; 844 trbs_left = DWC3_TRB_NUM; 845 /* 846 * In case we start from scratch, we queue the ISOC requests 847 * starting from slot 1. This is done because we use ring 848 * buffer and have no LST bit to stop us. Instead, we place 849 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt 850 * after the first request so we start at slot 1 and have 851 * 7 requests proceed before we hit the first IOC. 852 * Other transfer types don't use the ring buffer and are 853 * processed from the first TRB until the last one. Since we 854 * don't wrap around we have to start at the beginning. 855 */ 856 if (usb_endpoint_xfer_isoc(dep->desc)) { 857 dep->busy_slot = 1; 858 dep->free_slot = 1; 859 } else { 860 dep->busy_slot = 0; 861 dep->free_slot = 0; 862 } 863 } 864 865 /* The last TRB is a link TRB, not used for xfer */ 866 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc)) 867 return; 868 869 list_for_each_entry_safe(req, n, &dep->request_list, list) { 870 unsigned length; 871 dma_addr_t dma; 872 873 if (req->request.num_mapped_sgs > 0) { 874 struct usb_request *request = &req->request; 875 struct scatterlist *sg = request->sg; 876 struct scatterlist *s; 877 int i; 878 879 for_each_sg(sg, s, request->num_mapped_sgs, i) { 880 unsigned chain = true; 881 882 length = sg_dma_len(s); 883 dma = sg_dma_address(s); 884 885 if (i == (request->num_mapped_sgs - 1) 886 || sg_is_last(s)) { 887 last_one = true; 888 chain = false; 889 } 890 891 trbs_left--; 892 if (!trbs_left) 893 last_one = true; 894 895 if (last_one) 896 chain = false; 897 898 dwc3_prepare_one_trb(dep, req, dma, length, 899 last_one, chain); 900 901 if (last_one) 902 break; 903 } 904 } else { 905 dma = req->request.dma; 906 length = req->request.length; 907 trbs_left--; 908 909 if (!trbs_left) 910 last_one = 1; 911 912 /* Is this the last request? */ 913 if (list_is_last(&req->list, &dep->request_list)) 914 last_one = 1; 915 916 dwc3_prepare_one_trb(dep, req, dma, length, 917 last_one, false); 918 919 if (last_one) 920 break; 921 } 922 } 923} 924 925static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 926 int start_new) 927{ 928 struct dwc3_gadget_ep_cmd_params params; 929 struct dwc3_request *req; 930 struct dwc3 *dwc = dep->dwc; 931 int ret; 932 u32 cmd; 933 934 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 935 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 936 return -EBUSY; 937 } 938 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 939 940 /* 941 * If we are getting here after a short-out-packet we don't enqueue any 942 * new requests as we try to set the IOC bit only on the last request. 943 */ 944 if (start_new) { 945 if (list_empty(&dep->req_queued)) 946 dwc3_prepare_trbs(dep, start_new); 947 948 /* req points to the first request which will be sent */ 949 req = next_request(&dep->req_queued); 950 } else { 951 dwc3_prepare_trbs(dep, start_new); 952 953 /* 954 * req points to the first request where HWO changed 955 * from 0 to 1 956 */ 957 req = next_request(&dep->req_queued); 958 } 959 if (!req) { 960 dep->flags |= DWC3_EP_PENDING_REQUEST; 961 return 0; 962 } 963 964 memset(¶ms, 0, sizeof(params)); 965 params.param0 = upper_32_bits(req->trb_dma); 966 params.param1 = lower_32_bits(req->trb_dma); 967 968 if (start_new) 969 cmd = DWC3_DEPCMD_STARTTRANSFER; 970 else 971 cmd = DWC3_DEPCMD_UPDATETRANSFER; 972 973 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 974 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 975 if (ret < 0) { 976 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 977 978 /* 979 * FIXME we need to iterate over the list of requests 980 * here and stop, unmap, free and del each of the linked 981 * requests instead of we do now. 982 */ 983 dwc3_unmap_buffer_from_dma(req); 984 list_del(&req->list); 985 return ret; 986 } 987 988 dep->flags |= DWC3_EP_BUSY; 989 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, 990 dep->number); 991 992 WARN_ON_ONCE(!dep->res_trans_idx); 993 994 return 0; 995} 996 997static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 998{ 999 req->request.actual = 0; 1000 req->request.status = -EINPROGRESS; 1001 req->direction = dep->direction; 1002 req->epnum = dep->number; 1003 1004 /* 1005 * We only add to our list of requests now and 1006 * start consuming the list once we get XferNotReady 1007 * IRQ. 1008 * 1009 * That way, we avoid doing anything that we don't need 1010 * to do now and defer it until the point we receive a 1011 * particular token from the Host side. 1012 * 1013 * This will also avoid Host cancelling URBs due to too 1014 * many NACKs. 1015 */ 1016 dwc3_map_buffer_to_dma(req); 1017 list_add_tail(&req->list, &dep->request_list); 1018 1019 /* 1020 * There is one special case: XferNotReady with 1021 * empty list of requests. We need to kick the 1022 * transfer here in that situation, otherwise 1023 * we will be NAKing forever. 1024 * 1025 * If we get XferNotReady before gadget driver 1026 * has a chance to queue a request, we will ACK 1027 * the IRQ but won't be able to receive the data 1028 * until the next request is queued. The following 1029 * code is handling exactly that. 1030 */ 1031 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1032 int ret; 1033 int start_trans; 1034 1035 start_trans = 1; 1036 if (usb_endpoint_xfer_isoc(dep->desc) && 1037 dep->flags & DWC3_EP_BUSY) 1038 start_trans = 0; 1039 1040 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans); 1041 if (ret && ret != -EBUSY) { 1042 struct dwc3 *dwc = dep->dwc; 1043 1044 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1045 dep->name); 1046 } 1047 }; 1048 1049 return 0; 1050} 1051 1052static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1053 gfp_t gfp_flags) 1054{ 1055 struct dwc3_request *req = to_dwc3_request(request); 1056 struct dwc3_ep *dep = to_dwc3_ep(ep); 1057 struct dwc3 *dwc = dep->dwc; 1058 1059 unsigned long flags; 1060 1061 int ret; 1062 1063 if (!dep->desc) { 1064 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1065 request, ep->name); 1066 return -ESHUTDOWN; 1067 } 1068 1069 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1070 request, ep->name, request->length); 1071 1072 spin_lock_irqsave(&dwc->lock, flags); 1073 ret = __dwc3_gadget_ep_queue(dep, req); 1074 spin_unlock_irqrestore(&dwc->lock, flags); 1075 1076 return ret; 1077} 1078 1079static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1080 struct usb_request *request) 1081{ 1082 struct dwc3_request *req = to_dwc3_request(request); 1083 struct dwc3_request *r = NULL; 1084 1085 struct dwc3_ep *dep = to_dwc3_ep(ep); 1086 struct dwc3 *dwc = dep->dwc; 1087 1088 unsigned long flags; 1089 int ret = 0; 1090 1091 spin_lock_irqsave(&dwc->lock, flags); 1092 1093 list_for_each_entry(r, &dep->request_list, list) { 1094 if (r == req) 1095 break; 1096 } 1097 1098 if (r != req) { 1099 list_for_each_entry(r, &dep->req_queued, list) { 1100 if (r == req) 1101 break; 1102 } 1103 if (r == req) { 1104 /* wait until it is processed */ 1105 dwc3_stop_active_transfer(dwc, dep->number); 1106 goto out0; 1107 } 1108 dev_err(dwc->dev, "request %p was not queued to %s\n", 1109 request, ep->name); 1110 ret = -EINVAL; 1111 goto out0; 1112 } 1113 1114 /* giveback the request */ 1115 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1116 1117out0: 1118 spin_unlock_irqrestore(&dwc->lock, flags); 1119 1120 return ret; 1121} 1122 1123int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1124{ 1125 struct dwc3_gadget_ep_cmd_params params; 1126 struct dwc3 *dwc = dep->dwc; 1127 int ret; 1128 1129 memset(¶ms, 0x00, sizeof(params)); 1130 1131 if (value) { 1132 if (dep->number == 0 || dep->number == 1) { 1133 /* 1134 * Whenever EP0 is stalled, we will restart 1135 * the state machine, thus moving back to 1136 * Setup Phase 1137 */ 1138 dwc->ep0state = EP0_SETUP_PHASE; 1139 } 1140 1141 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1142 DWC3_DEPCMD_SETSTALL, ¶ms); 1143 if (ret) 1144 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1145 value ? "set" : "clear", 1146 dep->name); 1147 else 1148 dep->flags |= DWC3_EP_STALL; 1149 } else { 1150 if (dep->flags & DWC3_EP_WEDGE) 1151 return 0; 1152 1153 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1154 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1155 if (ret) 1156 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1157 value ? "set" : "clear", 1158 dep->name); 1159 else 1160 dep->flags &= ~DWC3_EP_STALL; 1161 } 1162 1163 return ret; 1164} 1165 1166static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1167{ 1168 struct dwc3_ep *dep = to_dwc3_ep(ep); 1169 struct dwc3 *dwc = dep->dwc; 1170 1171 unsigned long flags; 1172 1173 int ret; 1174 1175 spin_lock_irqsave(&dwc->lock, flags); 1176 1177 if (usb_endpoint_xfer_isoc(dep->desc)) { 1178 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1179 ret = -EINVAL; 1180 goto out; 1181 } 1182 1183 ret = __dwc3_gadget_ep_set_halt(dep, value); 1184out: 1185 spin_unlock_irqrestore(&dwc->lock, flags); 1186 1187 return ret; 1188} 1189 1190static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1191{ 1192 struct dwc3_ep *dep = to_dwc3_ep(ep); 1193 1194 dep->flags |= DWC3_EP_WEDGE; 1195 1196 return dwc3_gadget_ep_set_halt(ep, 1); 1197} 1198 1199/* -------------------------------------------------------------------------- */ 1200 1201static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1202 .bLength = USB_DT_ENDPOINT_SIZE, 1203 .bDescriptorType = USB_DT_ENDPOINT, 1204 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1205}; 1206 1207static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1208 .enable = dwc3_gadget_ep0_enable, 1209 .disable = dwc3_gadget_ep0_disable, 1210 .alloc_request = dwc3_gadget_ep_alloc_request, 1211 .free_request = dwc3_gadget_ep_free_request, 1212 .queue = dwc3_gadget_ep0_queue, 1213 .dequeue = dwc3_gadget_ep_dequeue, 1214 .set_halt = dwc3_gadget_ep_set_halt, 1215 .set_wedge = dwc3_gadget_ep_set_wedge, 1216}; 1217 1218static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1219 .enable = dwc3_gadget_ep_enable, 1220 .disable = dwc3_gadget_ep_disable, 1221 .alloc_request = dwc3_gadget_ep_alloc_request, 1222 .free_request = dwc3_gadget_ep_free_request, 1223 .queue = dwc3_gadget_ep_queue, 1224 .dequeue = dwc3_gadget_ep_dequeue, 1225 .set_halt = dwc3_gadget_ep_set_halt, 1226 .set_wedge = dwc3_gadget_ep_set_wedge, 1227}; 1228 1229/* -------------------------------------------------------------------------- */ 1230 1231static int dwc3_gadget_get_frame(struct usb_gadget *g) 1232{ 1233 struct dwc3 *dwc = gadget_to_dwc(g); 1234 u32 reg; 1235 1236 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1237 return DWC3_DSTS_SOFFN(reg); 1238} 1239 1240static int dwc3_gadget_wakeup(struct usb_gadget *g) 1241{ 1242 struct dwc3 *dwc = gadget_to_dwc(g); 1243 1244 unsigned long timeout; 1245 unsigned long flags; 1246 1247 u32 reg; 1248 1249 int ret = 0; 1250 1251 u8 link_state; 1252 u8 speed; 1253 1254 spin_lock_irqsave(&dwc->lock, flags); 1255 1256 /* 1257 * According to the Databook Remote wakeup request should 1258 * be issued only when the device is in early suspend state. 1259 * 1260 * We can check that via USB Link State bits in DSTS register. 1261 */ 1262 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1263 1264 speed = reg & DWC3_DSTS_CONNECTSPD; 1265 if (speed == DWC3_DSTS_SUPERSPEED) { 1266 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1267 ret = -EINVAL; 1268 goto out; 1269 } 1270 1271 link_state = DWC3_DSTS_USBLNKST(reg); 1272 1273 switch (link_state) { 1274 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1275 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1276 break; 1277 default: 1278 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1279 link_state); 1280 ret = -EINVAL; 1281 goto out; 1282 } 1283 1284 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1285 if (ret < 0) { 1286 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1287 goto out; 1288 } 1289 1290 /* write zeroes to Link Change Request */ 1291 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1292 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1293 1294 /* pool until Link State change to ON */ 1295 timeout = jiffies + msecs_to_jiffies(100); 1296 1297 while (!(time_after(jiffies, timeout))) { 1298 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1299 1300 /* in HS, means ON */ 1301 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1302 break; 1303 } 1304 1305 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1306 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1307 ret = -EINVAL; 1308 } 1309 1310out: 1311 spin_unlock_irqrestore(&dwc->lock, flags); 1312 1313 return ret; 1314} 1315 1316static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1317 int is_selfpowered) 1318{ 1319 struct dwc3 *dwc = gadget_to_dwc(g); 1320 1321 dwc->is_selfpowered = !!is_selfpowered; 1322 1323 return 0; 1324} 1325 1326static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) 1327{ 1328 u32 reg; 1329 u32 timeout = 500; 1330 1331 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1332 if (is_on) { 1333 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1334 reg |= (DWC3_DCTL_RUN_STOP 1335 | DWC3_DCTL_TRGTULST_RX_DET); 1336 } else { 1337 reg &= ~DWC3_DCTL_RUN_STOP; 1338 } 1339 1340 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1341 1342 do { 1343 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1344 if (is_on) { 1345 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1346 break; 1347 } else { 1348 if (reg & DWC3_DSTS_DEVCTRLHLT) 1349 break; 1350 } 1351 timeout--; 1352 if (!timeout) 1353 break; 1354 udelay(1); 1355 } while (1); 1356 1357 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1358 dwc->gadget_driver 1359 ? dwc->gadget_driver->function : "no-function", 1360 is_on ? "connect" : "disconnect"); 1361} 1362 1363static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1364{ 1365 struct dwc3 *dwc = gadget_to_dwc(g); 1366 unsigned long flags; 1367 1368 is_on = !!is_on; 1369 1370 spin_lock_irqsave(&dwc->lock, flags); 1371 dwc3_gadget_run_stop(dwc, is_on); 1372 spin_unlock_irqrestore(&dwc->lock, flags); 1373 1374 return 0; 1375} 1376 1377static int dwc3_gadget_start(struct usb_gadget *g, 1378 struct usb_gadget_driver *driver) 1379{ 1380 struct dwc3 *dwc = gadget_to_dwc(g); 1381 struct dwc3_ep *dep; 1382 unsigned long flags; 1383 int ret = 0; 1384 u32 reg; 1385 1386 spin_lock_irqsave(&dwc->lock, flags); 1387 1388 if (dwc->gadget_driver) { 1389 dev_err(dwc->dev, "%s is already bound to %s\n", 1390 dwc->gadget.name, 1391 dwc->gadget_driver->driver.name); 1392 ret = -EBUSY; 1393 goto err0; 1394 } 1395 1396 dwc->gadget_driver = driver; 1397 dwc->gadget.dev.driver = &driver->driver; 1398 1399 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1400 reg &= ~(DWC3_DCFG_SPEED_MASK); 1401 reg |= dwc->maximum_speed; 1402 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1403 1404 dwc->start_config_issued = false; 1405 1406 /* Start with SuperSpeed Default */ 1407 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1408 1409 dep = dwc->eps[0]; 1410 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1411 if (ret) { 1412 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1413 goto err0; 1414 } 1415 1416 dep = dwc->eps[1]; 1417 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1418 if (ret) { 1419 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1420 goto err1; 1421 } 1422 1423 /* begin to receive SETUP packets */ 1424 dwc->ep0state = EP0_SETUP_PHASE; 1425 dwc3_ep0_out_start(dwc); 1426 1427 spin_unlock_irqrestore(&dwc->lock, flags); 1428 1429 return 0; 1430 1431err1: 1432 __dwc3_gadget_ep_disable(dwc->eps[0]); 1433 1434err0: 1435 spin_unlock_irqrestore(&dwc->lock, flags); 1436 1437 return ret; 1438} 1439 1440static int dwc3_gadget_stop(struct usb_gadget *g, 1441 struct usb_gadget_driver *driver) 1442{ 1443 struct dwc3 *dwc = gadget_to_dwc(g); 1444 unsigned long flags; 1445 1446 spin_lock_irqsave(&dwc->lock, flags); 1447 1448 __dwc3_gadget_ep_disable(dwc->eps[0]); 1449 __dwc3_gadget_ep_disable(dwc->eps[1]); 1450 1451 dwc->gadget_driver = NULL; 1452 dwc->gadget.dev.driver = NULL; 1453 1454 spin_unlock_irqrestore(&dwc->lock, flags); 1455 1456 return 0; 1457} 1458static const struct usb_gadget_ops dwc3_gadget_ops = { 1459 .get_frame = dwc3_gadget_get_frame, 1460 .wakeup = dwc3_gadget_wakeup, 1461 .set_selfpowered = dwc3_gadget_set_selfpowered, 1462 .pullup = dwc3_gadget_pullup, 1463 .udc_start = dwc3_gadget_start, 1464 .udc_stop = dwc3_gadget_stop, 1465}; 1466 1467/* -------------------------------------------------------------------------- */ 1468 1469static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1470{ 1471 struct dwc3_ep *dep; 1472 u8 epnum; 1473 1474 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1475 1476 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1477 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1478 if (!dep) { 1479 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1480 epnum); 1481 return -ENOMEM; 1482 } 1483 1484 dep->dwc = dwc; 1485 dep->number = epnum; 1486 dwc->eps[epnum] = dep; 1487 1488 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1489 (epnum & 1) ? "in" : "out"); 1490 dep->endpoint.name = dep->name; 1491 dep->direction = (epnum & 1); 1492 1493 if (epnum == 0 || epnum == 1) { 1494 dep->endpoint.maxpacket = 512; 1495 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1496 if (!epnum) 1497 dwc->gadget.ep0 = &dep->endpoint; 1498 } else { 1499 int ret; 1500 1501 dep->endpoint.maxpacket = 1024; 1502 dep->endpoint.max_streams = 15; 1503 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1504 list_add_tail(&dep->endpoint.ep_list, 1505 &dwc->gadget.ep_list); 1506 1507 ret = dwc3_alloc_trb_pool(dep); 1508 if (ret) 1509 return ret; 1510 } 1511 1512 INIT_LIST_HEAD(&dep->request_list); 1513 INIT_LIST_HEAD(&dep->req_queued); 1514 } 1515 1516 return 0; 1517} 1518 1519static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1520{ 1521 struct dwc3_ep *dep; 1522 u8 epnum; 1523 1524 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1525 dep = dwc->eps[epnum]; 1526 dwc3_free_trb_pool(dep); 1527 1528 if (epnum != 0 && epnum != 1) 1529 list_del(&dep->endpoint.ep_list); 1530 1531 kfree(dep); 1532 } 1533} 1534 1535static void dwc3_gadget_release(struct device *dev) 1536{ 1537 dev_dbg(dev, "%s\n", __func__); 1538} 1539 1540/* -------------------------------------------------------------------------- */ 1541static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1542 const struct dwc3_event_depevt *event, int status) 1543{ 1544 struct dwc3_request *req; 1545 struct dwc3_trb trb; 1546 unsigned int count; 1547 unsigned int s_pkt = 0; 1548 1549 do { 1550 req = next_request(&dep->req_queued); 1551 if (!req) { 1552 WARN_ON_ONCE(1); 1553 return 1; 1554 } 1555 1556 dwc3_trb_to_nat(req->trb, &trb); 1557 1558 if (trb.hwo && status != -ESHUTDOWN) 1559 /* 1560 * We continue despite the error. There is not much we 1561 * can do. If we don't clean in up we loop for ever. If 1562 * we skip the TRB than it gets overwritten reused after 1563 * a while since we use them in a ring buffer. a BUG() 1564 * would help. Lets hope that if this occures, someone 1565 * fixes the root cause instead of looking away :) 1566 */ 1567 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1568 dep->name, req->trb); 1569 count = trb.length; 1570 1571 if (dep->direction) { 1572 if (count) { 1573 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1574 dep->name); 1575 status = -ECONNRESET; 1576 } 1577 } else { 1578 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1579 s_pkt = 1; 1580 } 1581 1582 /* 1583 * We assume here we will always receive the entire data block 1584 * which we should receive. Meaning, if we program RX to 1585 * receive 4K but we receive only 2K, we assume that's all we 1586 * should receive and we simply bounce the request back to the 1587 * gadget driver for further processing. 1588 */ 1589 req->request.actual += req->request.length - count; 1590 dwc3_gadget_giveback(dep, req, status); 1591 if (s_pkt) 1592 break; 1593 if ((event->status & DEPEVT_STATUS_LST) && trb.lst) 1594 break; 1595 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc) 1596 break; 1597 } while (1); 1598 1599 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc) 1600 return 0; 1601 return 1; 1602} 1603 1604static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1605 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1606 int start_new) 1607{ 1608 unsigned status = 0; 1609 int clean_busy; 1610 1611 if (event->status & DEPEVT_STATUS_BUSERR) 1612 status = -ECONNRESET; 1613 1614 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1615 if (clean_busy) { 1616 dep->flags &= ~DWC3_EP_BUSY; 1617 dep->res_trans_idx = 0; 1618 } 1619 1620 /* 1621 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1622 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1623 */ 1624 if (dwc->revision < DWC3_REVISION_183A) { 1625 u32 reg; 1626 int i; 1627 1628 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1629 struct dwc3_ep *dep = dwc->eps[i]; 1630 1631 if (!(dep->flags & DWC3_EP_ENABLED)) 1632 continue; 1633 1634 if (!list_empty(&dep->req_queued)) 1635 return; 1636 } 1637 1638 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1639 reg |= dwc->u1u2; 1640 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1641 1642 dwc->u1u2 = 0; 1643 } 1644} 1645 1646static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1647 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1648{ 1649 u32 uf; 1650 1651 if (list_empty(&dep->request_list)) { 1652 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1653 dep->name); 1654 return; 1655 } 1656 1657 if (event->parameters) { 1658 u32 mask; 1659 1660 mask = ~(dep->interval - 1); 1661 uf = event->parameters & mask; 1662 /* 4 micro frames in the future */ 1663 uf += dep->interval * 4; 1664 } else { 1665 uf = 0; 1666 } 1667 1668 __dwc3_gadget_kick_transfer(dep, uf, 1); 1669} 1670 1671static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep, 1672 const struct dwc3_event_depevt *event) 1673{ 1674 struct dwc3 *dwc = dep->dwc; 1675 struct dwc3_event_depevt mod_ev = *event; 1676 1677 /* 1678 * We were asked to remove one requests. It is possible that this 1679 * request and a few other were started together and have the same 1680 * transfer index. Since we stopped the complete endpoint we don't 1681 * know how many requests were already completed (and not yet) 1682 * reported and how could be done (later). We purge them all until 1683 * the end of the list. 1684 */ 1685 mod_ev.status = DEPEVT_STATUS_LST; 1686 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN); 1687 dep->flags &= ~DWC3_EP_BUSY; 1688 /* pending requets are ignored and are queued on XferNotReady */ 1689} 1690 1691static void dwc3_ep_cmd_compl(struct dwc3_ep *dep, 1692 const struct dwc3_event_depevt *event) 1693{ 1694 u32 param = event->parameters; 1695 u32 cmd_type = (param >> 8) & ((1 << 5) - 1); 1696 1697 switch (cmd_type) { 1698 case DWC3_DEPCMD_ENDTRANSFER: 1699 dwc3_process_ep_cmd_complete(dep, event); 1700 break; 1701 case DWC3_DEPCMD_STARTTRANSFER: 1702 dep->res_trans_idx = param & 0x7f; 1703 break; 1704 default: 1705 printk(KERN_ERR "%s() unknown /unexpected type: %d\n", 1706 __func__, cmd_type); 1707 break; 1708 }; 1709} 1710 1711static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1712 const struct dwc3_event_depevt *event) 1713{ 1714 struct dwc3_ep *dep; 1715 u8 epnum = event->endpoint_number; 1716 1717 dep = dwc->eps[epnum]; 1718 1719 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1720 dwc3_ep_event_string(event->endpoint_event)); 1721 1722 if (epnum == 0 || epnum == 1) { 1723 dwc3_ep0_interrupt(dwc, event); 1724 return; 1725 } 1726 1727 switch (event->endpoint_event) { 1728 case DWC3_DEPEVT_XFERCOMPLETE: 1729 if (usb_endpoint_xfer_isoc(dep->desc)) { 1730 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1731 dep->name); 1732 return; 1733 } 1734 1735 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1736 break; 1737 case DWC3_DEPEVT_XFERINPROGRESS: 1738 if (!usb_endpoint_xfer_isoc(dep->desc)) { 1739 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1740 dep->name); 1741 return; 1742 } 1743 1744 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1745 break; 1746 case DWC3_DEPEVT_XFERNOTREADY: 1747 if (usb_endpoint_xfer_isoc(dep->desc)) { 1748 dwc3_gadget_start_isoc(dwc, dep, event); 1749 } else { 1750 int ret; 1751 1752 dev_vdbg(dwc->dev, "%s: reason %s\n", 1753 dep->name, event->status & 1754 DEPEVT_STATUS_TRANSFER_ACTIVE 1755 ? "Transfer Active" 1756 : "Transfer Not Active"); 1757 1758 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1759 if (!ret || ret == -EBUSY) 1760 return; 1761 1762 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1763 dep->name); 1764 } 1765 1766 break; 1767 case DWC3_DEPEVT_STREAMEVT: 1768 if (!usb_endpoint_xfer_bulk(dep->desc)) { 1769 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1770 dep->name); 1771 return; 1772 } 1773 1774 switch (event->status) { 1775 case DEPEVT_STREAMEVT_FOUND: 1776 dev_vdbg(dwc->dev, "Stream %d found and started\n", 1777 event->parameters); 1778 1779 break; 1780 case DEPEVT_STREAMEVT_NOTFOUND: 1781 /* FALLTHROUGH */ 1782 default: 1783 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 1784 } 1785 break; 1786 case DWC3_DEPEVT_RXTXFIFOEVT: 1787 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 1788 break; 1789 case DWC3_DEPEVT_EPCMDCMPLT: 1790 dwc3_ep_cmd_compl(dep, event); 1791 break; 1792 } 1793} 1794 1795static void dwc3_disconnect_gadget(struct dwc3 *dwc) 1796{ 1797 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 1798 spin_unlock(&dwc->lock); 1799 dwc->gadget_driver->disconnect(&dwc->gadget); 1800 spin_lock(&dwc->lock); 1801 } 1802} 1803 1804static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) 1805{ 1806 struct dwc3_ep *dep; 1807 struct dwc3_gadget_ep_cmd_params params; 1808 u32 cmd; 1809 int ret; 1810 1811 dep = dwc->eps[epnum]; 1812 1813 WARN_ON(!dep->res_trans_idx); 1814 if (dep->res_trans_idx) { 1815 cmd = DWC3_DEPCMD_ENDTRANSFER; 1816 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; 1817 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx); 1818 memset(¶ms, 0, sizeof(params)); 1819 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1820 WARN_ON_ONCE(ret); 1821 dep->res_trans_idx = 0; 1822 } 1823} 1824 1825static void dwc3_stop_active_transfers(struct dwc3 *dwc) 1826{ 1827 u32 epnum; 1828 1829 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1830 struct dwc3_ep *dep; 1831 1832 dep = dwc->eps[epnum]; 1833 if (!(dep->flags & DWC3_EP_ENABLED)) 1834 continue; 1835 1836 dwc3_remove_requests(dwc, dep); 1837 } 1838} 1839 1840static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 1841{ 1842 u32 epnum; 1843 1844 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1845 struct dwc3_ep *dep; 1846 struct dwc3_gadget_ep_cmd_params params; 1847 int ret; 1848 1849 dep = dwc->eps[epnum]; 1850 1851 if (!(dep->flags & DWC3_EP_STALL)) 1852 continue; 1853 1854 dep->flags &= ~DWC3_EP_STALL; 1855 1856 memset(¶ms, 0, sizeof(params)); 1857 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1858 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1859 WARN_ON_ONCE(ret); 1860 } 1861} 1862 1863static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 1864{ 1865 dev_vdbg(dwc->dev, "%s\n", __func__); 1866#if 0 1867 XXX 1868 U1/U2 is powersave optimization. Skip it for now. Anyway we need to 1869 enable it before we can disable it. 1870 1871 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1872 reg &= ~DWC3_DCTL_INITU1ENA; 1873 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1874 1875 reg &= ~DWC3_DCTL_INITU2ENA; 1876 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1877#endif 1878 1879 dwc3_stop_active_transfers(dwc); 1880 dwc3_disconnect_gadget(dwc); 1881 dwc->start_config_issued = false; 1882 1883 dwc->gadget.speed = USB_SPEED_UNKNOWN; 1884 dwc->setup_packet_pending = false; 1885} 1886 1887static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on) 1888{ 1889 u32 reg; 1890 1891 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1892 1893 if (on) 1894 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 1895 else 1896 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1897 1898 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1899} 1900 1901static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on) 1902{ 1903 u32 reg; 1904 1905 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1906 1907 if (on) 1908 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1909 else 1910 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1911 1912 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1913} 1914 1915static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 1916{ 1917 u32 reg; 1918 1919 dev_vdbg(dwc->dev, "%s\n", __func__); 1920 1921 /* 1922 * WORKAROUND: DWC3 revisions <1.88a have an issue which 1923 * would cause a missing Disconnect Event if there's a 1924 * pending Setup Packet in the FIFO. 1925 * 1926 * There's no suggested workaround on the official Bug 1927 * report, which states that "unless the driver/application 1928 * is doing any special handling of a disconnect event, 1929 * there is no functional issue". 1930 * 1931 * Unfortunately, it turns out that we _do_ some special 1932 * handling of a disconnect event, namely complete all 1933 * pending transfers, notify gadget driver of the 1934 * disconnection, and so on. 1935 * 1936 * Our suggested workaround is to follow the Disconnect 1937 * Event steps here, instead, based on a setup_packet_pending 1938 * flag. Such flag gets set whenever we have a XferNotReady 1939 * event on EP0 and gets cleared on XferComplete for the 1940 * same endpoint. 1941 * 1942 * Refers to: 1943 * 1944 * STAR#9000466709: RTL: Device : Disconnect event not 1945 * generated if setup packet pending in FIFO 1946 */ 1947 if (dwc->revision < DWC3_REVISION_188A) { 1948 if (dwc->setup_packet_pending) 1949 dwc3_gadget_disconnect_interrupt(dwc); 1950 } 1951 1952 /* after reset -> Default State */ 1953 dwc->dev_state = DWC3_DEFAULT_STATE; 1954 1955 /* Enable PHYs */ 1956 dwc3_gadget_usb2_phy_power(dwc, true); 1957 dwc3_gadget_usb3_phy_power(dwc, true); 1958 1959 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 1960 dwc3_disconnect_gadget(dwc); 1961 1962 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1963 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 1964 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1965 1966 dwc3_stop_active_transfers(dwc); 1967 dwc3_clear_stall_all_ep(dwc); 1968 dwc->start_config_issued = false; 1969 1970 /* Reset device address to zero */ 1971 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1972 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 1973 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1974} 1975 1976static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 1977{ 1978 u32 reg; 1979 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 1980 1981 /* 1982 * We change the clock only at SS but I dunno why I would want to do 1983 * this. Maybe it becomes part of the power saving plan. 1984 */ 1985 1986 if (speed != DWC3_DSTS_SUPERSPEED) 1987 return; 1988 1989 /* 1990 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 1991 * each time on Connect Done. 1992 */ 1993 if (!usb30_clock) 1994 return; 1995 1996 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1997 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 1998 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1999} 2000 2001static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed) 2002{ 2003 switch (speed) { 2004 case USB_SPEED_SUPER: 2005 dwc3_gadget_usb2_phy_power(dwc, false); 2006 break; 2007 case USB_SPEED_HIGH: 2008 case USB_SPEED_FULL: 2009 case USB_SPEED_LOW: 2010 dwc3_gadget_usb3_phy_power(dwc, false); 2011 break; 2012 } 2013} 2014 2015static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2016{ 2017 struct dwc3_gadget_ep_cmd_params params; 2018 struct dwc3_ep *dep; 2019 int ret; 2020 u32 reg; 2021 u8 speed; 2022 2023 dev_vdbg(dwc->dev, "%s\n", __func__); 2024 2025 memset(¶ms, 0x00, sizeof(params)); 2026 2027 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2028 speed = reg & DWC3_DSTS_CONNECTSPD; 2029 dwc->speed = speed; 2030 2031 dwc3_update_ram_clk_sel(dwc, speed); 2032 2033 switch (speed) { 2034 case DWC3_DCFG_SUPERSPEED: 2035 /* 2036 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2037 * would cause a missing USB3 Reset event. 2038 * 2039 * In such situations, we should force a USB3 Reset 2040 * event by calling our dwc3_gadget_reset_interrupt() 2041 * routine. 2042 * 2043 * Refers to: 2044 * 2045 * STAR#9000483510: RTL: SS : USB3 reset event may 2046 * not be generated always when the link enters poll 2047 */ 2048 if (dwc->revision < DWC3_REVISION_190A) 2049 dwc3_gadget_reset_interrupt(dwc); 2050 2051 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2052 dwc->gadget.ep0->maxpacket = 512; 2053 dwc->gadget.speed = USB_SPEED_SUPER; 2054 break; 2055 case DWC3_DCFG_HIGHSPEED: 2056 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2057 dwc->gadget.ep0->maxpacket = 64; 2058 dwc->gadget.speed = USB_SPEED_HIGH; 2059 break; 2060 case DWC3_DCFG_FULLSPEED2: 2061 case DWC3_DCFG_FULLSPEED1: 2062 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2063 dwc->gadget.ep0->maxpacket = 64; 2064 dwc->gadget.speed = USB_SPEED_FULL; 2065 break; 2066 case DWC3_DCFG_LOWSPEED: 2067 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2068 dwc->gadget.ep0->maxpacket = 8; 2069 dwc->gadget.speed = USB_SPEED_LOW; 2070 break; 2071 } 2072 2073 /* Disable unneded PHY */ 2074 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed); 2075 2076 dep = dwc->eps[0]; 2077 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 2078 if (ret) { 2079 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2080 return; 2081 } 2082 2083 dep = dwc->eps[1]; 2084 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 2085 if (ret) { 2086 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2087 return; 2088 } 2089 2090 /* 2091 * Configure PHY via GUSB3PIPECTLn if required. 2092 * 2093 * Update GTXFIFOSIZn 2094 * 2095 * In both cases reset values should be sufficient. 2096 */ 2097} 2098 2099static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2100{ 2101 dev_vdbg(dwc->dev, "%s\n", __func__); 2102 2103 /* 2104 * TODO take core out of low power mode when that's 2105 * implemented. 2106 */ 2107 2108 dwc->gadget_driver->resume(&dwc->gadget); 2109} 2110 2111static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2112 unsigned int evtinfo) 2113{ 2114 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2115 2116 /* 2117 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2118 * on the link partner, the USB session might do multiple entry/exit 2119 * of low power states before a transfer takes place. 2120 * 2121 * Due to this problem, we might experience lower throughput. The 2122 * suggested workaround is to disable DCTL[12:9] bits if we're 2123 * transitioning from U1/U2 to U0 and enable those bits again 2124 * after a transfer completes and there are no pending transfers 2125 * on any of the enabled endpoints. 2126 * 2127 * This is the first half of that workaround. 2128 * 2129 * Refers to: 2130 * 2131 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2132 * core send LGO_Ux entering U0 2133 */ 2134 if (dwc->revision < DWC3_REVISION_183A) { 2135 if (next == DWC3_LINK_STATE_U0) { 2136 u32 u1u2; 2137 u32 reg; 2138 2139 switch (dwc->link_state) { 2140 case DWC3_LINK_STATE_U1: 2141 case DWC3_LINK_STATE_U2: 2142 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2143 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2144 | DWC3_DCTL_ACCEPTU2ENA 2145 | DWC3_DCTL_INITU1ENA 2146 | DWC3_DCTL_ACCEPTU1ENA); 2147 2148 if (!dwc->u1u2) 2149 dwc->u1u2 = reg & u1u2; 2150 2151 reg &= ~u1u2; 2152 2153 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2154 break; 2155 default: 2156 /* do nothing */ 2157 break; 2158 } 2159 } 2160 } 2161 2162 dwc->link_state = next; 2163 2164 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 2165} 2166 2167static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2168 const struct dwc3_event_devt *event) 2169{ 2170 switch (event->type) { 2171 case DWC3_DEVICE_EVENT_DISCONNECT: 2172 dwc3_gadget_disconnect_interrupt(dwc); 2173 break; 2174 case DWC3_DEVICE_EVENT_RESET: 2175 dwc3_gadget_reset_interrupt(dwc); 2176 break; 2177 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2178 dwc3_gadget_conndone_interrupt(dwc); 2179 break; 2180 case DWC3_DEVICE_EVENT_WAKEUP: 2181 dwc3_gadget_wakeup_interrupt(dwc); 2182 break; 2183 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2184 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2185 break; 2186 case DWC3_DEVICE_EVENT_EOPF: 2187 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2188 break; 2189 case DWC3_DEVICE_EVENT_SOF: 2190 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2191 break; 2192 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2193 dev_vdbg(dwc->dev, "Erratic Error\n"); 2194 break; 2195 case DWC3_DEVICE_EVENT_CMD_CMPL: 2196 dev_vdbg(dwc->dev, "Command Complete\n"); 2197 break; 2198 case DWC3_DEVICE_EVENT_OVERFLOW: 2199 dev_vdbg(dwc->dev, "Overflow\n"); 2200 break; 2201 default: 2202 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2203 } 2204} 2205 2206static void dwc3_process_event_entry(struct dwc3 *dwc, 2207 const union dwc3_event *event) 2208{ 2209 /* Endpoint IRQ, handle it and return early */ 2210 if (event->type.is_devspec == 0) { 2211 /* depevt */ 2212 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2213 } 2214 2215 switch (event->type.type) { 2216 case DWC3_EVENT_TYPE_DEV: 2217 dwc3_gadget_interrupt(dwc, &event->devt); 2218 break; 2219 /* REVISIT what to do with Carkit and I2C events ? */ 2220 default: 2221 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2222 } 2223} 2224 2225static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2226{ 2227 struct dwc3_event_buffer *evt; 2228 int left; 2229 u32 count; 2230 2231 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2232 count &= DWC3_GEVNTCOUNT_MASK; 2233 if (!count) 2234 return IRQ_NONE; 2235 2236 evt = dwc->ev_buffs[buf]; 2237 left = count; 2238 2239 while (left > 0) { 2240 union dwc3_event event; 2241 2242 event.raw = *(u32 *) (evt->buf + evt->lpos); 2243 2244 dwc3_process_event_entry(dwc, &event); 2245 /* 2246 * XXX we wrap around correctly to the next entry as almost all 2247 * entries are 4 bytes in size. There is one entry which has 12 2248 * bytes which is a regular entry followed by 8 bytes data. ATM 2249 * I don't know how things are organized if were get next to the 2250 * a boundary so I worry about that once we try to handle that. 2251 */ 2252 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2253 left -= 4; 2254 2255 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2256 } 2257 2258 return IRQ_HANDLED; 2259} 2260 2261static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2262{ 2263 struct dwc3 *dwc = _dwc; 2264 int i; 2265 irqreturn_t ret = IRQ_NONE; 2266 2267 spin_lock(&dwc->lock); 2268 2269 for (i = 0; i < dwc->num_event_buffers; i++) { 2270 irqreturn_t status; 2271 2272 status = dwc3_process_event_buf(dwc, i); 2273 if (status == IRQ_HANDLED) 2274 ret = status; 2275 } 2276 2277 spin_unlock(&dwc->lock); 2278 2279 return ret; 2280} 2281 2282/** 2283 * dwc3_gadget_init - Initializes gadget related registers 2284 * @dwc: Pointer to out controller context structure 2285 * 2286 * Returns 0 on success otherwise negative errno. 2287 */ 2288int __devinit dwc3_gadget_init(struct dwc3 *dwc) 2289{ 2290 u32 reg; 2291 int ret; 2292 int irq; 2293 2294 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2295 &dwc->ctrl_req_addr, GFP_KERNEL); 2296 if (!dwc->ctrl_req) { 2297 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2298 ret = -ENOMEM; 2299 goto err0; 2300 } 2301 2302 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2303 &dwc->ep0_trb_addr, GFP_KERNEL); 2304 if (!dwc->ep0_trb) { 2305 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2306 ret = -ENOMEM; 2307 goto err1; 2308 } 2309 2310 dwc->setup_buf = dma_alloc_coherent(dwc->dev, 2311 sizeof(*dwc->setup_buf) * 2, 2312 &dwc->setup_buf_addr, GFP_KERNEL); 2313 if (!dwc->setup_buf) { 2314 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2315 ret = -ENOMEM; 2316 goto err2; 2317 } 2318 2319 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2320 512, &dwc->ep0_bounce_addr, GFP_KERNEL); 2321 if (!dwc->ep0_bounce) { 2322 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2323 ret = -ENOMEM; 2324 goto err3; 2325 } 2326 2327 dev_set_name(&dwc->gadget.dev, "gadget"); 2328 2329 dwc->gadget.ops = &dwc3_gadget_ops; 2330 dwc->gadget.max_speed = USB_SPEED_SUPER; 2331 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2332 dwc->gadget.dev.parent = dwc->dev; 2333 dwc->gadget.sg_supported = true; 2334 2335 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); 2336 2337 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; 2338 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; 2339 dwc->gadget.dev.release = dwc3_gadget_release; 2340 dwc->gadget.name = "dwc3-gadget"; 2341 2342 /* 2343 * REVISIT: Here we should clear all pending IRQs to be 2344 * sure we're starting from a well known location. 2345 */ 2346 2347 ret = dwc3_gadget_init_endpoints(dwc); 2348 if (ret) 2349 goto err4; 2350 2351 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2352 2353 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, 2354 "dwc3", dwc); 2355 if (ret) { 2356 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 2357 irq, ret); 2358 goto err5; 2359 } 2360 2361 /* Enable all but Start and End of Frame IRQs */ 2362 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 2363 DWC3_DEVTEN_EVNTOVERFLOWEN | 2364 DWC3_DEVTEN_CMDCMPLTEN | 2365 DWC3_DEVTEN_ERRTICERREN | 2366 DWC3_DEVTEN_WKUPEVTEN | 2367 DWC3_DEVTEN_ULSTCNGEN | 2368 DWC3_DEVTEN_CONNECTDONEEN | 2369 DWC3_DEVTEN_USBRSTEN | 2370 DWC3_DEVTEN_DISCONNEVTEN); 2371 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 2372 2373 ret = device_register(&dwc->gadget.dev); 2374 if (ret) { 2375 dev_err(dwc->dev, "failed to register gadget device\n"); 2376 put_device(&dwc->gadget.dev); 2377 goto err6; 2378 } 2379 2380 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2381 if (ret) { 2382 dev_err(dwc->dev, "failed to register udc\n"); 2383 goto err7; 2384 } 2385 2386 return 0; 2387 2388err7: 2389 device_unregister(&dwc->gadget.dev); 2390 2391err6: 2392 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2393 free_irq(irq, dwc); 2394 2395err5: 2396 dwc3_gadget_free_endpoints(dwc); 2397 2398err4: 2399 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce, 2400 dwc->ep0_bounce_addr); 2401 2402err3: 2403 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2, 2404 dwc->setup_buf, dwc->setup_buf_addr); 2405 2406err2: 2407 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2408 dwc->ep0_trb, dwc->ep0_trb_addr); 2409 2410err1: 2411 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2412 dwc->ctrl_req, dwc->ctrl_req_addr); 2413 2414err0: 2415 return ret; 2416} 2417 2418void dwc3_gadget_exit(struct dwc3 *dwc) 2419{ 2420 int irq; 2421 2422 usb_del_gadget_udc(&dwc->gadget); 2423 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2424 2425 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2426 free_irq(irq, dwc); 2427 2428 dwc3_gadget_free_endpoints(dwc); 2429 2430 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce, 2431 dwc->ep0_bounce_addr); 2432 2433 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2, 2434 dwc->setup_buf, dwc->setup_buf_addr); 2435 2436 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2437 dwc->ep0_trb, dwc->ep0_trb_addr); 2438 2439 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2440 dwc->ctrl_req, dwc->ctrl_req_addr); 2441 2442 device_unregister(&dwc->gadget.dev); 2443} 2444