gadget.c revision 348e026fafe2501281db5fb7fed599b337cad358
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <linux/kernel.h> 40#include <linux/delay.h> 41#include <linux/slab.h> 42#include <linux/spinlock.h> 43#include <linux/platform_device.h> 44#include <linux/pm_runtime.h> 45#include <linux/interrupt.h> 46#include <linux/io.h> 47#include <linux/list.h> 48#include <linux/dma-mapping.h> 49 50#include <linux/usb/ch9.h> 51#include <linux/usb/gadget.h> 52 53#include "core.h" 54#include "gadget.h" 55#include "io.h" 56 57/** 58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 59 * @dwc: pointer to our context structure 60 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 61 * 62 * Caller should take care of locking. This function will 63 * return 0 on success or -EINVAL if wrong Test Selector 64 * is passed 65 */ 66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 67{ 68 u32 reg; 69 70 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 71 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 72 73 switch (mode) { 74 case TEST_J: 75 case TEST_K: 76 case TEST_SE0_NAK: 77 case TEST_PACKET: 78 case TEST_FORCE_EN: 79 reg |= mode << 1; 80 break; 81 default: 82 return -EINVAL; 83 } 84 85 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 86 87 return 0; 88} 89 90/** 91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 92 * @dwc: pointer to our context structure 93 * @state: the state to put link into 94 * 95 * Caller should take care of locking. This function will 96 * return 0 on success or -ETIMEDOUT. 97 */ 98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 99{ 100 int retries = 10000; 101 u32 reg; 102 103 /* 104 * Wait until device controller is ready. Only applies to 1.94a and 105 * later RTL. 106 */ 107 if (dwc->revision >= DWC3_REVISION_194A) { 108 while (--retries) { 109 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 110 if (reg & DWC3_DSTS_DCNRD) 111 udelay(5); 112 else 113 break; 114 } 115 116 if (retries <= 0) 117 return -ETIMEDOUT; 118 } 119 120 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 122 123 /* set requested state */ 124 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 125 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 126 127 /* 128 * The following code is racy when called from dwc3_gadget_wakeup, 129 * and is not needed, at least on newer versions 130 */ 131 if (dwc->revision >= DWC3_REVISION_194A) 132 return 0; 133 134 /* wait for a change in DSTS */ 135 retries = 10000; 136 while (--retries) { 137 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 138 139 if (DWC3_DSTS_USBLNKST(reg) == state) 140 return 0; 141 142 udelay(5); 143 } 144 145 dev_vdbg(dwc->dev, "link state change request timed out\n"); 146 147 return -ETIMEDOUT; 148} 149 150/** 151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 152 * @dwc: pointer to our context structure 153 * 154 * This function will a best effort FIFO allocation in order 155 * to improve FIFO usage and throughput, while still allowing 156 * us to enable as many endpoints as possible. 157 * 158 * Keep in mind that this operation will be highly dependent 159 * on the configured size for RAM1 - which contains TxFifo -, 160 * the amount of endpoints enabled on coreConsultant tool, and 161 * the width of the Master Bus. 162 * 163 * In the ideal world, we would always be able to satisfy the 164 * following equation: 165 * 166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 168 * 169 * Unfortunately, due to many variables that's not always the case. 170 */ 171int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 172{ 173 int last_fifo_depth = 0; 174 int ram1_depth; 175 int fifo_size; 176 int mdwidth; 177 int num; 178 179 if (!dwc->needs_fifo_resize) 180 return 0; 181 182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 184 185 /* MDWIDTH is represented in bits, we need it in bytes */ 186 mdwidth >>= 3; 187 188 /* 189 * FIXME For now we will only allocate 1 wMaxPacketSize space 190 * for each enabled endpoint, later patches will come to 191 * improve this algorithm so that we better use the internal 192 * FIFO space 193 */ 194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { 195 struct dwc3_ep *dep = dwc->eps[num]; 196 int fifo_number = dep->number >> 1; 197 int mult = 1; 198 int tmp; 199 200 if (!(dep->number & 1)) 201 continue; 202 203 if (!(dep->flags & DWC3_EP_ENABLED)) 204 continue; 205 206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) 207 || usb_endpoint_xfer_isoc(dep->endpoint.desc)) 208 mult = 3; 209 210 /* 211 * REVISIT: the following assumes we will always have enough 212 * space available on the FIFO RAM for all possible use cases. 213 * Make sure that's true somehow and change FIFO allocation 214 * accordingly. 215 * 216 * If we have Bulk or Isochronous endpoints, we want 217 * them to be able to be very, very fast. So we're giving 218 * those endpoints a fifo_size which is enough for 3 full 219 * packets 220 */ 221 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 222 tmp += mdwidth; 223 224 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 225 226 fifo_size |= (last_fifo_depth << 16); 227 228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 229 dep->name, last_fifo_depth, fifo_size & 0xffff); 230 231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), 232 fifo_size); 233 234 last_fifo_depth += (fifo_size & 0xffff); 235 } 236 237 return 0; 238} 239 240void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 241 int status) 242{ 243 struct dwc3 *dwc = dep->dwc; 244 245 if (req->queued) { 246 if (req->request.num_mapped_sgs) 247 dep->busy_slot += req->request.num_mapped_sgs; 248 else 249 dep->busy_slot++; 250 251 /* 252 * Skip LINK TRB. We can't use req->trb and check for 253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just 254 * completed (not the LINK TRB). 255 */ 256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 257 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 258 dep->busy_slot++; 259 } 260 list_del(&req->list); 261 req->trb = NULL; 262 263 if (req->request.status == -EINPROGRESS) 264 req->request.status = status; 265 266 usb_gadget_unmap_request(&dwc->gadget, &req->request, 267 req->direction); 268 269 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 270 req, dep->name, req->request.actual, 271 req->request.length, status); 272 273 spin_unlock(&dwc->lock); 274 req->request.complete(&dep->endpoint, &req->request); 275 spin_lock(&dwc->lock); 276} 277 278static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 279{ 280 switch (cmd) { 281 case DWC3_DEPCMD_DEPSTARTCFG: 282 return "Start New Configuration"; 283 case DWC3_DEPCMD_ENDTRANSFER: 284 return "End Transfer"; 285 case DWC3_DEPCMD_UPDATETRANSFER: 286 return "Update Transfer"; 287 case DWC3_DEPCMD_STARTTRANSFER: 288 return "Start Transfer"; 289 case DWC3_DEPCMD_CLEARSTALL: 290 return "Clear Stall"; 291 case DWC3_DEPCMD_SETSTALL: 292 return "Set Stall"; 293 case DWC3_DEPCMD_GETEPSTATE: 294 return "Get Endpoint State"; 295 case DWC3_DEPCMD_SETTRANSFRESOURCE: 296 return "Set Endpoint Transfer Resource"; 297 case DWC3_DEPCMD_SETEPCONFIG: 298 return "Set Endpoint Configuration"; 299 default: 300 return "UNKNOWN command"; 301 } 302} 303 304int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) 305{ 306 u32 timeout = 500; 307 u32 reg; 308 309 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 310 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 311 312 do { 313 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 314 if (!(reg & DWC3_DGCMD_CMDACT)) { 315 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 316 DWC3_DGCMD_STATUS(reg)); 317 return 0; 318 } 319 320 /* 321 * We can't sleep here, because it's also called from 322 * interrupt context. 323 */ 324 timeout--; 325 if (!timeout) 326 return -ETIMEDOUT; 327 udelay(1); 328 } while (1); 329} 330 331int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 332 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 333{ 334 struct dwc3_ep *dep = dwc->eps[ep]; 335 u32 timeout = 500; 336 u32 reg; 337 338 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 339 dep->name, 340 dwc3_gadget_ep_cmd_string(cmd), params->param0, 341 params->param1, params->param2); 342 343 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 346 347 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 348 do { 349 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 350 if (!(reg & DWC3_DEPCMD_CMDACT)) { 351 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 352 DWC3_DEPCMD_STATUS(reg)); 353 return 0; 354 } 355 356 /* 357 * We can't sleep here, because it is also called from 358 * interrupt context. 359 */ 360 timeout--; 361 if (!timeout) 362 return -ETIMEDOUT; 363 364 udelay(1); 365 } while (1); 366} 367 368static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 369 struct dwc3_trb *trb) 370{ 371 u32 offset = (char *) trb - (char *) dep->trb_pool; 372 373 return dep->trb_pool_dma + offset; 374} 375 376static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 377{ 378 struct dwc3 *dwc = dep->dwc; 379 380 if (dep->trb_pool) 381 return 0; 382 383 if (dep->number == 0 || dep->number == 1) 384 return 0; 385 386 dep->trb_pool = dma_alloc_coherent(dwc->dev, 387 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 388 &dep->trb_pool_dma, GFP_KERNEL); 389 if (!dep->trb_pool) { 390 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 391 dep->name); 392 return -ENOMEM; 393 } 394 395 return 0; 396} 397 398static void dwc3_free_trb_pool(struct dwc3_ep *dep) 399{ 400 struct dwc3 *dwc = dep->dwc; 401 402 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 403 dep->trb_pool, dep->trb_pool_dma); 404 405 dep->trb_pool = NULL; 406 dep->trb_pool_dma = 0; 407} 408 409static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 410{ 411 struct dwc3_gadget_ep_cmd_params params; 412 u32 cmd; 413 414 memset(¶ms, 0x00, sizeof(params)); 415 416 if (dep->number != 1) { 417 cmd = DWC3_DEPCMD_DEPSTARTCFG; 418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 419 if (dep->number > 1) { 420 if (dwc->start_config_issued) 421 return 0; 422 dwc->start_config_issued = true; 423 cmd |= DWC3_DEPCMD_PARAM(2); 424 } 425 426 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 427 } 428 429 return 0; 430} 431 432static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 433 const struct usb_endpoint_descriptor *desc, 434 const struct usb_ss_ep_comp_descriptor *comp_desc, 435 bool ignore) 436{ 437 struct dwc3_gadget_ep_cmd_params params; 438 439 memset(¶ms, 0x00, sizeof(params)); 440 441 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 442 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) 443 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst - 1); 444 445 if (ignore) 446 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; 447 448 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 449 | DWC3_DEPCFG_XFER_NOT_READY_EN; 450 451 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 452 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 453 | DWC3_DEPCFG_STREAM_EVENT_EN; 454 dep->stream_capable = true; 455 } 456 457 if (usb_endpoint_xfer_isoc(desc)) 458 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 459 460 /* 461 * We are doing 1:1 mapping for endpoints, meaning 462 * Physical Endpoints 2 maps to Logical Endpoint 2 and 463 * so on. We consider the direction bit as part of the physical 464 * endpoint number. So USB endpoint 0x81 is 0x03. 465 */ 466 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 467 468 /* 469 * We must use the lower 16 TX FIFOs even though 470 * HW might have more 471 */ 472 if (dep->direction) 473 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 474 475 if (desc->bInterval) { 476 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 477 dep->interval = 1 << (desc->bInterval - 1); 478 } 479 480 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 481 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 482} 483 484static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 485{ 486 struct dwc3_gadget_ep_cmd_params params; 487 488 memset(¶ms, 0x00, sizeof(params)); 489 490 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 491 492 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 493 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 494} 495 496/** 497 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 498 * @dep: endpoint to be initialized 499 * @desc: USB Endpoint Descriptor 500 * 501 * Caller should take care of locking 502 */ 503static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 504 const struct usb_endpoint_descriptor *desc, 505 const struct usb_ss_ep_comp_descriptor *comp_desc, 506 bool ignore) 507{ 508 struct dwc3 *dwc = dep->dwc; 509 u32 reg; 510 int ret = -ENOMEM; 511 512 if (!(dep->flags & DWC3_EP_ENABLED)) { 513 ret = dwc3_gadget_start_config(dwc, dep); 514 if (ret) 515 return ret; 516 } 517 518 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore); 519 if (ret) 520 return ret; 521 522 if (!(dep->flags & DWC3_EP_ENABLED)) { 523 struct dwc3_trb *trb_st_hw; 524 struct dwc3_trb *trb_link; 525 526 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 527 if (ret) 528 return ret; 529 530 dep->endpoint.desc = desc; 531 dep->comp_desc = comp_desc; 532 dep->type = usb_endpoint_type(desc); 533 dep->flags |= DWC3_EP_ENABLED; 534 535 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 536 reg |= DWC3_DALEPENA_EP(dep->number); 537 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 538 539 if (!usb_endpoint_xfer_isoc(desc)) 540 return 0; 541 542 memset(&trb_link, 0, sizeof(trb_link)); 543 544 /* Link TRB for ISOC. The HWO bit is never reset */ 545 trb_st_hw = &dep->trb_pool[0]; 546 547 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 548 549 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 550 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 551 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 552 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 553 } 554 555 return 0; 556} 557 558static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); 559static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 560{ 561 struct dwc3_request *req; 562 563 if (!list_empty(&dep->req_queued)) { 564 dwc3_stop_active_transfer(dwc, dep->number); 565 566 /* 567 * NOTICE: We are violating what the Databook says about the 568 * EndTransfer command. Ideally we would _always_ wait for the 569 * EndTransfer Command Completion IRQ, but that's causing too 570 * much trouble synchronizing between us and gadget driver. 571 * 572 * We have discussed this with the IP Provider and it was 573 * suggested to giveback all requests here, but give HW some 574 * extra time to synchronize with the interconnect. We're using 575 * an arbitraty 100us delay for that. 576 * 577 * Note also that a similar handling was tested by Synopsys 578 * (thanks a lot Paul) and nothing bad has come out of it. 579 * In short, what we're doing is: 580 * 581 * - Issue EndTransfer WITH CMDIOC bit set 582 * - Wait 100us 583 * - giveback all requests to gadget driver 584 */ 585 udelay(100); 586 587 while (!list_empty(&dep->req_queued)) { 588 req = next_request(&dep->req_queued); 589 590 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 591 } 592 } 593 594 while (!list_empty(&dep->request_list)) { 595 req = next_request(&dep->request_list); 596 597 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 598 } 599} 600 601/** 602 * __dwc3_gadget_ep_disable - Disables a HW endpoint 603 * @dep: the endpoint to disable 604 * 605 * This function also removes requests which are currently processed ny the 606 * hardware and those which are not yet scheduled. 607 * Caller should take care of locking. 608 */ 609static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 610{ 611 struct dwc3 *dwc = dep->dwc; 612 u32 reg; 613 614 dwc3_remove_requests(dwc, dep); 615 616 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 617 reg &= ~DWC3_DALEPENA_EP(dep->number); 618 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 619 620 dep->stream_capable = false; 621 dep->endpoint.desc = NULL; 622 dep->comp_desc = NULL; 623 dep->type = 0; 624 dep->flags = 0; 625 626 return 0; 627} 628 629/* -------------------------------------------------------------------------- */ 630 631static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 632 const struct usb_endpoint_descriptor *desc) 633{ 634 return -EINVAL; 635} 636 637static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 638{ 639 return -EINVAL; 640} 641 642/* -------------------------------------------------------------------------- */ 643 644static int dwc3_gadget_ep_enable(struct usb_ep *ep, 645 const struct usb_endpoint_descriptor *desc) 646{ 647 struct dwc3_ep *dep; 648 struct dwc3 *dwc; 649 unsigned long flags; 650 int ret; 651 652 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 653 pr_debug("dwc3: invalid parameters\n"); 654 return -EINVAL; 655 } 656 657 if (!desc->wMaxPacketSize) { 658 pr_debug("dwc3: missing wMaxPacketSize\n"); 659 return -EINVAL; 660 } 661 662 dep = to_dwc3_ep(ep); 663 dwc = dep->dwc; 664 665 switch (usb_endpoint_type(desc)) { 666 case USB_ENDPOINT_XFER_CONTROL: 667 strlcat(dep->name, "-control", sizeof(dep->name)); 668 break; 669 case USB_ENDPOINT_XFER_ISOC: 670 strlcat(dep->name, "-isoc", sizeof(dep->name)); 671 break; 672 case USB_ENDPOINT_XFER_BULK: 673 strlcat(dep->name, "-bulk", sizeof(dep->name)); 674 break; 675 case USB_ENDPOINT_XFER_INT: 676 strlcat(dep->name, "-int", sizeof(dep->name)); 677 break; 678 default: 679 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 680 } 681 682 if (dep->flags & DWC3_EP_ENABLED) { 683 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 684 dep->name); 685 return 0; 686 } 687 688 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 689 690 spin_lock_irqsave(&dwc->lock, flags); 691 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false); 692 spin_unlock_irqrestore(&dwc->lock, flags); 693 694 return ret; 695} 696 697static int dwc3_gadget_ep_disable(struct usb_ep *ep) 698{ 699 struct dwc3_ep *dep; 700 struct dwc3 *dwc; 701 unsigned long flags; 702 int ret; 703 704 if (!ep) { 705 pr_debug("dwc3: invalid parameters\n"); 706 return -EINVAL; 707 } 708 709 dep = to_dwc3_ep(ep); 710 dwc = dep->dwc; 711 712 if (!(dep->flags & DWC3_EP_ENABLED)) { 713 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 714 dep->name); 715 return 0; 716 } 717 718 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 719 dep->number >> 1, 720 (dep->number & 1) ? "in" : "out"); 721 722 spin_lock_irqsave(&dwc->lock, flags); 723 ret = __dwc3_gadget_ep_disable(dep); 724 spin_unlock_irqrestore(&dwc->lock, flags); 725 726 return ret; 727} 728 729static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 730 gfp_t gfp_flags) 731{ 732 struct dwc3_request *req; 733 struct dwc3_ep *dep = to_dwc3_ep(ep); 734 struct dwc3 *dwc = dep->dwc; 735 736 req = kzalloc(sizeof(*req), gfp_flags); 737 if (!req) { 738 dev_err(dwc->dev, "not enough memory\n"); 739 return NULL; 740 } 741 742 req->epnum = dep->number; 743 req->dep = dep; 744 745 return &req->request; 746} 747 748static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 749 struct usb_request *request) 750{ 751 struct dwc3_request *req = to_dwc3_request(request); 752 753 kfree(req); 754} 755 756/** 757 * dwc3_prepare_one_trb - setup one TRB from one request 758 * @dep: endpoint for which this request is prepared 759 * @req: dwc3_request pointer 760 */ 761static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 762 struct dwc3_request *req, dma_addr_t dma, 763 unsigned length, unsigned last, unsigned chain) 764{ 765 struct dwc3 *dwc = dep->dwc; 766 struct dwc3_trb *trb; 767 768 unsigned int cur_slot; 769 770 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 771 dep->name, req, (unsigned long long) dma, 772 length, last ? " last" : "", 773 chain ? " chain" : ""); 774 775 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 776 cur_slot = dep->free_slot; 777 dep->free_slot++; 778 779 /* Skip the LINK-TRB on ISOC */ 780 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 781 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 782 return; 783 784 if (!req->trb) { 785 dwc3_gadget_move_request_queued(req); 786 req->trb = trb; 787 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 788 } 789 790 trb->size = DWC3_TRB_SIZE_LENGTH(length); 791 trb->bpl = lower_32_bits(dma); 792 trb->bph = upper_32_bits(dma); 793 794 switch (usb_endpoint_type(dep->endpoint.desc)) { 795 case USB_ENDPOINT_XFER_CONTROL: 796 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 797 break; 798 799 case USB_ENDPOINT_XFER_ISOC: 800 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 801 802 if (!req->request.no_interrupt) 803 trb->ctrl |= DWC3_TRB_CTRL_IOC; 804 break; 805 806 case USB_ENDPOINT_XFER_BULK: 807 case USB_ENDPOINT_XFER_INT: 808 trb->ctrl = DWC3_TRBCTL_NORMAL; 809 break; 810 default: 811 /* 812 * This is only possible with faulty memory because we 813 * checked it already :) 814 */ 815 BUG(); 816 } 817 818 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 819 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 820 trb->ctrl |= DWC3_TRB_CTRL_CSP; 821 } else { 822 if (chain) 823 trb->ctrl |= DWC3_TRB_CTRL_CHN; 824 825 if (last) 826 trb->ctrl |= DWC3_TRB_CTRL_LST; 827 } 828 829 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 830 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); 831 832 trb->ctrl |= DWC3_TRB_CTRL_HWO; 833} 834 835/* 836 * dwc3_prepare_trbs - setup TRBs from requests 837 * @dep: endpoint for which requests are being prepared 838 * @starting: true if the endpoint is idle and no requests are queued. 839 * 840 * The function goes through the requests list and sets up TRBs for the 841 * transfers. The function returns once there are no more TRBs available or 842 * it runs out of requests. 843 */ 844static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 845{ 846 struct dwc3_request *req, *n; 847 u32 trbs_left; 848 u32 max; 849 unsigned int last_one = 0; 850 851 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 852 853 /* the first request must not be queued */ 854 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 855 856 /* Can't wrap around on a non-isoc EP since there's no link TRB */ 857 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 858 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); 859 if (trbs_left > max) 860 trbs_left = max; 861 } 862 863 /* 864 * If busy & slot are equal than it is either full or empty. If we are 865 * starting to process requests then we are empty. Otherwise we are 866 * full and don't do anything 867 */ 868 if (!trbs_left) { 869 if (!starting) 870 return; 871 trbs_left = DWC3_TRB_NUM; 872 /* 873 * In case we start from scratch, we queue the ISOC requests 874 * starting from slot 1. This is done because we use ring 875 * buffer and have no LST bit to stop us. Instead, we place 876 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt 877 * after the first request so we start at slot 1 and have 878 * 7 requests proceed before we hit the first IOC. 879 * Other transfer types don't use the ring buffer and are 880 * processed from the first TRB until the last one. Since we 881 * don't wrap around we have to start at the beginning. 882 */ 883 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 884 dep->busy_slot = 1; 885 dep->free_slot = 1; 886 } else { 887 dep->busy_slot = 0; 888 dep->free_slot = 0; 889 } 890 } 891 892 /* The last TRB is a link TRB, not used for xfer */ 893 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) 894 return; 895 896 list_for_each_entry_safe(req, n, &dep->request_list, list) { 897 unsigned length; 898 dma_addr_t dma; 899 900 if (req->request.num_mapped_sgs > 0) { 901 struct usb_request *request = &req->request; 902 struct scatterlist *sg = request->sg; 903 struct scatterlist *s; 904 int i; 905 906 for_each_sg(sg, s, request->num_mapped_sgs, i) { 907 unsigned chain = true; 908 909 length = sg_dma_len(s); 910 dma = sg_dma_address(s); 911 912 if (i == (request->num_mapped_sgs - 1) || 913 sg_is_last(s)) { 914 last_one = true; 915 chain = false; 916 } 917 918 trbs_left--; 919 if (!trbs_left) 920 last_one = true; 921 922 if (last_one) 923 chain = false; 924 925 dwc3_prepare_one_trb(dep, req, dma, length, 926 last_one, chain); 927 928 if (last_one) 929 break; 930 } 931 } else { 932 dma = req->request.dma; 933 length = req->request.length; 934 trbs_left--; 935 936 if (!trbs_left) 937 last_one = 1; 938 939 /* Is this the last request? */ 940 if (list_is_last(&req->list, &dep->request_list)) 941 last_one = 1; 942 943 dwc3_prepare_one_trb(dep, req, dma, length, 944 last_one, false); 945 946 if (last_one) 947 break; 948 } 949 } 950} 951 952static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 953 int start_new) 954{ 955 struct dwc3_gadget_ep_cmd_params params; 956 struct dwc3_request *req; 957 struct dwc3 *dwc = dep->dwc; 958 int ret; 959 u32 cmd; 960 961 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 962 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 963 return -EBUSY; 964 } 965 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 966 967 /* 968 * If we are getting here after a short-out-packet we don't enqueue any 969 * new requests as we try to set the IOC bit only on the last request. 970 */ 971 if (start_new) { 972 if (list_empty(&dep->req_queued)) 973 dwc3_prepare_trbs(dep, start_new); 974 975 /* req points to the first request which will be sent */ 976 req = next_request(&dep->req_queued); 977 } else { 978 dwc3_prepare_trbs(dep, start_new); 979 980 /* 981 * req points to the first request where HWO changed from 0 to 1 982 */ 983 req = next_request(&dep->req_queued); 984 } 985 if (!req) { 986 dep->flags |= DWC3_EP_PENDING_REQUEST; 987 return 0; 988 } 989 990 memset(¶ms, 0, sizeof(params)); 991 params.param0 = upper_32_bits(req->trb_dma); 992 params.param1 = lower_32_bits(req->trb_dma); 993 994 if (start_new) 995 cmd = DWC3_DEPCMD_STARTTRANSFER; 996 else 997 cmd = DWC3_DEPCMD_UPDATETRANSFER; 998 999 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 1000 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1001 if (ret < 0) { 1002 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 1003 1004 /* 1005 * FIXME we need to iterate over the list of requests 1006 * here and stop, unmap, free and del each of the linked 1007 * requests instead of what we do now. 1008 */ 1009 usb_gadget_unmap_request(&dwc->gadget, &req->request, 1010 req->direction); 1011 list_del(&req->list); 1012 return ret; 1013 } 1014 1015 dep->flags |= DWC3_EP_BUSY; 1016 1017 if (start_new) { 1018 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 1019 dep->number); 1020 WARN_ON_ONCE(!dep->resource_index); 1021 } 1022 1023 return 0; 1024} 1025 1026static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, 1027 struct dwc3_ep *dep, u32 cur_uf) 1028{ 1029 u32 uf; 1030 1031 if (list_empty(&dep->request_list)) { 1032 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1033 dep->name); 1034 return; 1035 } 1036 1037 /* 4 micro frames in the future */ 1038 uf = cur_uf + dep->interval * 4; 1039 1040 __dwc3_gadget_kick_transfer(dep, uf, 1); 1041} 1042 1043static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1044 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1045{ 1046 u32 cur_uf, mask; 1047 1048 mask = ~(dep->interval - 1); 1049 cur_uf = event->parameters & mask; 1050 1051 __dwc3_gadget_start_isoc(dwc, dep, cur_uf); 1052} 1053 1054static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 1055{ 1056 struct dwc3 *dwc = dep->dwc; 1057 int ret; 1058 1059 req->request.actual = 0; 1060 req->request.status = -EINPROGRESS; 1061 req->direction = dep->direction; 1062 req->epnum = dep->number; 1063 1064 /* 1065 * We only add to our list of requests now and 1066 * start consuming the list once we get XferNotReady 1067 * IRQ. 1068 * 1069 * That way, we avoid doing anything that we don't need 1070 * to do now and defer it until the point we receive a 1071 * particular token from the Host side. 1072 * 1073 * This will also avoid Host cancelling URBs due to too 1074 * many NAKs. 1075 */ 1076 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1077 dep->direction); 1078 if (ret) 1079 return ret; 1080 1081 list_add_tail(&req->list, &dep->request_list); 1082 1083 /* 1084 * There are a few special cases: 1085 * 1086 * 1. XferNotReady with empty list of requests. We need to kick the 1087 * transfer here in that situation, otherwise we will be NAKing 1088 * forever. If we get XferNotReady before gadget driver has a 1089 * chance to queue a request, we will ACK the IRQ but won't be 1090 * able to receive the data until the next request is queued. 1091 * The following code is handling exactly that. 1092 * 1093 */ 1094 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1095 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1096 if (ret && ret != -EBUSY) 1097 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1098 dep->name); 1099 } 1100 1101 /* 1102 * 2. XferInProgress on Isoc EP with an active transfer. We need to 1103 * kick the transfer here after queuing a request, otherwise the 1104 * core may not see the modified TRB(s). 1105 */ 1106 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1107 (dep->flags & DWC3_EP_BUSY)) { 1108 WARN_ON_ONCE(!dep->resource_index); 1109 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, 1110 false); 1111 if (ret && ret != -EBUSY) 1112 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1113 dep->name); 1114 } 1115 1116 /* 1117 * 3. Missed ISOC Handling. We need to start isoc transfer on the saved 1118 * uframe number. 1119 */ 1120 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1121 (dep->flags & DWC3_EP_MISSED_ISOC)) { 1122 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf); 1123 dep->flags &= ~DWC3_EP_MISSED_ISOC; 1124 } 1125 1126 return 0; 1127} 1128 1129static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1130 gfp_t gfp_flags) 1131{ 1132 struct dwc3_request *req = to_dwc3_request(request); 1133 struct dwc3_ep *dep = to_dwc3_ep(ep); 1134 struct dwc3 *dwc = dep->dwc; 1135 1136 unsigned long flags; 1137 1138 int ret; 1139 1140 if (!dep->endpoint.desc) { 1141 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1142 request, ep->name); 1143 return -ESHUTDOWN; 1144 } 1145 1146 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1147 request, ep->name, request->length); 1148 1149 spin_lock_irqsave(&dwc->lock, flags); 1150 ret = __dwc3_gadget_ep_queue(dep, req); 1151 spin_unlock_irqrestore(&dwc->lock, flags); 1152 1153 return ret; 1154} 1155 1156static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1157 struct usb_request *request) 1158{ 1159 struct dwc3_request *req = to_dwc3_request(request); 1160 struct dwc3_request *r = NULL; 1161 1162 struct dwc3_ep *dep = to_dwc3_ep(ep); 1163 struct dwc3 *dwc = dep->dwc; 1164 1165 unsigned long flags; 1166 int ret = 0; 1167 1168 spin_lock_irqsave(&dwc->lock, flags); 1169 1170 list_for_each_entry(r, &dep->request_list, list) { 1171 if (r == req) 1172 break; 1173 } 1174 1175 if (r != req) { 1176 list_for_each_entry(r, &dep->req_queued, list) { 1177 if (r == req) 1178 break; 1179 } 1180 if (r == req) { 1181 /* wait until it is processed */ 1182 dwc3_stop_active_transfer(dwc, dep->number); 1183 goto out1; 1184 } 1185 dev_err(dwc->dev, "request %p was not queued to %s\n", 1186 request, ep->name); 1187 ret = -EINVAL; 1188 goto out0; 1189 } 1190 1191out1: 1192 /* giveback the request */ 1193 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1194 1195out0: 1196 spin_unlock_irqrestore(&dwc->lock, flags); 1197 1198 return ret; 1199} 1200 1201int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1202{ 1203 struct dwc3_gadget_ep_cmd_params params; 1204 struct dwc3 *dwc = dep->dwc; 1205 int ret; 1206 1207 memset(¶ms, 0x00, sizeof(params)); 1208 1209 if (value) { 1210 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1211 DWC3_DEPCMD_SETSTALL, ¶ms); 1212 if (ret) 1213 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1214 value ? "set" : "clear", 1215 dep->name); 1216 else 1217 dep->flags |= DWC3_EP_STALL; 1218 } else { 1219 if (dep->flags & DWC3_EP_WEDGE) 1220 return 0; 1221 1222 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1223 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1224 if (ret) 1225 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1226 value ? "set" : "clear", 1227 dep->name); 1228 else 1229 dep->flags &= ~DWC3_EP_STALL; 1230 } 1231 1232 return ret; 1233} 1234 1235static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1236{ 1237 struct dwc3_ep *dep = to_dwc3_ep(ep); 1238 struct dwc3 *dwc = dep->dwc; 1239 1240 unsigned long flags; 1241 1242 int ret; 1243 1244 spin_lock_irqsave(&dwc->lock, flags); 1245 1246 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1247 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1248 ret = -EINVAL; 1249 goto out; 1250 } 1251 1252 ret = __dwc3_gadget_ep_set_halt(dep, value); 1253out: 1254 spin_unlock_irqrestore(&dwc->lock, flags); 1255 1256 return ret; 1257} 1258 1259static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1260{ 1261 struct dwc3_ep *dep = to_dwc3_ep(ep); 1262 struct dwc3 *dwc = dep->dwc; 1263 unsigned long flags; 1264 1265 spin_lock_irqsave(&dwc->lock, flags); 1266 dep->flags |= DWC3_EP_WEDGE; 1267 spin_unlock_irqrestore(&dwc->lock, flags); 1268 1269 if (dep->number == 0 || dep->number == 1) 1270 return dwc3_gadget_ep0_set_halt(ep, 1); 1271 else 1272 return dwc3_gadget_ep_set_halt(ep, 1); 1273} 1274 1275/* -------------------------------------------------------------------------- */ 1276 1277static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1278 .bLength = USB_DT_ENDPOINT_SIZE, 1279 .bDescriptorType = USB_DT_ENDPOINT, 1280 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1281}; 1282 1283static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1284 .enable = dwc3_gadget_ep0_enable, 1285 .disable = dwc3_gadget_ep0_disable, 1286 .alloc_request = dwc3_gadget_ep_alloc_request, 1287 .free_request = dwc3_gadget_ep_free_request, 1288 .queue = dwc3_gadget_ep0_queue, 1289 .dequeue = dwc3_gadget_ep_dequeue, 1290 .set_halt = dwc3_gadget_ep0_set_halt, 1291 .set_wedge = dwc3_gadget_ep_set_wedge, 1292}; 1293 1294static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1295 .enable = dwc3_gadget_ep_enable, 1296 .disable = dwc3_gadget_ep_disable, 1297 .alloc_request = dwc3_gadget_ep_alloc_request, 1298 .free_request = dwc3_gadget_ep_free_request, 1299 .queue = dwc3_gadget_ep_queue, 1300 .dequeue = dwc3_gadget_ep_dequeue, 1301 .set_halt = dwc3_gadget_ep_set_halt, 1302 .set_wedge = dwc3_gadget_ep_set_wedge, 1303}; 1304 1305/* -------------------------------------------------------------------------- */ 1306 1307static int dwc3_gadget_get_frame(struct usb_gadget *g) 1308{ 1309 struct dwc3 *dwc = gadget_to_dwc(g); 1310 u32 reg; 1311 1312 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1313 return DWC3_DSTS_SOFFN(reg); 1314} 1315 1316static int dwc3_gadget_wakeup(struct usb_gadget *g) 1317{ 1318 struct dwc3 *dwc = gadget_to_dwc(g); 1319 1320 unsigned long timeout; 1321 unsigned long flags; 1322 1323 u32 reg; 1324 1325 int ret = 0; 1326 1327 u8 link_state; 1328 u8 speed; 1329 1330 spin_lock_irqsave(&dwc->lock, flags); 1331 1332 /* 1333 * According to the Databook Remote wakeup request should 1334 * be issued only when the device is in early suspend state. 1335 * 1336 * We can check that via USB Link State bits in DSTS register. 1337 */ 1338 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1339 1340 speed = reg & DWC3_DSTS_CONNECTSPD; 1341 if (speed == DWC3_DSTS_SUPERSPEED) { 1342 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1343 ret = -EINVAL; 1344 goto out; 1345 } 1346 1347 link_state = DWC3_DSTS_USBLNKST(reg); 1348 1349 switch (link_state) { 1350 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1351 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1352 break; 1353 default: 1354 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1355 link_state); 1356 ret = -EINVAL; 1357 goto out; 1358 } 1359 1360 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1361 if (ret < 0) { 1362 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1363 goto out; 1364 } 1365 1366 /* Recent versions do this automatically */ 1367 if (dwc->revision < DWC3_REVISION_194A) { 1368 /* write zeroes to Link Change Request */ 1369 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1370 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1371 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1372 } 1373 1374 /* poll until Link State changes to ON */ 1375 timeout = jiffies + msecs_to_jiffies(100); 1376 1377 while (!time_after(jiffies, timeout)) { 1378 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1379 1380 /* in HS, means ON */ 1381 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1382 break; 1383 } 1384 1385 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1386 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1387 ret = -EINVAL; 1388 } 1389 1390out: 1391 spin_unlock_irqrestore(&dwc->lock, flags); 1392 1393 return ret; 1394} 1395 1396static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1397 int is_selfpowered) 1398{ 1399 struct dwc3 *dwc = gadget_to_dwc(g); 1400 unsigned long flags; 1401 1402 spin_lock_irqsave(&dwc->lock, flags); 1403 dwc->is_selfpowered = !!is_selfpowered; 1404 spin_unlock_irqrestore(&dwc->lock, flags); 1405 1406 return 0; 1407} 1408 1409static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) 1410{ 1411 u32 reg; 1412 u32 timeout = 500; 1413 1414 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1415 if (is_on) { 1416 if (dwc->revision <= DWC3_REVISION_187A) { 1417 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1418 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1419 } 1420 1421 if (dwc->revision >= DWC3_REVISION_194A) 1422 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1423 reg |= DWC3_DCTL_RUN_STOP; 1424 } else { 1425 reg &= ~DWC3_DCTL_RUN_STOP; 1426 } 1427 1428 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1429 1430 do { 1431 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1432 if (is_on) { 1433 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1434 break; 1435 } else { 1436 if (reg & DWC3_DSTS_DEVCTRLHLT) 1437 break; 1438 } 1439 timeout--; 1440 if (!timeout) 1441 return -ETIMEDOUT; 1442 udelay(1); 1443 } while (1); 1444 1445 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1446 dwc->gadget_driver 1447 ? dwc->gadget_driver->function : "no-function", 1448 is_on ? "connect" : "disconnect"); 1449 1450 return 0; 1451} 1452 1453static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1454{ 1455 struct dwc3 *dwc = gadget_to_dwc(g); 1456 unsigned long flags; 1457 int ret; 1458 1459 is_on = !!is_on; 1460 1461 spin_lock_irqsave(&dwc->lock, flags); 1462 ret = dwc3_gadget_run_stop(dwc, is_on); 1463 spin_unlock_irqrestore(&dwc->lock, flags); 1464 1465 return ret; 1466} 1467 1468static int dwc3_gadget_start(struct usb_gadget *g, 1469 struct usb_gadget_driver *driver) 1470{ 1471 struct dwc3 *dwc = gadget_to_dwc(g); 1472 struct dwc3_ep *dep; 1473 unsigned long flags; 1474 int ret = 0; 1475 u32 reg; 1476 1477 spin_lock_irqsave(&dwc->lock, flags); 1478 1479 if (dwc->gadget_driver) { 1480 dev_err(dwc->dev, "%s is already bound to %s\n", 1481 dwc->gadget.name, 1482 dwc->gadget_driver->driver.name); 1483 ret = -EBUSY; 1484 goto err0; 1485 } 1486 1487 dwc->gadget_driver = driver; 1488 dwc->gadget.dev.driver = &driver->driver; 1489 1490 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1491 reg &= ~(DWC3_DCFG_SPEED_MASK); 1492 1493 /** 1494 * WORKAROUND: DWC3 revision < 2.20a have an issue 1495 * which would cause metastability state on Run/Stop 1496 * bit if we try to force the IP to USB2-only mode. 1497 * 1498 * Because of that, we cannot configure the IP to any 1499 * speed other than the SuperSpeed 1500 * 1501 * Refers to: 1502 * 1503 * STAR#9000525659: Clock Domain Crossing on DCTL in 1504 * USB 2.0 Mode 1505 */ 1506 if (dwc->revision < DWC3_REVISION_220A) 1507 reg |= DWC3_DCFG_SUPERSPEED; 1508 else 1509 reg |= dwc->maximum_speed; 1510 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1511 1512 dwc->start_config_issued = false; 1513 1514 /* Start with SuperSpeed Default */ 1515 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1516 1517 dep = dwc->eps[0]; 1518 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); 1519 if (ret) { 1520 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1521 goto err0; 1522 } 1523 1524 dep = dwc->eps[1]; 1525 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); 1526 if (ret) { 1527 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1528 goto err1; 1529 } 1530 1531 /* begin to receive SETUP packets */ 1532 dwc->ep0state = EP0_SETUP_PHASE; 1533 dwc3_ep0_out_start(dwc); 1534 1535 spin_unlock_irqrestore(&dwc->lock, flags); 1536 1537 return 0; 1538 1539err1: 1540 __dwc3_gadget_ep_disable(dwc->eps[0]); 1541 1542err0: 1543 spin_unlock_irqrestore(&dwc->lock, flags); 1544 1545 return ret; 1546} 1547 1548static int dwc3_gadget_stop(struct usb_gadget *g, 1549 struct usb_gadget_driver *driver) 1550{ 1551 struct dwc3 *dwc = gadget_to_dwc(g); 1552 unsigned long flags; 1553 1554 spin_lock_irqsave(&dwc->lock, flags); 1555 1556 __dwc3_gadget_ep_disable(dwc->eps[0]); 1557 __dwc3_gadget_ep_disable(dwc->eps[1]); 1558 1559 dwc->gadget_driver = NULL; 1560 dwc->gadget.dev.driver = NULL; 1561 1562 spin_unlock_irqrestore(&dwc->lock, flags); 1563 1564 return 0; 1565} 1566 1567static const struct usb_gadget_ops dwc3_gadget_ops = { 1568 .get_frame = dwc3_gadget_get_frame, 1569 .wakeup = dwc3_gadget_wakeup, 1570 .set_selfpowered = dwc3_gadget_set_selfpowered, 1571 .pullup = dwc3_gadget_pullup, 1572 .udc_start = dwc3_gadget_start, 1573 .udc_stop = dwc3_gadget_stop, 1574}; 1575 1576/* -------------------------------------------------------------------------- */ 1577 1578static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1579{ 1580 struct dwc3_ep *dep; 1581 u8 epnum; 1582 1583 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1584 1585 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1586 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1587 if (!dep) { 1588 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1589 epnum); 1590 return -ENOMEM; 1591 } 1592 1593 dep->dwc = dwc; 1594 dep->number = epnum; 1595 dwc->eps[epnum] = dep; 1596 1597 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1598 (epnum & 1) ? "in" : "out"); 1599 dep->endpoint.name = dep->name; 1600 dep->direction = (epnum & 1); 1601 1602 if (epnum == 0 || epnum == 1) { 1603 dep->endpoint.maxpacket = 512; 1604 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1605 if (!epnum) 1606 dwc->gadget.ep0 = &dep->endpoint; 1607 } else { 1608 int ret; 1609 1610 dep->endpoint.maxpacket = 1024; 1611 dep->endpoint.max_streams = 15; 1612 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1613 list_add_tail(&dep->endpoint.ep_list, 1614 &dwc->gadget.ep_list); 1615 1616 ret = dwc3_alloc_trb_pool(dep); 1617 if (ret) 1618 return ret; 1619 } 1620 1621 INIT_LIST_HEAD(&dep->request_list); 1622 INIT_LIST_HEAD(&dep->req_queued); 1623 } 1624 1625 return 0; 1626} 1627 1628static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1629{ 1630 struct dwc3_ep *dep; 1631 u8 epnum; 1632 1633 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1634 dep = dwc->eps[epnum]; 1635 dwc3_free_trb_pool(dep); 1636 1637 if (epnum != 0 && epnum != 1) 1638 list_del(&dep->endpoint.ep_list); 1639 1640 kfree(dep); 1641 } 1642} 1643 1644static void dwc3_gadget_release(struct device *dev) 1645{ 1646 dev_dbg(dev, "%s\n", __func__); 1647} 1648 1649/* -------------------------------------------------------------------------- */ 1650static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1651 const struct dwc3_event_depevt *event, int status) 1652{ 1653 struct dwc3_request *req; 1654 struct dwc3_trb *trb; 1655 unsigned int count; 1656 unsigned int s_pkt = 0; 1657 unsigned int trb_status; 1658 1659 do { 1660 req = next_request(&dep->req_queued); 1661 if (!req) { 1662 WARN_ON_ONCE(1); 1663 return 1; 1664 } 1665 1666 trb = req->trb; 1667 1668 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 1669 /* 1670 * We continue despite the error. There is not much we 1671 * can do. If we don't clean it up we loop forever. If 1672 * we skip the TRB then it gets overwritten after a 1673 * while since we use them in a ring buffer. A BUG() 1674 * would help. Lets hope that if this occurs, someone 1675 * fixes the root cause instead of looking away :) 1676 */ 1677 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1678 dep->name, req->trb); 1679 count = trb->size & DWC3_TRB_SIZE_MASK; 1680 1681 if (dep->direction) { 1682 if (count) { 1683 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); 1684 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { 1685 dev_dbg(dwc->dev, "incomplete IN transfer %s\n", 1686 dep->name); 1687 dep->current_uf = event->parameters & 1688 ~(dep->interval - 1); 1689 dep->flags |= DWC3_EP_MISSED_ISOC; 1690 } else { 1691 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1692 dep->name); 1693 status = -ECONNRESET; 1694 } 1695 } 1696 } else { 1697 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1698 s_pkt = 1; 1699 } 1700 1701 /* 1702 * We assume here we will always receive the entire data block 1703 * which we should receive. Meaning, if we program RX to 1704 * receive 4K but we receive only 2K, we assume that's all we 1705 * should receive and we simply bounce the request back to the 1706 * gadget driver for further processing. 1707 */ 1708 req->request.actual += req->request.length - count; 1709 dwc3_gadget_giveback(dep, req, status); 1710 if (s_pkt) 1711 break; 1712 if ((event->status & DEPEVT_STATUS_LST) && 1713 (trb->ctrl & (DWC3_TRB_CTRL_LST | 1714 DWC3_TRB_CTRL_HWO))) 1715 break; 1716 if ((event->status & DEPEVT_STATUS_IOC) && 1717 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1718 break; 1719 } while (1); 1720 1721 if ((event->status & DEPEVT_STATUS_IOC) && 1722 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1723 return 0; 1724 return 1; 1725} 1726 1727static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1728 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1729 int start_new) 1730{ 1731 unsigned status = 0; 1732 int clean_busy; 1733 1734 if (event->status & DEPEVT_STATUS_BUSERR) 1735 status = -ECONNRESET; 1736 1737 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1738 if (clean_busy) 1739 dep->flags &= ~DWC3_EP_BUSY; 1740 1741 /* 1742 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1743 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1744 */ 1745 if (dwc->revision < DWC3_REVISION_183A) { 1746 u32 reg; 1747 int i; 1748 1749 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1750 dep = dwc->eps[i]; 1751 1752 if (!(dep->flags & DWC3_EP_ENABLED)) 1753 continue; 1754 1755 if (!list_empty(&dep->req_queued)) 1756 return; 1757 } 1758 1759 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1760 reg |= dwc->u1u2; 1761 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1762 1763 dwc->u1u2 = 0; 1764 } 1765} 1766 1767static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1768 const struct dwc3_event_depevt *event) 1769{ 1770 struct dwc3_ep *dep; 1771 u8 epnum = event->endpoint_number; 1772 1773 dep = dwc->eps[epnum]; 1774 1775 if (!(dep->flags & DWC3_EP_ENABLED)) 1776 return; 1777 1778 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1779 dwc3_ep_event_string(event->endpoint_event)); 1780 1781 if (epnum == 0 || epnum == 1) { 1782 dwc3_ep0_interrupt(dwc, event); 1783 return; 1784 } 1785 1786 switch (event->endpoint_event) { 1787 case DWC3_DEPEVT_XFERCOMPLETE: 1788 dep->resource_index = 0; 1789 1790 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1791 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1792 dep->name); 1793 return; 1794 } 1795 1796 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1797 break; 1798 case DWC3_DEPEVT_XFERINPROGRESS: 1799 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1800 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1801 dep->name); 1802 return; 1803 } 1804 1805 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1806 break; 1807 case DWC3_DEPEVT_XFERNOTREADY: 1808 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1809 dwc3_gadget_start_isoc(dwc, dep, event); 1810 } else { 1811 int ret; 1812 1813 dev_vdbg(dwc->dev, "%s: reason %s\n", 1814 dep->name, event->status & 1815 DEPEVT_STATUS_TRANSFER_ACTIVE 1816 ? "Transfer Active" 1817 : "Transfer Not Active"); 1818 1819 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1820 if (!ret || ret == -EBUSY) 1821 return; 1822 1823 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1824 dep->name); 1825 } 1826 1827 break; 1828 case DWC3_DEPEVT_STREAMEVT: 1829 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { 1830 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1831 dep->name); 1832 return; 1833 } 1834 1835 switch (event->status) { 1836 case DEPEVT_STREAMEVT_FOUND: 1837 dev_vdbg(dwc->dev, "Stream %d found and started\n", 1838 event->parameters); 1839 1840 break; 1841 case DEPEVT_STREAMEVT_NOTFOUND: 1842 /* FALLTHROUGH */ 1843 default: 1844 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 1845 } 1846 break; 1847 case DWC3_DEPEVT_RXTXFIFOEVT: 1848 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 1849 break; 1850 case DWC3_DEPEVT_EPCMDCMPLT: 1851 dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); 1852 break; 1853 } 1854} 1855 1856static void dwc3_disconnect_gadget(struct dwc3 *dwc) 1857{ 1858 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 1859 spin_unlock(&dwc->lock); 1860 dwc->gadget_driver->disconnect(&dwc->gadget); 1861 spin_lock(&dwc->lock); 1862 } 1863} 1864 1865static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) 1866{ 1867 struct dwc3_ep *dep; 1868 struct dwc3_gadget_ep_cmd_params params; 1869 u32 cmd; 1870 int ret; 1871 1872 dep = dwc->eps[epnum]; 1873 1874 if (!dep->resource_index) 1875 return; 1876 1877 cmd = DWC3_DEPCMD_ENDTRANSFER; 1878 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; 1879 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1880 memset(¶ms, 0, sizeof(params)); 1881 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1882 WARN_ON_ONCE(ret); 1883 dep->resource_index = 0; 1884} 1885 1886static void dwc3_stop_active_transfers(struct dwc3 *dwc) 1887{ 1888 u32 epnum; 1889 1890 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1891 struct dwc3_ep *dep; 1892 1893 dep = dwc->eps[epnum]; 1894 if (!(dep->flags & DWC3_EP_ENABLED)) 1895 continue; 1896 1897 dwc3_remove_requests(dwc, dep); 1898 } 1899} 1900 1901static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 1902{ 1903 u32 epnum; 1904 1905 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1906 struct dwc3_ep *dep; 1907 struct dwc3_gadget_ep_cmd_params params; 1908 int ret; 1909 1910 dep = dwc->eps[epnum]; 1911 1912 if (!(dep->flags & DWC3_EP_STALL)) 1913 continue; 1914 1915 dep->flags &= ~DWC3_EP_STALL; 1916 1917 memset(¶ms, 0, sizeof(params)); 1918 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1919 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1920 WARN_ON_ONCE(ret); 1921 } 1922} 1923 1924static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 1925{ 1926 int reg; 1927 1928 dev_vdbg(dwc->dev, "%s\n", __func__); 1929 1930 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1931 reg &= ~DWC3_DCTL_INITU1ENA; 1932 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1933 1934 reg &= ~DWC3_DCTL_INITU2ENA; 1935 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1936 1937 dwc3_disconnect_gadget(dwc); 1938 dwc->start_config_issued = false; 1939 1940 dwc->gadget.speed = USB_SPEED_UNKNOWN; 1941 dwc->setup_packet_pending = false; 1942} 1943 1944static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend) 1945{ 1946 u32 reg; 1947 1948 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1949 1950 if (suspend) 1951 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1952 else 1953 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 1954 1955 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1956} 1957 1958static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend) 1959{ 1960 u32 reg; 1961 1962 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1963 1964 if (suspend) 1965 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1966 else 1967 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1968 1969 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1970} 1971 1972static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 1973{ 1974 u32 reg; 1975 1976 dev_vdbg(dwc->dev, "%s\n", __func__); 1977 1978 /* 1979 * WORKAROUND: DWC3 revisions <1.88a have an issue which 1980 * would cause a missing Disconnect Event if there's a 1981 * pending Setup Packet in the FIFO. 1982 * 1983 * There's no suggested workaround on the official Bug 1984 * report, which states that "unless the driver/application 1985 * is doing any special handling of a disconnect event, 1986 * there is no functional issue". 1987 * 1988 * Unfortunately, it turns out that we _do_ some special 1989 * handling of a disconnect event, namely complete all 1990 * pending transfers, notify gadget driver of the 1991 * disconnection, and so on. 1992 * 1993 * Our suggested workaround is to follow the Disconnect 1994 * Event steps here, instead, based on a setup_packet_pending 1995 * flag. Such flag gets set whenever we have a XferNotReady 1996 * event on EP0 and gets cleared on XferComplete for the 1997 * same endpoint. 1998 * 1999 * Refers to: 2000 * 2001 * STAR#9000466709: RTL: Device : Disconnect event not 2002 * generated if setup packet pending in FIFO 2003 */ 2004 if (dwc->revision < DWC3_REVISION_188A) { 2005 if (dwc->setup_packet_pending) 2006 dwc3_gadget_disconnect_interrupt(dwc); 2007 } 2008 2009 /* after reset -> Default State */ 2010 dwc->dev_state = DWC3_DEFAULT_STATE; 2011 2012 /* Recent versions support automatic phy suspend and don't need this */ 2013 if (dwc->revision < DWC3_REVISION_194A) { 2014 /* Resume PHYs */ 2015 dwc3_gadget_usb2_phy_suspend(dwc, false); 2016 dwc3_gadget_usb3_phy_suspend(dwc, false); 2017 } 2018 2019 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 2020 dwc3_disconnect_gadget(dwc); 2021 2022 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2023 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2024 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2025 dwc->test_mode = false; 2026 2027 dwc3_stop_active_transfers(dwc); 2028 dwc3_clear_stall_all_ep(dwc); 2029 dwc->start_config_issued = false; 2030 2031 /* Reset device address to zero */ 2032 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2033 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2034 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2035} 2036 2037static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 2038{ 2039 u32 reg; 2040 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 2041 2042 /* 2043 * We change the clock only at SS but I dunno why I would want to do 2044 * this. Maybe it becomes part of the power saving plan. 2045 */ 2046 2047 if (speed != DWC3_DSTS_SUPERSPEED) 2048 return; 2049 2050 /* 2051 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2052 * each time on Connect Done. 2053 */ 2054 if (!usb30_clock) 2055 return; 2056 2057 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 2058 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 2059 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 2060} 2061 2062static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed) 2063{ 2064 switch (speed) { 2065 case USB_SPEED_SUPER: 2066 dwc3_gadget_usb2_phy_suspend(dwc, true); 2067 break; 2068 case USB_SPEED_HIGH: 2069 case USB_SPEED_FULL: 2070 case USB_SPEED_LOW: 2071 dwc3_gadget_usb3_phy_suspend(dwc, true); 2072 break; 2073 } 2074} 2075 2076static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2077{ 2078 struct dwc3_gadget_ep_cmd_params params; 2079 struct dwc3_ep *dep; 2080 int ret; 2081 u32 reg; 2082 u8 speed; 2083 2084 dev_vdbg(dwc->dev, "%s\n", __func__); 2085 2086 memset(¶ms, 0x00, sizeof(params)); 2087 2088 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2089 speed = reg & DWC3_DSTS_CONNECTSPD; 2090 dwc->speed = speed; 2091 2092 dwc3_update_ram_clk_sel(dwc, speed); 2093 2094 switch (speed) { 2095 case DWC3_DCFG_SUPERSPEED: 2096 /* 2097 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2098 * would cause a missing USB3 Reset event. 2099 * 2100 * In such situations, we should force a USB3 Reset 2101 * event by calling our dwc3_gadget_reset_interrupt() 2102 * routine. 2103 * 2104 * Refers to: 2105 * 2106 * STAR#9000483510: RTL: SS : USB3 reset event may 2107 * not be generated always when the link enters poll 2108 */ 2109 if (dwc->revision < DWC3_REVISION_190A) 2110 dwc3_gadget_reset_interrupt(dwc); 2111 2112 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2113 dwc->gadget.ep0->maxpacket = 512; 2114 dwc->gadget.speed = USB_SPEED_SUPER; 2115 break; 2116 case DWC3_DCFG_HIGHSPEED: 2117 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2118 dwc->gadget.ep0->maxpacket = 64; 2119 dwc->gadget.speed = USB_SPEED_HIGH; 2120 break; 2121 case DWC3_DCFG_FULLSPEED2: 2122 case DWC3_DCFG_FULLSPEED1: 2123 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2124 dwc->gadget.ep0->maxpacket = 64; 2125 dwc->gadget.speed = USB_SPEED_FULL; 2126 break; 2127 case DWC3_DCFG_LOWSPEED: 2128 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2129 dwc->gadget.ep0->maxpacket = 8; 2130 dwc->gadget.speed = USB_SPEED_LOW; 2131 break; 2132 } 2133 2134 /* Recent versions support automatic phy suspend and don't need this */ 2135 if (dwc->revision < DWC3_REVISION_194A) { 2136 /* Suspend unneeded PHY */ 2137 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed); 2138 } 2139 2140 dep = dwc->eps[0]; 2141 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true); 2142 if (ret) { 2143 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2144 return; 2145 } 2146 2147 dep = dwc->eps[1]; 2148 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true); 2149 if (ret) { 2150 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2151 return; 2152 } 2153 2154 /* 2155 * Configure PHY via GUSB3PIPECTLn if required. 2156 * 2157 * Update GTXFIFOSIZn 2158 * 2159 * In both cases reset values should be sufficient. 2160 */ 2161} 2162 2163static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2164{ 2165 dev_vdbg(dwc->dev, "%s\n", __func__); 2166 2167 /* 2168 * TODO take core out of low power mode when that's 2169 * implemented. 2170 */ 2171 2172 dwc->gadget_driver->resume(&dwc->gadget); 2173} 2174 2175static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2176 unsigned int evtinfo) 2177{ 2178 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2179 2180 /* 2181 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2182 * on the link partner, the USB session might do multiple entry/exit 2183 * of low power states before a transfer takes place. 2184 * 2185 * Due to this problem, we might experience lower throughput. The 2186 * suggested workaround is to disable DCTL[12:9] bits if we're 2187 * transitioning from U1/U2 to U0 and enable those bits again 2188 * after a transfer completes and there are no pending transfers 2189 * on any of the enabled endpoints. 2190 * 2191 * This is the first half of that workaround. 2192 * 2193 * Refers to: 2194 * 2195 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2196 * core send LGO_Ux entering U0 2197 */ 2198 if (dwc->revision < DWC3_REVISION_183A) { 2199 if (next == DWC3_LINK_STATE_U0) { 2200 u32 u1u2; 2201 u32 reg; 2202 2203 switch (dwc->link_state) { 2204 case DWC3_LINK_STATE_U1: 2205 case DWC3_LINK_STATE_U2: 2206 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2207 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2208 | DWC3_DCTL_ACCEPTU2ENA 2209 | DWC3_DCTL_INITU1ENA 2210 | DWC3_DCTL_ACCEPTU1ENA); 2211 2212 if (!dwc->u1u2) 2213 dwc->u1u2 = reg & u1u2; 2214 2215 reg &= ~u1u2; 2216 2217 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2218 break; 2219 default: 2220 /* do nothing */ 2221 break; 2222 } 2223 } 2224 } 2225 2226 dwc->link_state = next; 2227 2228 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 2229} 2230 2231static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2232 const struct dwc3_event_devt *event) 2233{ 2234 switch (event->type) { 2235 case DWC3_DEVICE_EVENT_DISCONNECT: 2236 dwc3_gadget_disconnect_interrupt(dwc); 2237 break; 2238 case DWC3_DEVICE_EVENT_RESET: 2239 dwc3_gadget_reset_interrupt(dwc); 2240 break; 2241 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2242 dwc3_gadget_conndone_interrupt(dwc); 2243 break; 2244 case DWC3_DEVICE_EVENT_WAKEUP: 2245 dwc3_gadget_wakeup_interrupt(dwc); 2246 break; 2247 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2248 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2249 break; 2250 case DWC3_DEVICE_EVENT_EOPF: 2251 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2252 break; 2253 case DWC3_DEVICE_EVENT_SOF: 2254 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2255 break; 2256 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2257 dev_vdbg(dwc->dev, "Erratic Error\n"); 2258 break; 2259 case DWC3_DEVICE_EVENT_CMD_CMPL: 2260 dev_vdbg(dwc->dev, "Command Complete\n"); 2261 break; 2262 case DWC3_DEVICE_EVENT_OVERFLOW: 2263 dev_vdbg(dwc->dev, "Overflow\n"); 2264 break; 2265 default: 2266 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2267 } 2268} 2269 2270static void dwc3_process_event_entry(struct dwc3 *dwc, 2271 const union dwc3_event *event) 2272{ 2273 /* Endpoint IRQ, handle it and return early */ 2274 if (event->type.is_devspec == 0) { 2275 /* depevt */ 2276 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2277 } 2278 2279 switch (event->type.type) { 2280 case DWC3_EVENT_TYPE_DEV: 2281 dwc3_gadget_interrupt(dwc, &event->devt); 2282 break; 2283 /* REVISIT what to do with Carkit and I2C events ? */ 2284 default: 2285 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2286 } 2287} 2288 2289static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2290{ 2291 struct dwc3_event_buffer *evt; 2292 int left; 2293 u32 count; 2294 2295 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2296 count &= DWC3_GEVNTCOUNT_MASK; 2297 if (!count) 2298 return IRQ_NONE; 2299 2300 evt = dwc->ev_buffs[buf]; 2301 left = count; 2302 2303 while (left > 0) { 2304 union dwc3_event event; 2305 2306 event.raw = *(u32 *) (evt->buf + evt->lpos); 2307 2308 dwc3_process_event_entry(dwc, &event); 2309 /* 2310 * XXX we wrap around correctly to the next entry as almost all 2311 * entries are 4 bytes in size. There is one entry which has 12 2312 * bytes which is a regular entry followed by 8 bytes data. ATM 2313 * I don't know how things are organized if were get next to the 2314 * a boundary so I worry about that once we try to handle that. 2315 */ 2316 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2317 left -= 4; 2318 2319 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2320 } 2321 2322 return IRQ_HANDLED; 2323} 2324 2325static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2326{ 2327 struct dwc3 *dwc = _dwc; 2328 int i; 2329 irqreturn_t ret = IRQ_NONE; 2330 2331 spin_lock(&dwc->lock); 2332 2333 for (i = 0; i < dwc->num_event_buffers; i++) { 2334 irqreturn_t status; 2335 2336 status = dwc3_process_event_buf(dwc, i); 2337 if (status == IRQ_HANDLED) 2338 ret = status; 2339 } 2340 2341 spin_unlock(&dwc->lock); 2342 2343 return ret; 2344} 2345 2346/** 2347 * dwc3_gadget_init - Initializes gadget related registers 2348 * @dwc: pointer to our controller context structure 2349 * 2350 * Returns 0 on success otherwise negative errno. 2351 */ 2352int __devinit dwc3_gadget_init(struct dwc3 *dwc) 2353{ 2354 u32 reg; 2355 int ret; 2356 int irq; 2357 2358 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2359 &dwc->ctrl_req_addr, GFP_KERNEL); 2360 if (!dwc->ctrl_req) { 2361 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2362 ret = -ENOMEM; 2363 goto err0; 2364 } 2365 2366 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2367 &dwc->ep0_trb_addr, GFP_KERNEL); 2368 if (!dwc->ep0_trb) { 2369 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2370 ret = -ENOMEM; 2371 goto err1; 2372 } 2373 2374 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); 2375 if (!dwc->setup_buf) { 2376 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2377 ret = -ENOMEM; 2378 goto err2; 2379 } 2380 2381 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2382 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, 2383 GFP_KERNEL); 2384 if (!dwc->ep0_bounce) { 2385 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2386 ret = -ENOMEM; 2387 goto err3; 2388 } 2389 2390 dev_set_name(&dwc->gadget.dev, "gadget"); 2391 2392 dwc->gadget.ops = &dwc3_gadget_ops; 2393 dwc->gadget.max_speed = USB_SPEED_SUPER; 2394 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2395 dwc->gadget.dev.parent = dwc->dev; 2396 dwc->gadget.sg_supported = true; 2397 2398 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); 2399 2400 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; 2401 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; 2402 dwc->gadget.dev.release = dwc3_gadget_release; 2403 dwc->gadget.name = "dwc3-gadget"; 2404 2405 /* 2406 * REVISIT: Here we should clear all pending IRQs to be 2407 * sure we're starting from a well known location. 2408 */ 2409 2410 ret = dwc3_gadget_init_endpoints(dwc); 2411 if (ret) 2412 goto err4; 2413 2414 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2415 2416 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, 2417 "dwc3", dwc); 2418 if (ret) { 2419 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 2420 irq, ret); 2421 goto err5; 2422 } 2423 2424 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2425 reg |= DWC3_DCFG_LPM_CAP; 2426 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2427 2428 /* Enable all but Start and End of Frame IRQs */ 2429 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 2430 DWC3_DEVTEN_EVNTOVERFLOWEN | 2431 DWC3_DEVTEN_CMDCMPLTEN | 2432 DWC3_DEVTEN_ERRTICERREN | 2433 DWC3_DEVTEN_WKUPEVTEN | 2434 DWC3_DEVTEN_ULSTCNGEN | 2435 DWC3_DEVTEN_CONNECTDONEEN | 2436 DWC3_DEVTEN_USBRSTEN | 2437 DWC3_DEVTEN_DISCONNEVTEN); 2438 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 2439 2440 /* Enable USB2 LPM and automatic phy suspend only on recent versions */ 2441 if (dwc->revision >= DWC3_REVISION_194A) { 2442 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2443 reg |= DWC3_DCFG_LPM_CAP; 2444 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2445 2446 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2447 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2448 2449 /* TODO: This should be configurable */ 2450 reg |= DWC3_DCTL_HIRD_THRES(28); 2451 2452 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2453 2454 dwc3_gadget_usb2_phy_suspend(dwc, false); 2455 dwc3_gadget_usb3_phy_suspend(dwc, false); 2456 } 2457 2458 ret = device_register(&dwc->gadget.dev); 2459 if (ret) { 2460 dev_err(dwc->dev, "failed to register gadget device\n"); 2461 put_device(&dwc->gadget.dev); 2462 goto err6; 2463 } 2464 2465 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2466 if (ret) { 2467 dev_err(dwc->dev, "failed to register udc\n"); 2468 goto err7; 2469 } 2470 2471 return 0; 2472 2473err7: 2474 device_unregister(&dwc->gadget.dev); 2475 2476err6: 2477 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2478 free_irq(irq, dwc); 2479 2480err5: 2481 dwc3_gadget_free_endpoints(dwc); 2482 2483err4: 2484 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2485 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2486 2487err3: 2488 kfree(dwc->setup_buf); 2489 2490err2: 2491 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2492 dwc->ep0_trb, dwc->ep0_trb_addr); 2493 2494err1: 2495 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2496 dwc->ctrl_req, dwc->ctrl_req_addr); 2497 2498err0: 2499 return ret; 2500} 2501 2502void dwc3_gadget_exit(struct dwc3 *dwc) 2503{ 2504 int irq; 2505 2506 usb_del_gadget_udc(&dwc->gadget); 2507 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2508 2509 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2510 free_irq(irq, dwc); 2511 2512 dwc3_gadget_free_endpoints(dwc); 2513 2514 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2515 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2516 2517 kfree(dwc->setup_buf); 2518 2519 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2520 dwc->ep0_trb, dwc->ep0_trb_addr); 2521 2522 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2523 dwc->ctrl_req, dwc->ctrl_req_addr); 2524 2525 device_unregister(&dwc->gadget.dev); 2526} 2527