gadget.c revision 687ef9817df7ed960d14575b9033dde3d04631fe
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#include <linux/kernel.h> 20#include <linux/delay.h> 21#include <linux/slab.h> 22#include <linux/spinlock.h> 23#include <linux/platform_device.h> 24#include <linux/pm_runtime.h> 25#include <linux/interrupt.h> 26#include <linux/io.h> 27#include <linux/list.h> 28#include <linux/dma-mapping.h> 29 30#include <linux/usb/ch9.h> 31#include <linux/usb/gadget.h> 32 33#include "core.h" 34#include "gadget.h" 35#include "io.h" 36 37/** 38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 39 * @dwc: pointer to our context structure 40 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 41 * 42 * Caller should take care of locking. This function will 43 * return 0 on success or -EINVAL if wrong Test Selector 44 * is passed 45 */ 46int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 47{ 48 u32 reg; 49 50 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 51 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 52 53 switch (mode) { 54 case TEST_J: 55 case TEST_K: 56 case TEST_SE0_NAK: 57 case TEST_PACKET: 58 case TEST_FORCE_EN: 59 reg |= mode << 1; 60 break; 61 default: 62 return -EINVAL; 63 } 64 65 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 66 67 return 0; 68} 69 70/** 71 * dwc3_gadget_get_link_state - Gets current state of USB Link 72 * @dwc: pointer to our context structure 73 * 74 * Caller should take care of locking. This function will 75 * return the link state on success (>= 0) or -ETIMEDOUT. 76 */ 77int dwc3_gadget_get_link_state(struct dwc3 *dwc) 78{ 79 u32 reg; 80 81 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 82 83 return DWC3_DSTS_USBLNKST(reg); 84} 85 86/** 87 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 88 * @dwc: pointer to our context structure 89 * @state: the state to put link into 90 * 91 * Caller should take care of locking. This function will 92 * return 0 on success or -ETIMEDOUT. 93 */ 94int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 95{ 96 int retries = 10000; 97 u32 reg; 98 99 /* 100 * Wait until device controller is ready. Only applies to 1.94a and 101 * later RTL. 102 */ 103 if (dwc->revision >= DWC3_REVISION_194A) { 104 while (--retries) { 105 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 106 if (reg & DWC3_DSTS_DCNRD) 107 udelay(5); 108 else 109 break; 110 } 111 112 if (retries <= 0) 113 return -ETIMEDOUT; 114 } 115 116 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 118 119 /* set requested state */ 120 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 121 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 122 123 /* 124 * The following code is racy when called from dwc3_gadget_wakeup, 125 * and is not needed, at least on newer versions 126 */ 127 if (dwc->revision >= DWC3_REVISION_194A) 128 return 0; 129 130 /* wait for a change in DSTS */ 131 retries = 10000; 132 while (--retries) { 133 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 134 135 if (DWC3_DSTS_USBLNKST(reg) == state) 136 return 0; 137 138 udelay(5); 139 } 140 141 dev_vdbg(dwc->dev, "link state change request timed out\n"); 142 143 return -ETIMEDOUT; 144} 145 146/** 147 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 148 * @dwc: pointer to our context structure 149 * 150 * This function will a best effort FIFO allocation in order 151 * to improve FIFO usage and throughput, while still allowing 152 * us to enable as many endpoints as possible. 153 * 154 * Keep in mind that this operation will be highly dependent 155 * on the configured size for RAM1 - which contains TxFifo -, 156 * the amount of endpoints enabled on coreConsultant tool, and 157 * the width of the Master Bus. 158 * 159 * In the ideal world, we would always be able to satisfy the 160 * following equation: 161 * 162 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 163 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 164 * 165 * Unfortunately, due to many variables that's not always the case. 166 */ 167int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 168{ 169 int last_fifo_depth = 0; 170 int ram1_depth; 171 int fifo_size; 172 int mdwidth; 173 int num; 174 175 if (!dwc->needs_fifo_resize) 176 return 0; 177 178 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 179 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 180 181 /* MDWIDTH is represented in bits, we need it in bytes */ 182 mdwidth >>= 3; 183 184 /* 185 * FIXME For now we will only allocate 1 wMaxPacketSize space 186 * for each enabled endpoint, later patches will come to 187 * improve this algorithm so that we better use the internal 188 * FIFO space 189 */ 190 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { 191 struct dwc3_ep *dep = dwc->eps[num]; 192 int fifo_number = dep->number >> 1; 193 int mult = 1; 194 int tmp; 195 196 if (!(dep->number & 1)) 197 continue; 198 199 if (!(dep->flags & DWC3_EP_ENABLED)) 200 continue; 201 202 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) 203 || usb_endpoint_xfer_isoc(dep->endpoint.desc)) 204 mult = 3; 205 206 /* 207 * REVISIT: the following assumes we will always have enough 208 * space available on the FIFO RAM for all possible use cases. 209 * Make sure that's true somehow and change FIFO allocation 210 * accordingly. 211 * 212 * If we have Bulk or Isochronous endpoints, we want 213 * them to be able to be very, very fast. So we're giving 214 * those endpoints a fifo_size which is enough for 3 full 215 * packets 216 */ 217 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 218 tmp += mdwidth; 219 220 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 221 222 fifo_size |= (last_fifo_depth << 16); 223 224 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 225 dep->name, last_fifo_depth, fifo_size & 0xffff); 226 227 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), 228 fifo_size); 229 230 last_fifo_depth += (fifo_size & 0xffff); 231 } 232 233 return 0; 234} 235 236void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 237 int status) 238{ 239 struct dwc3 *dwc = dep->dwc; 240 int i; 241 242 if (req->queued) { 243 i = 0; 244 do { 245 dep->busy_slot++; 246 /* 247 * Skip LINK TRB. We can't use req->trb and check for 248 * DWC3_TRBCTL_LINK_TRB because it points the TRB we 249 * just completed (not the LINK TRB). 250 */ 251 if (((dep->busy_slot & DWC3_TRB_MASK) == 252 DWC3_TRB_NUM- 1) && 253 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 254 dep->busy_slot++; 255 } while(++i < req->request.num_mapped_sgs); 256 req->queued = false; 257 } 258 list_del(&req->list); 259 req->trb = NULL; 260 261 if (req->request.status == -EINPROGRESS) 262 req->request.status = status; 263 264 if (dwc->ep0_bounced && dep->number == 0) 265 dwc->ep0_bounced = false; 266 else 267 usb_gadget_unmap_request(&dwc->gadget, &req->request, 268 req->direction); 269 270 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 271 req, dep->name, req->request.actual, 272 req->request.length, status); 273 274 spin_unlock(&dwc->lock); 275 req->request.complete(&dep->endpoint, &req->request); 276 spin_lock(&dwc->lock); 277} 278 279static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 280{ 281 switch (cmd) { 282 case DWC3_DEPCMD_DEPSTARTCFG: 283 return "Start New Configuration"; 284 case DWC3_DEPCMD_ENDTRANSFER: 285 return "End Transfer"; 286 case DWC3_DEPCMD_UPDATETRANSFER: 287 return "Update Transfer"; 288 case DWC3_DEPCMD_STARTTRANSFER: 289 return "Start Transfer"; 290 case DWC3_DEPCMD_CLEARSTALL: 291 return "Clear Stall"; 292 case DWC3_DEPCMD_SETSTALL: 293 return "Set Stall"; 294 case DWC3_DEPCMD_GETEPSTATE: 295 return "Get Endpoint State"; 296 case DWC3_DEPCMD_SETTRANSFRESOURCE: 297 return "Set Endpoint Transfer Resource"; 298 case DWC3_DEPCMD_SETEPCONFIG: 299 return "Set Endpoint Configuration"; 300 default: 301 return "UNKNOWN command"; 302 } 303} 304 305int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) 306{ 307 u32 timeout = 500; 308 u32 reg; 309 310 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 311 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 312 313 do { 314 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 315 if (!(reg & DWC3_DGCMD_CMDACT)) { 316 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 317 DWC3_DGCMD_STATUS(reg)); 318 return 0; 319 } 320 321 /* 322 * We can't sleep here, because it's also called from 323 * interrupt context. 324 */ 325 timeout--; 326 if (!timeout) 327 return -ETIMEDOUT; 328 udelay(1); 329 } while (1); 330} 331 332int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 333 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 334{ 335 struct dwc3_ep *dep = dwc->eps[ep]; 336 u32 timeout = 500; 337 u32 reg; 338 339 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 340 dep->name, 341 dwc3_gadget_ep_cmd_string(cmd), params->param0, 342 params->param1, params->param2); 343 344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 346 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 347 348 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 349 do { 350 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 351 if (!(reg & DWC3_DEPCMD_CMDACT)) { 352 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 353 DWC3_DEPCMD_STATUS(reg)); 354 return 0; 355 } 356 357 /* 358 * We can't sleep here, because it is also called from 359 * interrupt context. 360 */ 361 timeout--; 362 if (!timeout) 363 return -ETIMEDOUT; 364 365 udelay(1); 366 } while (1); 367} 368 369static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 370 struct dwc3_trb *trb) 371{ 372 u32 offset = (char *) trb - (char *) dep->trb_pool; 373 374 return dep->trb_pool_dma + offset; 375} 376 377static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 378{ 379 struct dwc3 *dwc = dep->dwc; 380 381 if (dep->trb_pool) 382 return 0; 383 384 if (dep->number == 0 || dep->number == 1) 385 return 0; 386 387 dep->trb_pool = dma_alloc_coherent(dwc->dev, 388 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 389 &dep->trb_pool_dma, GFP_KERNEL); 390 if (!dep->trb_pool) { 391 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 392 dep->name); 393 return -ENOMEM; 394 } 395 396 return 0; 397} 398 399static void dwc3_free_trb_pool(struct dwc3_ep *dep) 400{ 401 struct dwc3 *dwc = dep->dwc; 402 403 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 404 dep->trb_pool, dep->trb_pool_dma); 405 406 dep->trb_pool = NULL; 407 dep->trb_pool_dma = 0; 408} 409 410static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 411{ 412 struct dwc3_gadget_ep_cmd_params params; 413 u32 cmd; 414 415 memset(¶ms, 0x00, sizeof(params)); 416 417 if (dep->number != 1) { 418 cmd = DWC3_DEPCMD_DEPSTARTCFG; 419 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 420 if (dep->number > 1) { 421 if (dwc->start_config_issued) 422 return 0; 423 dwc->start_config_issued = true; 424 cmd |= DWC3_DEPCMD_PARAM(2); 425 } 426 427 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 428 } 429 430 return 0; 431} 432 433static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 434 const struct usb_endpoint_descriptor *desc, 435 const struct usb_ss_ep_comp_descriptor *comp_desc, 436 bool ignore, bool restore) 437{ 438 struct dwc3_gadget_ep_cmd_params params; 439 440 memset(¶ms, 0x00, sizeof(params)); 441 442 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 443 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); 444 445 /* Burst size is only needed in SuperSpeed mode */ 446 if (dwc->gadget.speed == USB_SPEED_SUPER) { 447 u32 burst = dep->endpoint.maxburst - 1; 448 449 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); 450 } 451 452 if (ignore) 453 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; 454 455 if (restore) { 456 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; 457 params.param2 |= dep->saved_state; 458 } 459 460 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 461 | DWC3_DEPCFG_XFER_NOT_READY_EN; 462 463 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 464 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 465 | DWC3_DEPCFG_STREAM_EVENT_EN; 466 dep->stream_capable = true; 467 } 468 469 if (usb_endpoint_xfer_isoc(desc)) 470 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 471 472 /* 473 * We are doing 1:1 mapping for endpoints, meaning 474 * Physical Endpoints 2 maps to Logical Endpoint 2 and 475 * so on. We consider the direction bit as part of the physical 476 * endpoint number. So USB endpoint 0x81 is 0x03. 477 */ 478 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 479 480 /* 481 * We must use the lower 16 TX FIFOs even though 482 * HW might have more 483 */ 484 if (dep->direction) 485 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 486 487 if (desc->bInterval) { 488 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 489 dep->interval = 1 << (desc->bInterval - 1); 490 } 491 492 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 493 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 494} 495 496static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 497{ 498 struct dwc3_gadget_ep_cmd_params params; 499 500 memset(¶ms, 0x00, sizeof(params)); 501 502 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 503 504 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 505 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 506} 507 508/** 509 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 510 * @dep: endpoint to be initialized 511 * @desc: USB Endpoint Descriptor 512 * 513 * Caller should take care of locking 514 */ 515static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 516 const struct usb_endpoint_descriptor *desc, 517 const struct usb_ss_ep_comp_descriptor *comp_desc, 518 bool ignore, bool restore) 519{ 520 struct dwc3 *dwc = dep->dwc; 521 u32 reg; 522 int ret = -ENOMEM; 523 524 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 525 526 if (!(dep->flags & DWC3_EP_ENABLED)) { 527 ret = dwc3_gadget_start_config(dwc, dep); 528 if (ret) 529 return ret; 530 } 531 532 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, 533 restore); 534 if (ret) 535 return ret; 536 537 if (!(dep->flags & DWC3_EP_ENABLED)) { 538 struct dwc3_trb *trb_st_hw; 539 struct dwc3_trb *trb_link; 540 541 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 542 if (ret) 543 return ret; 544 545 dep->endpoint.desc = desc; 546 dep->comp_desc = comp_desc; 547 dep->type = usb_endpoint_type(desc); 548 dep->flags |= DWC3_EP_ENABLED; 549 550 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 551 reg |= DWC3_DALEPENA_EP(dep->number); 552 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 553 554 if (!usb_endpoint_xfer_isoc(desc)) 555 return 0; 556 557 memset(&trb_link, 0, sizeof(trb_link)); 558 559 /* Link TRB for ISOC. The HWO bit is never reset */ 560 trb_st_hw = &dep->trb_pool[0]; 561 562 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 563 564 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 565 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 566 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 567 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 568 } 569 570 return 0; 571} 572 573static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); 574static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 575{ 576 struct dwc3_request *req; 577 578 if (!list_empty(&dep->req_queued)) { 579 dwc3_stop_active_transfer(dwc, dep->number, true); 580 581 /* - giveback all requests to gadget driver */ 582 while (!list_empty(&dep->req_queued)) { 583 req = next_request(&dep->req_queued); 584 585 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 586 } 587 } 588 589 while (!list_empty(&dep->request_list)) { 590 req = next_request(&dep->request_list); 591 592 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 593 } 594} 595 596/** 597 * __dwc3_gadget_ep_disable - Disables a HW endpoint 598 * @dep: the endpoint to disable 599 * 600 * This function also removes requests which are currently processed ny the 601 * hardware and those which are not yet scheduled. 602 * Caller should take care of locking. 603 */ 604static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 605{ 606 struct dwc3 *dwc = dep->dwc; 607 u32 reg; 608 609 dwc3_remove_requests(dwc, dep); 610 611 /* make sure HW endpoint isn't stalled */ 612 if (dep->flags & DWC3_EP_STALL) 613 __dwc3_gadget_ep_set_halt(dep, 0); 614 615 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 616 reg &= ~DWC3_DALEPENA_EP(dep->number); 617 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 618 619 dep->stream_capable = false; 620 dep->endpoint.desc = NULL; 621 dep->comp_desc = NULL; 622 dep->type = 0; 623 dep->flags = 0; 624 625 return 0; 626} 627 628/* -------------------------------------------------------------------------- */ 629 630static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 631 const struct usb_endpoint_descriptor *desc) 632{ 633 return -EINVAL; 634} 635 636static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 637{ 638 return -EINVAL; 639} 640 641/* -------------------------------------------------------------------------- */ 642 643static int dwc3_gadget_ep_enable(struct usb_ep *ep, 644 const struct usb_endpoint_descriptor *desc) 645{ 646 struct dwc3_ep *dep; 647 struct dwc3 *dwc; 648 unsigned long flags; 649 int ret; 650 651 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 652 pr_debug("dwc3: invalid parameters\n"); 653 return -EINVAL; 654 } 655 656 if (!desc->wMaxPacketSize) { 657 pr_debug("dwc3: missing wMaxPacketSize\n"); 658 return -EINVAL; 659 } 660 661 dep = to_dwc3_ep(ep); 662 dwc = dep->dwc; 663 664 if (dep->flags & DWC3_EP_ENABLED) { 665 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 666 dep->name); 667 return 0; 668 } 669 670 switch (usb_endpoint_type(desc)) { 671 case USB_ENDPOINT_XFER_CONTROL: 672 strlcat(dep->name, "-control", sizeof(dep->name)); 673 break; 674 case USB_ENDPOINT_XFER_ISOC: 675 strlcat(dep->name, "-isoc", sizeof(dep->name)); 676 break; 677 case USB_ENDPOINT_XFER_BULK: 678 strlcat(dep->name, "-bulk", sizeof(dep->name)); 679 break; 680 case USB_ENDPOINT_XFER_INT: 681 strlcat(dep->name, "-int", sizeof(dep->name)); 682 break; 683 default: 684 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 685 } 686 687 spin_lock_irqsave(&dwc->lock, flags); 688 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); 689 spin_unlock_irqrestore(&dwc->lock, flags); 690 691 return ret; 692} 693 694static int dwc3_gadget_ep_disable(struct usb_ep *ep) 695{ 696 struct dwc3_ep *dep; 697 struct dwc3 *dwc; 698 unsigned long flags; 699 int ret; 700 701 if (!ep) { 702 pr_debug("dwc3: invalid parameters\n"); 703 return -EINVAL; 704 } 705 706 dep = to_dwc3_ep(ep); 707 dwc = dep->dwc; 708 709 if (!(dep->flags & DWC3_EP_ENABLED)) { 710 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 711 dep->name); 712 return 0; 713 } 714 715 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 716 dep->number >> 1, 717 (dep->number & 1) ? "in" : "out"); 718 719 spin_lock_irqsave(&dwc->lock, flags); 720 ret = __dwc3_gadget_ep_disable(dep); 721 spin_unlock_irqrestore(&dwc->lock, flags); 722 723 return ret; 724} 725 726static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 727 gfp_t gfp_flags) 728{ 729 struct dwc3_request *req; 730 struct dwc3_ep *dep = to_dwc3_ep(ep); 731 struct dwc3 *dwc = dep->dwc; 732 733 req = kzalloc(sizeof(*req), gfp_flags); 734 if (!req) { 735 dev_err(dwc->dev, "not enough memory\n"); 736 return NULL; 737 } 738 739 req->epnum = dep->number; 740 req->dep = dep; 741 742 return &req->request; 743} 744 745static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 746 struct usb_request *request) 747{ 748 struct dwc3_request *req = to_dwc3_request(request); 749 750 kfree(req); 751} 752 753/** 754 * dwc3_prepare_one_trb - setup one TRB from one request 755 * @dep: endpoint for which this request is prepared 756 * @req: dwc3_request pointer 757 */ 758static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 759 struct dwc3_request *req, dma_addr_t dma, 760 unsigned length, unsigned last, unsigned chain, unsigned node) 761{ 762 struct dwc3 *dwc = dep->dwc; 763 struct dwc3_trb *trb; 764 765 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 766 dep->name, req, (unsigned long long) dma, 767 length, last ? " last" : "", 768 chain ? " chain" : ""); 769 770 /* Skip the LINK-TRB on ISOC */ 771 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 772 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 773 dep->free_slot++; 774 775 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 776 777 if (!req->trb) { 778 dwc3_gadget_move_request_queued(req); 779 req->trb = trb; 780 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 781 req->start_slot = dep->free_slot & DWC3_TRB_MASK; 782 } 783 784 dep->free_slot++; 785 786 trb->size = DWC3_TRB_SIZE_LENGTH(length); 787 trb->bpl = lower_32_bits(dma); 788 trb->bph = upper_32_bits(dma); 789 790 switch (usb_endpoint_type(dep->endpoint.desc)) { 791 case USB_ENDPOINT_XFER_CONTROL: 792 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 793 break; 794 795 case USB_ENDPOINT_XFER_ISOC: 796 if (!node) 797 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 798 else 799 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; 800 break; 801 802 case USB_ENDPOINT_XFER_BULK: 803 case USB_ENDPOINT_XFER_INT: 804 trb->ctrl = DWC3_TRBCTL_NORMAL; 805 break; 806 default: 807 /* 808 * This is only possible with faulty memory because we 809 * checked it already :) 810 */ 811 BUG(); 812 } 813 814 if (!req->request.no_interrupt && !chain) 815 trb->ctrl |= DWC3_TRB_CTRL_IOC; 816 817 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 818 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 819 trb->ctrl |= DWC3_TRB_CTRL_CSP; 820 } else if (last) { 821 trb->ctrl |= DWC3_TRB_CTRL_LST; 822 } 823 824 if (chain) 825 trb->ctrl |= DWC3_TRB_CTRL_CHN; 826 827 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 828 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); 829 830 trb->ctrl |= DWC3_TRB_CTRL_HWO; 831} 832 833/* 834 * dwc3_prepare_trbs - setup TRBs from requests 835 * @dep: endpoint for which requests are being prepared 836 * @starting: true if the endpoint is idle and no requests are queued. 837 * 838 * The function goes through the requests list and sets up TRBs for the 839 * transfers. The function returns once there are no more TRBs available or 840 * it runs out of requests. 841 */ 842static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 843{ 844 struct dwc3_request *req, *n; 845 u32 trbs_left; 846 u32 max; 847 unsigned int last_one = 0; 848 849 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 850 851 /* the first request must not be queued */ 852 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 853 854 /* Can't wrap around on a non-isoc EP since there's no link TRB */ 855 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 856 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); 857 if (trbs_left > max) 858 trbs_left = max; 859 } 860 861 /* 862 * If busy & slot are equal than it is either full or empty. If we are 863 * starting to process requests then we are empty. Otherwise we are 864 * full and don't do anything 865 */ 866 if (!trbs_left) { 867 if (!starting) 868 return; 869 trbs_left = DWC3_TRB_NUM; 870 /* 871 * In case we start from scratch, we queue the ISOC requests 872 * starting from slot 1. This is done because we use ring 873 * buffer and have no LST bit to stop us. Instead, we place 874 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt 875 * after the first request so we start at slot 1 and have 876 * 7 requests proceed before we hit the first IOC. 877 * Other transfer types don't use the ring buffer and are 878 * processed from the first TRB until the last one. Since we 879 * don't wrap around we have to start at the beginning. 880 */ 881 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 882 dep->busy_slot = 1; 883 dep->free_slot = 1; 884 } else { 885 dep->busy_slot = 0; 886 dep->free_slot = 0; 887 } 888 } 889 890 /* The last TRB is a link TRB, not used for xfer */ 891 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) 892 return; 893 894 list_for_each_entry_safe(req, n, &dep->request_list, list) { 895 unsigned length; 896 dma_addr_t dma; 897 last_one = false; 898 899 if (req->request.num_mapped_sgs > 0) { 900 struct usb_request *request = &req->request; 901 struct scatterlist *sg = request->sg; 902 struct scatterlist *s; 903 int i; 904 905 for_each_sg(sg, s, request->num_mapped_sgs, i) { 906 unsigned chain = true; 907 908 length = sg_dma_len(s); 909 dma = sg_dma_address(s); 910 911 if (i == (request->num_mapped_sgs - 1) || 912 sg_is_last(s)) { 913 if (list_is_last(&req->list, 914 &dep->request_list)) 915 last_one = true; 916 chain = false; 917 } 918 919 trbs_left--; 920 if (!trbs_left) 921 last_one = true; 922 923 if (last_one) 924 chain = false; 925 926 dwc3_prepare_one_trb(dep, req, dma, length, 927 last_one, chain, i); 928 929 if (last_one) 930 break; 931 } 932 } else { 933 dma = req->request.dma; 934 length = req->request.length; 935 trbs_left--; 936 937 if (!trbs_left) 938 last_one = 1; 939 940 /* Is this the last request? */ 941 if (list_is_last(&req->list, &dep->request_list)) 942 last_one = 1; 943 944 dwc3_prepare_one_trb(dep, req, dma, length, 945 last_one, false, 0); 946 947 if (last_one) 948 break; 949 } 950 } 951} 952 953static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 954 int start_new) 955{ 956 struct dwc3_gadget_ep_cmd_params params; 957 struct dwc3_request *req; 958 struct dwc3 *dwc = dep->dwc; 959 int ret; 960 u32 cmd; 961 962 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 963 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 964 return -EBUSY; 965 } 966 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 967 968 /* 969 * If we are getting here after a short-out-packet we don't enqueue any 970 * new requests as we try to set the IOC bit only on the last request. 971 */ 972 if (start_new) { 973 if (list_empty(&dep->req_queued)) 974 dwc3_prepare_trbs(dep, start_new); 975 976 /* req points to the first request which will be sent */ 977 req = next_request(&dep->req_queued); 978 } else { 979 dwc3_prepare_trbs(dep, start_new); 980 981 /* 982 * req points to the first request where HWO changed from 0 to 1 983 */ 984 req = next_request(&dep->req_queued); 985 } 986 if (!req) { 987 dep->flags |= DWC3_EP_PENDING_REQUEST; 988 return 0; 989 } 990 991 memset(¶ms, 0, sizeof(params)); 992 993 if (start_new) { 994 params.param0 = upper_32_bits(req->trb_dma); 995 params.param1 = lower_32_bits(req->trb_dma); 996 cmd = DWC3_DEPCMD_STARTTRANSFER; 997 } else { 998 cmd = DWC3_DEPCMD_UPDATETRANSFER; 999 } 1000 1001 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 1002 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1003 if (ret < 0) { 1004 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 1005 1006 /* 1007 * FIXME we need to iterate over the list of requests 1008 * here and stop, unmap, free and del each of the linked 1009 * requests instead of what we do now. 1010 */ 1011 usb_gadget_unmap_request(&dwc->gadget, &req->request, 1012 req->direction); 1013 list_del(&req->list); 1014 return ret; 1015 } 1016 1017 dep->flags |= DWC3_EP_BUSY; 1018 1019 if (start_new) { 1020 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 1021 dep->number); 1022 WARN_ON_ONCE(!dep->resource_index); 1023 } 1024 1025 return 0; 1026} 1027 1028static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, 1029 struct dwc3_ep *dep, u32 cur_uf) 1030{ 1031 u32 uf; 1032 1033 if (list_empty(&dep->request_list)) { 1034 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1035 dep->name); 1036 dep->flags |= DWC3_EP_PENDING_REQUEST; 1037 return; 1038 } 1039 1040 /* 4 micro frames in the future */ 1041 uf = cur_uf + dep->interval * 4; 1042 1043 __dwc3_gadget_kick_transfer(dep, uf, 1); 1044} 1045 1046static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1047 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1048{ 1049 u32 cur_uf, mask; 1050 1051 mask = ~(dep->interval - 1); 1052 cur_uf = event->parameters & mask; 1053 1054 __dwc3_gadget_start_isoc(dwc, dep, cur_uf); 1055} 1056 1057static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 1058{ 1059 struct dwc3 *dwc = dep->dwc; 1060 int ret; 1061 1062 req->request.actual = 0; 1063 req->request.status = -EINPROGRESS; 1064 req->direction = dep->direction; 1065 req->epnum = dep->number; 1066 1067 /* 1068 * We only add to our list of requests now and 1069 * start consuming the list once we get XferNotReady 1070 * IRQ. 1071 * 1072 * That way, we avoid doing anything that we don't need 1073 * to do now and defer it until the point we receive a 1074 * particular token from the Host side. 1075 * 1076 * This will also avoid Host cancelling URBs due to too 1077 * many NAKs. 1078 */ 1079 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1080 dep->direction); 1081 if (ret) 1082 return ret; 1083 1084 list_add_tail(&req->list, &dep->request_list); 1085 1086 /* 1087 * There are a few special cases: 1088 * 1089 * 1. XferNotReady with empty list of requests. We need to kick the 1090 * transfer here in that situation, otherwise we will be NAKing 1091 * forever. If we get XferNotReady before gadget driver has a 1092 * chance to queue a request, we will ACK the IRQ but won't be 1093 * able to receive the data until the next request is queued. 1094 * The following code is handling exactly that. 1095 * 1096 */ 1097 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1098 /* 1099 * If xfernotready is already elapsed and it is a case 1100 * of isoc transfer, then issue END TRANSFER, so that 1101 * you can receive xfernotready again and can have 1102 * notion of current microframe. 1103 */ 1104 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1105 if (list_empty(&dep->req_queued)) { 1106 dwc3_stop_active_transfer(dwc, dep->number, true); 1107 dep->flags = DWC3_EP_ENABLED; 1108 } 1109 return 0; 1110 } 1111 1112 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1113 if (ret && ret != -EBUSY) 1114 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1115 dep->name); 1116 return ret; 1117 } 1118 1119 /* 1120 * 2. XferInProgress on Isoc EP with an active transfer. We need to 1121 * kick the transfer here after queuing a request, otherwise the 1122 * core may not see the modified TRB(s). 1123 */ 1124 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1125 (dep->flags & DWC3_EP_BUSY) && 1126 !(dep->flags & DWC3_EP_MISSED_ISOC)) { 1127 WARN_ON_ONCE(!dep->resource_index); 1128 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, 1129 false); 1130 if (ret && ret != -EBUSY) 1131 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1132 dep->name); 1133 return ret; 1134 } 1135 1136 /* 1137 * 4. Stream Capable Bulk Endpoints. We need to start the transfer 1138 * right away, otherwise host will not know we have streams to be 1139 * handled. 1140 */ 1141 if (dep->stream_capable) { 1142 int ret; 1143 1144 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1145 if (ret && ret != -EBUSY) { 1146 struct dwc3 *dwc = dep->dwc; 1147 1148 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1149 dep->name); 1150 } 1151 } 1152 1153 return 0; 1154} 1155 1156static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1157 gfp_t gfp_flags) 1158{ 1159 struct dwc3_request *req = to_dwc3_request(request); 1160 struct dwc3_ep *dep = to_dwc3_ep(ep); 1161 struct dwc3 *dwc = dep->dwc; 1162 1163 unsigned long flags; 1164 1165 int ret; 1166 1167 if (!dep->endpoint.desc) { 1168 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1169 request, ep->name); 1170 return -ESHUTDOWN; 1171 } 1172 1173 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1174 request, ep->name, request->length); 1175 1176 spin_lock_irqsave(&dwc->lock, flags); 1177 ret = __dwc3_gadget_ep_queue(dep, req); 1178 spin_unlock_irqrestore(&dwc->lock, flags); 1179 1180 return ret; 1181} 1182 1183static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1184 struct usb_request *request) 1185{ 1186 struct dwc3_request *req = to_dwc3_request(request); 1187 struct dwc3_request *r = NULL; 1188 1189 struct dwc3_ep *dep = to_dwc3_ep(ep); 1190 struct dwc3 *dwc = dep->dwc; 1191 1192 unsigned long flags; 1193 int ret = 0; 1194 1195 spin_lock_irqsave(&dwc->lock, flags); 1196 1197 list_for_each_entry(r, &dep->request_list, list) { 1198 if (r == req) 1199 break; 1200 } 1201 1202 if (r != req) { 1203 list_for_each_entry(r, &dep->req_queued, list) { 1204 if (r == req) 1205 break; 1206 } 1207 if (r == req) { 1208 /* wait until it is processed */ 1209 dwc3_stop_active_transfer(dwc, dep->number, true); 1210 goto out1; 1211 } 1212 dev_err(dwc->dev, "request %p was not queued to %s\n", 1213 request, ep->name); 1214 ret = -EINVAL; 1215 goto out0; 1216 } 1217 1218out1: 1219 /* giveback the request */ 1220 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1221 1222out0: 1223 spin_unlock_irqrestore(&dwc->lock, flags); 1224 1225 return ret; 1226} 1227 1228int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1229{ 1230 struct dwc3_gadget_ep_cmd_params params; 1231 struct dwc3 *dwc = dep->dwc; 1232 int ret; 1233 1234 memset(¶ms, 0x00, sizeof(params)); 1235 1236 if (value) { 1237 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1238 DWC3_DEPCMD_SETSTALL, ¶ms); 1239 if (ret) 1240 dev_err(dwc->dev, "failed to set STALL on %s\n", 1241 dep->name); 1242 else 1243 dep->flags |= DWC3_EP_STALL; 1244 } else { 1245 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1246 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1247 if (ret) 1248 dev_err(dwc->dev, "failed to clear STALL on %s\n", 1249 dep->name); 1250 else 1251 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); 1252 } 1253 1254 return ret; 1255} 1256 1257static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1258{ 1259 struct dwc3_ep *dep = to_dwc3_ep(ep); 1260 struct dwc3 *dwc = dep->dwc; 1261 1262 unsigned long flags; 1263 1264 int ret; 1265 1266 spin_lock_irqsave(&dwc->lock, flags); 1267 1268 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1269 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1270 ret = -EINVAL; 1271 goto out; 1272 } 1273 1274 ret = __dwc3_gadget_ep_set_halt(dep, value); 1275out: 1276 spin_unlock_irqrestore(&dwc->lock, flags); 1277 1278 return ret; 1279} 1280 1281static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1282{ 1283 struct dwc3_ep *dep = to_dwc3_ep(ep); 1284 struct dwc3 *dwc = dep->dwc; 1285 unsigned long flags; 1286 1287 spin_lock_irqsave(&dwc->lock, flags); 1288 dep->flags |= DWC3_EP_WEDGE; 1289 spin_unlock_irqrestore(&dwc->lock, flags); 1290 1291 if (dep->number == 0 || dep->number == 1) 1292 return dwc3_gadget_ep0_set_halt(ep, 1); 1293 else 1294 return dwc3_gadget_ep_set_halt(ep, 1); 1295} 1296 1297/* -------------------------------------------------------------------------- */ 1298 1299static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1300 .bLength = USB_DT_ENDPOINT_SIZE, 1301 .bDescriptorType = USB_DT_ENDPOINT, 1302 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1303}; 1304 1305static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1306 .enable = dwc3_gadget_ep0_enable, 1307 .disable = dwc3_gadget_ep0_disable, 1308 .alloc_request = dwc3_gadget_ep_alloc_request, 1309 .free_request = dwc3_gadget_ep_free_request, 1310 .queue = dwc3_gadget_ep0_queue, 1311 .dequeue = dwc3_gadget_ep_dequeue, 1312 .set_halt = dwc3_gadget_ep0_set_halt, 1313 .set_wedge = dwc3_gadget_ep_set_wedge, 1314}; 1315 1316static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1317 .enable = dwc3_gadget_ep_enable, 1318 .disable = dwc3_gadget_ep_disable, 1319 .alloc_request = dwc3_gadget_ep_alloc_request, 1320 .free_request = dwc3_gadget_ep_free_request, 1321 .queue = dwc3_gadget_ep_queue, 1322 .dequeue = dwc3_gadget_ep_dequeue, 1323 .set_halt = dwc3_gadget_ep_set_halt, 1324 .set_wedge = dwc3_gadget_ep_set_wedge, 1325}; 1326 1327/* -------------------------------------------------------------------------- */ 1328 1329static int dwc3_gadget_get_frame(struct usb_gadget *g) 1330{ 1331 struct dwc3 *dwc = gadget_to_dwc(g); 1332 u32 reg; 1333 1334 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1335 return DWC3_DSTS_SOFFN(reg); 1336} 1337 1338static int dwc3_gadget_wakeup(struct usb_gadget *g) 1339{ 1340 struct dwc3 *dwc = gadget_to_dwc(g); 1341 1342 unsigned long timeout; 1343 unsigned long flags; 1344 1345 u32 reg; 1346 1347 int ret = 0; 1348 1349 u8 link_state; 1350 u8 speed; 1351 1352 spin_lock_irqsave(&dwc->lock, flags); 1353 1354 /* 1355 * According to the Databook Remote wakeup request should 1356 * be issued only when the device is in early suspend state. 1357 * 1358 * We can check that via USB Link State bits in DSTS register. 1359 */ 1360 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1361 1362 speed = reg & DWC3_DSTS_CONNECTSPD; 1363 if (speed == DWC3_DSTS_SUPERSPEED) { 1364 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1365 ret = -EINVAL; 1366 goto out; 1367 } 1368 1369 link_state = DWC3_DSTS_USBLNKST(reg); 1370 1371 switch (link_state) { 1372 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1373 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1374 break; 1375 default: 1376 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1377 link_state); 1378 ret = -EINVAL; 1379 goto out; 1380 } 1381 1382 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1383 if (ret < 0) { 1384 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1385 goto out; 1386 } 1387 1388 /* Recent versions do this automatically */ 1389 if (dwc->revision < DWC3_REVISION_194A) { 1390 /* write zeroes to Link Change Request */ 1391 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1392 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1393 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1394 } 1395 1396 /* poll until Link State changes to ON */ 1397 timeout = jiffies + msecs_to_jiffies(100); 1398 1399 while (!time_after(jiffies, timeout)) { 1400 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1401 1402 /* in HS, means ON */ 1403 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1404 break; 1405 } 1406 1407 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1408 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1409 ret = -EINVAL; 1410 } 1411 1412out: 1413 spin_unlock_irqrestore(&dwc->lock, flags); 1414 1415 return ret; 1416} 1417 1418static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1419 int is_selfpowered) 1420{ 1421 struct dwc3 *dwc = gadget_to_dwc(g); 1422 unsigned long flags; 1423 1424 spin_lock_irqsave(&dwc->lock, flags); 1425 dwc->is_selfpowered = !!is_selfpowered; 1426 spin_unlock_irqrestore(&dwc->lock, flags); 1427 1428 return 0; 1429} 1430 1431static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) 1432{ 1433 u32 reg; 1434 u32 timeout = 500; 1435 1436 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1437 if (is_on) { 1438 if (dwc->revision <= DWC3_REVISION_187A) { 1439 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1440 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1441 } 1442 1443 if (dwc->revision >= DWC3_REVISION_194A) 1444 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1445 reg |= DWC3_DCTL_RUN_STOP; 1446 1447 if (dwc->has_hibernation) 1448 reg |= DWC3_DCTL_KEEP_CONNECT; 1449 1450 dwc->pullups_connected = true; 1451 } else { 1452 reg &= ~DWC3_DCTL_RUN_STOP; 1453 1454 if (dwc->has_hibernation && !suspend) 1455 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1456 1457 dwc->pullups_connected = false; 1458 } 1459 1460 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1461 1462 do { 1463 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1464 if (is_on) { 1465 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1466 break; 1467 } else { 1468 if (reg & DWC3_DSTS_DEVCTRLHLT) 1469 break; 1470 } 1471 timeout--; 1472 if (!timeout) 1473 return -ETIMEDOUT; 1474 udelay(1); 1475 } while (1); 1476 1477 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1478 dwc->gadget_driver 1479 ? dwc->gadget_driver->function : "no-function", 1480 is_on ? "connect" : "disconnect"); 1481 1482 return 0; 1483} 1484 1485static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1486{ 1487 struct dwc3 *dwc = gadget_to_dwc(g); 1488 unsigned long flags; 1489 int ret; 1490 1491 is_on = !!is_on; 1492 1493 spin_lock_irqsave(&dwc->lock, flags); 1494 ret = dwc3_gadget_run_stop(dwc, is_on, false); 1495 spin_unlock_irqrestore(&dwc->lock, flags); 1496 1497 return ret; 1498} 1499 1500static void dwc3_gadget_enable_irq(struct dwc3 *dwc) 1501{ 1502 u32 reg; 1503 1504 /* Enable all but Start and End of Frame IRQs */ 1505 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 1506 DWC3_DEVTEN_EVNTOVERFLOWEN | 1507 DWC3_DEVTEN_CMDCMPLTEN | 1508 DWC3_DEVTEN_ERRTICERREN | 1509 DWC3_DEVTEN_WKUPEVTEN | 1510 DWC3_DEVTEN_ULSTCNGEN | 1511 DWC3_DEVTEN_CONNECTDONEEN | 1512 DWC3_DEVTEN_USBRSTEN | 1513 DWC3_DEVTEN_DISCONNEVTEN); 1514 1515 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 1516} 1517 1518static void dwc3_gadget_disable_irq(struct dwc3 *dwc) 1519{ 1520 /* mask all interrupts */ 1521 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 1522} 1523 1524static irqreturn_t dwc3_interrupt(int irq, void *_dwc); 1525static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); 1526 1527static int dwc3_gadget_start(struct usb_gadget *g, 1528 struct usb_gadget_driver *driver) 1529{ 1530 struct dwc3 *dwc = gadget_to_dwc(g); 1531 struct dwc3_ep *dep; 1532 unsigned long flags; 1533 int ret = 0; 1534 int irq; 1535 u32 reg; 1536 1537 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1538 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, 1539 IRQF_SHARED, "dwc3", dwc); 1540 if (ret) { 1541 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 1542 irq, ret); 1543 goto err0; 1544 } 1545 1546 spin_lock_irqsave(&dwc->lock, flags); 1547 1548 if (dwc->gadget_driver) { 1549 dev_err(dwc->dev, "%s is already bound to %s\n", 1550 dwc->gadget.name, 1551 dwc->gadget_driver->driver.name); 1552 ret = -EBUSY; 1553 goto err1; 1554 } 1555 1556 dwc->gadget_driver = driver; 1557 1558 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1559 reg &= ~(DWC3_DCFG_SPEED_MASK); 1560 1561 /** 1562 * WORKAROUND: DWC3 revision < 2.20a have an issue 1563 * which would cause metastability state on Run/Stop 1564 * bit if we try to force the IP to USB2-only mode. 1565 * 1566 * Because of that, we cannot configure the IP to any 1567 * speed other than the SuperSpeed 1568 * 1569 * Refers to: 1570 * 1571 * STAR#9000525659: Clock Domain Crossing on DCTL in 1572 * USB 2.0 Mode 1573 */ 1574 if (dwc->revision < DWC3_REVISION_220A) { 1575 reg |= DWC3_DCFG_SUPERSPEED; 1576 } else { 1577 switch (dwc->maximum_speed) { 1578 case USB_SPEED_LOW: 1579 reg |= DWC3_DSTS_LOWSPEED; 1580 break; 1581 case USB_SPEED_FULL: 1582 reg |= DWC3_DSTS_FULLSPEED1; 1583 break; 1584 case USB_SPEED_HIGH: 1585 reg |= DWC3_DSTS_HIGHSPEED; 1586 break; 1587 case USB_SPEED_SUPER: /* FALLTHROUGH */ 1588 case USB_SPEED_UNKNOWN: /* FALTHROUGH */ 1589 default: 1590 reg |= DWC3_DSTS_SUPERSPEED; 1591 } 1592 } 1593 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1594 1595 dwc->start_config_issued = false; 1596 1597 /* Start with SuperSpeed Default */ 1598 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1599 1600 dep = dwc->eps[0]; 1601 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 1602 false); 1603 if (ret) { 1604 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1605 goto err2; 1606 } 1607 1608 dep = dwc->eps[1]; 1609 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 1610 false); 1611 if (ret) { 1612 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1613 goto err3; 1614 } 1615 1616 /* begin to receive SETUP packets */ 1617 dwc->ep0state = EP0_SETUP_PHASE; 1618 dwc3_ep0_out_start(dwc); 1619 1620 dwc3_gadget_enable_irq(dwc); 1621 1622 spin_unlock_irqrestore(&dwc->lock, flags); 1623 1624 return 0; 1625 1626err3: 1627 __dwc3_gadget_ep_disable(dwc->eps[0]); 1628 1629err2: 1630 dwc->gadget_driver = NULL; 1631 1632err1: 1633 spin_unlock_irqrestore(&dwc->lock, flags); 1634 1635 free_irq(irq, dwc); 1636 1637err0: 1638 return ret; 1639} 1640 1641static int dwc3_gadget_stop(struct usb_gadget *g, 1642 struct usb_gadget_driver *driver) 1643{ 1644 struct dwc3 *dwc = gadget_to_dwc(g); 1645 unsigned long flags; 1646 int irq; 1647 1648 spin_lock_irqsave(&dwc->lock, flags); 1649 1650 dwc3_gadget_disable_irq(dwc); 1651 __dwc3_gadget_ep_disable(dwc->eps[0]); 1652 __dwc3_gadget_ep_disable(dwc->eps[1]); 1653 1654 dwc->gadget_driver = NULL; 1655 1656 spin_unlock_irqrestore(&dwc->lock, flags); 1657 1658 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1659 free_irq(irq, dwc); 1660 1661 return 0; 1662} 1663 1664static const struct usb_gadget_ops dwc3_gadget_ops = { 1665 .get_frame = dwc3_gadget_get_frame, 1666 .wakeup = dwc3_gadget_wakeup, 1667 .set_selfpowered = dwc3_gadget_set_selfpowered, 1668 .pullup = dwc3_gadget_pullup, 1669 .udc_start = dwc3_gadget_start, 1670 .udc_stop = dwc3_gadget_stop, 1671}; 1672 1673/* -------------------------------------------------------------------------- */ 1674 1675static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, 1676 u8 num, u32 direction) 1677{ 1678 struct dwc3_ep *dep; 1679 u8 i; 1680 1681 for (i = 0; i < num; i++) { 1682 u8 epnum = (i << 1) | (!!direction); 1683 1684 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1685 if (!dep) { 1686 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1687 epnum); 1688 return -ENOMEM; 1689 } 1690 1691 dep->dwc = dwc; 1692 dep->number = epnum; 1693 dep->direction = !!direction; 1694 dwc->eps[epnum] = dep; 1695 1696 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1697 (epnum & 1) ? "in" : "out"); 1698 1699 dep->endpoint.name = dep->name; 1700 1701 dev_vdbg(dwc->dev, "initializing %s\n", dep->name); 1702 1703 if (epnum == 0 || epnum == 1) { 1704 usb_ep_set_maxpacket_limit(&dep->endpoint, 512); 1705 dep->endpoint.maxburst = 1; 1706 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1707 if (!epnum) 1708 dwc->gadget.ep0 = &dep->endpoint; 1709 } else { 1710 int ret; 1711 1712 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); 1713 dep->endpoint.max_streams = 15; 1714 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1715 list_add_tail(&dep->endpoint.ep_list, 1716 &dwc->gadget.ep_list); 1717 1718 ret = dwc3_alloc_trb_pool(dep); 1719 if (ret) 1720 return ret; 1721 } 1722 1723 INIT_LIST_HEAD(&dep->request_list); 1724 INIT_LIST_HEAD(&dep->req_queued); 1725 } 1726 1727 return 0; 1728} 1729 1730static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1731{ 1732 int ret; 1733 1734 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1735 1736 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); 1737 if (ret < 0) { 1738 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n"); 1739 return ret; 1740 } 1741 1742 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); 1743 if (ret < 0) { 1744 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n"); 1745 return ret; 1746 } 1747 1748 return 0; 1749} 1750 1751static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1752{ 1753 struct dwc3_ep *dep; 1754 u8 epnum; 1755 1756 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1757 dep = dwc->eps[epnum]; 1758 if (!dep) 1759 continue; 1760 /* 1761 * Physical endpoints 0 and 1 are special; they form the 1762 * bi-directional USB endpoint 0. 1763 * 1764 * For those two physical endpoints, we don't allocate a TRB 1765 * pool nor do we add them the endpoints list. Due to that, we 1766 * shouldn't do these two operations otherwise we would end up 1767 * with all sorts of bugs when removing dwc3.ko. 1768 */ 1769 if (epnum != 0 && epnum != 1) { 1770 dwc3_free_trb_pool(dep); 1771 list_del(&dep->endpoint.ep_list); 1772 } 1773 1774 kfree(dep); 1775 } 1776} 1777 1778/* -------------------------------------------------------------------------- */ 1779 1780static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, 1781 struct dwc3_request *req, struct dwc3_trb *trb, 1782 const struct dwc3_event_depevt *event, int status) 1783{ 1784 unsigned int count; 1785 unsigned int s_pkt = 0; 1786 unsigned int trb_status; 1787 1788 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 1789 /* 1790 * We continue despite the error. There is not much we 1791 * can do. If we don't clean it up we loop forever. If 1792 * we skip the TRB then it gets overwritten after a 1793 * while since we use them in a ring buffer. A BUG() 1794 * would help. Lets hope that if this occurs, someone 1795 * fixes the root cause instead of looking away :) 1796 */ 1797 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1798 dep->name, trb); 1799 count = trb->size & DWC3_TRB_SIZE_MASK; 1800 1801 if (dep->direction) { 1802 if (count) { 1803 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); 1804 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { 1805 dev_dbg(dwc->dev, "incomplete IN transfer %s\n", 1806 dep->name); 1807 /* 1808 * If missed isoc occurred and there is 1809 * no request queued then issue END 1810 * TRANSFER, so that core generates 1811 * next xfernotready and we will issue 1812 * a fresh START TRANSFER. 1813 * If there are still queued request 1814 * then wait, do not issue either END 1815 * or UPDATE TRANSFER, just attach next 1816 * request in request_list during 1817 * giveback.If any future queued request 1818 * is successfully transferred then we 1819 * will issue UPDATE TRANSFER for all 1820 * request in the request_list. 1821 */ 1822 dep->flags |= DWC3_EP_MISSED_ISOC; 1823 } else { 1824 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1825 dep->name); 1826 status = -ECONNRESET; 1827 } 1828 } else { 1829 dep->flags &= ~DWC3_EP_MISSED_ISOC; 1830 } 1831 } else { 1832 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1833 s_pkt = 1; 1834 } 1835 1836 /* 1837 * We assume here we will always receive the entire data block 1838 * which we should receive. Meaning, if we program RX to 1839 * receive 4K but we receive only 2K, we assume that's all we 1840 * should receive and we simply bounce the request back to the 1841 * gadget driver for further processing. 1842 */ 1843 req->request.actual += req->request.length - count; 1844 if (s_pkt) 1845 return 1; 1846 if ((event->status & DEPEVT_STATUS_LST) && 1847 (trb->ctrl & (DWC3_TRB_CTRL_LST | 1848 DWC3_TRB_CTRL_HWO))) 1849 return 1; 1850 if ((event->status & DEPEVT_STATUS_IOC) && 1851 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1852 return 1; 1853 return 0; 1854} 1855 1856static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1857 const struct dwc3_event_depevt *event, int status) 1858{ 1859 struct dwc3_request *req; 1860 struct dwc3_trb *trb; 1861 unsigned int slot; 1862 unsigned int i; 1863 int ret; 1864 1865 do { 1866 req = next_request(&dep->req_queued); 1867 if (!req) { 1868 WARN_ON_ONCE(1); 1869 return 1; 1870 } 1871 i = 0; 1872 do { 1873 slot = req->start_slot + i; 1874 if ((slot == DWC3_TRB_NUM - 1) && 1875 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 1876 slot++; 1877 slot %= DWC3_TRB_NUM; 1878 trb = &dep->trb_pool[slot]; 1879 1880 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, 1881 event, status); 1882 if (ret) 1883 break; 1884 }while (++i < req->request.num_mapped_sgs); 1885 1886 dwc3_gadget_giveback(dep, req, status); 1887 1888 if (ret) 1889 break; 1890 } while (1); 1891 1892 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1893 list_empty(&dep->req_queued)) { 1894 if (list_empty(&dep->request_list)) { 1895 /* 1896 * If there is no entry in request list then do 1897 * not issue END TRANSFER now. Just set PENDING 1898 * flag, so that END TRANSFER is issued when an 1899 * entry is added into request list. 1900 */ 1901 dep->flags = DWC3_EP_PENDING_REQUEST; 1902 } else { 1903 dwc3_stop_active_transfer(dwc, dep->number, true); 1904 dep->flags = DWC3_EP_ENABLED; 1905 } 1906 return 1; 1907 } 1908 1909 return 1; 1910} 1911 1912static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1913 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1914 int start_new) 1915{ 1916 unsigned status = 0; 1917 int clean_busy; 1918 1919 if (event->status & DEPEVT_STATUS_BUSERR) 1920 status = -ECONNRESET; 1921 1922 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1923 if (clean_busy) 1924 dep->flags &= ~DWC3_EP_BUSY; 1925 1926 /* 1927 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1928 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1929 */ 1930 if (dwc->revision < DWC3_REVISION_183A) { 1931 u32 reg; 1932 int i; 1933 1934 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1935 dep = dwc->eps[i]; 1936 1937 if (!(dep->flags & DWC3_EP_ENABLED)) 1938 continue; 1939 1940 if (!list_empty(&dep->req_queued)) 1941 return; 1942 } 1943 1944 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1945 reg |= dwc->u1u2; 1946 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1947 1948 dwc->u1u2 = 0; 1949 } 1950} 1951 1952static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1953 const struct dwc3_event_depevt *event) 1954{ 1955 struct dwc3_ep *dep; 1956 u8 epnum = event->endpoint_number; 1957 1958 dep = dwc->eps[epnum]; 1959 1960 if (!(dep->flags & DWC3_EP_ENABLED)) 1961 return; 1962 1963 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1964 dwc3_ep_event_string(event->endpoint_event)); 1965 1966 if (epnum == 0 || epnum == 1) { 1967 dwc3_ep0_interrupt(dwc, event); 1968 return; 1969 } 1970 1971 switch (event->endpoint_event) { 1972 case DWC3_DEPEVT_XFERCOMPLETE: 1973 dep->resource_index = 0; 1974 1975 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1976 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1977 dep->name); 1978 return; 1979 } 1980 1981 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1982 break; 1983 case DWC3_DEPEVT_XFERINPROGRESS: 1984 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1985 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1986 dep->name); 1987 return; 1988 } 1989 1990 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1991 break; 1992 case DWC3_DEPEVT_XFERNOTREADY: 1993 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1994 dwc3_gadget_start_isoc(dwc, dep, event); 1995 } else { 1996 int ret; 1997 1998 dev_vdbg(dwc->dev, "%s: reason %s\n", 1999 dep->name, event->status & 2000 DEPEVT_STATUS_TRANSFER_ACTIVE 2001 ? "Transfer Active" 2002 : "Transfer Not Active"); 2003 2004 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 2005 if (!ret || ret == -EBUSY) 2006 return; 2007 2008 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 2009 dep->name); 2010 } 2011 2012 break; 2013 case DWC3_DEPEVT_STREAMEVT: 2014 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { 2015 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 2016 dep->name); 2017 return; 2018 } 2019 2020 switch (event->status) { 2021 case DEPEVT_STREAMEVT_FOUND: 2022 dev_vdbg(dwc->dev, "Stream %d found and started\n", 2023 event->parameters); 2024 2025 break; 2026 case DEPEVT_STREAMEVT_NOTFOUND: 2027 /* FALLTHROUGH */ 2028 default: 2029 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 2030 } 2031 break; 2032 case DWC3_DEPEVT_RXTXFIFOEVT: 2033 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 2034 break; 2035 case DWC3_DEPEVT_EPCMDCMPLT: 2036 dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); 2037 break; 2038 } 2039} 2040 2041static void dwc3_disconnect_gadget(struct dwc3 *dwc) 2042{ 2043 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 2044 spin_unlock(&dwc->lock); 2045 dwc->gadget_driver->disconnect(&dwc->gadget); 2046 spin_lock(&dwc->lock); 2047 } 2048} 2049 2050static void dwc3_suspend_gadget(struct dwc3 *dwc) 2051{ 2052 if (dwc->gadget_driver && dwc->gadget_driver->suspend) { 2053 spin_unlock(&dwc->lock); 2054 dwc->gadget_driver->suspend(&dwc->gadget); 2055 spin_lock(&dwc->lock); 2056 } 2057} 2058 2059static void dwc3_resume_gadget(struct dwc3 *dwc) 2060{ 2061 if (dwc->gadget_driver && dwc->gadget_driver->resume) { 2062 spin_unlock(&dwc->lock); 2063 dwc->gadget_driver->resume(&dwc->gadget); 2064 spin_lock(&dwc->lock); 2065 } 2066} 2067 2068static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) 2069{ 2070 struct dwc3_ep *dep; 2071 struct dwc3_gadget_ep_cmd_params params; 2072 u32 cmd; 2073 int ret; 2074 2075 dep = dwc->eps[epnum]; 2076 2077 if (!dep->resource_index) 2078 return; 2079 2080 /* 2081 * NOTICE: We are violating what the Databook says about the 2082 * EndTransfer command. Ideally we would _always_ wait for the 2083 * EndTransfer Command Completion IRQ, but that's causing too 2084 * much trouble synchronizing between us and gadget driver. 2085 * 2086 * We have discussed this with the IP Provider and it was 2087 * suggested to giveback all requests here, but give HW some 2088 * extra time to synchronize with the interconnect. We're using 2089 * an arbitraty 100us delay for that. 2090 * 2091 * Note also that a similar handling was tested by Synopsys 2092 * (thanks a lot Paul) and nothing bad has come out of it. 2093 * In short, what we're doing is: 2094 * 2095 * - Issue EndTransfer WITH CMDIOC bit set 2096 * - Wait 100us 2097 */ 2098 2099 cmd = DWC3_DEPCMD_ENDTRANSFER; 2100 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; 2101 cmd |= DWC3_DEPCMD_CMDIOC; 2102 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 2103 memset(¶ms, 0, sizeof(params)); 2104 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 2105 WARN_ON_ONCE(ret); 2106 dep->resource_index = 0; 2107 dep->flags &= ~DWC3_EP_BUSY; 2108 udelay(100); 2109} 2110 2111static void dwc3_stop_active_transfers(struct dwc3 *dwc) 2112{ 2113 u32 epnum; 2114 2115 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2116 struct dwc3_ep *dep; 2117 2118 dep = dwc->eps[epnum]; 2119 if (!dep) 2120 continue; 2121 2122 if (!(dep->flags & DWC3_EP_ENABLED)) 2123 continue; 2124 2125 dwc3_remove_requests(dwc, dep); 2126 } 2127} 2128 2129static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 2130{ 2131 u32 epnum; 2132 2133 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2134 struct dwc3_ep *dep; 2135 struct dwc3_gadget_ep_cmd_params params; 2136 int ret; 2137 2138 dep = dwc->eps[epnum]; 2139 if (!dep) 2140 continue; 2141 2142 if (!(dep->flags & DWC3_EP_STALL)) 2143 continue; 2144 2145 dep->flags &= ~DWC3_EP_STALL; 2146 2147 memset(¶ms, 0, sizeof(params)); 2148 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 2149 DWC3_DEPCMD_CLEARSTALL, ¶ms); 2150 WARN_ON_ONCE(ret); 2151 } 2152} 2153 2154static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 2155{ 2156 int reg; 2157 2158 dev_vdbg(dwc->dev, "%s\n", __func__); 2159 2160 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2161 reg &= ~DWC3_DCTL_INITU1ENA; 2162 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2163 2164 reg &= ~DWC3_DCTL_INITU2ENA; 2165 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2166 2167 dwc3_disconnect_gadget(dwc); 2168 dwc->start_config_issued = false; 2169 2170 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2171 dwc->setup_packet_pending = false; 2172} 2173 2174static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 2175{ 2176 u32 reg; 2177 2178 dev_vdbg(dwc->dev, "%s\n", __func__); 2179 2180 /* 2181 * WORKAROUND: DWC3 revisions <1.88a have an issue which 2182 * would cause a missing Disconnect Event if there's a 2183 * pending Setup Packet in the FIFO. 2184 * 2185 * There's no suggested workaround on the official Bug 2186 * report, which states that "unless the driver/application 2187 * is doing any special handling of a disconnect event, 2188 * there is no functional issue". 2189 * 2190 * Unfortunately, it turns out that we _do_ some special 2191 * handling of a disconnect event, namely complete all 2192 * pending transfers, notify gadget driver of the 2193 * disconnection, and so on. 2194 * 2195 * Our suggested workaround is to follow the Disconnect 2196 * Event steps here, instead, based on a setup_packet_pending 2197 * flag. Such flag gets set whenever we have a XferNotReady 2198 * event on EP0 and gets cleared on XferComplete for the 2199 * same endpoint. 2200 * 2201 * Refers to: 2202 * 2203 * STAR#9000466709: RTL: Device : Disconnect event not 2204 * generated if setup packet pending in FIFO 2205 */ 2206 if (dwc->revision < DWC3_REVISION_188A) { 2207 if (dwc->setup_packet_pending) 2208 dwc3_gadget_disconnect_interrupt(dwc); 2209 } 2210 2211 /* after reset -> Default State */ 2212 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 2213 2214 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 2215 dwc3_disconnect_gadget(dwc); 2216 2217 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2218 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2219 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2220 dwc->test_mode = false; 2221 2222 dwc3_stop_active_transfers(dwc); 2223 dwc3_clear_stall_all_ep(dwc); 2224 dwc->start_config_issued = false; 2225 2226 /* Reset device address to zero */ 2227 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2228 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2229 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2230} 2231 2232static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 2233{ 2234 u32 reg; 2235 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 2236 2237 /* 2238 * We change the clock only at SS but I dunno why I would want to do 2239 * this. Maybe it becomes part of the power saving plan. 2240 */ 2241 2242 if (speed != DWC3_DSTS_SUPERSPEED) 2243 return; 2244 2245 /* 2246 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2247 * each time on Connect Done. 2248 */ 2249 if (!usb30_clock) 2250 return; 2251 2252 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 2253 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 2254 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 2255} 2256 2257static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2258{ 2259 struct dwc3_ep *dep; 2260 int ret; 2261 u32 reg; 2262 u8 speed; 2263 2264 dev_vdbg(dwc->dev, "%s\n", __func__); 2265 2266 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2267 speed = reg & DWC3_DSTS_CONNECTSPD; 2268 dwc->speed = speed; 2269 2270 dwc3_update_ram_clk_sel(dwc, speed); 2271 2272 switch (speed) { 2273 case DWC3_DCFG_SUPERSPEED: 2274 /* 2275 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2276 * would cause a missing USB3 Reset event. 2277 * 2278 * In such situations, we should force a USB3 Reset 2279 * event by calling our dwc3_gadget_reset_interrupt() 2280 * routine. 2281 * 2282 * Refers to: 2283 * 2284 * STAR#9000483510: RTL: SS : USB3 reset event may 2285 * not be generated always when the link enters poll 2286 */ 2287 if (dwc->revision < DWC3_REVISION_190A) 2288 dwc3_gadget_reset_interrupt(dwc); 2289 2290 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2291 dwc->gadget.ep0->maxpacket = 512; 2292 dwc->gadget.speed = USB_SPEED_SUPER; 2293 break; 2294 case DWC3_DCFG_HIGHSPEED: 2295 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2296 dwc->gadget.ep0->maxpacket = 64; 2297 dwc->gadget.speed = USB_SPEED_HIGH; 2298 break; 2299 case DWC3_DCFG_FULLSPEED2: 2300 case DWC3_DCFG_FULLSPEED1: 2301 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2302 dwc->gadget.ep0->maxpacket = 64; 2303 dwc->gadget.speed = USB_SPEED_FULL; 2304 break; 2305 case DWC3_DCFG_LOWSPEED: 2306 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2307 dwc->gadget.ep0->maxpacket = 8; 2308 dwc->gadget.speed = USB_SPEED_LOW; 2309 break; 2310 } 2311 2312 /* Enable USB2 LPM Capability */ 2313 2314 if ((dwc->revision > DWC3_REVISION_194A) 2315 && (speed != DWC3_DCFG_SUPERSPEED)) { 2316 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2317 reg |= DWC3_DCFG_LPM_CAP; 2318 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2319 2320 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2321 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2322 2323 /* 2324 * TODO: This should be configurable. For now using 2325 * maximum allowed HIRD threshold value of 0b1100 2326 */ 2327 reg |= DWC3_DCTL_HIRD_THRES(12); 2328 2329 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2330 } else { 2331 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2332 reg &= ~DWC3_DCTL_HIRD_THRES_MASK; 2333 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2334 } 2335 2336 dep = dwc->eps[0]; 2337 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, 2338 false); 2339 if (ret) { 2340 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2341 return; 2342 } 2343 2344 dep = dwc->eps[1]; 2345 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, 2346 false); 2347 if (ret) { 2348 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2349 return; 2350 } 2351 2352 /* 2353 * Configure PHY via GUSB3PIPECTLn if required. 2354 * 2355 * Update GTXFIFOSIZn 2356 * 2357 * In both cases reset values should be sufficient. 2358 */ 2359} 2360 2361static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2362{ 2363 dev_vdbg(dwc->dev, "%s\n", __func__); 2364 2365 /* 2366 * TODO take core out of low power mode when that's 2367 * implemented. 2368 */ 2369 2370 dwc->gadget_driver->resume(&dwc->gadget); 2371} 2372 2373static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2374 unsigned int evtinfo) 2375{ 2376 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2377 unsigned int pwropt; 2378 2379 /* 2380 * WORKAROUND: DWC3 < 2.50a have an issue when configured without 2381 * Hibernation mode enabled which would show up when device detects 2382 * host-initiated U3 exit. 2383 * 2384 * In that case, device will generate a Link State Change Interrupt 2385 * from U3 to RESUME which is only necessary if Hibernation is 2386 * configured in. 2387 * 2388 * There are no functional changes due to such spurious event and we 2389 * just need to ignore it. 2390 * 2391 * Refers to: 2392 * 2393 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation 2394 * operational mode 2395 */ 2396 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 2397 if ((dwc->revision < DWC3_REVISION_250A) && 2398 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { 2399 if ((dwc->link_state == DWC3_LINK_STATE_U3) && 2400 (next == DWC3_LINK_STATE_RESUME)) { 2401 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n"); 2402 return; 2403 } 2404 } 2405 2406 /* 2407 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2408 * on the link partner, the USB session might do multiple entry/exit 2409 * of low power states before a transfer takes place. 2410 * 2411 * Due to this problem, we might experience lower throughput. The 2412 * suggested workaround is to disable DCTL[12:9] bits if we're 2413 * transitioning from U1/U2 to U0 and enable those bits again 2414 * after a transfer completes and there are no pending transfers 2415 * on any of the enabled endpoints. 2416 * 2417 * This is the first half of that workaround. 2418 * 2419 * Refers to: 2420 * 2421 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2422 * core send LGO_Ux entering U0 2423 */ 2424 if (dwc->revision < DWC3_REVISION_183A) { 2425 if (next == DWC3_LINK_STATE_U0) { 2426 u32 u1u2; 2427 u32 reg; 2428 2429 switch (dwc->link_state) { 2430 case DWC3_LINK_STATE_U1: 2431 case DWC3_LINK_STATE_U2: 2432 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2433 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2434 | DWC3_DCTL_ACCEPTU2ENA 2435 | DWC3_DCTL_INITU1ENA 2436 | DWC3_DCTL_ACCEPTU1ENA); 2437 2438 if (!dwc->u1u2) 2439 dwc->u1u2 = reg & u1u2; 2440 2441 reg &= ~u1u2; 2442 2443 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2444 break; 2445 default: 2446 /* do nothing */ 2447 break; 2448 } 2449 } 2450 } 2451 2452 dwc->link_state = next; 2453 2454 switch (next) { 2455 case DWC3_LINK_STATE_U1: 2456 if (dwc->speed == USB_SPEED_SUPER) 2457 dwc3_suspend_gadget(dwc); 2458 break; 2459 case DWC3_LINK_STATE_U2: 2460 case DWC3_LINK_STATE_U3: 2461 dwc3_suspend_gadget(dwc); 2462 break; 2463 case DWC3_LINK_STATE_RESUME: 2464 dwc3_resume_gadget(dwc); 2465 break; 2466 default: 2467 /* do nothing */ 2468 break; 2469 } 2470 2471 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 2472} 2473 2474static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, 2475 unsigned int evtinfo) 2476{ 2477 unsigned int is_ss = evtinfo & BIT(4); 2478 2479 /** 2480 * WORKAROUND: DWC3 revison 2.20a with hibernation support 2481 * have a known issue which can cause USB CV TD.9.23 to fail 2482 * randomly. 2483 * 2484 * Because of this issue, core could generate bogus hibernation 2485 * events which SW needs to ignore. 2486 * 2487 * Refers to: 2488 * 2489 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 2490 * Device Fallback from SuperSpeed 2491 */ 2492 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) 2493 return; 2494 2495 /* enter hibernation here */ 2496} 2497 2498static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2499 const struct dwc3_event_devt *event) 2500{ 2501 switch (event->type) { 2502 case DWC3_DEVICE_EVENT_DISCONNECT: 2503 dwc3_gadget_disconnect_interrupt(dwc); 2504 break; 2505 case DWC3_DEVICE_EVENT_RESET: 2506 dwc3_gadget_reset_interrupt(dwc); 2507 break; 2508 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2509 dwc3_gadget_conndone_interrupt(dwc); 2510 break; 2511 case DWC3_DEVICE_EVENT_WAKEUP: 2512 dwc3_gadget_wakeup_interrupt(dwc); 2513 break; 2514 case DWC3_DEVICE_EVENT_HIBER_REQ: 2515 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, 2516 "unexpected hibernation event\n")) 2517 break; 2518 2519 dwc3_gadget_hibernation_interrupt(dwc, event->event_info); 2520 break; 2521 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2522 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2523 break; 2524 case DWC3_DEVICE_EVENT_EOPF: 2525 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2526 break; 2527 case DWC3_DEVICE_EVENT_SOF: 2528 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2529 break; 2530 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2531 dev_vdbg(dwc->dev, "Erratic Error\n"); 2532 break; 2533 case DWC3_DEVICE_EVENT_CMD_CMPL: 2534 dev_vdbg(dwc->dev, "Command Complete\n"); 2535 break; 2536 case DWC3_DEVICE_EVENT_OVERFLOW: 2537 dev_vdbg(dwc->dev, "Overflow\n"); 2538 break; 2539 default: 2540 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2541 } 2542} 2543 2544static void dwc3_process_event_entry(struct dwc3 *dwc, 2545 const union dwc3_event *event) 2546{ 2547 /* Endpoint IRQ, handle it and return early */ 2548 if (event->type.is_devspec == 0) { 2549 /* depevt */ 2550 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2551 } 2552 2553 switch (event->type.type) { 2554 case DWC3_EVENT_TYPE_DEV: 2555 dwc3_gadget_interrupt(dwc, &event->devt); 2556 break; 2557 /* REVISIT what to do with Carkit and I2C events ? */ 2558 default: 2559 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2560 } 2561} 2562 2563static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2564{ 2565 struct dwc3_event_buffer *evt; 2566 irqreturn_t ret = IRQ_NONE; 2567 int left; 2568 u32 reg; 2569 2570 evt = dwc->ev_buffs[buf]; 2571 left = evt->count; 2572 2573 if (!(evt->flags & DWC3_EVENT_PENDING)) 2574 return IRQ_NONE; 2575 2576 while (left > 0) { 2577 union dwc3_event event; 2578 2579 event.raw = *(u32 *) (evt->buf + evt->lpos); 2580 2581 dwc3_process_event_entry(dwc, &event); 2582 2583 /* 2584 * FIXME we wrap around correctly to the next entry as 2585 * almost all entries are 4 bytes in size. There is one 2586 * entry which has 12 bytes which is a regular entry 2587 * followed by 8 bytes data. ATM I don't know how 2588 * things are organized if we get next to the a 2589 * boundary so I worry about that once we try to handle 2590 * that. 2591 */ 2592 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2593 left -= 4; 2594 2595 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2596 } 2597 2598 evt->count = 0; 2599 evt->flags &= ~DWC3_EVENT_PENDING; 2600 ret = IRQ_HANDLED; 2601 2602 /* Unmask interrupt */ 2603 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); 2604 reg &= ~DWC3_GEVNTSIZ_INTMASK; 2605 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); 2606 2607 return ret; 2608} 2609 2610static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) 2611{ 2612 struct dwc3 *dwc = _dwc; 2613 unsigned long flags; 2614 irqreturn_t ret = IRQ_NONE; 2615 int i; 2616 2617 spin_lock_irqsave(&dwc->lock, flags); 2618 2619 for (i = 0; i < dwc->num_event_buffers; i++) 2620 ret |= dwc3_process_event_buf(dwc, i); 2621 2622 spin_unlock_irqrestore(&dwc->lock, flags); 2623 2624 return ret; 2625} 2626 2627static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) 2628{ 2629 struct dwc3_event_buffer *evt; 2630 u32 count; 2631 u32 reg; 2632 2633 evt = dwc->ev_buffs[buf]; 2634 2635 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2636 count &= DWC3_GEVNTCOUNT_MASK; 2637 if (!count) 2638 return IRQ_NONE; 2639 2640 evt->count = count; 2641 evt->flags |= DWC3_EVENT_PENDING; 2642 2643 /* Mask interrupt */ 2644 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); 2645 reg |= DWC3_GEVNTSIZ_INTMASK; 2646 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); 2647 2648 return IRQ_WAKE_THREAD; 2649} 2650 2651static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2652{ 2653 struct dwc3 *dwc = _dwc; 2654 int i; 2655 irqreturn_t ret = IRQ_NONE; 2656 2657 spin_lock(&dwc->lock); 2658 2659 for (i = 0; i < dwc->num_event_buffers; i++) { 2660 irqreturn_t status; 2661 2662 status = dwc3_check_event_buf(dwc, i); 2663 if (status == IRQ_WAKE_THREAD) 2664 ret = status; 2665 } 2666 2667 spin_unlock(&dwc->lock); 2668 2669 return ret; 2670} 2671 2672/** 2673 * dwc3_gadget_init - Initializes gadget related registers 2674 * @dwc: pointer to our controller context structure 2675 * 2676 * Returns 0 on success otherwise negative errno. 2677 */ 2678int dwc3_gadget_init(struct dwc3 *dwc) 2679{ 2680 int ret; 2681 2682 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2683 &dwc->ctrl_req_addr, GFP_KERNEL); 2684 if (!dwc->ctrl_req) { 2685 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2686 ret = -ENOMEM; 2687 goto err0; 2688 } 2689 2690 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2691 &dwc->ep0_trb_addr, GFP_KERNEL); 2692 if (!dwc->ep0_trb) { 2693 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2694 ret = -ENOMEM; 2695 goto err1; 2696 } 2697 2698 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); 2699 if (!dwc->setup_buf) { 2700 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2701 ret = -ENOMEM; 2702 goto err2; 2703 } 2704 2705 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2706 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, 2707 GFP_KERNEL); 2708 if (!dwc->ep0_bounce) { 2709 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2710 ret = -ENOMEM; 2711 goto err3; 2712 } 2713 2714 dwc->gadget.ops = &dwc3_gadget_ops; 2715 dwc->gadget.max_speed = USB_SPEED_SUPER; 2716 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2717 dwc->gadget.sg_supported = true; 2718 dwc->gadget.name = "dwc3-gadget"; 2719 2720 /* 2721 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize 2722 * on ep out. 2723 */ 2724 dwc->gadget.quirk_ep_out_aligned_size = true; 2725 2726 /* 2727 * REVISIT: Here we should clear all pending IRQs to be 2728 * sure we're starting from a well known location. 2729 */ 2730 2731 ret = dwc3_gadget_init_endpoints(dwc); 2732 if (ret) 2733 goto err4; 2734 2735 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2736 if (ret) { 2737 dev_err(dwc->dev, "failed to register udc\n"); 2738 goto err4; 2739 } 2740 2741 return 0; 2742 2743err4: 2744 dwc3_gadget_free_endpoints(dwc); 2745 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2746 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2747 2748err3: 2749 kfree(dwc->setup_buf); 2750 2751err2: 2752 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2753 dwc->ep0_trb, dwc->ep0_trb_addr); 2754 2755err1: 2756 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2757 dwc->ctrl_req, dwc->ctrl_req_addr); 2758 2759err0: 2760 return ret; 2761} 2762 2763/* -------------------------------------------------------------------------- */ 2764 2765void dwc3_gadget_exit(struct dwc3 *dwc) 2766{ 2767 usb_del_gadget_udc(&dwc->gadget); 2768 2769 dwc3_gadget_free_endpoints(dwc); 2770 2771 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2772 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2773 2774 kfree(dwc->setup_buf); 2775 2776 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2777 dwc->ep0_trb, dwc->ep0_trb_addr); 2778 2779 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2780 dwc->ctrl_req, dwc->ctrl_req_addr); 2781} 2782 2783int dwc3_gadget_prepare(struct dwc3 *dwc) 2784{ 2785 if (dwc->pullups_connected) { 2786 dwc3_gadget_disable_irq(dwc); 2787 dwc3_gadget_run_stop(dwc, true, true); 2788 } 2789 2790 return 0; 2791} 2792 2793void dwc3_gadget_complete(struct dwc3 *dwc) 2794{ 2795 if (dwc->pullups_connected) { 2796 dwc3_gadget_enable_irq(dwc); 2797 dwc3_gadget_run_stop(dwc, true, false); 2798 } 2799} 2800 2801int dwc3_gadget_suspend(struct dwc3 *dwc) 2802{ 2803 __dwc3_gadget_ep_disable(dwc->eps[0]); 2804 __dwc3_gadget_ep_disable(dwc->eps[1]); 2805 2806 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); 2807 2808 return 0; 2809} 2810 2811int dwc3_gadget_resume(struct dwc3 *dwc) 2812{ 2813 struct dwc3_ep *dep; 2814 int ret; 2815 2816 /* Start with SuperSpeed Default */ 2817 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2818 2819 dep = dwc->eps[0]; 2820 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 2821 false); 2822 if (ret) 2823 goto err0; 2824 2825 dep = dwc->eps[1]; 2826 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 2827 false); 2828 if (ret) 2829 goto err1; 2830 2831 /* begin to receive SETUP packets */ 2832 dwc->ep0state = EP0_SETUP_PHASE; 2833 dwc3_ep0_out_start(dwc); 2834 2835 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); 2836 2837 return 0; 2838 2839err1: 2840 __dwc3_gadget_ep_disable(dwc->eps[0]); 2841 2842err0: 2843 return ret; 2844} 2845