gadget.c revision b997ada5db905e24494bcc689c7b2c07d278ca27
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#include <linux/kernel.h> 20#include <linux/delay.h> 21#include <linux/slab.h> 22#include <linux/spinlock.h> 23#include <linux/platform_device.h> 24#include <linux/pm_runtime.h> 25#include <linux/interrupt.h> 26#include <linux/io.h> 27#include <linux/list.h> 28#include <linux/dma-mapping.h> 29 30#include <linux/usb/ch9.h> 31#include <linux/usb/gadget.h> 32 33#include "core.h" 34#include "gadget.h" 35#include "io.h" 36 37/** 38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 39 * @dwc: pointer to our context structure 40 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 41 * 42 * Caller should take care of locking. This function will 43 * return 0 on success or -EINVAL if wrong Test Selector 44 * is passed 45 */ 46int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 47{ 48 u32 reg; 49 50 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 51 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 52 53 switch (mode) { 54 case TEST_J: 55 case TEST_K: 56 case TEST_SE0_NAK: 57 case TEST_PACKET: 58 case TEST_FORCE_EN: 59 reg |= mode << 1; 60 break; 61 default: 62 return -EINVAL; 63 } 64 65 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 66 67 return 0; 68} 69 70/** 71 * dwc3_gadget_get_link_state - Gets current state of USB Link 72 * @dwc: pointer to our context structure 73 * 74 * Caller should take care of locking. This function will 75 * return the link state on success (>= 0) or -ETIMEDOUT. 76 */ 77int dwc3_gadget_get_link_state(struct dwc3 *dwc) 78{ 79 u32 reg; 80 81 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 82 83 return DWC3_DSTS_USBLNKST(reg); 84} 85 86/** 87 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 88 * @dwc: pointer to our context structure 89 * @state: the state to put link into 90 * 91 * Caller should take care of locking. This function will 92 * return 0 on success or -ETIMEDOUT. 93 */ 94int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 95{ 96 int retries = 10000; 97 u32 reg; 98 99 /* 100 * Wait until device controller is ready. Only applies to 1.94a and 101 * later RTL. 102 */ 103 if (dwc->revision >= DWC3_REVISION_194A) { 104 while (--retries) { 105 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 106 if (reg & DWC3_DSTS_DCNRD) 107 udelay(5); 108 else 109 break; 110 } 111 112 if (retries <= 0) 113 return -ETIMEDOUT; 114 } 115 116 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 118 119 /* set requested state */ 120 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 121 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 122 123 /* 124 * The following code is racy when called from dwc3_gadget_wakeup, 125 * and is not needed, at least on newer versions 126 */ 127 if (dwc->revision >= DWC3_REVISION_194A) 128 return 0; 129 130 /* wait for a change in DSTS */ 131 retries = 10000; 132 while (--retries) { 133 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 134 135 if (DWC3_DSTS_USBLNKST(reg) == state) 136 return 0; 137 138 udelay(5); 139 } 140 141 dev_vdbg(dwc->dev, "link state change request timed out\n"); 142 143 return -ETIMEDOUT; 144} 145 146/** 147 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 148 * @dwc: pointer to our context structure 149 * 150 * This function will a best effort FIFO allocation in order 151 * to improve FIFO usage and throughput, while still allowing 152 * us to enable as many endpoints as possible. 153 * 154 * Keep in mind that this operation will be highly dependent 155 * on the configured size for RAM1 - which contains TxFifo -, 156 * the amount of endpoints enabled on coreConsultant tool, and 157 * the width of the Master Bus. 158 * 159 * In the ideal world, we would always be able to satisfy the 160 * following equation: 161 * 162 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 163 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 164 * 165 * Unfortunately, due to many variables that's not always the case. 166 */ 167int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 168{ 169 int last_fifo_depth = 0; 170 int ram1_depth; 171 int fifo_size; 172 int mdwidth; 173 int num; 174 175 if (!dwc->needs_fifo_resize) 176 return 0; 177 178 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 179 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 180 181 /* MDWIDTH is represented in bits, we need it in bytes */ 182 mdwidth >>= 3; 183 184 /* 185 * FIXME For now we will only allocate 1 wMaxPacketSize space 186 * for each enabled endpoint, later patches will come to 187 * improve this algorithm so that we better use the internal 188 * FIFO space 189 */ 190 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { 191 struct dwc3_ep *dep = dwc->eps[num]; 192 int fifo_number = dep->number >> 1; 193 int mult = 1; 194 int tmp; 195 196 if (!(dep->number & 1)) 197 continue; 198 199 if (!(dep->flags & DWC3_EP_ENABLED)) 200 continue; 201 202 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) 203 || usb_endpoint_xfer_isoc(dep->endpoint.desc)) 204 mult = 3; 205 206 /* 207 * REVISIT: the following assumes we will always have enough 208 * space available on the FIFO RAM for all possible use cases. 209 * Make sure that's true somehow and change FIFO allocation 210 * accordingly. 211 * 212 * If we have Bulk or Isochronous endpoints, we want 213 * them to be able to be very, very fast. So we're giving 214 * those endpoints a fifo_size which is enough for 3 full 215 * packets 216 */ 217 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 218 tmp += mdwidth; 219 220 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 221 222 fifo_size |= (last_fifo_depth << 16); 223 224 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 225 dep->name, last_fifo_depth, fifo_size & 0xffff); 226 227 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), 228 fifo_size); 229 230 last_fifo_depth += (fifo_size & 0xffff); 231 } 232 233 return 0; 234} 235 236void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 237 int status) 238{ 239 struct dwc3 *dwc = dep->dwc; 240 int i; 241 242 if (req->queued) { 243 i = 0; 244 do { 245 dep->busy_slot++; 246 /* 247 * Skip LINK TRB. We can't use req->trb and check for 248 * DWC3_TRBCTL_LINK_TRB because it points the TRB we 249 * just completed (not the LINK TRB). 250 */ 251 if (((dep->busy_slot & DWC3_TRB_MASK) == 252 DWC3_TRB_NUM- 1) && 253 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 254 dep->busy_slot++; 255 } while(++i < req->request.num_mapped_sgs); 256 req->queued = false; 257 } 258 list_del(&req->list); 259 req->trb = NULL; 260 261 if (req->request.status == -EINPROGRESS) 262 req->request.status = status; 263 264 if (dwc->ep0_bounced && dep->number == 0) 265 dwc->ep0_bounced = false; 266 else 267 usb_gadget_unmap_request(&dwc->gadget, &req->request, 268 req->direction); 269 270 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 271 req, dep->name, req->request.actual, 272 req->request.length, status); 273 274 spin_unlock(&dwc->lock); 275 req->request.complete(&dep->endpoint, &req->request); 276 spin_lock(&dwc->lock); 277} 278 279static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 280{ 281 switch (cmd) { 282 case DWC3_DEPCMD_DEPSTARTCFG: 283 return "Start New Configuration"; 284 case DWC3_DEPCMD_ENDTRANSFER: 285 return "End Transfer"; 286 case DWC3_DEPCMD_UPDATETRANSFER: 287 return "Update Transfer"; 288 case DWC3_DEPCMD_STARTTRANSFER: 289 return "Start Transfer"; 290 case DWC3_DEPCMD_CLEARSTALL: 291 return "Clear Stall"; 292 case DWC3_DEPCMD_SETSTALL: 293 return "Set Stall"; 294 case DWC3_DEPCMD_GETEPSTATE: 295 return "Get Endpoint State"; 296 case DWC3_DEPCMD_SETTRANSFRESOURCE: 297 return "Set Endpoint Transfer Resource"; 298 case DWC3_DEPCMD_SETEPCONFIG: 299 return "Set Endpoint Configuration"; 300 default: 301 return "UNKNOWN command"; 302 } 303} 304 305int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) 306{ 307 u32 timeout = 500; 308 u32 reg; 309 310 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 311 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 312 313 do { 314 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 315 if (!(reg & DWC3_DGCMD_CMDACT)) { 316 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 317 DWC3_DGCMD_STATUS(reg)); 318 return 0; 319 } 320 321 /* 322 * We can't sleep here, because it's also called from 323 * interrupt context. 324 */ 325 timeout--; 326 if (!timeout) 327 return -ETIMEDOUT; 328 udelay(1); 329 } while (1); 330} 331 332int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 333 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 334{ 335 struct dwc3_ep *dep = dwc->eps[ep]; 336 u32 timeout = 500; 337 u32 reg; 338 339 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 340 dep->name, 341 dwc3_gadget_ep_cmd_string(cmd), params->param0, 342 params->param1, params->param2); 343 344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 346 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 347 348 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 349 do { 350 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 351 if (!(reg & DWC3_DEPCMD_CMDACT)) { 352 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 353 DWC3_DEPCMD_STATUS(reg)); 354 return 0; 355 } 356 357 /* 358 * We can't sleep here, because it is also called from 359 * interrupt context. 360 */ 361 timeout--; 362 if (!timeout) 363 return -ETIMEDOUT; 364 365 udelay(1); 366 } while (1); 367} 368 369static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 370 struct dwc3_trb *trb) 371{ 372 u32 offset = (char *) trb - (char *) dep->trb_pool; 373 374 return dep->trb_pool_dma + offset; 375} 376 377static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 378{ 379 struct dwc3 *dwc = dep->dwc; 380 381 if (dep->trb_pool) 382 return 0; 383 384 if (dep->number == 0 || dep->number == 1) 385 return 0; 386 387 dep->trb_pool = dma_alloc_coherent(dwc->dev, 388 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 389 &dep->trb_pool_dma, GFP_KERNEL); 390 if (!dep->trb_pool) { 391 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 392 dep->name); 393 return -ENOMEM; 394 } 395 396 return 0; 397} 398 399static void dwc3_free_trb_pool(struct dwc3_ep *dep) 400{ 401 struct dwc3 *dwc = dep->dwc; 402 403 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 404 dep->trb_pool, dep->trb_pool_dma); 405 406 dep->trb_pool = NULL; 407 dep->trb_pool_dma = 0; 408} 409 410static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 411{ 412 struct dwc3_gadget_ep_cmd_params params; 413 u32 cmd; 414 415 memset(¶ms, 0x00, sizeof(params)); 416 417 if (dep->number != 1) { 418 cmd = DWC3_DEPCMD_DEPSTARTCFG; 419 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 420 if (dep->number > 1) { 421 if (dwc->start_config_issued) 422 return 0; 423 dwc->start_config_issued = true; 424 cmd |= DWC3_DEPCMD_PARAM(2); 425 } 426 427 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 428 } 429 430 return 0; 431} 432 433static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 434 const struct usb_endpoint_descriptor *desc, 435 const struct usb_ss_ep_comp_descriptor *comp_desc, 436 bool ignore, bool restore) 437{ 438 struct dwc3_gadget_ep_cmd_params params; 439 440 memset(¶ms, 0x00, sizeof(params)); 441 442 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 443 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); 444 445 /* Burst size is only needed in SuperSpeed mode */ 446 if (dwc->gadget.speed == USB_SPEED_SUPER) { 447 u32 burst = dep->endpoint.maxburst - 1; 448 449 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); 450 } 451 452 if (ignore) 453 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; 454 455 if (restore) { 456 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; 457 params.param2 |= dep->saved_state; 458 } 459 460 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 461 | DWC3_DEPCFG_XFER_NOT_READY_EN; 462 463 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 464 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 465 | DWC3_DEPCFG_STREAM_EVENT_EN; 466 dep->stream_capable = true; 467 } 468 469 if (usb_endpoint_xfer_isoc(desc)) 470 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 471 472 /* 473 * We are doing 1:1 mapping for endpoints, meaning 474 * Physical Endpoints 2 maps to Logical Endpoint 2 and 475 * so on. We consider the direction bit as part of the physical 476 * endpoint number. So USB endpoint 0x81 is 0x03. 477 */ 478 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 479 480 /* 481 * We must use the lower 16 TX FIFOs even though 482 * HW might have more 483 */ 484 if (dep->direction) 485 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 486 487 if (desc->bInterval) { 488 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 489 dep->interval = 1 << (desc->bInterval - 1); 490 } 491 492 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 493 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 494} 495 496static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 497{ 498 struct dwc3_gadget_ep_cmd_params params; 499 500 memset(¶ms, 0x00, sizeof(params)); 501 502 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 503 504 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 505 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 506} 507 508/** 509 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 510 * @dep: endpoint to be initialized 511 * @desc: USB Endpoint Descriptor 512 * 513 * Caller should take care of locking 514 */ 515static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 516 const struct usb_endpoint_descriptor *desc, 517 const struct usb_ss_ep_comp_descriptor *comp_desc, 518 bool ignore, bool restore) 519{ 520 struct dwc3 *dwc = dep->dwc; 521 u32 reg; 522 int ret = -ENOMEM; 523 524 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 525 526 if (!(dep->flags & DWC3_EP_ENABLED)) { 527 ret = dwc3_gadget_start_config(dwc, dep); 528 if (ret) 529 return ret; 530 } 531 532 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, 533 restore); 534 if (ret) 535 return ret; 536 537 if (!(dep->flags & DWC3_EP_ENABLED)) { 538 struct dwc3_trb *trb_st_hw; 539 struct dwc3_trb *trb_link; 540 541 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 542 if (ret) 543 return ret; 544 545 dep->endpoint.desc = desc; 546 dep->comp_desc = comp_desc; 547 dep->type = usb_endpoint_type(desc); 548 dep->flags |= DWC3_EP_ENABLED; 549 550 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 551 reg |= DWC3_DALEPENA_EP(dep->number); 552 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 553 554 if (!usb_endpoint_xfer_isoc(desc)) 555 return 0; 556 557 memset(&trb_link, 0, sizeof(trb_link)); 558 559 /* Link TRB for ISOC. The HWO bit is never reset */ 560 trb_st_hw = &dep->trb_pool[0]; 561 562 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 563 564 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 565 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 566 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 567 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 568 } 569 570 return 0; 571} 572 573static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); 574static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 575{ 576 struct dwc3_request *req; 577 578 if (!list_empty(&dep->req_queued)) { 579 dwc3_stop_active_transfer(dwc, dep->number, true); 580 581 /* - giveback all requests to gadget driver */ 582 while (!list_empty(&dep->req_queued)) { 583 req = next_request(&dep->req_queued); 584 585 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 586 } 587 } 588 589 while (!list_empty(&dep->request_list)) { 590 req = next_request(&dep->request_list); 591 592 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 593 } 594} 595 596/** 597 * __dwc3_gadget_ep_disable - Disables a HW endpoint 598 * @dep: the endpoint to disable 599 * 600 * This function also removes requests which are currently processed ny the 601 * hardware and those which are not yet scheduled. 602 * Caller should take care of locking. 603 */ 604static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 605{ 606 struct dwc3 *dwc = dep->dwc; 607 u32 reg; 608 609 dwc3_remove_requests(dwc, dep); 610 611 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 612 reg &= ~DWC3_DALEPENA_EP(dep->number); 613 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 614 615 dep->stream_capable = false; 616 dep->endpoint.desc = NULL; 617 dep->comp_desc = NULL; 618 dep->type = 0; 619 dep->flags = 0; 620 621 return 0; 622} 623 624/* -------------------------------------------------------------------------- */ 625 626static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 627 const struct usb_endpoint_descriptor *desc) 628{ 629 return -EINVAL; 630} 631 632static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 633{ 634 return -EINVAL; 635} 636 637/* -------------------------------------------------------------------------- */ 638 639static int dwc3_gadget_ep_enable(struct usb_ep *ep, 640 const struct usb_endpoint_descriptor *desc) 641{ 642 struct dwc3_ep *dep; 643 struct dwc3 *dwc; 644 unsigned long flags; 645 int ret; 646 647 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 648 pr_debug("dwc3: invalid parameters\n"); 649 return -EINVAL; 650 } 651 652 if (!desc->wMaxPacketSize) { 653 pr_debug("dwc3: missing wMaxPacketSize\n"); 654 return -EINVAL; 655 } 656 657 dep = to_dwc3_ep(ep); 658 dwc = dep->dwc; 659 660 if (dep->flags & DWC3_EP_ENABLED) { 661 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 662 dep->name); 663 return 0; 664 } 665 666 switch (usb_endpoint_type(desc)) { 667 case USB_ENDPOINT_XFER_CONTROL: 668 strlcat(dep->name, "-control", sizeof(dep->name)); 669 break; 670 case USB_ENDPOINT_XFER_ISOC: 671 strlcat(dep->name, "-isoc", sizeof(dep->name)); 672 break; 673 case USB_ENDPOINT_XFER_BULK: 674 strlcat(dep->name, "-bulk", sizeof(dep->name)); 675 break; 676 case USB_ENDPOINT_XFER_INT: 677 strlcat(dep->name, "-int", sizeof(dep->name)); 678 break; 679 default: 680 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 681 } 682 683 spin_lock_irqsave(&dwc->lock, flags); 684 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); 685 spin_unlock_irqrestore(&dwc->lock, flags); 686 687 return ret; 688} 689 690static int dwc3_gadget_ep_disable(struct usb_ep *ep) 691{ 692 struct dwc3_ep *dep; 693 struct dwc3 *dwc; 694 unsigned long flags; 695 int ret; 696 697 if (!ep) { 698 pr_debug("dwc3: invalid parameters\n"); 699 return -EINVAL; 700 } 701 702 dep = to_dwc3_ep(ep); 703 dwc = dep->dwc; 704 705 if (!(dep->flags & DWC3_EP_ENABLED)) { 706 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 707 dep->name); 708 return 0; 709 } 710 711 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 712 dep->number >> 1, 713 (dep->number & 1) ? "in" : "out"); 714 715 spin_lock_irqsave(&dwc->lock, flags); 716 ret = __dwc3_gadget_ep_disable(dep); 717 spin_unlock_irqrestore(&dwc->lock, flags); 718 719 return ret; 720} 721 722static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 723 gfp_t gfp_flags) 724{ 725 struct dwc3_request *req; 726 struct dwc3_ep *dep = to_dwc3_ep(ep); 727 struct dwc3 *dwc = dep->dwc; 728 729 req = kzalloc(sizeof(*req), gfp_flags); 730 if (!req) { 731 dev_err(dwc->dev, "not enough memory\n"); 732 return NULL; 733 } 734 735 req->epnum = dep->number; 736 req->dep = dep; 737 738 return &req->request; 739} 740 741static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 742 struct usb_request *request) 743{ 744 struct dwc3_request *req = to_dwc3_request(request); 745 746 kfree(req); 747} 748 749/** 750 * dwc3_prepare_one_trb - setup one TRB from one request 751 * @dep: endpoint for which this request is prepared 752 * @req: dwc3_request pointer 753 */ 754static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 755 struct dwc3_request *req, dma_addr_t dma, 756 unsigned length, unsigned last, unsigned chain, unsigned node) 757{ 758 struct dwc3 *dwc = dep->dwc; 759 struct dwc3_trb *trb; 760 761 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 762 dep->name, req, (unsigned long long) dma, 763 length, last ? " last" : "", 764 chain ? " chain" : ""); 765 766 /* Skip the LINK-TRB on ISOC */ 767 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 768 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 769 dep->free_slot++; 770 771 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 772 773 if (!req->trb) { 774 dwc3_gadget_move_request_queued(req); 775 req->trb = trb; 776 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 777 req->start_slot = dep->free_slot & DWC3_TRB_MASK; 778 } 779 780 dep->free_slot++; 781 782 trb->size = DWC3_TRB_SIZE_LENGTH(length); 783 trb->bpl = lower_32_bits(dma); 784 trb->bph = upper_32_bits(dma); 785 786 switch (usb_endpoint_type(dep->endpoint.desc)) { 787 case USB_ENDPOINT_XFER_CONTROL: 788 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 789 break; 790 791 case USB_ENDPOINT_XFER_ISOC: 792 if (!node) 793 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 794 else 795 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; 796 break; 797 798 case USB_ENDPOINT_XFER_BULK: 799 case USB_ENDPOINT_XFER_INT: 800 trb->ctrl = DWC3_TRBCTL_NORMAL; 801 break; 802 default: 803 /* 804 * This is only possible with faulty memory because we 805 * checked it already :) 806 */ 807 BUG(); 808 } 809 810 if (!req->request.no_interrupt && !chain) 811 trb->ctrl |= DWC3_TRB_CTRL_IOC; 812 813 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 814 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 815 trb->ctrl |= DWC3_TRB_CTRL_CSP; 816 } else if (last) { 817 trb->ctrl |= DWC3_TRB_CTRL_LST; 818 } 819 820 if (chain) 821 trb->ctrl |= DWC3_TRB_CTRL_CHN; 822 823 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 824 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); 825 826 trb->ctrl |= DWC3_TRB_CTRL_HWO; 827} 828 829/* 830 * dwc3_prepare_trbs - setup TRBs from requests 831 * @dep: endpoint for which requests are being prepared 832 * @starting: true if the endpoint is idle and no requests are queued. 833 * 834 * The function goes through the requests list and sets up TRBs for the 835 * transfers. The function returns once there are no more TRBs available or 836 * it runs out of requests. 837 */ 838static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 839{ 840 struct dwc3_request *req, *n; 841 u32 trbs_left; 842 u32 max; 843 unsigned int last_one = 0; 844 845 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 846 847 /* the first request must not be queued */ 848 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 849 850 /* Can't wrap around on a non-isoc EP since there's no link TRB */ 851 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 852 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); 853 if (trbs_left > max) 854 trbs_left = max; 855 } 856 857 /* 858 * If busy & slot are equal than it is either full or empty. If we are 859 * starting to process requests then we are empty. Otherwise we are 860 * full and don't do anything 861 */ 862 if (!trbs_left) { 863 if (!starting) 864 return; 865 trbs_left = DWC3_TRB_NUM; 866 /* 867 * In case we start from scratch, we queue the ISOC requests 868 * starting from slot 1. This is done because we use ring 869 * buffer and have no LST bit to stop us. Instead, we place 870 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt 871 * after the first request so we start at slot 1 and have 872 * 7 requests proceed before we hit the first IOC. 873 * Other transfer types don't use the ring buffer and are 874 * processed from the first TRB until the last one. Since we 875 * don't wrap around we have to start at the beginning. 876 */ 877 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 878 dep->busy_slot = 1; 879 dep->free_slot = 1; 880 } else { 881 dep->busy_slot = 0; 882 dep->free_slot = 0; 883 } 884 } 885 886 /* The last TRB is a link TRB, not used for xfer */ 887 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) 888 return; 889 890 list_for_each_entry_safe(req, n, &dep->request_list, list) { 891 unsigned length; 892 dma_addr_t dma; 893 last_one = false; 894 895 if (req->request.num_mapped_sgs > 0) { 896 struct usb_request *request = &req->request; 897 struct scatterlist *sg = request->sg; 898 struct scatterlist *s; 899 int i; 900 901 for_each_sg(sg, s, request->num_mapped_sgs, i) { 902 unsigned chain = true; 903 904 length = sg_dma_len(s); 905 dma = sg_dma_address(s); 906 907 if (i == (request->num_mapped_sgs - 1) || 908 sg_is_last(s)) { 909 if (list_is_last(&req->list, 910 &dep->request_list)) 911 last_one = true; 912 chain = false; 913 } 914 915 trbs_left--; 916 if (!trbs_left) 917 last_one = true; 918 919 if (last_one) 920 chain = false; 921 922 dwc3_prepare_one_trb(dep, req, dma, length, 923 last_one, chain, i); 924 925 if (last_one) 926 break; 927 } 928 } else { 929 dma = req->request.dma; 930 length = req->request.length; 931 trbs_left--; 932 933 if (!trbs_left) 934 last_one = 1; 935 936 /* Is this the last request? */ 937 if (list_is_last(&req->list, &dep->request_list)) 938 last_one = 1; 939 940 dwc3_prepare_one_trb(dep, req, dma, length, 941 last_one, false, 0); 942 943 if (last_one) 944 break; 945 } 946 } 947} 948 949static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 950 int start_new) 951{ 952 struct dwc3_gadget_ep_cmd_params params; 953 struct dwc3_request *req; 954 struct dwc3 *dwc = dep->dwc; 955 int ret; 956 u32 cmd; 957 958 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 959 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 960 return -EBUSY; 961 } 962 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 963 964 /* 965 * If we are getting here after a short-out-packet we don't enqueue any 966 * new requests as we try to set the IOC bit only on the last request. 967 */ 968 if (start_new) { 969 if (list_empty(&dep->req_queued)) 970 dwc3_prepare_trbs(dep, start_new); 971 972 /* req points to the first request which will be sent */ 973 req = next_request(&dep->req_queued); 974 } else { 975 dwc3_prepare_trbs(dep, start_new); 976 977 /* 978 * req points to the first request where HWO changed from 0 to 1 979 */ 980 req = next_request(&dep->req_queued); 981 } 982 if (!req) { 983 dep->flags |= DWC3_EP_PENDING_REQUEST; 984 return 0; 985 } 986 987 memset(¶ms, 0, sizeof(params)); 988 989 if (start_new) { 990 params.param0 = upper_32_bits(req->trb_dma); 991 params.param1 = lower_32_bits(req->trb_dma); 992 cmd = DWC3_DEPCMD_STARTTRANSFER; 993 } else { 994 cmd = DWC3_DEPCMD_UPDATETRANSFER; 995 } 996 997 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 998 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 999 if (ret < 0) { 1000 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 1001 1002 /* 1003 * FIXME we need to iterate over the list of requests 1004 * here and stop, unmap, free and del each of the linked 1005 * requests instead of what we do now. 1006 */ 1007 usb_gadget_unmap_request(&dwc->gadget, &req->request, 1008 req->direction); 1009 list_del(&req->list); 1010 return ret; 1011 } 1012 1013 dep->flags |= DWC3_EP_BUSY; 1014 1015 if (start_new) { 1016 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 1017 dep->number); 1018 WARN_ON_ONCE(!dep->resource_index); 1019 } 1020 1021 return 0; 1022} 1023 1024static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, 1025 struct dwc3_ep *dep, u32 cur_uf) 1026{ 1027 u32 uf; 1028 1029 if (list_empty(&dep->request_list)) { 1030 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1031 dep->name); 1032 dep->flags |= DWC3_EP_PENDING_REQUEST; 1033 return; 1034 } 1035 1036 /* 4 micro frames in the future */ 1037 uf = cur_uf + dep->interval * 4; 1038 1039 __dwc3_gadget_kick_transfer(dep, uf, 1); 1040} 1041 1042static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1043 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1044{ 1045 u32 cur_uf, mask; 1046 1047 mask = ~(dep->interval - 1); 1048 cur_uf = event->parameters & mask; 1049 1050 __dwc3_gadget_start_isoc(dwc, dep, cur_uf); 1051} 1052 1053static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 1054{ 1055 struct dwc3 *dwc = dep->dwc; 1056 int ret; 1057 1058 req->request.actual = 0; 1059 req->request.status = -EINPROGRESS; 1060 req->direction = dep->direction; 1061 req->epnum = dep->number; 1062 1063 /* 1064 * We only add to our list of requests now and 1065 * start consuming the list once we get XferNotReady 1066 * IRQ. 1067 * 1068 * That way, we avoid doing anything that we don't need 1069 * to do now and defer it until the point we receive a 1070 * particular token from the Host side. 1071 * 1072 * This will also avoid Host cancelling URBs due to too 1073 * many NAKs. 1074 */ 1075 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1076 dep->direction); 1077 if (ret) 1078 return ret; 1079 1080 list_add_tail(&req->list, &dep->request_list); 1081 1082 /* 1083 * There are a few special cases: 1084 * 1085 * 1. XferNotReady with empty list of requests. We need to kick the 1086 * transfer here in that situation, otherwise we will be NAKing 1087 * forever. If we get XferNotReady before gadget driver has a 1088 * chance to queue a request, we will ACK the IRQ but won't be 1089 * able to receive the data until the next request is queued. 1090 * The following code is handling exactly that. 1091 * 1092 */ 1093 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1094 /* 1095 * If xfernotready is already elapsed and it is a case 1096 * of isoc transfer, then issue END TRANSFER, so that 1097 * you can receive xfernotready again and can have 1098 * notion of current microframe. 1099 */ 1100 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1101 if (list_empty(&dep->req_queued)) { 1102 dwc3_stop_active_transfer(dwc, dep->number, true); 1103 dep->flags = DWC3_EP_ENABLED; 1104 } 1105 return 0; 1106 } 1107 1108 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1109 if (ret && ret != -EBUSY) 1110 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1111 dep->name); 1112 return ret; 1113 } 1114 1115 /* 1116 * 2. XferInProgress on Isoc EP with an active transfer. We need to 1117 * kick the transfer here after queuing a request, otherwise the 1118 * core may not see the modified TRB(s). 1119 */ 1120 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1121 (dep->flags & DWC3_EP_BUSY) && 1122 !(dep->flags & DWC3_EP_MISSED_ISOC)) { 1123 WARN_ON_ONCE(!dep->resource_index); 1124 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, 1125 false); 1126 if (ret && ret != -EBUSY) 1127 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1128 dep->name); 1129 return ret; 1130 } 1131 1132 /* 1133 * 4. Stream Capable Bulk Endpoints. We need to start the transfer 1134 * right away, otherwise host will not know we have streams to be 1135 * handled. 1136 */ 1137 if (dep->stream_capable) { 1138 int ret; 1139 1140 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1141 if (ret && ret != -EBUSY) { 1142 struct dwc3 *dwc = dep->dwc; 1143 1144 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1145 dep->name); 1146 } 1147 } 1148 1149 return 0; 1150} 1151 1152static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1153 gfp_t gfp_flags) 1154{ 1155 struct dwc3_request *req = to_dwc3_request(request); 1156 struct dwc3_ep *dep = to_dwc3_ep(ep); 1157 struct dwc3 *dwc = dep->dwc; 1158 1159 unsigned long flags; 1160 1161 int ret; 1162 1163 if (!dep->endpoint.desc) { 1164 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1165 request, ep->name); 1166 return -ESHUTDOWN; 1167 } 1168 1169 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1170 request, ep->name, request->length); 1171 1172 spin_lock_irqsave(&dwc->lock, flags); 1173 ret = __dwc3_gadget_ep_queue(dep, req); 1174 spin_unlock_irqrestore(&dwc->lock, flags); 1175 1176 return ret; 1177} 1178 1179static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1180 struct usb_request *request) 1181{ 1182 struct dwc3_request *req = to_dwc3_request(request); 1183 struct dwc3_request *r = NULL; 1184 1185 struct dwc3_ep *dep = to_dwc3_ep(ep); 1186 struct dwc3 *dwc = dep->dwc; 1187 1188 unsigned long flags; 1189 int ret = 0; 1190 1191 spin_lock_irqsave(&dwc->lock, flags); 1192 1193 list_for_each_entry(r, &dep->request_list, list) { 1194 if (r == req) 1195 break; 1196 } 1197 1198 if (r != req) { 1199 list_for_each_entry(r, &dep->req_queued, list) { 1200 if (r == req) 1201 break; 1202 } 1203 if (r == req) { 1204 /* wait until it is processed */ 1205 dwc3_stop_active_transfer(dwc, dep->number, true); 1206 goto out1; 1207 } 1208 dev_err(dwc->dev, "request %p was not queued to %s\n", 1209 request, ep->name); 1210 ret = -EINVAL; 1211 goto out0; 1212 } 1213 1214out1: 1215 /* giveback the request */ 1216 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1217 1218out0: 1219 spin_unlock_irqrestore(&dwc->lock, flags); 1220 1221 return ret; 1222} 1223 1224int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1225{ 1226 struct dwc3_gadget_ep_cmd_params params; 1227 struct dwc3 *dwc = dep->dwc; 1228 int ret; 1229 1230 memset(¶ms, 0x00, sizeof(params)); 1231 1232 if (value) { 1233 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1234 DWC3_DEPCMD_SETSTALL, ¶ms); 1235 if (ret) 1236 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1237 value ? "set" : "clear", 1238 dep->name); 1239 else 1240 dep->flags |= DWC3_EP_STALL; 1241 } else { 1242 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1243 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1244 if (ret) 1245 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1246 value ? "set" : "clear", 1247 dep->name); 1248 else 1249 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); 1250 } 1251 1252 return ret; 1253} 1254 1255static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1256{ 1257 struct dwc3_ep *dep = to_dwc3_ep(ep); 1258 struct dwc3 *dwc = dep->dwc; 1259 1260 unsigned long flags; 1261 1262 int ret; 1263 1264 spin_lock_irqsave(&dwc->lock, flags); 1265 1266 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1267 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1268 ret = -EINVAL; 1269 goto out; 1270 } 1271 1272 ret = __dwc3_gadget_ep_set_halt(dep, value); 1273out: 1274 spin_unlock_irqrestore(&dwc->lock, flags); 1275 1276 return ret; 1277} 1278 1279static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1280{ 1281 struct dwc3_ep *dep = to_dwc3_ep(ep); 1282 struct dwc3 *dwc = dep->dwc; 1283 unsigned long flags; 1284 1285 spin_lock_irqsave(&dwc->lock, flags); 1286 dep->flags |= DWC3_EP_WEDGE; 1287 spin_unlock_irqrestore(&dwc->lock, flags); 1288 1289 if (dep->number == 0 || dep->number == 1) 1290 return dwc3_gadget_ep0_set_halt(ep, 1); 1291 else 1292 return dwc3_gadget_ep_set_halt(ep, 1); 1293} 1294 1295/* -------------------------------------------------------------------------- */ 1296 1297static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1298 .bLength = USB_DT_ENDPOINT_SIZE, 1299 .bDescriptorType = USB_DT_ENDPOINT, 1300 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1301}; 1302 1303static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1304 .enable = dwc3_gadget_ep0_enable, 1305 .disable = dwc3_gadget_ep0_disable, 1306 .alloc_request = dwc3_gadget_ep_alloc_request, 1307 .free_request = dwc3_gadget_ep_free_request, 1308 .queue = dwc3_gadget_ep0_queue, 1309 .dequeue = dwc3_gadget_ep_dequeue, 1310 .set_halt = dwc3_gadget_ep0_set_halt, 1311 .set_wedge = dwc3_gadget_ep_set_wedge, 1312}; 1313 1314static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1315 .enable = dwc3_gadget_ep_enable, 1316 .disable = dwc3_gadget_ep_disable, 1317 .alloc_request = dwc3_gadget_ep_alloc_request, 1318 .free_request = dwc3_gadget_ep_free_request, 1319 .queue = dwc3_gadget_ep_queue, 1320 .dequeue = dwc3_gadget_ep_dequeue, 1321 .set_halt = dwc3_gadget_ep_set_halt, 1322 .set_wedge = dwc3_gadget_ep_set_wedge, 1323}; 1324 1325/* -------------------------------------------------------------------------- */ 1326 1327static int dwc3_gadget_get_frame(struct usb_gadget *g) 1328{ 1329 struct dwc3 *dwc = gadget_to_dwc(g); 1330 u32 reg; 1331 1332 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1333 return DWC3_DSTS_SOFFN(reg); 1334} 1335 1336static int dwc3_gadget_wakeup(struct usb_gadget *g) 1337{ 1338 struct dwc3 *dwc = gadget_to_dwc(g); 1339 1340 unsigned long timeout; 1341 unsigned long flags; 1342 1343 u32 reg; 1344 1345 int ret = 0; 1346 1347 u8 link_state; 1348 u8 speed; 1349 1350 spin_lock_irqsave(&dwc->lock, flags); 1351 1352 /* 1353 * According to the Databook Remote wakeup request should 1354 * be issued only when the device is in early suspend state. 1355 * 1356 * We can check that via USB Link State bits in DSTS register. 1357 */ 1358 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1359 1360 speed = reg & DWC3_DSTS_CONNECTSPD; 1361 if (speed == DWC3_DSTS_SUPERSPEED) { 1362 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1363 ret = -EINVAL; 1364 goto out; 1365 } 1366 1367 link_state = DWC3_DSTS_USBLNKST(reg); 1368 1369 switch (link_state) { 1370 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1371 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1372 break; 1373 default: 1374 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1375 link_state); 1376 ret = -EINVAL; 1377 goto out; 1378 } 1379 1380 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1381 if (ret < 0) { 1382 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1383 goto out; 1384 } 1385 1386 /* Recent versions do this automatically */ 1387 if (dwc->revision < DWC3_REVISION_194A) { 1388 /* write zeroes to Link Change Request */ 1389 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1390 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1391 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1392 } 1393 1394 /* poll until Link State changes to ON */ 1395 timeout = jiffies + msecs_to_jiffies(100); 1396 1397 while (!time_after(jiffies, timeout)) { 1398 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1399 1400 /* in HS, means ON */ 1401 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1402 break; 1403 } 1404 1405 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1406 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1407 ret = -EINVAL; 1408 } 1409 1410out: 1411 spin_unlock_irqrestore(&dwc->lock, flags); 1412 1413 return ret; 1414} 1415 1416static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1417 int is_selfpowered) 1418{ 1419 struct dwc3 *dwc = gadget_to_dwc(g); 1420 unsigned long flags; 1421 1422 spin_lock_irqsave(&dwc->lock, flags); 1423 dwc->is_selfpowered = !!is_selfpowered; 1424 spin_unlock_irqrestore(&dwc->lock, flags); 1425 1426 return 0; 1427} 1428 1429static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) 1430{ 1431 u32 reg; 1432 u32 timeout = 500; 1433 1434 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1435 if (is_on) { 1436 if (dwc->revision <= DWC3_REVISION_187A) { 1437 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1438 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1439 } 1440 1441 if (dwc->revision >= DWC3_REVISION_194A) 1442 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1443 reg |= DWC3_DCTL_RUN_STOP; 1444 1445 if (dwc->has_hibernation) 1446 reg |= DWC3_DCTL_KEEP_CONNECT; 1447 1448 dwc->pullups_connected = true; 1449 } else { 1450 reg &= ~DWC3_DCTL_RUN_STOP; 1451 1452 if (dwc->has_hibernation && !suspend) 1453 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1454 1455 dwc->pullups_connected = false; 1456 } 1457 1458 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1459 1460 do { 1461 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1462 if (is_on) { 1463 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1464 break; 1465 } else { 1466 if (reg & DWC3_DSTS_DEVCTRLHLT) 1467 break; 1468 } 1469 timeout--; 1470 if (!timeout) 1471 return -ETIMEDOUT; 1472 udelay(1); 1473 } while (1); 1474 1475 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1476 dwc->gadget_driver 1477 ? dwc->gadget_driver->function : "no-function", 1478 is_on ? "connect" : "disconnect"); 1479 1480 return 0; 1481} 1482 1483static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1484{ 1485 struct dwc3 *dwc = gadget_to_dwc(g); 1486 unsigned long flags; 1487 int ret; 1488 1489 is_on = !!is_on; 1490 1491 spin_lock_irqsave(&dwc->lock, flags); 1492 ret = dwc3_gadget_run_stop(dwc, is_on, false); 1493 spin_unlock_irqrestore(&dwc->lock, flags); 1494 1495 return ret; 1496} 1497 1498static void dwc3_gadget_enable_irq(struct dwc3 *dwc) 1499{ 1500 u32 reg; 1501 1502 /* Enable all but Start and End of Frame IRQs */ 1503 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 1504 DWC3_DEVTEN_EVNTOVERFLOWEN | 1505 DWC3_DEVTEN_CMDCMPLTEN | 1506 DWC3_DEVTEN_ERRTICERREN | 1507 DWC3_DEVTEN_WKUPEVTEN | 1508 DWC3_DEVTEN_ULSTCNGEN | 1509 DWC3_DEVTEN_CONNECTDONEEN | 1510 DWC3_DEVTEN_USBRSTEN | 1511 DWC3_DEVTEN_DISCONNEVTEN); 1512 1513 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 1514} 1515 1516static void dwc3_gadget_disable_irq(struct dwc3 *dwc) 1517{ 1518 /* mask all interrupts */ 1519 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 1520} 1521 1522static irqreturn_t dwc3_interrupt(int irq, void *_dwc); 1523static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); 1524 1525static int dwc3_gadget_start(struct usb_gadget *g, 1526 struct usb_gadget_driver *driver) 1527{ 1528 struct dwc3 *dwc = gadget_to_dwc(g); 1529 struct dwc3_ep *dep; 1530 unsigned long flags; 1531 int ret = 0; 1532 int irq; 1533 u32 reg; 1534 1535 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1536 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, 1537 IRQF_SHARED, "dwc3", dwc); 1538 if (ret) { 1539 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 1540 irq, ret); 1541 goto err0; 1542 } 1543 1544 spin_lock_irqsave(&dwc->lock, flags); 1545 1546 if (dwc->gadget_driver) { 1547 dev_err(dwc->dev, "%s is already bound to %s\n", 1548 dwc->gadget.name, 1549 dwc->gadget_driver->driver.name); 1550 ret = -EBUSY; 1551 goto err1; 1552 } 1553 1554 dwc->gadget_driver = driver; 1555 1556 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1557 reg &= ~(DWC3_DCFG_SPEED_MASK); 1558 1559 /** 1560 * WORKAROUND: DWC3 revision < 2.20a have an issue 1561 * which would cause metastability state on Run/Stop 1562 * bit if we try to force the IP to USB2-only mode. 1563 * 1564 * Because of that, we cannot configure the IP to any 1565 * speed other than the SuperSpeed 1566 * 1567 * Refers to: 1568 * 1569 * STAR#9000525659: Clock Domain Crossing on DCTL in 1570 * USB 2.0 Mode 1571 */ 1572 if (dwc->revision < DWC3_REVISION_220A) { 1573 reg |= DWC3_DCFG_SUPERSPEED; 1574 } else { 1575 switch (dwc->maximum_speed) { 1576 case USB_SPEED_LOW: 1577 reg |= DWC3_DSTS_LOWSPEED; 1578 break; 1579 case USB_SPEED_FULL: 1580 reg |= DWC3_DSTS_FULLSPEED1; 1581 break; 1582 case USB_SPEED_HIGH: 1583 reg |= DWC3_DSTS_HIGHSPEED; 1584 break; 1585 case USB_SPEED_SUPER: /* FALLTHROUGH */ 1586 case USB_SPEED_UNKNOWN: /* FALTHROUGH */ 1587 default: 1588 reg |= DWC3_DSTS_SUPERSPEED; 1589 } 1590 } 1591 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1592 1593 dwc->start_config_issued = false; 1594 1595 /* Start with SuperSpeed Default */ 1596 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1597 1598 dep = dwc->eps[0]; 1599 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 1600 false); 1601 if (ret) { 1602 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1603 goto err2; 1604 } 1605 1606 dep = dwc->eps[1]; 1607 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 1608 false); 1609 if (ret) { 1610 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1611 goto err3; 1612 } 1613 1614 /* begin to receive SETUP packets */ 1615 dwc->ep0state = EP0_SETUP_PHASE; 1616 dwc3_ep0_out_start(dwc); 1617 1618 dwc3_gadget_enable_irq(dwc); 1619 1620 spin_unlock_irqrestore(&dwc->lock, flags); 1621 1622 return 0; 1623 1624err3: 1625 __dwc3_gadget_ep_disable(dwc->eps[0]); 1626 1627err2: 1628 dwc->gadget_driver = NULL; 1629 1630err1: 1631 spin_unlock_irqrestore(&dwc->lock, flags); 1632 1633 free_irq(irq, dwc); 1634 1635err0: 1636 return ret; 1637} 1638 1639static int dwc3_gadget_stop(struct usb_gadget *g, 1640 struct usb_gadget_driver *driver) 1641{ 1642 struct dwc3 *dwc = gadget_to_dwc(g); 1643 unsigned long flags; 1644 int irq; 1645 1646 spin_lock_irqsave(&dwc->lock, flags); 1647 1648 dwc3_gadget_disable_irq(dwc); 1649 __dwc3_gadget_ep_disable(dwc->eps[0]); 1650 __dwc3_gadget_ep_disable(dwc->eps[1]); 1651 1652 dwc->gadget_driver = NULL; 1653 1654 spin_unlock_irqrestore(&dwc->lock, flags); 1655 1656 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1657 free_irq(irq, dwc); 1658 1659 return 0; 1660} 1661 1662static const struct usb_gadget_ops dwc3_gadget_ops = { 1663 .get_frame = dwc3_gadget_get_frame, 1664 .wakeup = dwc3_gadget_wakeup, 1665 .set_selfpowered = dwc3_gadget_set_selfpowered, 1666 .pullup = dwc3_gadget_pullup, 1667 .udc_start = dwc3_gadget_start, 1668 .udc_stop = dwc3_gadget_stop, 1669}; 1670 1671/* -------------------------------------------------------------------------- */ 1672 1673static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, 1674 u8 num, u32 direction) 1675{ 1676 struct dwc3_ep *dep; 1677 u8 i; 1678 1679 for (i = 0; i < num; i++) { 1680 u8 epnum = (i << 1) | (!!direction); 1681 1682 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1683 if (!dep) { 1684 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1685 epnum); 1686 return -ENOMEM; 1687 } 1688 1689 dep->dwc = dwc; 1690 dep->number = epnum; 1691 dep->direction = !!direction; 1692 dwc->eps[epnum] = dep; 1693 1694 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1695 (epnum & 1) ? "in" : "out"); 1696 1697 dep->endpoint.name = dep->name; 1698 1699 dev_vdbg(dwc->dev, "initializing %s\n", dep->name); 1700 1701 if (epnum == 0 || epnum == 1) { 1702 usb_ep_set_maxpacket_limit(&dep->endpoint, 512); 1703 dep->endpoint.maxburst = 1; 1704 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1705 if (!epnum) 1706 dwc->gadget.ep0 = &dep->endpoint; 1707 } else { 1708 int ret; 1709 1710 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); 1711 dep->endpoint.max_streams = 15; 1712 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1713 list_add_tail(&dep->endpoint.ep_list, 1714 &dwc->gadget.ep_list); 1715 1716 ret = dwc3_alloc_trb_pool(dep); 1717 if (ret) 1718 return ret; 1719 } 1720 1721 INIT_LIST_HEAD(&dep->request_list); 1722 INIT_LIST_HEAD(&dep->req_queued); 1723 } 1724 1725 return 0; 1726} 1727 1728static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1729{ 1730 int ret; 1731 1732 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1733 1734 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); 1735 if (ret < 0) { 1736 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n"); 1737 return ret; 1738 } 1739 1740 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); 1741 if (ret < 0) { 1742 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n"); 1743 return ret; 1744 } 1745 1746 return 0; 1747} 1748 1749static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1750{ 1751 struct dwc3_ep *dep; 1752 u8 epnum; 1753 1754 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1755 dep = dwc->eps[epnum]; 1756 if (!dep) 1757 continue; 1758 /* 1759 * Physical endpoints 0 and 1 are special; they form the 1760 * bi-directional USB endpoint 0. 1761 * 1762 * For those two physical endpoints, we don't allocate a TRB 1763 * pool nor do we add them the endpoints list. Due to that, we 1764 * shouldn't do these two operations otherwise we would end up 1765 * with all sorts of bugs when removing dwc3.ko. 1766 */ 1767 if (epnum != 0 && epnum != 1) { 1768 dwc3_free_trb_pool(dep); 1769 list_del(&dep->endpoint.ep_list); 1770 } 1771 1772 kfree(dep); 1773 } 1774} 1775 1776/* -------------------------------------------------------------------------- */ 1777 1778static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, 1779 struct dwc3_request *req, struct dwc3_trb *trb, 1780 const struct dwc3_event_depevt *event, int status) 1781{ 1782 unsigned int count; 1783 unsigned int s_pkt = 0; 1784 unsigned int trb_status; 1785 1786 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 1787 /* 1788 * We continue despite the error. There is not much we 1789 * can do. If we don't clean it up we loop forever. If 1790 * we skip the TRB then it gets overwritten after a 1791 * while since we use them in a ring buffer. A BUG() 1792 * would help. Lets hope that if this occurs, someone 1793 * fixes the root cause instead of looking away :) 1794 */ 1795 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1796 dep->name, trb); 1797 count = trb->size & DWC3_TRB_SIZE_MASK; 1798 1799 if (dep->direction) { 1800 if (count) { 1801 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); 1802 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { 1803 dev_dbg(dwc->dev, "incomplete IN transfer %s\n", 1804 dep->name); 1805 /* 1806 * If missed isoc occurred and there is 1807 * no request queued then issue END 1808 * TRANSFER, so that core generates 1809 * next xfernotready and we will issue 1810 * a fresh START TRANSFER. 1811 * If there are still queued request 1812 * then wait, do not issue either END 1813 * or UPDATE TRANSFER, just attach next 1814 * request in request_list during 1815 * giveback.If any future queued request 1816 * is successfully transferred then we 1817 * will issue UPDATE TRANSFER for all 1818 * request in the request_list. 1819 */ 1820 dep->flags |= DWC3_EP_MISSED_ISOC; 1821 } else { 1822 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1823 dep->name); 1824 status = -ECONNRESET; 1825 } 1826 } else { 1827 dep->flags &= ~DWC3_EP_MISSED_ISOC; 1828 } 1829 } else { 1830 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1831 s_pkt = 1; 1832 } 1833 1834 /* 1835 * We assume here we will always receive the entire data block 1836 * which we should receive. Meaning, if we program RX to 1837 * receive 4K but we receive only 2K, we assume that's all we 1838 * should receive and we simply bounce the request back to the 1839 * gadget driver for further processing. 1840 */ 1841 req->request.actual += req->request.length - count; 1842 if (s_pkt) 1843 return 1; 1844 if ((event->status & DEPEVT_STATUS_LST) && 1845 (trb->ctrl & (DWC3_TRB_CTRL_LST | 1846 DWC3_TRB_CTRL_HWO))) 1847 return 1; 1848 if ((event->status & DEPEVT_STATUS_IOC) && 1849 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1850 return 1; 1851 return 0; 1852} 1853 1854static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1855 const struct dwc3_event_depevt *event, int status) 1856{ 1857 struct dwc3_request *req; 1858 struct dwc3_trb *trb; 1859 unsigned int slot; 1860 unsigned int i; 1861 int ret; 1862 1863 do { 1864 req = next_request(&dep->req_queued); 1865 if (!req) { 1866 WARN_ON_ONCE(1); 1867 return 1; 1868 } 1869 i = 0; 1870 do { 1871 slot = req->start_slot + i; 1872 if ((slot == DWC3_TRB_NUM - 1) && 1873 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 1874 slot++; 1875 slot %= DWC3_TRB_NUM; 1876 trb = &dep->trb_pool[slot]; 1877 1878 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, 1879 event, status); 1880 if (ret) 1881 break; 1882 }while (++i < req->request.num_mapped_sgs); 1883 1884 dwc3_gadget_giveback(dep, req, status); 1885 1886 if (ret) 1887 break; 1888 } while (1); 1889 1890 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1891 list_empty(&dep->req_queued)) { 1892 if (list_empty(&dep->request_list)) { 1893 /* 1894 * If there is no entry in request list then do 1895 * not issue END TRANSFER now. Just set PENDING 1896 * flag, so that END TRANSFER is issued when an 1897 * entry is added into request list. 1898 */ 1899 dep->flags = DWC3_EP_PENDING_REQUEST; 1900 } else { 1901 dwc3_stop_active_transfer(dwc, dep->number, true); 1902 dep->flags = DWC3_EP_ENABLED; 1903 } 1904 return 1; 1905 } 1906 1907 return 1; 1908} 1909 1910static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1911 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1912 int start_new) 1913{ 1914 unsigned status = 0; 1915 int clean_busy; 1916 1917 if (event->status & DEPEVT_STATUS_BUSERR) 1918 status = -ECONNRESET; 1919 1920 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1921 if (clean_busy) 1922 dep->flags &= ~DWC3_EP_BUSY; 1923 1924 /* 1925 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1926 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1927 */ 1928 if (dwc->revision < DWC3_REVISION_183A) { 1929 u32 reg; 1930 int i; 1931 1932 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1933 dep = dwc->eps[i]; 1934 1935 if (!(dep->flags & DWC3_EP_ENABLED)) 1936 continue; 1937 1938 if (!list_empty(&dep->req_queued)) 1939 return; 1940 } 1941 1942 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1943 reg |= dwc->u1u2; 1944 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1945 1946 dwc->u1u2 = 0; 1947 } 1948} 1949 1950static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1951 const struct dwc3_event_depevt *event) 1952{ 1953 struct dwc3_ep *dep; 1954 u8 epnum = event->endpoint_number; 1955 1956 dep = dwc->eps[epnum]; 1957 1958 if (!(dep->flags & DWC3_EP_ENABLED)) 1959 return; 1960 1961 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1962 dwc3_ep_event_string(event->endpoint_event)); 1963 1964 if (epnum == 0 || epnum == 1) { 1965 dwc3_ep0_interrupt(dwc, event); 1966 return; 1967 } 1968 1969 switch (event->endpoint_event) { 1970 case DWC3_DEPEVT_XFERCOMPLETE: 1971 dep->resource_index = 0; 1972 1973 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1974 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1975 dep->name); 1976 return; 1977 } 1978 1979 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1980 break; 1981 case DWC3_DEPEVT_XFERINPROGRESS: 1982 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1983 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1984 dep->name); 1985 return; 1986 } 1987 1988 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1989 break; 1990 case DWC3_DEPEVT_XFERNOTREADY: 1991 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1992 dwc3_gadget_start_isoc(dwc, dep, event); 1993 } else { 1994 int ret; 1995 1996 dev_vdbg(dwc->dev, "%s: reason %s\n", 1997 dep->name, event->status & 1998 DEPEVT_STATUS_TRANSFER_ACTIVE 1999 ? "Transfer Active" 2000 : "Transfer Not Active"); 2001 2002 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 2003 if (!ret || ret == -EBUSY) 2004 return; 2005 2006 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 2007 dep->name); 2008 } 2009 2010 break; 2011 case DWC3_DEPEVT_STREAMEVT: 2012 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { 2013 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 2014 dep->name); 2015 return; 2016 } 2017 2018 switch (event->status) { 2019 case DEPEVT_STREAMEVT_FOUND: 2020 dev_vdbg(dwc->dev, "Stream %d found and started\n", 2021 event->parameters); 2022 2023 break; 2024 case DEPEVT_STREAMEVT_NOTFOUND: 2025 /* FALLTHROUGH */ 2026 default: 2027 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 2028 } 2029 break; 2030 case DWC3_DEPEVT_RXTXFIFOEVT: 2031 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 2032 break; 2033 case DWC3_DEPEVT_EPCMDCMPLT: 2034 dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); 2035 break; 2036 } 2037} 2038 2039static void dwc3_disconnect_gadget(struct dwc3 *dwc) 2040{ 2041 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 2042 spin_unlock(&dwc->lock); 2043 dwc->gadget_driver->disconnect(&dwc->gadget); 2044 spin_lock(&dwc->lock); 2045 } 2046} 2047 2048static void dwc3_suspend_gadget(struct dwc3 *dwc) 2049{ 2050 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 2051 spin_unlock(&dwc->lock); 2052 dwc->gadget_driver->suspend(&dwc->gadget); 2053 spin_lock(&dwc->lock); 2054 } 2055} 2056 2057static void dwc3_resume_gadget(struct dwc3 *dwc) 2058{ 2059 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 2060 spin_unlock(&dwc->lock); 2061 dwc->gadget_driver->resume(&dwc->gadget); 2062 spin_lock(&dwc->lock); 2063 } 2064} 2065 2066static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) 2067{ 2068 struct dwc3_ep *dep; 2069 struct dwc3_gadget_ep_cmd_params params; 2070 u32 cmd; 2071 int ret; 2072 2073 dep = dwc->eps[epnum]; 2074 2075 if (!dep->resource_index) 2076 return; 2077 2078 /* 2079 * NOTICE: We are violating what the Databook says about the 2080 * EndTransfer command. Ideally we would _always_ wait for the 2081 * EndTransfer Command Completion IRQ, but that's causing too 2082 * much trouble synchronizing between us and gadget driver. 2083 * 2084 * We have discussed this with the IP Provider and it was 2085 * suggested to giveback all requests here, but give HW some 2086 * extra time to synchronize with the interconnect. We're using 2087 * an arbitraty 100us delay for that. 2088 * 2089 * Note also that a similar handling was tested by Synopsys 2090 * (thanks a lot Paul) and nothing bad has come out of it. 2091 * In short, what we're doing is: 2092 * 2093 * - Issue EndTransfer WITH CMDIOC bit set 2094 * - Wait 100us 2095 */ 2096 2097 cmd = DWC3_DEPCMD_ENDTRANSFER; 2098 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; 2099 cmd |= DWC3_DEPCMD_CMDIOC; 2100 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 2101 memset(¶ms, 0, sizeof(params)); 2102 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 2103 WARN_ON_ONCE(ret); 2104 dep->resource_index = 0; 2105 dep->flags &= ~DWC3_EP_BUSY; 2106 udelay(100); 2107} 2108 2109static void dwc3_stop_active_transfers(struct dwc3 *dwc) 2110{ 2111 u32 epnum; 2112 2113 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2114 struct dwc3_ep *dep; 2115 2116 dep = dwc->eps[epnum]; 2117 if (!dep) 2118 continue; 2119 2120 if (!(dep->flags & DWC3_EP_ENABLED)) 2121 continue; 2122 2123 dwc3_remove_requests(dwc, dep); 2124 } 2125} 2126 2127static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 2128{ 2129 u32 epnum; 2130 2131 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2132 struct dwc3_ep *dep; 2133 struct dwc3_gadget_ep_cmd_params params; 2134 int ret; 2135 2136 dep = dwc->eps[epnum]; 2137 if (!dep) 2138 continue; 2139 2140 if (!(dep->flags & DWC3_EP_STALL)) 2141 continue; 2142 2143 dep->flags &= ~DWC3_EP_STALL; 2144 2145 memset(¶ms, 0, sizeof(params)); 2146 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 2147 DWC3_DEPCMD_CLEARSTALL, ¶ms); 2148 WARN_ON_ONCE(ret); 2149 } 2150} 2151 2152static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 2153{ 2154 int reg; 2155 2156 dev_vdbg(dwc->dev, "%s\n", __func__); 2157 2158 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2159 reg &= ~DWC3_DCTL_INITU1ENA; 2160 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2161 2162 reg &= ~DWC3_DCTL_INITU2ENA; 2163 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2164 2165 dwc3_disconnect_gadget(dwc); 2166 dwc->start_config_issued = false; 2167 2168 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2169 dwc->setup_packet_pending = false; 2170} 2171 2172static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 2173{ 2174 u32 reg; 2175 2176 dev_vdbg(dwc->dev, "%s\n", __func__); 2177 2178 /* 2179 * WORKAROUND: DWC3 revisions <1.88a have an issue which 2180 * would cause a missing Disconnect Event if there's a 2181 * pending Setup Packet in the FIFO. 2182 * 2183 * There's no suggested workaround on the official Bug 2184 * report, which states that "unless the driver/application 2185 * is doing any special handling of a disconnect event, 2186 * there is no functional issue". 2187 * 2188 * Unfortunately, it turns out that we _do_ some special 2189 * handling of a disconnect event, namely complete all 2190 * pending transfers, notify gadget driver of the 2191 * disconnection, and so on. 2192 * 2193 * Our suggested workaround is to follow the Disconnect 2194 * Event steps here, instead, based on a setup_packet_pending 2195 * flag. Such flag gets set whenever we have a XferNotReady 2196 * event on EP0 and gets cleared on XferComplete for the 2197 * same endpoint. 2198 * 2199 * Refers to: 2200 * 2201 * STAR#9000466709: RTL: Device : Disconnect event not 2202 * generated if setup packet pending in FIFO 2203 */ 2204 if (dwc->revision < DWC3_REVISION_188A) { 2205 if (dwc->setup_packet_pending) 2206 dwc3_gadget_disconnect_interrupt(dwc); 2207 } 2208 2209 /* after reset -> Default State */ 2210 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 2211 2212 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 2213 dwc3_disconnect_gadget(dwc); 2214 2215 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2216 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2217 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2218 dwc->test_mode = false; 2219 2220 dwc3_stop_active_transfers(dwc); 2221 dwc3_clear_stall_all_ep(dwc); 2222 dwc->start_config_issued = false; 2223 2224 /* Reset device address to zero */ 2225 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2226 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2227 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2228} 2229 2230static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 2231{ 2232 u32 reg; 2233 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 2234 2235 /* 2236 * We change the clock only at SS but I dunno why I would want to do 2237 * this. Maybe it becomes part of the power saving plan. 2238 */ 2239 2240 if (speed != DWC3_DSTS_SUPERSPEED) 2241 return; 2242 2243 /* 2244 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2245 * each time on Connect Done. 2246 */ 2247 if (!usb30_clock) 2248 return; 2249 2250 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 2251 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 2252 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 2253} 2254 2255static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2256{ 2257 struct dwc3_ep *dep; 2258 int ret; 2259 u32 reg; 2260 u8 speed; 2261 2262 dev_vdbg(dwc->dev, "%s\n", __func__); 2263 2264 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2265 speed = reg & DWC3_DSTS_CONNECTSPD; 2266 dwc->speed = speed; 2267 2268 dwc3_update_ram_clk_sel(dwc, speed); 2269 2270 switch (speed) { 2271 case DWC3_DCFG_SUPERSPEED: 2272 /* 2273 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2274 * would cause a missing USB3 Reset event. 2275 * 2276 * In such situations, we should force a USB3 Reset 2277 * event by calling our dwc3_gadget_reset_interrupt() 2278 * routine. 2279 * 2280 * Refers to: 2281 * 2282 * STAR#9000483510: RTL: SS : USB3 reset event may 2283 * not be generated always when the link enters poll 2284 */ 2285 if (dwc->revision < DWC3_REVISION_190A) 2286 dwc3_gadget_reset_interrupt(dwc); 2287 2288 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2289 dwc->gadget.ep0->maxpacket = 512; 2290 dwc->gadget.speed = USB_SPEED_SUPER; 2291 break; 2292 case DWC3_DCFG_HIGHSPEED: 2293 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2294 dwc->gadget.ep0->maxpacket = 64; 2295 dwc->gadget.speed = USB_SPEED_HIGH; 2296 break; 2297 case DWC3_DCFG_FULLSPEED2: 2298 case DWC3_DCFG_FULLSPEED1: 2299 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2300 dwc->gadget.ep0->maxpacket = 64; 2301 dwc->gadget.speed = USB_SPEED_FULL; 2302 break; 2303 case DWC3_DCFG_LOWSPEED: 2304 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2305 dwc->gadget.ep0->maxpacket = 8; 2306 dwc->gadget.speed = USB_SPEED_LOW; 2307 break; 2308 } 2309 2310 /* Enable USB2 LPM Capability */ 2311 2312 if ((dwc->revision > DWC3_REVISION_194A) 2313 && (speed != DWC3_DCFG_SUPERSPEED)) { 2314 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2315 reg |= DWC3_DCFG_LPM_CAP; 2316 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2317 2318 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2319 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2320 2321 /* 2322 * TODO: This should be configurable. For now using 2323 * maximum allowed HIRD threshold value of 0b1100 2324 */ 2325 reg |= DWC3_DCTL_HIRD_THRES(12); 2326 2327 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2328 } else { 2329 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2330 reg &= ~DWC3_DCTL_HIRD_THRES_MASK; 2331 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2332 } 2333 2334 dep = dwc->eps[0]; 2335 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, 2336 false); 2337 if (ret) { 2338 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2339 return; 2340 } 2341 2342 dep = dwc->eps[1]; 2343 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, 2344 false); 2345 if (ret) { 2346 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2347 return; 2348 } 2349 2350 /* 2351 * Configure PHY via GUSB3PIPECTLn if required. 2352 * 2353 * Update GTXFIFOSIZn 2354 * 2355 * In both cases reset values should be sufficient. 2356 */ 2357} 2358 2359static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2360{ 2361 dev_vdbg(dwc->dev, "%s\n", __func__); 2362 2363 /* 2364 * TODO take core out of low power mode when that's 2365 * implemented. 2366 */ 2367 2368 dwc->gadget_driver->resume(&dwc->gadget); 2369} 2370 2371static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2372 unsigned int evtinfo) 2373{ 2374 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2375 unsigned int pwropt; 2376 2377 /* 2378 * WORKAROUND: DWC3 < 2.50a have an issue when configured without 2379 * Hibernation mode enabled which would show up when device detects 2380 * host-initiated U3 exit. 2381 * 2382 * In that case, device will generate a Link State Change Interrupt 2383 * from U3 to RESUME which is only necessary if Hibernation is 2384 * configured in. 2385 * 2386 * There are no functional changes due to such spurious event and we 2387 * just need to ignore it. 2388 * 2389 * Refers to: 2390 * 2391 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation 2392 * operational mode 2393 */ 2394 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 2395 if ((dwc->revision < DWC3_REVISION_250A) && 2396 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { 2397 if ((dwc->link_state == DWC3_LINK_STATE_U3) && 2398 (next == DWC3_LINK_STATE_RESUME)) { 2399 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n"); 2400 return; 2401 } 2402 } 2403 2404 /* 2405 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2406 * on the link partner, the USB session might do multiple entry/exit 2407 * of low power states before a transfer takes place. 2408 * 2409 * Due to this problem, we might experience lower throughput. The 2410 * suggested workaround is to disable DCTL[12:9] bits if we're 2411 * transitioning from U1/U2 to U0 and enable those bits again 2412 * after a transfer completes and there are no pending transfers 2413 * on any of the enabled endpoints. 2414 * 2415 * This is the first half of that workaround. 2416 * 2417 * Refers to: 2418 * 2419 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2420 * core send LGO_Ux entering U0 2421 */ 2422 if (dwc->revision < DWC3_REVISION_183A) { 2423 if (next == DWC3_LINK_STATE_U0) { 2424 u32 u1u2; 2425 u32 reg; 2426 2427 switch (dwc->link_state) { 2428 case DWC3_LINK_STATE_U1: 2429 case DWC3_LINK_STATE_U2: 2430 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2431 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2432 | DWC3_DCTL_ACCEPTU2ENA 2433 | DWC3_DCTL_INITU1ENA 2434 | DWC3_DCTL_ACCEPTU1ENA); 2435 2436 if (!dwc->u1u2) 2437 dwc->u1u2 = reg & u1u2; 2438 2439 reg &= ~u1u2; 2440 2441 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2442 break; 2443 default: 2444 /* do nothing */ 2445 break; 2446 } 2447 } 2448 } 2449 2450 dwc->link_state = next; 2451 2452 switch (next) { 2453 case DWC3_LINK_STATE_U1: 2454 if (dwc->speed == USB_SPEED_SUPER) 2455 dwc3_suspend_gadget(dwc); 2456 break; 2457 case DWC3_LINK_STATE_U2: 2458 case DWC3_LINK_STATE_U3: 2459 dwc3_suspend_gadget(dwc); 2460 break; 2461 case DWC3_LINK_STATE_RESUME: 2462 dwc3_resume_gadget(dwc); 2463 break; 2464 default: 2465 /* do nothing */ 2466 break; 2467 } 2468 2469 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 2470} 2471 2472static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, 2473 unsigned int evtinfo) 2474{ 2475 unsigned int is_ss = evtinfo & BIT(4); 2476 2477 /** 2478 * WORKAROUND: DWC3 revison 2.20a with hibernation support 2479 * have a known issue which can cause USB CV TD.9.23 to fail 2480 * randomly. 2481 * 2482 * Because of this issue, core could generate bogus hibernation 2483 * events which SW needs to ignore. 2484 * 2485 * Refers to: 2486 * 2487 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 2488 * Device Fallback from SuperSpeed 2489 */ 2490 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) 2491 return; 2492 2493 /* enter hibernation here */ 2494} 2495 2496static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2497 const struct dwc3_event_devt *event) 2498{ 2499 switch (event->type) { 2500 case DWC3_DEVICE_EVENT_DISCONNECT: 2501 dwc3_gadget_disconnect_interrupt(dwc); 2502 break; 2503 case DWC3_DEVICE_EVENT_RESET: 2504 dwc3_gadget_reset_interrupt(dwc); 2505 break; 2506 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2507 dwc3_gadget_conndone_interrupt(dwc); 2508 break; 2509 case DWC3_DEVICE_EVENT_WAKEUP: 2510 dwc3_gadget_wakeup_interrupt(dwc); 2511 break; 2512 case DWC3_DEVICE_EVENT_HIBER_REQ: 2513 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, 2514 "unexpected hibernation event\n")) 2515 break; 2516 2517 dwc3_gadget_hibernation_interrupt(dwc, event->event_info); 2518 break; 2519 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2520 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2521 break; 2522 case DWC3_DEVICE_EVENT_EOPF: 2523 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2524 break; 2525 case DWC3_DEVICE_EVENT_SOF: 2526 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2527 break; 2528 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2529 dev_vdbg(dwc->dev, "Erratic Error\n"); 2530 break; 2531 case DWC3_DEVICE_EVENT_CMD_CMPL: 2532 dev_vdbg(dwc->dev, "Command Complete\n"); 2533 break; 2534 case DWC3_DEVICE_EVENT_OVERFLOW: 2535 dev_vdbg(dwc->dev, "Overflow\n"); 2536 break; 2537 default: 2538 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2539 } 2540} 2541 2542static void dwc3_process_event_entry(struct dwc3 *dwc, 2543 const union dwc3_event *event) 2544{ 2545 /* Endpoint IRQ, handle it and return early */ 2546 if (event->type.is_devspec == 0) { 2547 /* depevt */ 2548 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2549 } 2550 2551 switch (event->type.type) { 2552 case DWC3_EVENT_TYPE_DEV: 2553 dwc3_gadget_interrupt(dwc, &event->devt); 2554 break; 2555 /* REVISIT what to do with Carkit and I2C events ? */ 2556 default: 2557 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2558 } 2559} 2560 2561static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2562{ 2563 struct dwc3_event_buffer *evt; 2564 irqreturn_t ret = IRQ_NONE; 2565 int left; 2566 u32 reg; 2567 2568 evt = dwc->ev_buffs[buf]; 2569 left = evt->count; 2570 2571 if (!(evt->flags & DWC3_EVENT_PENDING)) 2572 return IRQ_NONE; 2573 2574 while (left > 0) { 2575 union dwc3_event event; 2576 2577 event.raw = *(u32 *) (evt->buf + evt->lpos); 2578 2579 dwc3_process_event_entry(dwc, &event); 2580 2581 /* 2582 * FIXME we wrap around correctly to the next entry as 2583 * almost all entries are 4 bytes in size. There is one 2584 * entry which has 12 bytes which is a regular entry 2585 * followed by 8 bytes data. ATM I don't know how 2586 * things are organized if we get next to the a 2587 * boundary so I worry about that once we try to handle 2588 * that. 2589 */ 2590 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2591 left -= 4; 2592 2593 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2594 } 2595 2596 evt->count = 0; 2597 evt->flags &= ~DWC3_EVENT_PENDING; 2598 ret = IRQ_HANDLED; 2599 2600 /* Unmask interrupt */ 2601 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); 2602 reg &= ~DWC3_GEVNTSIZ_INTMASK; 2603 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); 2604 2605 return ret; 2606} 2607 2608static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) 2609{ 2610 struct dwc3 *dwc = _dwc; 2611 unsigned long flags; 2612 irqreturn_t ret = IRQ_NONE; 2613 int i; 2614 2615 spin_lock_irqsave(&dwc->lock, flags); 2616 2617 for (i = 0; i < dwc->num_event_buffers; i++) 2618 ret |= dwc3_process_event_buf(dwc, i); 2619 2620 spin_unlock_irqrestore(&dwc->lock, flags); 2621 2622 return ret; 2623} 2624 2625static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) 2626{ 2627 struct dwc3_event_buffer *evt; 2628 u32 count; 2629 u32 reg; 2630 2631 evt = dwc->ev_buffs[buf]; 2632 2633 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2634 count &= DWC3_GEVNTCOUNT_MASK; 2635 if (!count) 2636 return IRQ_NONE; 2637 2638 evt->count = count; 2639 evt->flags |= DWC3_EVENT_PENDING; 2640 2641 /* Mask interrupt */ 2642 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); 2643 reg |= DWC3_GEVNTSIZ_INTMASK; 2644 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); 2645 2646 return IRQ_WAKE_THREAD; 2647} 2648 2649static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2650{ 2651 struct dwc3 *dwc = _dwc; 2652 int i; 2653 irqreturn_t ret = IRQ_NONE; 2654 2655 spin_lock(&dwc->lock); 2656 2657 for (i = 0; i < dwc->num_event_buffers; i++) { 2658 irqreturn_t status; 2659 2660 status = dwc3_check_event_buf(dwc, i); 2661 if (status == IRQ_WAKE_THREAD) 2662 ret = status; 2663 } 2664 2665 spin_unlock(&dwc->lock); 2666 2667 return ret; 2668} 2669 2670/** 2671 * dwc3_gadget_init - Initializes gadget related registers 2672 * @dwc: pointer to our controller context structure 2673 * 2674 * Returns 0 on success otherwise negative errno. 2675 */ 2676int dwc3_gadget_init(struct dwc3 *dwc) 2677{ 2678 int ret; 2679 2680 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2681 &dwc->ctrl_req_addr, GFP_KERNEL); 2682 if (!dwc->ctrl_req) { 2683 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2684 ret = -ENOMEM; 2685 goto err0; 2686 } 2687 2688 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2689 &dwc->ep0_trb_addr, GFP_KERNEL); 2690 if (!dwc->ep0_trb) { 2691 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2692 ret = -ENOMEM; 2693 goto err1; 2694 } 2695 2696 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); 2697 if (!dwc->setup_buf) { 2698 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2699 ret = -ENOMEM; 2700 goto err2; 2701 } 2702 2703 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2704 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, 2705 GFP_KERNEL); 2706 if (!dwc->ep0_bounce) { 2707 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2708 ret = -ENOMEM; 2709 goto err3; 2710 } 2711 2712 dwc->gadget.ops = &dwc3_gadget_ops; 2713 dwc->gadget.max_speed = USB_SPEED_SUPER; 2714 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2715 dwc->gadget.sg_supported = true; 2716 dwc->gadget.name = "dwc3-gadget"; 2717 2718 /* 2719 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize 2720 * on ep out. 2721 */ 2722 dwc->gadget.quirk_ep_out_aligned_size = true; 2723 2724 /* 2725 * REVISIT: Here we should clear all pending IRQs to be 2726 * sure we're starting from a well known location. 2727 */ 2728 2729 ret = dwc3_gadget_init_endpoints(dwc); 2730 if (ret) 2731 goto err4; 2732 2733 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2734 if (ret) { 2735 dev_err(dwc->dev, "failed to register udc\n"); 2736 goto err4; 2737 } 2738 2739 return 0; 2740 2741err4: 2742 dwc3_gadget_free_endpoints(dwc); 2743 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2744 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2745 2746err3: 2747 kfree(dwc->setup_buf); 2748 2749err2: 2750 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2751 dwc->ep0_trb, dwc->ep0_trb_addr); 2752 2753err1: 2754 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2755 dwc->ctrl_req, dwc->ctrl_req_addr); 2756 2757err0: 2758 return ret; 2759} 2760 2761/* -------------------------------------------------------------------------- */ 2762 2763void dwc3_gadget_exit(struct dwc3 *dwc) 2764{ 2765 usb_del_gadget_udc(&dwc->gadget); 2766 2767 dwc3_gadget_free_endpoints(dwc); 2768 2769 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2770 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2771 2772 kfree(dwc->setup_buf); 2773 2774 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2775 dwc->ep0_trb, dwc->ep0_trb_addr); 2776 2777 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2778 dwc->ctrl_req, dwc->ctrl_req_addr); 2779} 2780 2781int dwc3_gadget_prepare(struct dwc3 *dwc) 2782{ 2783 if (dwc->pullups_connected) { 2784 dwc3_gadget_disable_irq(dwc); 2785 dwc3_gadget_run_stop(dwc, true, true); 2786 } 2787 2788 return 0; 2789} 2790 2791void dwc3_gadget_complete(struct dwc3 *dwc) 2792{ 2793 if (dwc->pullups_connected) { 2794 dwc3_gadget_enable_irq(dwc); 2795 dwc3_gadget_run_stop(dwc, true, false); 2796 } 2797} 2798 2799int dwc3_gadget_suspend(struct dwc3 *dwc) 2800{ 2801 __dwc3_gadget_ep_disable(dwc->eps[0]); 2802 __dwc3_gadget_ep_disable(dwc->eps[1]); 2803 2804 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); 2805 2806 return 0; 2807} 2808 2809int dwc3_gadget_resume(struct dwc3 *dwc) 2810{ 2811 struct dwc3_ep *dep; 2812 int ret; 2813 2814 /* Start with SuperSpeed Default */ 2815 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2816 2817 dep = dwc->eps[0]; 2818 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 2819 false); 2820 if (ret) 2821 goto err0; 2822 2823 dep = dwc->eps[1]; 2824 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 2825 false); 2826 if (ret) 2827 goto err1; 2828 2829 /* begin to receive SETUP packets */ 2830 dwc->ep0state = EP0_SETUP_PHASE; 2831 dwc3_ep0_out_start(dwc); 2832 2833 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); 2834 2835 return 0; 2836 2837err1: 2838 __dwc3_gadget_ep_disable(dwc->eps[0]); 2839 2840err0: 2841 return ret; 2842} 2843