gadget.c revision bc5ba2e0b829c9397f96df1191c7d2319ebc36d9
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#include <linux/kernel.h> 20#include <linux/delay.h> 21#include <linux/slab.h> 22#include <linux/spinlock.h> 23#include <linux/platform_device.h> 24#include <linux/pm_runtime.h> 25#include <linux/interrupt.h> 26#include <linux/io.h> 27#include <linux/list.h> 28#include <linux/dma-mapping.h> 29 30#include <linux/usb/ch9.h> 31#include <linux/usb/gadget.h> 32 33#include "core.h" 34#include "gadget.h" 35#include "io.h" 36 37/** 38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 39 * @dwc: pointer to our context structure 40 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 41 * 42 * Caller should take care of locking. This function will 43 * return 0 on success or -EINVAL if wrong Test Selector 44 * is passed 45 */ 46int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 47{ 48 u32 reg; 49 50 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 51 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 52 53 switch (mode) { 54 case TEST_J: 55 case TEST_K: 56 case TEST_SE0_NAK: 57 case TEST_PACKET: 58 case TEST_FORCE_EN: 59 reg |= mode << 1; 60 break; 61 default: 62 return -EINVAL; 63 } 64 65 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 66 67 return 0; 68} 69 70/** 71 * dwc3_gadget_get_link_state - Gets current state of USB Link 72 * @dwc: pointer to our context structure 73 * 74 * Caller should take care of locking. This function will 75 * return the link state on success (>= 0) or -ETIMEDOUT. 76 */ 77int dwc3_gadget_get_link_state(struct dwc3 *dwc) 78{ 79 u32 reg; 80 81 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 82 83 return DWC3_DSTS_USBLNKST(reg); 84} 85 86/** 87 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 88 * @dwc: pointer to our context structure 89 * @state: the state to put link into 90 * 91 * Caller should take care of locking. This function will 92 * return 0 on success or -ETIMEDOUT. 93 */ 94int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 95{ 96 int retries = 10000; 97 u32 reg; 98 99 /* 100 * Wait until device controller is ready. Only applies to 1.94a and 101 * later RTL. 102 */ 103 if (dwc->revision >= DWC3_REVISION_194A) { 104 while (--retries) { 105 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 106 if (reg & DWC3_DSTS_DCNRD) 107 udelay(5); 108 else 109 break; 110 } 111 112 if (retries <= 0) 113 return -ETIMEDOUT; 114 } 115 116 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 118 119 /* set requested state */ 120 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 121 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 122 123 /* 124 * The following code is racy when called from dwc3_gadget_wakeup, 125 * and is not needed, at least on newer versions 126 */ 127 if (dwc->revision >= DWC3_REVISION_194A) 128 return 0; 129 130 /* wait for a change in DSTS */ 131 retries = 10000; 132 while (--retries) { 133 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 134 135 if (DWC3_DSTS_USBLNKST(reg) == state) 136 return 0; 137 138 udelay(5); 139 } 140 141 dev_vdbg(dwc->dev, "link state change request timed out\n"); 142 143 return -ETIMEDOUT; 144} 145 146/** 147 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 148 * @dwc: pointer to our context structure 149 * 150 * This function will a best effort FIFO allocation in order 151 * to improve FIFO usage and throughput, while still allowing 152 * us to enable as many endpoints as possible. 153 * 154 * Keep in mind that this operation will be highly dependent 155 * on the configured size for RAM1 - which contains TxFifo -, 156 * the amount of endpoints enabled on coreConsultant tool, and 157 * the width of the Master Bus. 158 * 159 * In the ideal world, we would always be able to satisfy the 160 * following equation: 161 * 162 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 163 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 164 * 165 * Unfortunately, due to many variables that's not always the case. 166 */ 167int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 168{ 169 int last_fifo_depth = 0; 170 int ram1_depth; 171 int fifo_size; 172 int mdwidth; 173 int num; 174 175 if (!dwc->needs_fifo_resize) 176 return 0; 177 178 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 179 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 180 181 /* MDWIDTH is represented in bits, we need it in bytes */ 182 mdwidth >>= 3; 183 184 /* 185 * FIXME For now we will only allocate 1 wMaxPacketSize space 186 * for each enabled endpoint, later patches will come to 187 * improve this algorithm so that we better use the internal 188 * FIFO space 189 */ 190 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { 191 struct dwc3_ep *dep = dwc->eps[num]; 192 int fifo_number = dep->number >> 1; 193 int mult = 1; 194 int tmp; 195 196 if (!(dep->number & 1)) 197 continue; 198 199 if (!(dep->flags & DWC3_EP_ENABLED)) 200 continue; 201 202 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) 203 || usb_endpoint_xfer_isoc(dep->endpoint.desc)) 204 mult = 3; 205 206 /* 207 * REVISIT: the following assumes we will always have enough 208 * space available on the FIFO RAM for all possible use cases. 209 * Make sure that's true somehow and change FIFO allocation 210 * accordingly. 211 * 212 * If we have Bulk or Isochronous endpoints, we want 213 * them to be able to be very, very fast. So we're giving 214 * those endpoints a fifo_size which is enough for 3 full 215 * packets 216 */ 217 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 218 tmp += mdwidth; 219 220 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 221 222 fifo_size |= (last_fifo_depth << 16); 223 224 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 225 dep->name, last_fifo_depth, fifo_size & 0xffff); 226 227 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), 228 fifo_size); 229 230 last_fifo_depth += (fifo_size & 0xffff); 231 } 232 233 return 0; 234} 235 236void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 237 int status) 238{ 239 struct dwc3 *dwc = dep->dwc; 240 int i; 241 242 if (req->queued) { 243 i = 0; 244 do { 245 dep->busy_slot++; 246 /* 247 * Skip LINK TRB. We can't use req->trb and check for 248 * DWC3_TRBCTL_LINK_TRB because it points the TRB we 249 * just completed (not the LINK TRB). 250 */ 251 if (((dep->busy_slot & DWC3_TRB_MASK) == 252 DWC3_TRB_NUM- 1) && 253 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 254 dep->busy_slot++; 255 } while(++i < req->request.num_mapped_sgs); 256 req->queued = false; 257 } 258 list_del(&req->list); 259 req->trb = NULL; 260 261 if (req->request.status == -EINPROGRESS) 262 req->request.status = status; 263 264 if (dwc->ep0_bounced && dep->number == 0) 265 dwc->ep0_bounced = false; 266 else 267 usb_gadget_unmap_request(&dwc->gadget, &req->request, 268 req->direction); 269 270 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 271 req, dep->name, req->request.actual, 272 req->request.length, status); 273 274 spin_unlock(&dwc->lock); 275 req->request.complete(&dep->endpoint, &req->request); 276 spin_lock(&dwc->lock); 277} 278 279static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 280{ 281 switch (cmd) { 282 case DWC3_DEPCMD_DEPSTARTCFG: 283 return "Start New Configuration"; 284 case DWC3_DEPCMD_ENDTRANSFER: 285 return "End Transfer"; 286 case DWC3_DEPCMD_UPDATETRANSFER: 287 return "Update Transfer"; 288 case DWC3_DEPCMD_STARTTRANSFER: 289 return "Start Transfer"; 290 case DWC3_DEPCMD_CLEARSTALL: 291 return "Clear Stall"; 292 case DWC3_DEPCMD_SETSTALL: 293 return "Set Stall"; 294 case DWC3_DEPCMD_GETEPSTATE: 295 return "Get Endpoint State"; 296 case DWC3_DEPCMD_SETTRANSFRESOURCE: 297 return "Set Endpoint Transfer Resource"; 298 case DWC3_DEPCMD_SETEPCONFIG: 299 return "Set Endpoint Configuration"; 300 default: 301 return "UNKNOWN command"; 302 } 303} 304 305int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) 306{ 307 u32 timeout = 500; 308 u32 reg; 309 310 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 311 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 312 313 do { 314 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 315 if (!(reg & DWC3_DGCMD_CMDACT)) { 316 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 317 DWC3_DGCMD_STATUS(reg)); 318 return 0; 319 } 320 321 /* 322 * We can't sleep here, because it's also called from 323 * interrupt context. 324 */ 325 timeout--; 326 if (!timeout) 327 return -ETIMEDOUT; 328 udelay(1); 329 } while (1); 330} 331 332int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 333 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 334{ 335 struct dwc3_ep *dep = dwc->eps[ep]; 336 u32 timeout = 500; 337 u32 reg; 338 339 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 340 dep->name, 341 dwc3_gadget_ep_cmd_string(cmd), params->param0, 342 params->param1, params->param2); 343 344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 346 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 347 348 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 349 do { 350 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 351 if (!(reg & DWC3_DEPCMD_CMDACT)) { 352 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 353 DWC3_DEPCMD_STATUS(reg)); 354 return 0; 355 } 356 357 /* 358 * We can't sleep here, because it is also called from 359 * interrupt context. 360 */ 361 timeout--; 362 if (!timeout) 363 return -ETIMEDOUT; 364 365 udelay(1); 366 } while (1); 367} 368 369static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 370 struct dwc3_trb *trb) 371{ 372 u32 offset = (char *) trb - (char *) dep->trb_pool; 373 374 return dep->trb_pool_dma + offset; 375} 376 377static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 378{ 379 struct dwc3 *dwc = dep->dwc; 380 381 if (dep->trb_pool) 382 return 0; 383 384 if (dep->number == 0 || dep->number == 1) 385 return 0; 386 387 dep->trb_pool = dma_alloc_coherent(dwc->dev, 388 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 389 &dep->trb_pool_dma, GFP_KERNEL); 390 if (!dep->trb_pool) { 391 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 392 dep->name); 393 return -ENOMEM; 394 } 395 396 return 0; 397} 398 399static void dwc3_free_trb_pool(struct dwc3_ep *dep) 400{ 401 struct dwc3 *dwc = dep->dwc; 402 403 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 404 dep->trb_pool, dep->trb_pool_dma); 405 406 dep->trb_pool = NULL; 407 dep->trb_pool_dma = 0; 408} 409 410static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 411{ 412 struct dwc3_gadget_ep_cmd_params params; 413 u32 cmd; 414 415 memset(¶ms, 0x00, sizeof(params)); 416 417 if (dep->number != 1) { 418 cmd = DWC3_DEPCMD_DEPSTARTCFG; 419 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 420 if (dep->number > 1) { 421 if (dwc->start_config_issued) 422 return 0; 423 dwc->start_config_issued = true; 424 cmd |= DWC3_DEPCMD_PARAM(2); 425 } 426 427 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 428 } 429 430 return 0; 431} 432 433static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 434 const struct usb_endpoint_descriptor *desc, 435 const struct usb_ss_ep_comp_descriptor *comp_desc, 436 bool ignore, bool restore) 437{ 438 struct dwc3_gadget_ep_cmd_params params; 439 440 memset(¶ms, 0x00, sizeof(params)); 441 442 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 443 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); 444 445 /* Burst size is only needed in SuperSpeed mode */ 446 if (dwc->gadget.speed == USB_SPEED_SUPER) { 447 u32 burst = dep->endpoint.maxburst - 1; 448 449 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); 450 } 451 452 if (ignore) 453 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; 454 455 if (restore) { 456 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; 457 params.param2 |= dep->saved_state; 458 } 459 460 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 461 | DWC3_DEPCFG_XFER_NOT_READY_EN; 462 463 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 464 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 465 | DWC3_DEPCFG_STREAM_EVENT_EN; 466 dep->stream_capable = true; 467 } 468 469 if (usb_endpoint_xfer_isoc(desc)) 470 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 471 472 /* 473 * We are doing 1:1 mapping for endpoints, meaning 474 * Physical Endpoints 2 maps to Logical Endpoint 2 and 475 * so on. We consider the direction bit as part of the physical 476 * endpoint number. So USB endpoint 0x81 is 0x03. 477 */ 478 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 479 480 /* 481 * We must use the lower 16 TX FIFOs even though 482 * HW might have more 483 */ 484 if (dep->direction) 485 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 486 487 if (desc->bInterval) { 488 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 489 dep->interval = 1 << (desc->bInterval - 1); 490 } 491 492 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 493 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 494} 495 496static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 497{ 498 struct dwc3_gadget_ep_cmd_params params; 499 500 memset(¶ms, 0x00, sizeof(params)); 501 502 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 503 504 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 505 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 506} 507 508/** 509 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 510 * @dep: endpoint to be initialized 511 * @desc: USB Endpoint Descriptor 512 * 513 * Caller should take care of locking 514 */ 515static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 516 const struct usb_endpoint_descriptor *desc, 517 const struct usb_ss_ep_comp_descriptor *comp_desc, 518 bool ignore, bool restore) 519{ 520 struct dwc3 *dwc = dep->dwc; 521 u32 reg; 522 int ret = -ENOMEM; 523 524 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 525 526 if (!(dep->flags & DWC3_EP_ENABLED)) { 527 ret = dwc3_gadget_start_config(dwc, dep); 528 if (ret) 529 return ret; 530 } 531 532 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, 533 restore); 534 if (ret) 535 return ret; 536 537 if (!(dep->flags & DWC3_EP_ENABLED)) { 538 struct dwc3_trb *trb_st_hw; 539 struct dwc3_trb *trb_link; 540 541 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 542 if (ret) 543 return ret; 544 545 dep->endpoint.desc = desc; 546 dep->comp_desc = comp_desc; 547 dep->type = usb_endpoint_type(desc); 548 dep->flags |= DWC3_EP_ENABLED; 549 550 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 551 reg |= DWC3_DALEPENA_EP(dep->number); 552 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 553 554 if (!usb_endpoint_xfer_isoc(desc)) 555 return 0; 556 557 memset(&trb_link, 0, sizeof(trb_link)); 558 559 /* Link TRB for ISOC. The HWO bit is never reset */ 560 trb_st_hw = &dep->trb_pool[0]; 561 562 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 563 564 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 565 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 566 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 567 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 568 } 569 570 return 0; 571} 572 573static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); 574static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 575{ 576 struct dwc3_request *req; 577 578 if (!list_empty(&dep->req_queued)) { 579 dwc3_stop_active_transfer(dwc, dep->number, true); 580 581 /* - giveback all requests to gadget driver */ 582 while (!list_empty(&dep->req_queued)) { 583 req = next_request(&dep->req_queued); 584 585 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 586 } 587 } 588 589 while (!list_empty(&dep->request_list)) { 590 req = next_request(&dep->request_list); 591 592 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 593 } 594} 595 596/** 597 * __dwc3_gadget_ep_disable - Disables a HW endpoint 598 * @dep: the endpoint to disable 599 * 600 * This function also removes requests which are currently processed ny the 601 * hardware and those which are not yet scheduled. 602 * Caller should take care of locking. 603 */ 604static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 605{ 606 struct dwc3 *dwc = dep->dwc; 607 u32 reg; 608 609 dwc3_remove_requests(dwc, dep); 610 611 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 612 reg &= ~DWC3_DALEPENA_EP(dep->number); 613 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 614 615 dep->stream_capable = false; 616 dep->endpoint.desc = NULL; 617 dep->comp_desc = NULL; 618 dep->type = 0; 619 dep->flags = 0; 620 621 return 0; 622} 623 624/* -------------------------------------------------------------------------- */ 625 626static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 627 const struct usb_endpoint_descriptor *desc) 628{ 629 return -EINVAL; 630} 631 632static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 633{ 634 return -EINVAL; 635} 636 637/* -------------------------------------------------------------------------- */ 638 639static int dwc3_gadget_ep_enable(struct usb_ep *ep, 640 const struct usb_endpoint_descriptor *desc) 641{ 642 struct dwc3_ep *dep; 643 struct dwc3 *dwc; 644 unsigned long flags; 645 int ret; 646 647 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 648 pr_debug("dwc3: invalid parameters\n"); 649 return -EINVAL; 650 } 651 652 if (!desc->wMaxPacketSize) { 653 pr_debug("dwc3: missing wMaxPacketSize\n"); 654 return -EINVAL; 655 } 656 657 dep = to_dwc3_ep(ep); 658 dwc = dep->dwc; 659 660 if (dep->flags & DWC3_EP_ENABLED) { 661 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 662 dep->name); 663 return 0; 664 } 665 666 switch (usb_endpoint_type(desc)) { 667 case USB_ENDPOINT_XFER_CONTROL: 668 strlcat(dep->name, "-control", sizeof(dep->name)); 669 break; 670 case USB_ENDPOINT_XFER_ISOC: 671 strlcat(dep->name, "-isoc", sizeof(dep->name)); 672 break; 673 case USB_ENDPOINT_XFER_BULK: 674 strlcat(dep->name, "-bulk", sizeof(dep->name)); 675 break; 676 case USB_ENDPOINT_XFER_INT: 677 strlcat(dep->name, "-int", sizeof(dep->name)); 678 break; 679 default: 680 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 681 } 682 683 spin_lock_irqsave(&dwc->lock, flags); 684 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); 685 spin_unlock_irqrestore(&dwc->lock, flags); 686 687 return ret; 688} 689 690static int dwc3_gadget_ep_disable(struct usb_ep *ep) 691{ 692 struct dwc3_ep *dep; 693 struct dwc3 *dwc; 694 unsigned long flags; 695 int ret; 696 697 if (!ep) { 698 pr_debug("dwc3: invalid parameters\n"); 699 return -EINVAL; 700 } 701 702 dep = to_dwc3_ep(ep); 703 dwc = dep->dwc; 704 705 if (!(dep->flags & DWC3_EP_ENABLED)) { 706 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 707 dep->name); 708 return 0; 709 } 710 711 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 712 dep->number >> 1, 713 (dep->number & 1) ? "in" : "out"); 714 715 spin_lock_irqsave(&dwc->lock, flags); 716 ret = __dwc3_gadget_ep_disable(dep); 717 spin_unlock_irqrestore(&dwc->lock, flags); 718 719 return ret; 720} 721 722static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 723 gfp_t gfp_flags) 724{ 725 struct dwc3_request *req; 726 struct dwc3_ep *dep = to_dwc3_ep(ep); 727 struct dwc3 *dwc = dep->dwc; 728 729 req = kzalloc(sizeof(*req), gfp_flags); 730 if (!req) { 731 dev_err(dwc->dev, "not enough memory\n"); 732 return NULL; 733 } 734 735 req->epnum = dep->number; 736 req->dep = dep; 737 738 return &req->request; 739} 740 741static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 742 struct usb_request *request) 743{ 744 struct dwc3_request *req = to_dwc3_request(request); 745 746 kfree(req); 747} 748 749/** 750 * dwc3_prepare_one_trb - setup one TRB from one request 751 * @dep: endpoint for which this request is prepared 752 * @req: dwc3_request pointer 753 */ 754static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 755 struct dwc3_request *req, dma_addr_t dma, 756 unsigned length, unsigned last, unsigned chain, unsigned node) 757{ 758 struct dwc3 *dwc = dep->dwc; 759 struct dwc3_trb *trb; 760 761 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 762 dep->name, req, (unsigned long long) dma, 763 length, last ? " last" : "", 764 chain ? " chain" : ""); 765 766 /* Skip the LINK-TRB on ISOC */ 767 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 768 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 769 dep->free_slot++; 770 771 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 772 773 if (!req->trb) { 774 dwc3_gadget_move_request_queued(req); 775 req->trb = trb; 776 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 777 req->start_slot = dep->free_slot & DWC3_TRB_MASK; 778 } 779 780 dep->free_slot++; 781 782 trb->size = DWC3_TRB_SIZE_LENGTH(length); 783 trb->bpl = lower_32_bits(dma); 784 trb->bph = upper_32_bits(dma); 785 786 switch (usb_endpoint_type(dep->endpoint.desc)) { 787 case USB_ENDPOINT_XFER_CONTROL: 788 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 789 break; 790 791 case USB_ENDPOINT_XFER_ISOC: 792 if (!node) 793 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 794 else 795 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; 796 break; 797 798 case USB_ENDPOINT_XFER_BULK: 799 case USB_ENDPOINT_XFER_INT: 800 trb->ctrl = DWC3_TRBCTL_NORMAL; 801 break; 802 default: 803 /* 804 * This is only possible with faulty memory because we 805 * checked it already :) 806 */ 807 BUG(); 808 } 809 810 if (!req->request.no_interrupt && !chain) 811 trb->ctrl |= DWC3_TRB_CTRL_IOC; 812 813 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 814 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 815 trb->ctrl |= DWC3_TRB_CTRL_CSP; 816 } else if (last) { 817 trb->ctrl |= DWC3_TRB_CTRL_LST; 818 } 819 820 if (chain) 821 trb->ctrl |= DWC3_TRB_CTRL_CHN; 822 823 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 824 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); 825 826 trb->ctrl |= DWC3_TRB_CTRL_HWO; 827} 828 829/* 830 * dwc3_prepare_trbs - setup TRBs from requests 831 * @dep: endpoint for which requests are being prepared 832 * @starting: true if the endpoint is idle and no requests are queued. 833 * 834 * The function goes through the requests list and sets up TRBs for the 835 * transfers. The function returns once there are no more TRBs available or 836 * it runs out of requests. 837 */ 838static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 839{ 840 struct dwc3_request *req, *n; 841 u32 trbs_left; 842 u32 max; 843 unsigned int last_one = 0; 844 845 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 846 847 /* the first request must not be queued */ 848 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 849 850 /* Can't wrap around on a non-isoc EP since there's no link TRB */ 851 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 852 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); 853 if (trbs_left > max) 854 trbs_left = max; 855 } 856 857 /* 858 * If busy & slot are equal than it is either full or empty. If we are 859 * starting to process requests then we are empty. Otherwise we are 860 * full and don't do anything 861 */ 862 if (!trbs_left) { 863 if (!starting) 864 return; 865 trbs_left = DWC3_TRB_NUM; 866 /* 867 * In case we start from scratch, we queue the ISOC requests 868 * starting from slot 1. This is done because we use ring 869 * buffer and have no LST bit to stop us. Instead, we place 870 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt 871 * after the first request so we start at slot 1 and have 872 * 7 requests proceed before we hit the first IOC. 873 * Other transfer types don't use the ring buffer and are 874 * processed from the first TRB until the last one. Since we 875 * don't wrap around we have to start at the beginning. 876 */ 877 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 878 dep->busy_slot = 1; 879 dep->free_slot = 1; 880 } else { 881 dep->busy_slot = 0; 882 dep->free_slot = 0; 883 } 884 } 885 886 /* The last TRB is a link TRB, not used for xfer */ 887 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) 888 return; 889 890 list_for_each_entry_safe(req, n, &dep->request_list, list) { 891 unsigned length; 892 dma_addr_t dma; 893 last_one = false; 894 895 if (req->request.num_mapped_sgs > 0) { 896 struct usb_request *request = &req->request; 897 struct scatterlist *sg = request->sg; 898 struct scatterlist *s; 899 int i; 900 901 for_each_sg(sg, s, request->num_mapped_sgs, i) { 902 unsigned chain = true; 903 904 length = sg_dma_len(s); 905 dma = sg_dma_address(s); 906 907 if (i == (request->num_mapped_sgs - 1) || 908 sg_is_last(s)) { 909 if (list_is_last(&req->list, 910 &dep->request_list)) 911 last_one = true; 912 chain = false; 913 } 914 915 trbs_left--; 916 if (!trbs_left) 917 last_one = true; 918 919 if (last_one) 920 chain = false; 921 922 dwc3_prepare_one_trb(dep, req, dma, length, 923 last_one, chain, i); 924 925 if (last_one) 926 break; 927 } 928 } else { 929 dma = req->request.dma; 930 length = req->request.length; 931 trbs_left--; 932 933 if (!trbs_left) 934 last_one = 1; 935 936 /* Is this the last request? */ 937 if (list_is_last(&req->list, &dep->request_list)) 938 last_one = 1; 939 940 dwc3_prepare_one_trb(dep, req, dma, length, 941 last_one, false, 0); 942 943 if (last_one) 944 break; 945 } 946 } 947} 948 949static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 950 int start_new) 951{ 952 struct dwc3_gadget_ep_cmd_params params; 953 struct dwc3_request *req; 954 struct dwc3 *dwc = dep->dwc; 955 int ret; 956 u32 cmd; 957 958 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 959 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 960 return -EBUSY; 961 } 962 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 963 964 /* 965 * If we are getting here after a short-out-packet we don't enqueue any 966 * new requests as we try to set the IOC bit only on the last request. 967 */ 968 if (start_new) { 969 if (list_empty(&dep->req_queued)) 970 dwc3_prepare_trbs(dep, start_new); 971 972 /* req points to the first request which will be sent */ 973 req = next_request(&dep->req_queued); 974 } else { 975 dwc3_prepare_trbs(dep, start_new); 976 977 /* 978 * req points to the first request where HWO changed from 0 to 1 979 */ 980 req = next_request(&dep->req_queued); 981 } 982 if (!req) { 983 dep->flags |= DWC3_EP_PENDING_REQUEST; 984 return 0; 985 } 986 987 memset(¶ms, 0, sizeof(params)); 988 989 if (start_new) { 990 params.param0 = upper_32_bits(req->trb_dma); 991 params.param1 = lower_32_bits(req->trb_dma); 992 cmd = DWC3_DEPCMD_STARTTRANSFER; 993 } else { 994 cmd = DWC3_DEPCMD_UPDATETRANSFER; 995 } 996 997 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 998 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 999 if (ret < 0) { 1000 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 1001 1002 /* 1003 * FIXME we need to iterate over the list of requests 1004 * here and stop, unmap, free and del each of the linked 1005 * requests instead of what we do now. 1006 */ 1007 usb_gadget_unmap_request(&dwc->gadget, &req->request, 1008 req->direction); 1009 list_del(&req->list); 1010 return ret; 1011 } 1012 1013 dep->flags |= DWC3_EP_BUSY; 1014 1015 if (start_new) { 1016 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 1017 dep->number); 1018 WARN_ON_ONCE(!dep->resource_index); 1019 } 1020 1021 return 0; 1022} 1023 1024static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, 1025 struct dwc3_ep *dep, u32 cur_uf) 1026{ 1027 u32 uf; 1028 1029 if (list_empty(&dep->request_list)) { 1030 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1031 dep->name); 1032 dep->flags |= DWC3_EP_PENDING_REQUEST; 1033 return; 1034 } 1035 1036 /* 4 micro frames in the future */ 1037 uf = cur_uf + dep->interval * 4; 1038 1039 __dwc3_gadget_kick_transfer(dep, uf, 1); 1040} 1041 1042static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1043 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1044{ 1045 u32 cur_uf, mask; 1046 1047 mask = ~(dep->interval - 1); 1048 cur_uf = event->parameters & mask; 1049 1050 __dwc3_gadget_start_isoc(dwc, dep, cur_uf); 1051} 1052 1053static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 1054{ 1055 struct dwc3 *dwc = dep->dwc; 1056 int ret; 1057 1058 req->request.actual = 0; 1059 req->request.status = -EINPROGRESS; 1060 req->direction = dep->direction; 1061 req->epnum = dep->number; 1062 1063 /* 1064 * We only add to our list of requests now and 1065 * start consuming the list once we get XferNotReady 1066 * IRQ. 1067 * 1068 * That way, we avoid doing anything that we don't need 1069 * to do now and defer it until the point we receive a 1070 * particular token from the Host side. 1071 * 1072 * This will also avoid Host cancelling URBs due to too 1073 * many NAKs. 1074 */ 1075 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1076 dep->direction); 1077 if (ret) 1078 return ret; 1079 1080 list_add_tail(&req->list, &dep->request_list); 1081 1082 /* 1083 * There are a few special cases: 1084 * 1085 * 1. XferNotReady with empty list of requests. We need to kick the 1086 * transfer here in that situation, otherwise we will be NAKing 1087 * forever. If we get XferNotReady before gadget driver has a 1088 * chance to queue a request, we will ACK the IRQ but won't be 1089 * able to receive the data until the next request is queued. 1090 * The following code is handling exactly that. 1091 * 1092 */ 1093 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1094 /* 1095 * If xfernotready is already elapsed and it is a case 1096 * of isoc transfer, then issue END TRANSFER, so that 1097 * you can receive xfernotready again and can have 1098 * notion of current microframe. 1099 */ 1100 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1101 if (list_empty(&dep->req_queued)) { 1102 dwc3_stop_active_transfer(dwc, dep->number, true); 1103 dep->flags = DWC3_EP_ENABLED; 1104 } 1105 return 0; 1106 } 1107 1108 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1109 if (ret && ret != -EBUSY) 1110 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1111 dep->name); 1112 return ret; 1113 } 1114 1115 /* 1116 * 2. XferInProgress on Isoc EP with an active transfer. We need to 1117 * kick the transfer here after queuing a request, otherwise the 1118 * core may not see the modified TRB(s). 1119 */ 1120 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1121 (dep->flags & DWC3_EP_BUSY) && 1122 !(dep->flags & DWC3_EP_MISSED_ISOC)) { 1123 WARN_ON_ONCE(!dep->resource_index); 1124 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, 1125 false); 1126 if (ret && ret != -EBUSY) 1127 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1128 dep->name); 1129 return ret; 1130 } 1131 1132 return 0; 1133} 1134 1135static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1136 gfp_t gfp_flags) 1137{ 1138 struct dwc3_request *req = to_dwc3_request(request); 1139 struct dwc3_ep *dep = to_dwc3_ep(ep); 1140 struct dwc3 *dwc = dep->dwc; 1141 1142 unsigned long flags; 1143 1144 int ret; 1145 1146 if (!dep->endpoint.desc) { 1147 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1148 request, ep->name); 1149 return -ESHUTDOWN; 1150 } 1151 1152 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1153 request, ep->name, request->length); 1154 1155 spin_lock_irqsave(&dwc->lock, flags); 1156 ret = __dwc3_gadget_ep_queue(dep, req); 1157 spin_unlock_irqrestore(&dwc->lock, flags); 1158 1159 return ret; 1160} 1161 1162static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1163 struct usb_request *request) 1164{ 1165 struct dwc3_request *req = to_dwc3_request(request); 1166 struct dwc3_request *r = NULL; 1167 1168 struct dwc3_ep *dep = to_dwc3_ep(ep); 1169 struct dwc3 *dwc = dep->dwc; 1170 1171 unsigned long flags; 1172 int ret = 0; 1173 1174 spin_lock_irqsave(&dwc->lock, flags); 1175 1176 list_for_each_entry(r, &dep->request_list, list) { 1177 if (r == req) 1178 break; 1179 } 1180 1181 if (r != req) { 1182 list_for_each_entry(r, &dep->req_queued, list) { 1183 if (r == req) 1184 break; 1185 } 1186 if (r == req) { 1187 /* wait until it is processed */ 1188 dwc3_stop_active_transfer(dwc, dep->number, true); 1189 goto out1; 1190 } 1191 dev_err(dwc->dev, "request %p was not queued to %s\n", 1192 request, ep->name); 1193 ret = -EINVAL; 1194 goto out0; 1195 } 1196 1197out1: 1198 /* giveback the request */ 1199 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1200 1201out0: 1202 spin_unlock_irqrestore(&dwc->lock, flags); 1203 1204 return ret; 1205} 1206 1207int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1208{ 1209 struct dwc3_gadget_ep_cmd_params params; 1210 struct dwc3 *dwc = dep->dwc; 1211 int ret; 1212 1213 memset(¶ms, 0x00, sizeof(params)); 1214 1215 if (value) { 1216 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1217 DWC3_DEPCMD_SETSTALL, ¶ms); 1218 if (ret) 1219 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1220 value ? "set" : "clear", 1221 dep->name); 1222 else 1223 dep->flags |= DWC3_EP_STALL; 1224 } else { 1225 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1226 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1227 if (ret) 1228 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1229 value ? "set" : "clear", 1230 dep->name); 1231 else 1232 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); 1233 } 1234 1235 return ret; 1236} 1237 1238static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1239{ 1240 struct dwc3_ep *dep = to_dwc3_ep(ep); 1241 struct dwc3 *dwc = dep->dwc; 1242 1243 unsigned long flags; 1244 1245 int ret; 1246 1247 spin_lock_irqsave(&dwc->lock, flags); 1248 1249 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1250 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1251 ret = -EINVAL; 1252 goto out; 1253 } 1254 1255 ret = __dwc3_gadget_ep_set_halt(dep, value); 1256out: 1257 spin_unlock_irqrestore(&dwc->lock, flags); 1258 1259 return ret; 1260} 1261 1262static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1263{ 1264 struct dwc3_ep *dep = to_dwc3_ep(ep); 1265 struct dwc3 *dwc = dep->dwc; 1266 unsigned long flags; 1267 1268 spin_lock_irqsave(&dwc->lock, flags); 1269 dep->flags |= DWC3_EP_WEDGE; 1270 spin_unlock_irqrestore(&dwc->lock, flags); 1271 1272 if (dep->number == 0 || dep->number == 1) 1273 return dwc3_gadget_ep0_set_halt(ep, 1); 1274 else 1275 return dwc3_gadget_ep_set_halt(ep, 1); 1276} 1277 1278/* -------------------------------------------------------------------------- */ 1279 1280static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1281 .bLength = USB_DT_ENDPOINT_SIZE, 1282 .bDescriptorType = USB_DT_ENDPOINT, 1283 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1284}; 1285 1286static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1287 .enable = dwc3_gadget_ep0_enable, 1288 .disable = dwc3_gadget_ep0_disable, 1289 .alloc_request = dwc3_gadget_ep_alloc_request, 1290 .free_request = dwc3_gadget_ep_free_request, 1291 .queue = dwc3_gadget_ep0_queue, 1292 .dequeue = dwc3_gadget_ep_dequeue, 1293 .set_halt = dwc3_gadget_ep0_set_halt, 1294 .set_wedge = dwc3_gadget_ep_set_wedge, 1295}; 1296 1297static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1298 .enable = dwc3_gadget_ep_enable, 1299 .disable = dwc3_gadget_ep_disable, 1300 .alloc_request = dwc3_gadget_ep_alloc_request, 1301 .free_request = dwc3_gadget_ep_free_request, 1302 .queue = dwc3_gadget_ep_queue, 1303 .dequeue = dwc3_gadget_ep_dequeue, 1304 .set_halt = dwc3_gadget_ep_set_halt, 1305 .set_wedge = dwc3_gadget_ep_set_wedge, 1306}; 1307 1308/* -------------------------------------------------------------------------- */ 1309 1310static int dwc3_gadget_get_frame(struct usb_gadget *g) 1311{ 1312 struct dwc3 *dwc = gadget_to_dwc(g); 1313 u32 reg; 1314 1315 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1316 return DWC3_DSTS_SOFFN(reg); 1317} 1318 1319static int dwc3_gadget_wakeup(struct usb_gadget *g) 1320{ 1321 struct dwc3 *dwc = gadget_to_dwc(g); 1322 1323 unsigned long timeout; 1324 unsigned long flags; 1325 1326 u32 reg; 1327 1328 int ret = 0; 1329 1330 u8 link_state; 1331 u8 speed; 1332 1333 spin_lock_irqsave(&dwc->lock, flags); 1334 1335 /* 1336 * According to the Databook Remote wakeup request should 1337 * be issued only when the device is in early suspend state. 1338 * 1339 * We can check that via USB Link State bits in DSTS register. 1340 */ 1341 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1342 1343 speed = reg & DWC3_DSTS_CONNECTSPD; 1344 if (speed == DWC3_DSTS_SUPERSPEED) { 1345 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1346 ret = -EINVAL; 1347 goto out; 1348 } 1349 1350 link_state = DWC3_DSTS_USBLNKST(reg); 1351 1352 switch (link_state) { 1353 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1354 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1355 break; 1356 default: 1357 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1358 link_state); 1359 ret = -EINVAL; 1360 goto out; 1361 } 1362 1363 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1364 if (ret < 0) { 1365 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1366 goto out; 1367 } 1368 1369 /* Recent versions do this automatically */ 1370 if (dwc->revision < DWC3_REVISION_194A) { 1371 /* write zeroes to Link Change Request */ 1372 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1373 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1374 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1375 } 1376 1377 /* poll until Link State changes to ON */ 1378 timeout = jiffies + msecs_to_jiffies(100); 1379 1380 while (!time_after(jiffies, timeout)) { 1381 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1382 1383 /* in HS, means ON */ 1384 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1385 break; 1386 } 1387 1388 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1389 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1390 ret = -EINVAL; 1391 } 1392 1393out: 1394 spin_unlock_irqrestore(&dwc->lock, flags); 1395 1396 return ret; 1397} 1398 1399static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1400 int is_selfpowered) 1401{ 1402 struct dwc3 *dwc = gadget_to_dwc(g); 1403 unsigned long flags; 1404 1405 spin_lock_irqsave(&dwc->lock, flags); 1406 dwc->is_selfpowered = !!is_selfpowered; 1407 spin_unlock_irqrestore(&dwc->lock, flags); 1408 1409 return 0; 1410} 1411 1412static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) 1413{ 1414 u32 reg; 1415 u32 timeout = 500; 1416 1417 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1418 if (is_on) { 1419 if (dwc->revision <= DWC3_REVISION_187A) { 1420 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1421 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1422 } 1423 1424 if (dwc->revision >= DWC3_REVISION_194A) 1425 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1426 reg |= DWC3_DCTL_RUN_STOP; 1427 1428 if (dwc->has_hibernation) 1429 reg |= DWC3_DCTL_KEEP_CONNECT; 1430 1431 dwc->pullups_connected = true; 1432 } else { 1433 reg &= ~DWC3_DCTL_RUN_STOP; 1434 1435 if (dwc->has_hibernation && !suspend) 1436 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1437 1438 dwc->pullups_connected = false; 1439 } 1440 1441 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1442 1443 do { 1444 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1445 if (is_on) { 1446 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1447 break; 1448 } else { 1449 if (reg & DWC3_DSTS_DEVCTRLHLT) 1450 break; 1451 } 1452 timeout--; 1453 if (!timeout) 1454 return -ETIMEDOUT; 1455 udelay(1); 1456 } while (1); 1457 1458 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1459 dwc->gadget_driver 1460 ? dwc->gadget_driver->function : "no-function", 1461 is_on ? "connect" : "disconnect"); 1462 1463 return 0; 1464} 1465 1466static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1467{ 1468 struct dwc3 *dwc = gadget_to_dwc(g); 1469 unsigned long flags; 1470 int ret; 1471 1472 is_on = !!is_on; 1473 1474 spin_lock_irqsave(&dwc->lock, flags); 1475 ret = dwc3_gadget_run_stop(dwc, is_on, false); 1476 spin_unlock_irqrestore(&dwc->lock, flags); 1477 1478 return ret; 1479} 1480 1481static void dwc3_gadget_enable_irq(struct dwc3 *dwc) 1482{ 1483 u32 reg; 1484 1485 /* Enable all but Start and End of Frame IRQs */ 1486 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 1487 DWC3_DEVTEN_EVNTOVERFLOWEN | 1488 DWC3_DEVTEN_CMDCMPLTEN | 1489 DWC3_DEVTEN_ERRTICERREN | 1490 DWC3_DEVTEN_WKUPEVTEN | 1491 DWC3_DEVTEN_ULSTCNGEN | 1492 DWC3_DEVTEN_CONNECTDONEEN | 1493 DWC3_DEVTEN_USBRSTEN | 1494 DWC3_DEVTEN_DISCONNEVTEN); 1495 1496 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 1497} 1498 1499static void dwc3_gadget_disable_irq(struct dwc3 *dwc) 1500{ 1501 /* mask all interrupts */ 1502 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 1503} 1504 1505static irqreturn_t dwc3_interrupt(int irq, void *_dwc); 1506static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); 1507 1508static int dwc3_gadget_start(struct usb_gadget *g, 1509 struct usb_gadget_driver *driver) 1510{ 1511 struct dwc3 *dwc = gadget_to_dwc(g); 1512 struct dwc3_ep *dep; 1513 unsigned long flags; 1514 int ret = 0; 1515 int irq; 1516 u32 reg; 1517 1518 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1519 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, 1520 IRQF_SHARED, "dwc3", dwc); 1521 if (ret) { 1522 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 1523 irq, ret); 1524 goto err0; 1525 } 1526 1527 spin_lock_irqsave(&dwc->lock, flags); 1528 1529 if (dwc->gadget_driver) { 1530 dev_err(dwc->dev, "%s is already bound to %s\n", 1531 dwc->gadget.name, 1532 dwc->gadget_driver->driver.name); 1533 ret = -EBUSY; 1534 goto err1; 1535 } 1536 1537 dwc->gadget_driver = driver; 1538 1539 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1540 reg &= ~(DWC3_DCFG_SPEED_MASK); 1541 1542 /** 1543 * WORKAROUND: DWC3 revision < 2.20a have an issue 1544 * which would cause metastability state on Run/Stop 1545 * bit if we try to force the IP to USB2-only mode. 1546 * 1547 * Because of that, we cannot configure the IP to any 1548 * speed other than the SuperSpeed 1549 * 1550 * Refers to: 1551 * 1552 * STAR#9000525659: Clock Domain Crossing on DCTL in 1553 * USB 2.0 Mode 1554 */ 1555 if (dwc->revision < DWC3_REVISION_220A) { 1556 reg |= DWC3_DCFG_SUPERSPEED; 1557 } else { 1558 switch (dwc->maximum_speed) { 1559 case USB_SPEED_LOW: 1560 reg |= DWC3_DSTS_LOWSPEED; 1561 break; 1562 case USB_SPEED_FULL: 1563 reg |= DWC3_DSTS_FULLSPEED1; 1564 break; 1565 case USB_SPEED_HIGH: 1566 reg |= DWC3_DSTS_HIGHSPEED; 1567 break; 1568 case USB_SPEED_SUPER: /* FALLTHROUGH */ 1569 case USB_SPEED_UNKNOWN: /* FALTHROUGH */ 1570 default: 1571 reg |= DWC3_DSTS_SUPERSPEED; 1572 } 1573 } 1574 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1575 1576 dwc->start_config_issued = false; 1577 1578 /* Start with SuperSpeed Default */ 1579 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1580 1581 dep = dwc->eps[0]; 1582 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 1583 false); 1584 if (ret) { 1585 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1586 goto err2; 1587 } 1588 1589 dep = dwc->eps[1]; 1590 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 1591 false); 1592 if (ret) { 1593 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1594 goto err3; 1595 } 1596 1597 /* begin to receive SETUP packets */ 1598 dwc->ep0state = EP0_SETUP_PHASE; 1599 dwc3_ep0_out_start(dwc); 1600 1601 dwc3_gadget_enable_irq(dwc); 1602 1603 spin_unlock_irqrestore(&dwc->lock, flags); 1604 1605 return 0; 1606 1607err3: 1608 __dwc3_gadget_ep_disable(dwc->eps[0]); 1609 1610err2: 1611 dwc->gadget_driver = NULL; 1612 1613err1: 1614 spin_unlock_irqrestore(&dwc->lock, flags); 1615 1616 free_irq(irq, dwc); 1617 1618err0: 1619 return ret; 1620} 1621 1622static int dwc3_gadget_stop(struct usb_gadget *g, 1623 struct usb_gadget_driver *driver) 1624{ 1625 struct dwc3 *dwc = gadget_to_dwc(g); 1626 unsigned long flags; 1627 int irq; 1628 1629 spin_lock_irqsave(&dwc->lock, flags); 1630 1631 dwc3_gadget_disable_irq(dwc); 1632 __dwc3_gadget_ep_disable(dwc->eps[0]); 1633 __dwc3_gadget_ep_disable(dwc->eps[1]); 1634 1635 dwc->gadget_driver = NULL; 1636 1637 spin_unlock_irqrestore(&dwc->lock, flags); 1638 1639 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1640 free_irq(irq, dwc); 1641 1642 return 0; 1643} 1644 1645static const struct usb_gadget_ops dwc3_gadget_ops = { 1646 .get_frame = dwc3_gadget_get_frame, 1647 .wakeup = dwc3_gadget_wakeup, 1648 .set_selfpowered = dwc3_gadget_set_selfpowered, 1649 .pullup = dwc3_gadget_pullup, 1650 .udc_start = dwc3_gadget_start, 1651 .udc_stop = dwc3_gadget_stop, 1652}; 1653 1654/* -------------------------------------------------------------------------- */ 1655 1656static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, 1657 u8 num, u32 direction) 1658{ 1659 struct dwc3_ep *dep; 1660 u8 i; 1661 1662 for (i = 0; i < num; i++) { 1663 u8 epnum = (i << 1) | (!!direction); 1664 1665 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1666 if (!dep) { 1667 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1668 epnum); 1669 return -ENOMEM; 1670 } 1671 1672 dep->dwc = dwc; 1673 dep->number = epnum; 1674 dep->direction = !!direction; 1675 dwc->eps[epnum] = dep; 1676 1677 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1678 (epnum & 1) ? "in" : "out"); 1679 1680 dep->endpoint.name = dep->name; 1681 1682 dev_vdbg(dwc->dev, "initializing %s\n", dep->name); 1683 1684 if (epnum == 0 || epnum == 1) { 1685 usb_ep_set_maxpacket_limit(&dep->endpoint, 512); 1686 dep->endpoint.maxburst = 1; 1687 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1688 if (!epnum) 1689 dwc->gadget.ep0 = &dep->endpoint; 1690 } else { 1691 int ret; 1692 1693 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); 1694 dep->endpoint.max_streams = 15; 1695 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1696 list_add_tail(&dep->endpoint.ep_list, 1697 &dwc->gadget.ep_list); 1698 1699 ret = dwc3_alloc_trb_pool(dep); 1700 if (ret) 1701 return ret; 1702 } 1703 1704 INIT_LIST_HEAD(&dep->request_list); 1705 INIT_LIST_HEAD(&dep->req_queued); 1706 } 1707 1708 return 0; 1709} 1710 1711static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1712{ 1713 int ret; 1714 1715 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1716 1717 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); 1718 if (ret < 0) { 1719 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n"); 1720 return ret; 1721 } 1722 1723 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); 1724 if (ret < 0) { 1725 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n"); 1726 return ret; 1727 } 1728 1729 return 0; 1730} 1731 1732static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1733{ 1734 struct dwc3_ep *dep; 1735 u8 epnum; 1736 1737 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1738 dep = dwc->eps[epnum]; 1739 if (!dep) 1740 continue; 1741 /* 1742 * Physical endpoints 0 and 1 are special; they form the 1743 * bi-directional USB endpoint 0. 1744 * 1745 * For those two physical endpoints, we don't allocate a TRB 1746 * pool nor do we add them the endpoints list. Due to that, we 1747 * shouldn't do these two operations otherwise we would end up 1748 * with all sorts of bugs when removing dwc3.ko. 1749 */ 1750 if (epnum != 0 && epnum != 1) { 1751 dwc3_free_trb_pool(dep); 1752 list_del(&dep->endpoint.ep_list); 1753 } 1754 1755 kfree(dep); 1756 } 1757} 1758 1759/* -------------------------------------------------------------------------- */ 1760 1761static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, 1762 struct dwc3_request *req, struct dwc3_trb *trb, 1763 const struct dwc3_event_depevt *event, int status) 1764{ 1765 unsigned int count; 1766 unsigned int s_pkt = 0; 1767 unsigned int trb_status; 1768 1769 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 1770 /* 1771 * We continue despite the error. There is not much we 1772 * can do. If we don't clean it up we loop forever. If 1773 * we skip the TRB then it gets overwritten after a 1774 * while since we use them in a ring buffer. A BUG() 1775 * would help. Lets hope that if this occurs, someone 1776 * fixes the root cause instead of looking away :) 1777 */ 1778 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1779 dep->name, trb); 1780 count = trb->size & DWC3_TRB_SIZE_MASK; 1781 1782 if (dep->direction) { 1783 if (count) { 1784 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); 1785 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { 1786 dev_dbg(dwc->dev, "incomplete IN transfer %s\n", 1787 dep->name); 1788 /* 1789 * If missed isoc occurred and there is 1790 * no request queued then issue END 1791 * TRANSFER, so that core generates 1792 * next xfernotready and we will issue 1793 * a fresh START TRANSFER. 1794 * If there are still queued request 1795 * then wait, do not issue either END 1796 * or UPDATE TRANSFER, just attach next 1797 * request in request_list during 1798 * giveback.If any future queued request 1799 * is successfully transferred then we 1800 * will issue UPDATE TRANSFER for all 1801 * request in the request_list. 1802 */ 1803 dep->flags |= DWC3_EP_MISSED_ISOC; 1804 } else { 1805 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1806 dep->name); 1807 status = -ECONNRESET; 1808 } 1809 } else { 1810 dep->flags &= ~DWC3_EP_MISSED_ISOC; 1811 } 1812 } else { 1813 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1814 s_pkt = 1; 1815 } 1816 1817 /* 1818 * We assume here we will always receive the entire data block 1819 * which we should receive. Meaning, if we program RX to 1820 * receive 4K but we receive only 2K, we assume that's all we 1821 * should receive and we simply bounce the request back to the 1822 * gadget driver for further processing. 1823 */ 1824 req->request.actual += req->request.length - count; 1825 if (s_pkt) 1826 return 1; 1827 if ((event->status & DEPEVT_STATUS_LST) && 1828 (trb->ctrl & (DWC3_TRB_CTRL_LST | 1829 DWC3_TRB_CTRL_HWO))) 1830 return 1; 1831 if ((event->status & DEPEVT_STATUS_IOC) && 1832 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1833 return 1; 1834 return 0; 1835} 1836 1837static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1838 const struct dwc3_event_depevt *event, int status) 1839{ 1840 struct dwc3_request *req; 1841 struct dwc3_trb *trb; 1842 unsigned int slot; 1843 unsigned int i; 1844 int ret; 1845 1846 do { 1847 req = next_request(&dep->req_queued); 1848 if (!req) { 1849 WARN_ON_ONCE(1); 1850 return 1; 1851 } 1852 i = 0; 1853 do { 1854 slot = req->start_slot + i; 1855 if ((slot == DWC3_TRB_NUM - 1) && 1856 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 1857 slot++; 1858 slot %= DWC3_TRB_NUM; 1859 trb = &dep->trb_pool[slot]; 1860 1861 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, 1862 event, status); 1863 if (ret) 1864 break; 1865 }while (++i < req->request.num_mapped_sgs); 1866 1867 dwc3_gadget_giveback(dep, req, status); 1868 1869 if (ret) 1870 break; 1871 } while (1); 1872 1873 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1874 list_empty(&dep->req_queued)) { 1875 if (list_empty(&dep->request_list)) { 1876 /* 1877 * If there is no entry in request list then do 1878 * not issue END TRANSFER now. Just set PENDING 1879 * flag, so that END TRANSFER is issued when an 1880 * entry is added into request list. 1881 */ 1882 dep->flags = DWC3_EP_PENDING_REQUEST; 1883 } else { 1884 dwc3_stop_active_transfer(dwc, dep->number, true); 1885 dep->flags = DWC3_EP_ENABLED; 1886 } 1887 return 1; 1888 } 1889 1890 return 1; 1891} 1892 1893static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1894 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1895 int start_new) 1896{ 1897 unsigned status = 0; 1898 int clean_busy; 1899 1900 if (event->status & DEPEVT_STATUS_BUSERR) 1901 status = -ECONNRESET; 1902 1903 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1904 if (clean_busy) 1905 dep->flags &= ~DWC3_EP_BUSY; 1906 1907 /* 1908 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1909 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1910 */ 1911 if (dwc->revision < DWC3_REVISION_183A) { 1912 u32 reg; 1913 int i; 1914 1915 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1916 dep = dwc->eps[i]; 1917 1918 if (!(dep->flags & DWC3_EP_ENABLED)) 1919 continue; 1920 1921 if (!list_empty(&dep->req_queued)) 1922 return; 1923 } 1924 1925 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1926 reg |= dwc->u1u2; 1927 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1928 1929 dwc->u1u2 = 0; 1930 } 1931} 1932 1933static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1934 const struct dwc3_event_depevt *event) 1935{ 1936 struct dwc3_ep *dep; 1937 u8 epnum = event->endpoint_number; 1938 1939 dep = dwc->eps[epnum]; 1940 1941 if (!(dep->flags & DWC3_EP_ENABLED)) 1942 return; 1943 1944 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1945 dwc3_ep_event_string(event->endpoint_event)); 1946 1947 if (epnum == 0 || epnum == 1) { 1948 dwc3_ep0_interrupt(dwc, event); 1949 return; 1950 } 1951 1952 switch (event->endpoint_event) { 1953 case DWC3_DEPEVT_XFERCOMPLETE: 1954 dep->resource_index = 0; 1955 1956 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1957 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1958 dep->name); 1959 return; 1960 } 1961 1962 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1963 break; 1964 case DWC3_DEPEVT_XFERINPROGRESS: 1965 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1966 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1967 dep->name); 1968 return; 1969 } 1970 1971 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1972 break; 1973 case DWC3_DEPEVT_XFERNOTREADY: 1974 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1975 dwc3_gadget_start_isoc(dwc, dep, event); 1976 } else { 1977 int ret; 1978 1979 dev_vdbg(dwc->dev, "%s: reason %s\n", 1980 dep->name, event->status & 1981 DEPEVT_STATUS_TRANSFER_ACTIVE 1982 ? "Transfer Active" 1983 : "Transfer Not Active"); 1984 1985 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1986 if (!ret || ret == -EBUSY) 1987 return; 1988 1989 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1990 dep->name); 1991 } 1992 1993 break; 1994 case DWC3_DEPEVT_STREAMEVT: 1995 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { 1996 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1997 dep->name); 1998 return; 1999 } 2000 2001 switch (event->status) { 2002 case DEPEVT_STREAMEVT_FOUND: 2003 dev_vdbg(dwc->dev, "Stream %d found and started\n", 2004 event->parameters); 2005 2006 break; 2007 case DEPEVT_STREAMEVT_NOTFOUND: 2008 /* FALLTHROUGH */ 2009 default: 2010 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 2011 } 2012 break; 2013 case DWC3_DEPEVT_RXTXFIFOEVT: 2014 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 2015 break; 2016 case DWC3_DEPEVT_EPCMDCMPLT: 2017 dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); 2018 break; 2019 } 2020} 2021 2022static void dwc3_disconnect_gadget(struct dwc3 *dwc) 2023{ 2024 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 2025 spin_unlock(&dwc->lock); 2026 dwc->gadget_driver->disconnect(&dwc->gadget); 2027 spin_lock(&dwc->lock); 2028 } 2029} 2030 2031static void dwc3_suspend_gadget(struct dwc3 *dwc) 2032{ 2033 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 2034 spin_unlock(&dwc->lock); 2035 dwc->gadget_driver->suspend(&dwc->gadget); 2036 spin_lock(&dwc->lock); 2037 } 2038} 2039 2040static void dwc3_resume_gadget(struct dwc3 *dwc) 2041{ 2042 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 2043 spin_unlock(&dwc->lock); 2044 dwc->gadget_driver->resume(&dwc->gadget); 2045 spin_lock(&dwc->lock); 2046 } 2047} 2048 2049static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) 2050{ 2051 struct dwc3_ep *dep; 2052 struct dwc3_gadget_ep_cmd_params params; 2053 u32 cmd; 2054 int ret; 2055 2056 dep = dwc->eps[epnum]; 2057 2058 if (!dep->resource_index) 2059 return; 2060 2061 /* 2062 * NOTICE: We are violating what the Databook says about the 2063 * EndTransfer command. Ideally we would _always_ wait for the 2064 * EndTransfer Command Completion IRQ, but that's causing too 2065 * much trouble synchronizing between us and gadget driver. 2066 * 2067 * We have discussed this with the IP Provider and it was 2068 * suggested to giveback all requests here, but give HW some 2069 * extra time to synchronize with the interconnect. We're using 2070 * an arbitraty 100us delay for that. 2071 * 2072 * Note also that a similar handling was tested by Synopsys 2073 * (thanks a lot Paul) and nothing bad has come out of it. 2074 * In short, what we're doing is: 2075 * 2076 * - Issue EndTransfer WITH CMDIOC bit set 2077 * - Wait 100us 2078 */ 2079 2080 cmd = DWC3_DEPCMD_ENDTRANSFER; 2081 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; 2082 cmd |= DWC3_DEPCMD_CMDIOC; 2083 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 2084 memset(¶ms, 0, sizeof(params)); 2085 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 2086 WARN_ON_ONCE(ret); 2087 dep->resource_index = 0; 2088 dep->flags &= ~DWC3_EP_BUSY; 2089 udelay(100); 2090} 2091 2092static void dwc3_stop_active_transfers(struct dwc3 *dwc) 2093{ 2094 u32 epnum; 2095 2096 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2097 struct dwc3_ep *dep; 2098 2099 dep = dwc->eps[epnum]; 2100 if (!dep) 2101 continue; 2102 2103 if (!(dep->flags & DWC3_EP_ENABLED)) 2104 continue; 2105 2106 dwc3_remove_requests(dwc, dep); 2107 } 2108} 2109 2110static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 2111{ 2112 u32 epnum; 2113 2114 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2115 struct dwc3_ep *dep; 2116 struct dwc3_gadget_ep_cmd_params params; 2117 int ret; 2118 2119 dep = dwc->eps[epnum]; 2120 if (!dep) 2121 continue; 2122 2123 if (!(dep->flags & DWC3_EP_STALL)) 2124 continue; 2125 2126 dep->flags &= ~DWC3_EP_STALL; 2127 2128 memset(¶ms, 0, sizeof(params)); 2129 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 2130 DWC3_DEPCMD_CLEARSTALL, ¶ms); 2131 WARN_ON_ONCE(ret); 2132 } 2133} 2134 2135static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 2136{ 2137 int reg; 2138 2139 dev_vdbg(dwc->dev, "%s\n", __func__); 2140 2141 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2142 reg &= ~DWC3_DCTL_INITU1ENA; 2143 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2144 2145 reg &= ~DWC3_DCTL_INITU2ENA; 2146 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2147 2148 dwc3_disconnect_gadget(dwc); 2149 dwc->start_config_issued = false; 2150 2151 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2152 dwc->setup_packet_pending = false; 2153} 2154 2155static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 2156{ 2157 u32 reg; 2158 2159 dev_vdbg(dwc->dev, "%s\n", __func__); 2160 2161 /* 2162 * WORKAROUND: DWC3 revisions <1.88a have an issue which 2163 * would cause a missing Disconnect Event if there's a 2164 * pending Setup Packet in the FIFO. 2165 * 2166 * There's no suggested workaround on the official Bug 2167 * report, which states that "unless the driver/application 2168 * is doing any special handling of a disconnect event, 2169 * there is no functional issue". 2170 * 2171 * Unfortunately, it turns out that we _do_ some special 2172 * handling of a disconnect event, namely complete all 2173 * pending transfers, notify gadget driver of the 2174 * disconnection, and so on. 2175 * 2176 * Our suggested workaround is to follow the Disconnect 2177 * Event steps here, instead, based on a setup_packet_pending 2178 * flag. Such flag gets set whenever we have a XferNotReady 2179 * event on EP0 and gets cleared on XferComplete for the 2180 * same endpoint. 2181 * 2182 * Refers to: 2183 * 2184 * STAR#9000466709: RTL: Device : Disconnect event not 2185 * generated if setup packet pending in FIFO 2186 */ 2187 if (dwc->revision < DWC3_REVISION_188A) { 2188 if (dwc->setup_packet_pending) 2189 dwc3_gadget_disconnect_interrupt(dwc); 2190 } 2191 2192 /* after reset -> Default State */ 2193 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 2194 2195 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 2196 dwc3_disconnect_gadget(dwc); 2197 2198 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2199 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2200 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2201 dwc->test_mode = false; 2202 2203 dwc3_stop_active_transfers(dwc); 2204 dwc3_clear_stall_all_ep(dwc); 2205 dwc->start_config_issued = false; 2206 2207 /* Reset device address to zero */ 2208 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2209 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2210 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2211} 2212 2213static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 2214{ 2215 u32 reg; 2216 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 2217 2218 /* 2219 * We change the clock only at SS but I dunno why I would want to do 2220 * this. Maybe it becomes part of the power saving plan. 2221 */ 2222 2223 if (speed != DWC3_DSTS_SUPERSPEED) 2224 return; 2225 2226 /* 2227 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2228 * each time on Connect Done. 2229 */ 2230 if (!usb30_clock) 2231 return; 2232 2233 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 2234 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 2235 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 2236} 2237 2238static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2239{ 2240 struct dwc3_ep *dep; 2241 int ret; 2242 u32 reg; 2243 u8 speed; 2244 2245 dev_vdbg(dwc->dev, "%s\n", __func__); 2246 2247 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2248 speed = reg & DWC3_DSTS_CONNECTSPD; 2249 dwc->speed = speed; 2250 2251 dwc3_update_ram_clk_sel(dwc, speed); 2252 2253 switch (speed) { 2254 case DWC3_DCFG_SUPERSPEED: 2255 /* 2256 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2257 * would cause a missing USB3 Reset event. 2258 * 2259 * In such situations, we should force a USB3 Reset 2260 * event by calling our dwc3_gadget_reset_interrupt() 2261 * routine. 2262 * 2263 * Refers to: 2264 * 2265 * STAR#9000483510: RTL: SS : USB3 reset event may 2266 * not be generated always when the link enters poll 2267 */ 2268 if (dwc->revision < DWC3_REVISION_190A) 2269 dwc3_gadget_reset_interrupt(dwc); 2270 2271 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2272 dwc->gadget.ep0->maxpacket = 512; 2273 dwc->gadget.speed = USB_SPEED_SUPER; 2274 break; 2275 case DWC3_DCFG_HIGHSPEED: 2276 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2277 dwc->gadget.ep0->maxpacket = 64; 2278 dwc->gadget.speed = USB_SPEED_HIGH; 2279 break; 2280 case DWC3_DCFG_FULLSPEED2: 2281 case DWC3_DCFG_FULLSPEED1: 2282 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2283 dwc->gadget.ep0->maxpacket = 64; 2284 dwc->gadget.speed = USB_SPEED_FULL; 2285 break; 2286 case DWC3_DCFG_LOWSPEED: 2287 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2288 dwc->gadget.ep0->maxpacket = 8; 2289 dwc->gadget.speed = USB_SPEED_LOW; 2290 break; 2291 } 2292 2293 /* Enable USB2 LPM Capability */ 2294 2295 if ((dwc->revision > DWC3_REVISION_194A) 2296 && (speed != DWC3_DCFG_SUPERSPEED)) { 2297 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2298 reg |= DWC3_DCFG_LPM_CAP; 2299 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2300 2301 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2302 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2303 2304 /* 2305 * TODO: This should be configurable. For now using 2306 * maximum allowed HIRD threshold value of 0b1100 2307 */ 2308 reg |= DWC3_DCTL_HIRD_THRES(12); 2309 2310 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2311 } else { 2312 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2313 reg &= ~DWC3_DCTL_HIRD_THRES_MASK; 2314 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2315 } 2316 2317 dep = dwc->eps[0]; 2318 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, 2319 false); 2320 if (ret) { 2321 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2322 return; 2323 } 2324 2325 dep = dwc->eps[1]; 2326 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, 2327 false); 2328 if (ret) { 2329 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2330 return; 2331 } 2332 2333 /* 2334 * Configure PHY via GUSB3PIPECTLn if required. 2335 * 2336 * Update GTXFIFOSIZn 2337 * 2338 * In both cases reset values should be sufficient. 2339 */ 2340} 2341 2342static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2343{ 2344 dev_vdbg(dwc->dev, "%s\n", __func__); 2345 2346 /* 2347 * TODO take core out of low power mode when that's 2348 * implemented. 2349 */ 2350 2351 dwc->gadget_driver->resume(&dwc->gadget); 2352} 2353 2354static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2355 unsigned int evtinfo) 2356{ 2357 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2358 unsigned int pwropt; 2359 2360 /* 2361 * WORKAROUND: DWC3 < 2.50a have an issue when configured without 2362 * Hibernation mode enabled which would show up when device detects 2363 * host-initiated U3 exit. 2364 * 2365 * In that case, device will generate a Link State Change Interrupt 2366 * from U3 to RESUME which is only necessary if Hibernation is 2367 * configured in. 2368 * 2369 * There are no functional changes due to such spurious event and we 2370 * just need to ignore it. 2371 * 2372 * Refers to: 2373 * 2374 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation 2375 * operational mode 2376 */ 2377 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 2378 if ((dwc->revision < DWC3_REVISION_250A) && 2379 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { 2380 if ((dwc->link_state == DWC3_LINK_STATE_U3) && 2381 (next == DWC3_LINK_STATE_RESUME)) { 2382 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n"); 2383 return; 2384 } 2385 } 2386 2387 /* 2388 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2389 * on the link partner, the USB session might do multiple entry/exit 2390 * of low power states before a transfer takes place. 2391 * 2392 * Due to this problem, we might experience lower throughput. The 2393 * suggested workaround is to disable DCTL[12:9] bits if we're 2394 * transitioning from U1/U2 to U0 and enable those bits again 2395 * after a transfer completes and there are no pending transfers 2396 * on any of the enabled endpoints. 2397 * 2398 * This is the first half of that workaround. 2399 * 2400 * Refers to: 2401 * 2402 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2403 * core send LGO_Ux entering U0 2404 */ 2405 if (dwc->revision < DWC3_REVISION_183A) { 2406 if (next == DWC3_LINK_STATE_U0) { 2407 u32 u1u2; 2408 u32 reg; 2409 2410 switch (dwc->link_state) { 2411 case DWC3_LINK_STATE_U1: 2412 case DWC3_LINK_STATE_U2: 2413 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2414 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2415 | DWC3_DCTL_ACCEPTU2ENA 2416 | DWC3_DCTL_INITU1ENA 2417 | DWC3_DCTL_ACCEPTU1ENA); 2418 2419 if (!dwc->u1u2) 2420 dwc->u1u2 = reg & u1u2; 2421 2422 reg &= ~u1u2; 2423 2424 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2425 break; 2426 default: 2427 /* do nothing */ 2428 break; 2429 } 2430 } 2431 } 2432 2433 dwc->link_state = next; 2434 2435 switch (next) { 2436 case DWC3_LINK_STATE_U1: 2437 if (dwc->speed == USB_SPEED_SUPER) 2438 dwc3_suspend_gadget(dwc); 2439 break; 2440 case DWC3_LINK_STATE_U2: 2441 case DWC3_LINK_STATE_U3: 2442 dwc3_suspend_gadget(dwc); 2443 break; 2444 case DWC3_LINK_STATE_RESUME: 2445 dwc3_resume_gadget(dwc); 2446 break; 2447 default: 2448 /* do nothing */ 2449 break; 2450 } 2451 2452 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 2453} 2454 2455static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, 2456 unsigned int evtinfo) 2457{ 2458 unsigned int is_ss = evtinfo & BIT(4); 2459 2460 /** 2461 * WORKAROUND: DWC3 revison 2.20a with hibernation support 2462 * have a known issue which can cause USB CV TD.9.23 to fail 2463 * randomly. 2464 * 2465 * Because of this issue, core could generate bogus hibernation 2466 * events which SW needs to ignore. 2467 * 2468 * Refers to: 2469 * 2470 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 2471 * Device Fallback from SuperSpeed 2472 */ 2473 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) 2474 return; 2475 2476 /* enter hibernation here */ 2477} 2478 2479static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2480 const struct dwc3_event_devt *event) 2481{ 2482 switch (event->type) { 2483 case DWC3_DEVICE_EVENT_DISCONNECT: 2484 dwc3_gadget_disconnect_interrupt(dwc); 2485 break; 2486 case DWC3_DEVICE_EVENT_RESET: 2487 dwc3_gadget_reset_interrupt(dwc); 2488 break; 2489 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2490 dwc3_gadget_conndone_interrupt(dwc); 2491 break; 2492 case DWC3_DEVICE_EVENT_WAKEUP: 2493 dwc3_gadget_wakeup_interrupt(dwc); 2494 break; 2495 case DWC3_DEVICE_EVENT_HIBER_REQ: 2496 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, 2497 "unexpected hibernation event\n")) 2498 break; 2499 2500 dwc3_gadget_hibernation_interrupt(dwc, event->event_info); 2501 break; 2502 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2503 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2504 break; 2505 case DWC3_DEVICE_EVENT_EOPF: 2506 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2507 break; 2508 case DWC3_DEVICE_EVENT_SOF: 2509 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2510 break; 2511 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2512 dev_vdbg(dwc->dev, "Erratic Error\n"); 2513 break; 2514 case DWC3_DEVICE_EVENT_CMD_CMPL: 2515 dev_vdbg(dwc->dev, "Command Complete\n"); 2516 break; 2517 case DWC3_DEVICE_EVENT_OVERFLOW: 2518 dev_vdbg(dwc->dev, "Overflow\n"); 2519 break; 2520 default: 2521 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2522 } 2523} 2524 2525static void dwc3_process_event_entry(struct dwc3 *dwc, 2526 const union dwc3_event *event) 2527{ 2528 /* Endpoint IRQ, handle it and return early */ 2529 if (event->type.is_devspec == 0) { 2530 /* depevt */ 2531 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2532 } 2533 2534 switch (event->type.type) { 2535 case DWC3_EVENT_TYPE_DEV: 2536 dwc3_gadget_interrupt(dwc, &event->devt); 2537 break; 2538 /* REVISIT what to do with Carkit and I2C events ? */ 2539 default: 2540 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2541 } 2542} 2543 2544static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2545{ 2546 struct dwc3_event_buffer *evt; 2547 irqreturn_t ret = IRQ_NONE; 2548 int left; 2549 u32 reg; 2550 2551 evt = dwc->ev_buffs[buf]; 2552 left = evt->count; 2553 2554 if (!(evt->flags & DWC3_EVENT_PENDING)) 2555 return IRQ_NONE; 2556 2557 while (left > 0) { 2558 union dwc3_event event; 2559 2560 event.raw = *(u32 *) (evt->buf + evt->lpos); 2561 2562 dwc3_process_event_entry(dwc, &event); 2563 2564 /* 2565 * FIXME we wrap around correctly to the next entry as 2566 * almost all entries are 4 bytes in size. There is one 2567 * entry which has 12 bytes which is a regular entry 2568 * followed by 8 bytes data. ATM I don't know how 2569 * things are organized if we get next to the a 2570 * boundary so I worry about that once we try to handle 2571 * that. 2572 */ 2573 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2574 left -= 4; 2575 2576 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2577 } 2578 2579 evt->count = 0; 2580 evt->flags &= ~DWC3_EVENT_PENDING; 2581 ret = IRQ_HANDLED; 2582 2583 /* Unmask interrupt */ 2584 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); 2585 reg &= ~DWC3_GEVNTSIZ_INTMASK; 2586 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); 2587 2588 return ret; 2589} 2590 2591static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) 2592{ 2593 struct dwc3 *dwc = _dwc; 2594 unsigned long flags; 2595 irqreturn_t ret = IRQ_NONE; 2596 int i; 2597 2598 spin_lock_irqsave(&dwc->lock, flags); 2599 2600 for (i = 0; i < dwc->num_event_buffers; i++) 2601 ret |= dwc3_process_event_buf(dwc, i); 2602 2603 spin_unlock_irqrestore(&dwc->lock, flags); 2604 2605 return ret; 2606} 2607 2608static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) 2609{ 2610 struct dwc3_event_buffer *evt; 2611 u32 count; 2612 u32 reg; 2613 2614 evt = dwc->ev_buffs[buf]; 2615 2616 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2617 count &= DWC3_GEVNTCOUNT_MASK; 2618 if (!count) 2619 return IRQ_NONE; 2620 2621 evt->count = count; 2622 evt->flags |= DWC3_EVENT_PENDING; 2623 2624 /* Mask interrupt */ 2625 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); 2626 reg |= DWC3_GEVNTSIZ_INTMASK; 2627 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); 2628 2629 return IRQ_WAKE_THREAD; 2630} 2631 2632static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2633{ 2634 struct dwc3 *dwc = _dwc; 2635 int i; 2636 irqreturn_t ret = IRQ_NONE; 2637 2638 spin_lock(&dwc->lock); 2639 2640 for (i = 0; i < dwc->num_event_buffers; i++) { 2641 irqreturn_t status; 2642 2643 status = dwc3_check_event_buf(dwc, i); 2644 if (status == IRQ_WAKE_THREAD) 2645 ret = status; 2646 } 2647 2648 spin_unlock(&dwc->lock); 2649 2650 return ret; 2651} 2652 2653/** 2654 * dwc3_gadget_init - Initializes gadget related registers 2655 * @dwc: pointer to our controller context structure 2656 * 2657 * Returns 0 on success otherwise negative errno. 2658 */ 2659int dwc3_gadget_init(struct dwc3 *dwc) 2660{ 2661 int ret; 2662 2663 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2664 &dwc->ctrl_req_addr, GFP_KERNEL); 2665 if (!dwc->ctrl_req) { 2666 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2667 ret = -ENOMEM; 2668 goto err0; 2669 } 2670 2671 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2672 &dwc->ep0_trb_addr, GFP_KERNEL); 2673 if (!dwc->ep0_trb) { 2674 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2675 ret = -ENOMEM; 2676 goto err1; 2677 } 2678 2679 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); 2680 if (!dwc->setup_buf) { 2681 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2682 ret = -ENOMEM; 2683 goto err2; 2684 } 2685 2686 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2687 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, 2688 GFP_KERNEL); 2689 if (!dwc->ep0_bounce) { 2690 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2691 ret = -ENOMEM; 2692 goto err3; 2693 } 2694 2695 dwc->gadget.ops = &dwc3_gadget_ops; 2696 dwc->gadget.max_speed = USB_SPEED_SUPER; 2697 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2698 dwc->gadget.sg_supported = true; 2699 dwc->gadget.name = "dwc3-gadget"; 2700 2701 /* 2702 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize 2703 * on ep out. 2704 */ 2705 dwc->gadget.quirk_ep_out_aligned_size = true; 2706 2707 /* 2708 * REVISIT: Here we should clear all pending IRQs to be 2709 * sure we're starting from a well known location. 2710 */ 2711 2712 ret = dwc3_gadget_init_endpoints(dwc); 2713 if (ret) 2714 goto err4; 2715 2716 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2717 if (ret) { 2718 dev_err(dwc->dev, "failed to register udc\n"); 2719 goto err4; 2720 } 2721 2722 return 0; 2723 2724err4: 2725 dwc3_gadget_free_endpoints(dwc); 2726 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2727 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2728 2729err3: 2730 kfree(dwc->setup_buf); 2731 2732err2: 2733 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2734 dwc->ep0_trb, dwc->ep0_trb_addr); 2735 2736err1: 2737 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2738 dwc->ctrl_req, dwc->ctrl_req_addr); 2739 2740err0: 2741 return ret; 2742} 2743 2744/* -------------------------------------------------------------------------- */ 2745 2746void dwc3_gadget_exit(struct dwc3 *dwc) 2747{ 2748 usb_del_gadget_udc(&dwc->gadget); 2749 2750 dwc3_gadget_free_endpoints(dwc); 2751 2752 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2753 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2754 2755 kfree(dwc->setup_buf); 2756 2757 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2758 dwc->ep0_trb, dwc->ep0_trb_addr); 2759 2760 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2761 dwc->ctrl_req, dwc->ctrl_req_addr); 2762} 2763 2764int dwc3_gadget_prepare(struct dwc3 *dwc) 2765{ 2766 if (dwc->pullups_connected) { 2767 dwc3_gadget_disable_irq(dwc); 2768 dwc3_gadget_run_stop(dwc, true, true); 2769 } 2770 2771 return 0; 2772} 2773 2774void dwc3_gadget_complete(struct dwc3 *dwc) 2775{ 2776 if (dwc->pullups_connected) { 2777 dwc3_gadget_enable_irq(dwc); 2778 dwc3_gadget_run_stop(dwc, true, false); 2779 } 2780} 2781 2782int dwc3_gadget_suspend(struct dwc3 *dwc) 2783{ 2784 __dwc3_gadget_ep_disable(dwc->eps[0]); 2785 __dwc3_gadget_ep_disable(dwc->eps[1]); 2786 2787 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); 2788 2789 return 0; 2790} 2791 2792int dwc3_gadget_resume(struct dwc3 *dwc) 2793{ 2794 struct dwc3_ep *dep; 2795 int ret; 2796 2797 /* Start with SuperSpeed Default */ 2798 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2799 2800 dep = dwc->eps[0]; 2801 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 2802 false); 2803 if (ret) 2804 goto err0; 2805 2806 dep = dwc->eps[1]; 2807 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 2808 false); 2809 if (ret) 2810 goto err1; 2811 2812 /* begin to receive SETUP packets */ 2813 dwc->ep0state = EP0_SETUP_PHASE; 2814 dwc3_ep0_out_start(dwc); 2815 2816 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); 2817 2818 return 0; 2819 2820err1: 2821 __dwc3_gadget_ep_disable(dwc->eps[0]); 2822 2823err0: 2824 return ret; 2825} 2826