gadget.c revision c4430a26948b84c0d820e83f8c640229f960d3b6
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <linux/kernel.h> 40#include <linux/delay.h> 41#include <linux/slab.h> 42#include <linux/spinlock.h> 43#include <linux/platform_device.h> 44#include <linux/pm_runtime.h> 45#include <linux/interrupt.h> 46#include <linux/io.h> 47#include <linux/list.h> 48#include <linux/dma-mapping.h> 49 50#include <linux/usb/ch9.h> 51#include <linux/usb/gadget.h> 52 53#include "core.h" 54#include "gadget.h" 55#include "io.h" 56 57/** 58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 59 * @dwc: pointer to our context structure 60 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 61 * 62 * Caller should take care of locking. This function will 63 * return 0 on success or -EINVAL if wrong Test Selector 64 * is passed 65 */ 66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 67{ 68 u32 reg; 69 70 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 71 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 72 73 switch (mode) { 74 case TEST_J: 75 case TEST_K: 76 case TEST_SE0_NAK: 77 case TEST_PACKET: 78 case TEST_FORCE_EN: 79 reg |= mode << 1; 80 break; 81 default: 82 return -EINVAL; 83 } 84 85 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 86 87 return 0; 88} 89 90/** 91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 92 * @dwc: pointer to our context structure 93 * @state: the state to put link into 94 * 95 * Caller should take care of locking. This function will 96 * return 0 on success or -ETIMEDOUT. 97 */ 98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 99{ 100 int retries = 10000; 101 u32 reg; 102 103 /* 104 * Wait until device controller is ready. Only applies to 1.94a and 105 * later RTL. 106 */ 107 if (dwc->revision >= DWC3_REVISION_194A) { 108 while (--retries) { 109 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 110 if (reg & DWC3_DSTS_DCNRD) 111 udelay(5); 112 else 113 break; 114 } 115 116 if (retries <= 0) 117 return -ETIMEDOUT; 118 } 119 120 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 122 123 /* set requested state */ 124 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 125 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 126 127 /* 128 * The following code is racy when called from dwc3_gadget_wakeup, 129 * and is not needed, at least on newer versions 130 */ 131 if (dwc->revision >= DWC3_REVISION_194A) 132 return 0; 133 134 /* wait for a change in DSTS */ 135 retries = 10000; 136 while (--retries) { 137 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 138 139 if (DWC3_DSTS_USBLNKST(reg) == state) 140 return 0; 141 142 udelay(5); 143 } 144 145 dev_vdbg(dwc->dev, "link state change request timed out\n"); 146 147 return -ETIMEDOUT; 148} 149 150/** 151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 152 * @dwc: pointer to our context structure 153 * 154 * This function will a best effort FIFO allocation in order 155 * to improve FIFO usage and throughput, while still allowing 156 * us to enable as many endpoints as possible. 157 * 158 * Keep in mind that this operation will be highly dependent 159 * on the configured size for RAM1 - which contains TxFifo -, 160 * the amount of endpoints enabled on coreConsultant tool, and 161 * the width of the Master Bus. 162 * 163 * In the ideal world, we would always be able to satisfy the 164 * following equation: 165 * 166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 168 * 169 * Unfortunately, due to many variables that's not always the case. 170 */ 171int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 172{ 173 int last_fifo_depth = 0; 174 int ram1_depth; 175 int fifo_size; 176 int mdwidth; 177 int num; 178 179 if (!dwc->needs_fifo_resize) 180 return 0; 181 182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 184 185 /* MDWIDTH is represented in bits, we need it in bytes */ 186 mdwidth >>= 3; 187 188 /* 189 * FIXME For now we will only allocate 1 wMaxPacketSize space 190 * for each enabled endpoint, later patches will come to 191 * improve this algorithm so that we better use the internal 192 * FIFO space 193 */ 194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { 195 struct dwc3_ep *dep = dwc->eps[num]; 196 int fifo_number = dep->number >> 1; 197 int mult = 1; 198 int tmp; 199 200 if (!(dep->number & 1)) 201 continue; 202 203 if (!(dep->flags & DWC3_EP_ENABLED)) 204 continue; 205 206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) 207 || usb_endpoint_xfer_isoc(dep->endpoint.desc)) 208 mult = 3; 209 210 /* 211 * REVISIT: the following assumes we will always have enough 212 * space available on the FIFO RAM for all possible use cases. 213 * Make sure that's true somehow and change FIFO allocation 214 * accordingly. 215 * 216 * If we have Bulk or Isochronous endpoints, we want 217 * them to be able to be very, very fast. So we're giving 218 * those endpoints a fifo_size which is enough for 3 full 219 * packets 220 */ 221 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 222 tmp += mdwidth; 223 224 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 225 226 fifo_size |= (last_fifo_depth << 16); 227 228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 229 dep->name, last_fifo_depth, fifo_size & 0xffff); 230 231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), 232 fifo_size); 233 234 last_fifo_depth += (fifo_size & 0xffff); 235 } 236 237 return 0; 238} 239 240void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 241 int status) 242{ 243 struct dwc3 *dwc = dep->dwc; 244 245 if (req->queued) { 246 if (req->request.num_mapped_sgs) 247 dep->busy_slot += req->request.num_mapped_sgs; 248 else 249 dep->busy_slot++; 250 251 /* 252 * Skip LINK TRB. We can't use req->trb and check for 253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just 254 * completed (not the LINK TRB). 255 */ 256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 257 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 258 dep->busy_slot++; 259 } 260 list_del(&req->list); 261 req->trb = NULL; 262 263 if (req->request.status == -EINPROGRESS) 264 req->request.status = status; 265 266 usb_gadget_unmap_request(&dwc->gadget, &req->request, 267 req->direction); 268 269 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 270 req, dep->name, req->request.actual, 271 req->request.length, status); 272 273 spin_unlock(&dwc->lock); 274 req->request.complete(&dep->endpoint, &req->request); 275 spin_lock(&dwc->lock); 276} 277 278static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 279{ 280 switch (cmd) { 281 case DWC3_DEPCMD_DEPSTARTCFG: 282 return "Start New Configuration"; 283 case DWC3_DEPCMD_ENDTRANSFER: 284 return "End Transfer"; 285 case DWC3_DEPCMD_UPDATETRANSFER: 286 return "Update Transfer"; 287 case DWC3_DEPCMD_STARTTRANSFER: 288 return "Start Transfer"; 289 case DWC3_DEPCMD_CLEARSTALL: 290 return "Clear Stall"; 291 case DWC3_DEPCMD_SETSTALL: 292 return "Set Stall"; 293 case DWC3_DEPCMD_GETEPSTATE: 294 return "Get Endpoint State"; 295 case DWC3_DEPCMD_SETTRANSFRESOURCE: 296 return "Set Endpoint Transfer Resource"; 297 case DWC3_DEPCMD_SETEPCONFIG: 298 return "Set Endpoint Configuration"; 299 default: 300 return "UNKNOWN command"; 301 } 302} 303 304int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) 305{ 306 u32 timeout = 500; 307 u32 reg; 308 309 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 310 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 311 312 do { 313 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 314 if (!(reg & DWC3_DGCMD_CMDACT)) { 315 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 316 DWC3_DGCMD_STATUS(reg)); 317 return 0; 318 } 319 320 /* 321 * We can't sleep here, because it's also called from 322 * interrupt context. 323 */ 324 timeout--; 325 if (!timeout) 326 return -ETIMEDOUT; 327 udelay(1); 328 } while (1); 329} 330 331int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 332 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 333{ 334 struct dwc3_ep *dep = dwc->eps[ep]; 335 u32 timeout = 500; 336 u32 reg; 337 338 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 339 dep->name, 340 dwc3_gadget_ep_cmd_string(cmd), params->param0, 341 params->param1, params->param2); 342 343 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 346 347 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 348 do { 349 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 350 if (!(reg & DWC3_DEPCMD_CMDACT)) { 351 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 352 DWC3_DEPCMD_STATUS(reg)); 353 return 0; 354 } 355 356 /* 357 * We can't sleep here, because it is also called from 358 * interrupt context. 359 */ 360 timeout--; 361 if (!timeout) 362 return -ETIMEDOUT; 363 364 udelay(1); 365 } while (1); 366} 367 368static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 369 struct dwc3_trb *trb) 370{ 371 u32 offset = (char *) trb - (char *) dep->trb_pool; 372 373 return dep->trb_pool_dma + offset; 374} 375 376static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 377{ 378 struct dwc3 *dwc = dep->dwc; 379 380 if (dep->trb_pool) 381 return 0; 382 383 if (dep->number == 0 || dep->number == 1) 384 return 0; 385 386 dep->trb_pool = dma_alloc_coherent(dwc->dev, 387 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 388 &dep->trb_pool_dma, GFP_KERNEL); 389 if (!dep->trb_pool) { 390 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 391 dep->name); 392 return -ENOMEM; 393 } 394 395 return 0; 396} 397 398static void dwc3_free_trb_pool(struct dwc3_ep *dep) 399{ 400 struct dwc3 *dwc = dep->dwc; 401 402 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 403 dep->trb_pool, dep->trb_pool_dma); 404 405 dep->trb_pool = NULL; 406 dep->trb_pool_dma = 0; 407} 408 409static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 410{ 411 struct dwc3_gadget_ep_cmd_params params; 412 u32 cmd; 413 414 memset(¶ms, 0x00, sizeof(params)); 415 416 if (dep->number != 1) { 417 cmd = DWC3_DEPCMD_DEPSTARTCFG; 418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 419 if (dep->number > 1) { 420 if (dwc->start_config_issued) 421 return 0; 422 dwc->start_config_issued = true; 423 cmd |= DWC3_DEPCMD_PARAM(2); 424 } 425 426 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 427 } 428 429 return 0; 430} 431 432static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 433 const struct usb_endpoint_descriptor *desc, 434 const struct usb_ss_ep_comp_descriptor *comp_desc) 435{ 436 struct dwc3_gadget_ep_cmd_params params; 437 438 memset(¶ms, 0x00, sizeof(params)); 439 440 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 441 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) 442 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst); 443 444 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 445 | DWC3_DEPCFG_XFER_NOT_READY_EN; 446 447 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 448 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 449 | DWC3_DEPCFG_STREAM_EVENT_EN; 450 dep->stream_capable = true; 451 } 452 453 if (usb_endpoint_xfer_isoc(desc)) 454 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 455 456 /* 457 * We are doing 1:1 mapping for endpoints, meaning 458 * Physical Endpoints 2 maps to Logical Endpoint 2 and 459 * so on. We consider the direction bit as part of the physical 460 * endpoint number. So USB endpoint 0x81 is 0x03. 461 */ 462 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 463 464 /* 465 * We must use the lower 16 TX FIFOs even though 466 * HW might have more 467 */ 468 if (dep->direction) 469 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 470 471 if (desc->bInterval) { 472 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 473 dep->interval = 1 << (desc->bInterval - 1); 474 } 475 476 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 477 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 478} 479 480static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 481{ 482 struct dwc3_gadget_ep_cmd_params params; 483 484 memset(¶ms, 0x00, sizeof(params)); 485 486 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 487 488 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 489 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 490} 491 492/** 493 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 494 * @dep: endpoint to be initialized 495 * @desc: USB Endpoint Descriptor 496 * 497 * Caller should take care of locking 498 */ 499static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 500 const struct usb_endpoint_descriptor *desc, 501 const struct usb_ss_ep_comp_descriptor *comp_desc) 502{ 503 struct dwc3 *dwc = dep->dwc; 504 u32 reg; 505 int ret = -ENOMEM; 506 507 if (!(dep->flags & DWC3_EP_ENABLED)) { 508 ret = dwc3_gadget_start_config(dwc, dep); 509 if (ret) 510 return ret; 511 } 512 513 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc); 514 if (ret) 515 return ret; 516 517 if (!(dep->flags & DWC3_EP_ENABLED)) { 518 struct dwc3_trb *trb_st_hw; 519 struct dwc3_trb *trb_link; 520 521 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 522 if (ret) 523 return ret; 524 525 dep->endpoint.desc = desc; 526 dep->comp_desc = comp_desc; 527 dep->type = usb_endpoint_type(desc); 528 dep->flags |= DWC3_EP_ENABLED; 529 530 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 531 reg |= DWC3_DALEPENA_EP(dep->number); 532 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 533 534 if (!usb_endpoint_xfer_isoc(desc)) 535 return 0; 536 537 memset(&trb_link, 0, sizeof(trb_link)); 538 539 /* Link TRB for ISOC. The HWO bit is never reset */ 540 trb_st_hw = &dep->trb_pool[0]; 541 542 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 543 544 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 545 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 546 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 547 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 548 } 549 550 return 0; 551} 552 553static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); 554static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 555{ 556 struct dwc3_request *req; 557 558 if (!list_empty(&dep->req_queued)) 559 dwc3_stop_active_transfer(dwc, dep->number); 560 561 while (!list_empty(&dep->request_list)) { 562 req = next_request(&dep->request_list); 563 564 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 565 } 566} 567 568/** 569 * __dwc3_gadget_ep_disable - Disables a HW endpoint 570 * @dep: the endpoint to disable 571 * 572 * This function also removes requests which are currently processed ny the 573 * hardware and those which are not yet scheduled. 574 * Caller should take care of locking. 575 */ 576static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 577{ 578 struct dwc3 *dwc = dep->dwc; 579 u32 reg; 580 581 dwc3_remove_requests(dwc, dep); 582 583 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 584 reg &= ~DWC3_DALEPENA_EP(dep->number); 585 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 586 587 dep->stream_capable = false; 588 dep->endpoint.desc = NULL; 589 dep->comp_desc = NULL; 590 dep->type = 0; 591 dep->flags = 0; 592 593 return 0; 594} 595 596/* -------------------------------------------------------------------------- */ 597 598static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 599 const struct usb_endpoint_descriptor *desc) 600{ 601 return -EINVAL; 602} 603 604static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 605{ 606 return -EINVAL; 607} 608 609/* -------------------------------------------------------------------------- */ 610 611static int dwc3_gadget_ep_enable(struct usb_ep *ep, 612 const struct usb_endpoint_descriptor *desc) 613{ 614 struct dwc3_ep *dep; 615 struct dwc3 *dwc; 616 unsigned long flags; 617 int ret; 618 619 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 620 pr_debug("dwc3: invalid parameters\n"); 621 return -EINVAL; 622 } 623 624 if (!desc->wMaxPacketSize) { 625 pr_debug("dwc3: missing wMaxPacketSize\n"); 626 return -EINVAL; 627 } 628 629 dep = to_dwc3_ep(ep); 630 dwc = dep->dwc; 631 632 switch (usb_endpoint_type(desc)) { 633 case USB_ENDPOINT_XFER_CONTROL: 634 strlcat(dep->name, "-control", sizeof(dep->name)); 635 break; 636 case USB_ENDPOINT_XFER_ISOC: 637 strlcat(dep->name, "-isoc", sizeof(dep->name)); 638 break; 639 case USB_ENDPOINT_XFER_BULK: 640 strlcat(dep->name, "-bulk", sizeof(dep->name)); 641 break; 642 case USB_ENDPOINT_XFER_INT: 643 strlcat(dep->name, "-int", sizeof(dep->name)); 644 break; 645 default: 646 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 647 } 648 649 if (dep->flags & DWC3_EP_ENABLED) { 650 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 651 dep->name); 652 return 0; 653 } 654 655 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 656 657 spin_lock_irqsave(&dwc->lock, flags); 658 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc); 659 spin_unlock_irqrestore(&dwc->lock, flags); 660 661 return ret; 662} 663 664static int dwc3_gadget_ep_disable(struct usb_ep *ep) 665{ 666 struct dwc3_ep *dep; 667 struct dwc3 *dwc; 668 unsigned long flags; 669 int ret; 670 671 if (!ep) { 672 pr_debug("dwc3: invalid parameters\n"); 673 return -EINVAL; 674 } 675 676 dep = to_dwc3_ep(ep); 677 dwc = dep->dwc; 678 679 if (!(dep->flags & DWC3_EP_ENABLED)) { 680 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 681 dep->name); 682 return 0; 683 } 684 685 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 686 dep->number >> 1, 687 (dep->number & 1) ? "in" : "out"); 688 689 spin_lock_irqsave(&dwc->lock, flags); 690 ret = __dwc3_gadget_ep_disable(dep); 691 spin_unlock_irqrestore(&dwc->lock, flags); 692 693 return ret; 694} 695 696static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 697 gfp_t gfp_flags) 698{ 699 struct dwc3_request *req; 700 struct dwc3_ep *dep = to_dwc3_ep(ep); 701 struct dwc3 *dwc = dep->dwc; 702 703 req = kzalloc(sizeof(*req), gfp_flags); 704 if (!req) { 705 dev_err(dwc->dev, "not enough memory\n"); 706 return NULL; 707 } 708 709 req->epnum = dep->number; 710 req->dep = dep; 711 712 return &req->request; 713} 714 715static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 716 struct usb_request *request) 717{ 718 struct dwc3_request *req = to_dwc3_request(request); 719 720 kfree(req); 721} 722 723/** 724 * dwc3_prepare_one_trb - setup one TRB from one request 725 * @dep: endpoint for which this request is prepared 726 * @req: dwc3_request pointer 727 */ 728static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 729 struct dwc3_request *req, dma_addr_t dma, 730 unsigned length, unsigned last, unsigned chain) 731{ 732 struct dwc3 *dwc = dep->dwc; 733 struct dwc3_trb *trb; 734 735 unsigned int cur_slot; 736 737 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 738 dep->name, req, (unsigned long long) dma, 739 length, last ? " last" : "", 740 chain ? " chain" : ""); 741 742 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 743 cur_slot = dep->free_slot; 744 dep->free_slot++; 745 746 /* Skip the LINK-TRB on ISOC */ 747 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 748 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 749 return; 750 751 if (!req->trb) { 752 dwc3_gadget_move_request_queued(req); 753 req->trb = trb; 754 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 755 } 756 757 trb->size = DWC3_TRB_SIZE_LENGTH(length); 758 trb->bpl = lower_32_bits(dma); 759 trb->bph = upper_32_bits(dma); 760 761 switch (usb_endpoint_type(dep->endpoint.desc)) { 762 case USB_ENDPOINT_XFER_CONTROL: 763 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 764 break; 765 766 case USB_ENDPOINT_XFER_ISOC: 767 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 768 769 /* IOC every DWC3_TRB_NUM / 4 so we can refill */ 770 if (!(cur_slot % (DWC3_TRB_NUM / 4))) 771 trb->ctrl |= DWC3_TRB_CTRL_IOC; 772 break; 773 774 case USB_ENDPOINT_XFER_BULK: 775 case USB_ENDPOINT_XFER_INT: 776 trb->ctrl = DWC3_TRBCTL_NORMAL; 777 break; 778 default: 779 /* 780 * This is only possible with faulty memory because we 781 * checked it already :) 782 */ 783 BUG(); 784 } 785 786 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 787 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 788 trb->ctrl |= DWC3_TRB_CTRL_CSP; 789 } else { 790 if (chain) 791 trb->ctrl |= DWC3_TRB_CTRL_CHN; 792 793 if (last) 794 trb->ctrl |= DWC3_TRB_CTRL_LST; 795 } 796 797 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 798 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); 799 800 trb->ctrl |= DWC3_TRB_CTRL_HWO; 801} 802 803/* 804 * dwc3_prepare_trbs - setup TRBs from requests 805 * @dep: endpoint for which requests are being prepared 806 * @starting: true if the endpoint is idle and no requests are queued. 807 * 808 * The function goes through the requests list and sets up TRBs for the 809 * transfers. The function returns once there are no more TRBs available or 810 * it runs out of requests. 811 */ 812static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 813{ 814 struct dwc3_request *req, *n; 815 u32 trbs_left; 816 u32 max; 817 unsigned int last_one = 0; 818 819 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 820 821 /* the first request must not be queued */ 822 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 823 824 /* Can't wrap around on a non-isoc EP since there's no link TRB */ 825 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 826 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); 827 if (trbs_left > max) 828 trbs_left = max; 829 } 830 831 /* 832 * If busy & slot are equal than it is either full or empty. If we are 833 * starting to process requests then we are empty. Otherwise we are 834 * full and don't do anything 835 */ 836 if (!trbs_left) { 837 if (!starting) 838 return; 839 trbs_left = DWC3_TRB_NUM; 840 /* 841 * In case we start from scratch, we queue the ISOC requests 842 * starting from slot 1. This is done because we use ring 843 * buffer and have no LST bit to stop us. Instead, we place 844 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt 845 * after the first request so we start at slot 1 and have 846 * 7 requests proceed before we hit the first IOC. 847 * Other transfer types don't use the ring buffer and are 848 * processed from the first TRB until the last one. Since we 849 * don't wrap around we have to start at the beginning. 850 */ 851 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 852 dep->busy_slot = 1; 853 dep->free_slot = 1; 854 } else { 855 dep->busy_slot = 0; 856 dep->free_slot = 0; 857 } 858 } 859 860 /* The last TRB is a link TRB, not used for xfer */ 861 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) 862 return; 863 864 list_for_each_entry_safe(req, n, &dep->request_list, list) { 865 unsigned length; 866 dma_addr_t dma; 867 868 if (req->request.num_mapped_sgs > 0) { 869 struct usb_request *request = &req->request; 870 struct scatterlist *sg = request->sg; 871 struct scatterlist *s; 872 int i; 873 874 for_each_sg(sg, s, request->num_mapped_sgs, i) { 875 unsigned chain = true; 876 877 length = sg_dma_len(s); 878 dma = sg_dma_address(s); 879 880 if (i == (request->num_mapped_sgs - 1) || 881 sg_is_last(s)) { 882 last_one = true; 883 chain = false; 884 } 885 886 trbs_left--; 887 if (!trbs_left) 888 last_one = true; 889 890 if (last_one) 891 chain = false; 892 893 dwc3_prepare_one_trb(dep, req, dma, length, 894 last_one, chain); 895 896 if (last_one) 897 break; 898 } 899 } else { 900 dma = req->request.dma; 901 length = req->request.length; 902 trbs_left--; 903 904 if (!trbs_left) 905 last_one = 1; 906 907 /* Is this the last request? */ 908 if (list_is_last(&req->list, &dep->request_list)) 909 last_one = 1; 910 911 dwc3_prepare_one_trb(dep, req, dma, length, 912 last_one, false); 913 914 if (last_one) 915 break; 916 } 917 } 918} 919 920static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 921 int start_new) 922{ 923 struct dwc3_gadget_ep_cmd_params params; 924 struct dwc3_request *req; 925 struct dwc3 *dwc = dep->dwc; 926 int ret; 927 u32 cmd; 928 929 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 930 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 931 return -EBUSY; 932 } 933 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 934 935 /* 936 * If we are getting here after a short-out-packet we don't enqueue any 937 * new requests as we try to set the IOC bit only on the last request. 938 */ 939 if (start_new) { 940 if (list_empty(&dep->req_queued)) 941 dwc3_prepare_trbs(dep, start_new); 942 943 /* req points to the first request which will be sent */ 944 req = next_request(&dep->req_queued); 945 } else { 946 dwc3_prepare_trbs(dep, start_new); 947 948 /* 949 * req points to the first request where HWO changed from 0 to 1 950 */ 951 req = next_request(&dep->req_queued); 952 } 953 if (!req) { 954 dep->flags |= DWC3_EP_PENDING_REQUEST; 955 return 0; 956 } 957 958 memset(¶ms, 0, sizeof(params)); 959 params.param0 = upper_32_bits(req->trb_dma); 960 params.param1 = lower_32_bits(req->trb_dma); 961 962 if (start_new) 963 cmd = DWC3_DEPCMD_STARTTRANSFER; 964 else 965 cmd = DWC3_DEPCMD_UPDATETRANSFER; 966 967 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 968 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 969 if (ret < 0) { 970 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 971 972 /* 973 * FIXME we need to iterate over the list of requests 974 * here and stop, unmap, free and del each of the linked 975 * requests instead of what we do now. 976 */ 977 usb_gadget_unmap_request(&dwc->gadget, &req->request, 978 req->direction); 979 list_del(&req->list); 980 return ret; 981 } 982 983 dep->flags |= DWC3_EP_BUSY; 984 985 if (start_new) { 986 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, 987 dep->number); 988 WARN_ON_ONCE(!dep->res_trans_idx); 989 } 990 991 return 0; 992} 993 994static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 995{ 996 struct dwc3 *dwc = dep->dwc; 997 int ret; 998 999 req->request.actual = 0; 1000 req->request.status = -EINPROGRESS; 1001 req->direction = dep->direction; 1002 req->epnum = dep->number; 1003 1004 /* 1005 * We only add to our list of requests now and 1006 * start consuming the list once we get XferNotReady 1007 * IRQ. 1008 * 1009 * That way, we avoid doing anything that we don't need 1010 * to do now and defer it until the point we receive a 1011 * particular token from the Host side. 1012 * 1013 * This will also avoid Host cancelling URBs due to too 1014 * many NAKs. 1015 */ 1016 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1017 dep->direction); 1018 if (ret) 1019 return ret; 1020 1021 list_add_tail(&req->list, &dep->request_list); 1022 1023 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && (dep->flags & DWC3_EP_BUSY)) 1024 dep->flags |= DWC3_EP_PENDING_REQUEST; 1025 1026 /* 1027 * There are two special cases: 1028 * 1029 * 1. XferNotReady with empty list of requests. We need to kick the 1030 * transfer here in that situation, otherwise we will be NAKing 1031 * forever. If we get XferNotReady before gadget driver has a 1032 * chance to queue a request, we will ACK the IRQ but won't be 1033 * able to receive the data until the next request is queued. 1034 * The following code is handling exactly that. 1035 * 1036 * 2. XferInProgress on Isoc EP with an active transfer. We need to 1037 * kick the transfer here after queuing a request, otherwise the 1038 * core may not see the modified TRB(s). 1039 */ 1040 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1041 int ret; 1042 int start_trans = 1; 1043 u8 trans_idx = dep->res_trans_idx; 1044 1045 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1046 (dep->flags & DWC3_EP_BUSY)) { 1047 start_trans = 0; 1048 WARN_ON_ONCE(!trans_idx); 1049 } else { 1050 trans_idx = 0; 1051 } 1052 1053 ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans); 1054 if (ret && ret != -EBUSY) { 1055 struct dwc3 *dwc = dep->dwc; 1056 1057 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1058 dep->name); 1059 } 1060 } 1061 1062 return 0; 1063} 1064 1065static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1066 gfp_t gfp_flags) 1067{ 1068 struct dwc3_request *req = to_dwc3_request(request); 1069 struct dwc3_ep *dep = to_dwc3_ep(ep); 1070 struct dwc3 *dwc = dep->dwc; 1071 1072 unsigned long flags; 1073 1074 int ret; 1075 1076 if (!dep->endpoint.desc) { 1077 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1078 request, ep->name); 1079 return -ESHUTDOWN; 1080 } 1081 1082 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1083 request, ep->name, request->length); 1084 1085 spin_lock_irqsave(&dwc->lock, flags); 1086 ret = __dwc3_gadget_ep_queue(dep, req); 1087 spin_unlock_irqrestore(&dwc->lock, flags); 1088 1089 return ret; 1090} 1091 1092static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1093 struct usb_request *request) 1094{ 1095 struct dwc3_request *req = to_dwc3_request(request); 1096 struct dwc3_request *r = NULL; 1097 1098 struct dwc3_ep *dep = to_dwc3_ep(ep); 1099 struct dwc3 *dwc = dep->dwc; 1100 1101 unsigned long flags; 1102 int ret = 0; 1103 1104 spin_lock_irqsave(&dwc->lock, flags); 1105 1106 list_for_each_entry(r, &dep->request_list, list) { 1107 if (r == req) 1108 break; 1109 } 1110 1111 if (r != req) { 1112 list_for_each_entry(r, &dep->req_queued, list) { 1113 if (r == req) 1114 break; 1115 } 1116 if (r == req) { 1117 /* wait until it is processed */ 1118 dwc3_stop_active_transfer(dwc, dep->number); 1119 goto out0; 1120 } 1121 dev_err(dwc->dev, "request %p was not queued to %s\n", 1122 request, ep->name); 1123 ret = -EINVAL; 1124 goto out0; 1125 } 1126 1127 /* giveback the request */ 1128 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1129 1130out0: 1131 spin_unlock_irqrestore(&dwc->lock, flags); 1132 1133 return ret; 1134} 1135 1136int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1137{ 1138 struct dwc3_gadget_ep_cmd_params params; 1139 struct dwc3 *dwc = dep->dwc; 1140 int ret; 1141 1142 memset(¶ms, 0x00, sizeof(params)); 1143 1144 if (value) { 1145 if (dep->number == 0 || dep->number == 1) { 1146 /* 1147 * Whenever EP0 is stalled, we will restart 1148 * the state machine, thus moving back to 1149 * Setup Phase 1150 */ 1151 dwc->ep0state = EP0_SETUP_PHASE; 1152 } 1153 1154 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1155 DWC3_DEPCMD_SETSTALL, ¶ms); 1156 if (ret) 1157 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1158 value ? "set" : "clear", 1159 dep->name); 1160 else 1161 dep->flags |= DWC3_EP_STALL; 1162 } else { 1163 if (dep->flags & DWC3_EP_WEDGE) 1164 return 0; 1165 1166 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1167 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1168 if (ret) 1169 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1170 value ? "set" : "clear", 1171 dep->name); 1172 else 1173 dep->flags &= ~DWC3_EP_STALL; 1174 } 1175 1176 return ret; 1177} 1178 1179static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1180{ 1181 struct dwc3_ep *dep = to_dwc3_ep(ep); 1182 struct dwc3 *dwc = dep->dwc; 1183 1184 unsigned long flags; 1185 1186 int ret; 1187 1188 spin_lock_irqsave(&dwc->lock, flags); 1189 1190 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1191 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1192 ret = -EINVAL; 1193 goto out; 1194 } 1195 1196 ret = __dwc3_gadget_ep_set_halt(dep, value); 1197out: 1198 spin_unlock_irqrestore(&dwc->lock, flags); 1199 1200 return ret; 1201} 1202 1203static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1204{ 1205 struct dwc3_ep *dep = to_dwc3_ep(ep); 1206 struct dwc3 *dwc = dep->dwc; 1207 unsigned long flags; 1208 1209 spin_lock_irqsave(&dwc->lock, flags); 1210 dep->flags |= DWC3_EP_WEDGE; 1211 spin_unlock_irqrestore(&dwc->lock, flags); 1212 1213 return dwc3_gadget_ep_set_halt(ep, 1); 1214} 1215 1216/* -------------------------------------------------------------------------- */ 1217 1218static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1219 .bLength = USB_DT_ENDPOINT_SIZE, 1220 .bDescriptorType = USB_DT_ENDPOINT, 1221 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1222}; 1223 1224static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1225 .enable = dwc3_gadget_ep0_enable, 1226 .disable = dwc3_gadget_ep0_disable, 1227 .alloc_request = dwc3_gadget_ep_alloc_request, 1228 .free_request = dwc3_gadget_ep_free_request, 1229 .queue = dwc3_gadget_ep0_queue, 1230 .dequeue = dwc3_gadget_ep_dequeue, 1231 .set_halt = dwc3_gadget_ep_set_halt, 1232 .set_wedge = dwc3_gadget_ep_set_wedge, 1233}; 1234 1235static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1236 .enable = dwc3_gadget_ep_enable, 1237 .disable = dwc3_gadget_ep_disable, 1238 .alloc_request = dwc3_gadget_ep_alloc_request, 1239 .free_request = dwc3_gadget_ep_free_request, 1240 .queue = dwc3_gadget_ep_queue, 1241 .dequeue = dwc3_gadget_ep_dequeue, 1242 .set_halt = dwc3_gadget_ep_set_halt, 1243 .set_wedge = dwc3_gadget_ep_set_wedge, 1244}; 1245 1246/* -------------------------------------------------------------------------- */ 1247 1248static int dwc3_gadget_get_frame(struct usb_gadget *g) 1249{ 1250 struct dwc3 *dwc = gadget_to_dwc(g); 1251 u32 reg; 1252 1253 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1254 return DWC3_DSTS_SOFFN(reg); 1255} 1256 1257static int dwc3_gadget_wakeup(struct usb_gadget *g) 1258{ 1259 struct dwc3 *dwc = gadget_to_dwc(g); 1260 1261 unsigned long timeout; 1262 unsigned long flags; 1263 1264 u32 reg; 1265 1266 int ret = 0; 1267 1268 u8 link_state; 1269 u8 speed; 1270 1271 spin_lock_irqsave(&dwc->lock, flags); 1272 1273 /* 1274 * According to the Databook Remote wakeup request should 1275 * be issued only when the device is in early suspend state. 1276 * 1277 * We can check that via USB Link State bits in DSTS register. 1278 */ 1279 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1280 1281 speed = reg & DWC3_DSTS_CONNECTSPD; 1282 if (speed == DWC3_DSTS_SUPERSPEED) { 1283 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1284 ret = -EINVAL; 1285 goto out; 1286 } 1287 1288 link_state = DWC3_DSTS_USBLNKST(reg); 1289 1290 switch (link_state) { 1291 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1292 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1293 break; 1294 default: 1295 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1296 link_state); 1297 ret = -EINVAL; 1298 goto out; 1299 } 1300 1301 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1302 if (ret < 0) { 1303 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1304 goto out; 1305 } 1306 1307 /* Recent versions do this automatically */ 1308 if (dwc->revision < DWC3_REVISION_194A) { 1309 /* write zeroes to Link Change Request */ 1310 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1311 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1312 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1313 } 1314 1315 /* poll until Link State changes to ON */ 1316 timeout = jiffies + msecs_to_jiffies(100); 1317 1318 while (!time_after(jiffies, timeout)) { 1319 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1320 1321 /* in HS, means ON */ 1322 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1323 break; 1324 } 1325 1326 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1327 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1328 ret = -EINVAL; 1329 } 1330 1331out: 1332 spin_unlock_irqrestore(&dwc->lock, flags); 1333 1334 return ret; 1335} 1336 1337static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1338 int is_selfpowered) 1339{ 1340 struct dwc3 *dwc = gadget_to_dwc(g); 1341 unsigned long flags; 1342 1343 spin_lock_irqsave(&dwc->lock, flags); 1344 dwc->is_selfpowered = !!is_selfpowered; 1345 spin_unlock_irqrestore(&dwc->lock, flags); 1346 1347 return 0; 1348} 1349 1350static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) 1351{ 1352 u32 reg; 1353 u32 timeout = 500; 1354 1355 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1356 if (is_on) { 1357 if (dwc->revision <= DWC3_REVISION_187A) { 1358 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1359 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1360 } 1361 1362 if (dwc->revision >= DWC3_REVISION_194A) 1363 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1364 reg |= DWC3_DCTL_RUN_STOP; 1365 } else { 1366 reg &= ~DWC3_DCTL_RUN_STOP; 1367 } 1368 1369 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1370 1371 do { 1372 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1373 if (is_on) { 1374 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1375 break; 1376 } else { 1377 if (reg & DWC3_DSTS_DEVCTRLHLT) 1378 break; 1379 } 1380 timeout--; 1381 if (!timeout) 1382 break; 1383 udelay(1); 1384 } while (1); 1385 1386 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1387 dwc->gadget_driver 1388 ? dwc->gadget_driver->function : "no-function", 1389 is_on ? "connect" : "disconnect"); 1390} 1391 1392static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1393{ 1394 struct dwc3 *dwc = gadget_to_dwc(g); 1395 unsigned long flags; 1396 1397 is_on = !!is_on; 1398 1399 spin_lock_irqsave(&dwc->lock, flags); 1400 dwc3_gadget_run_stop(dwc, is_on); 1401 spin_unlock_irqrestore(&dwc->lock, flags); 1402 1403 return 0; 1404} 1405 1406static int dwc3_gadget_start(struct usb_gadget *g, 1407 struct usb_gadget_driver *driver) 1408{ 1409 struct dwc3 *dwc = gadget_to_dwc(g); 1410 struct dwc3_ep *dep; 1411 unsigned long flags; 1412 int ret = 0; 1413 u32 reg; 1414 1415 spin_lock_irqsave(&dwc->lock, flags); 1416 1417 if (dwc->gadget_driver) { 1418 dev_err(dwc->dev, "%s is already bound to %s\n", 1419 dwc->gadget.name, 1420 dwc->gadget_driver->driver.name); 1421 ret = -EBUSY; 1422 goto err0; 1423 } 1424 1425 dwc->gadget_driver = driver; 1426 dwc->gadget.dev.driver = &driver->driver; 1427 1428 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1429 reg &= ~(DWC3_DCFG_SPEED_MASK); 1430 1431 /** 1432 * WORKAROUND: DWC3 revision < 2.20a have an issue 1433 * which would cause metastability state on Run/Stop 1434 * bit if we try to force the IP to USB2-only mode. 1435 * 1436 * Because of that, we cannot configure the IP to any 1437 * speed other than the SuperSpeed 1438 * 1439 * Refers to: 1440 * 1441 * STAR#9000525659: Clock Domain Crossing on DCTL in 1442 * USB 2.0 Mode 1443 */ 1444 if (dwc->revision < DWC3_REVISION_220A) 1445 reg |= DWC3_DCFG_SUPERSPEED; 1446 else 1447 reg |= dwc->maximum_speed; 1448 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1449 1450 dwc->start_config_issued = false; 1451 1452 /* Start with SuperSpeed Default */ 1453 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1454 1455 dep = dwc->eps[0]; 1456 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1457 if (ret) { 1458 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1459 goto err0; 1460 } 1461 1462 dep = dwc->eps[1]; 1463 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1464 if (ret) { 1465 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1466 goto err1; 1467 } 1468 1469 /* begin to receive SETUP packets */ 1470 dwc->ep0state = EP0_SETUP_PHASE; 1471 dwc3_ep0_out_start(dwc); 1472 1473 spin_unlock_irqrestore(&dwc->lock, flags); 1474 1475 return 0; 1476 1477err1: 1478 __dwc3_gadget_ep_disable(dwc->eps[0]); 1479 1480err0: 1481 spin_unlock_irqrestore(&dwc->lock, flags); 1482 1483 return ret; 1484} 1485 1486static int dwc3_gadget_stop(struct usb_gadget *g, 1487 struct usb_gadget_driver *driver) 1488{ 1489 struct dwc3 *dwc = gadget_to_dwc(g); 1490 unsigned long flags; 1491 1492 spin_lock_irqsave(&dwc->lock, flags); 1493 1494 __dwc3_gadget_ep_disable(dwc->eps[0]); 1495 __dwc3_gadget_ep_disable(dwc->eps[1]); 1496 1497 dwc->gadget_driver = NULL; 1498 dwc->gadget.dev.driver = NULL; 1499 1500 spin_unlock_irqrestore(&dwc->lock, flags); 1501 1502 return 0; 1503} 1504 1505static const struct usb_gadget_ops dwc3_gadget_ops = { 1506 .get_frame = dwc3_gadget_get_frame, 1507 .wakeup = dwc3_gadget_wakeup, 1508 .set_selfpowered = dwc3_gadget_set_selfpowered, 1509 .pullup = dwc3_gadget_pullup, 1510 .udc_start = dwc3_gadget_start, 1511 .udc_stop = dwc3_gadget_stop, 1512}; 1513 1514/* -------------------------------------------------------------------------- */ 1515 1516static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1517{ 1518 struct dwc3_ep *dep; 1519 u8 epnum; 1520 1521 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1522 1523 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1524 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1525 if (!dep) { 1526 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1527 epnum); 1528 return -ENOMEM; 1529 } 1530 1531 dep->dwc = dwc; 1532 dep->number = epnum; 1533 dwc->eps[epnum] = dep; 1534 1535 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1536 (epnum & 1) ? "in" : "out"); 1537 dep->endpoint.name = dep->name; 1538 dep->direction = (epnum & 1); 1539 1540 if (epnum == 0 || epnum == 1) { 1541 dep->endpoint.maxpacket = 512; 1542 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1543 if (!epnum) 1544 dwc->gadget.ep0 = &dep->endpoint; 1545 } else { 1546 int ret; 1547 1548 dep->endpoint.maxpacket = 1024; 1549 dep->endpoint.max_streams = 15; 1550 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1551 list_add_tail(&dep->endpoint.ep_list, 1552 &dwc->gadget.ep_list); 1553 1554 ret = dwc3_alloc_trb_pool(dep); 1555 if (ret) 1556 return ret; 1557 } 1558 1559 INIT_LIST_HEAD(&dep->request_list); 1560 INIT_LIST_HEAD(&dep->req_queued); 1561 } 1562 1563 return 0; 1564} 1565 1566static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1567{ 1568 struct dwc3_ep *dep; 1569 u8 epnum; 1570 1571 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1572 dep = dwc->eps[epnum]; 1573 dwc3_free_trb_pool(dep); 1574 1575 if (epnum != 0 && epnum != 1) 1576 list_del(&dep->endpoint.ep_list); 1577 1578 kfree(dep); 1579 } 1580} 1581 1582static void dwc3_gadget_release(struct device *dev) 1583{ 1584 dev_dbg(dev, "%s\n", __func__); 1585} 1586 1587/* -------------------------------------------------------------------------- */ 1588static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1589 const struct dwc3_event_depevt *event, int status) 1590{ 1591 struct dwc3_request *req; 1592 struct dwc3_trb *trb; 1593 unsigned int count; 1594 unsigned int s_pkt = 0; 1595 1596 do { 1597 req = next_request(&dep->req_queued); 1598 if (!req) { 1599 WARN_ON_ONCE(1); 1600 return 1; 1601 } 1602 1603 trb = req->trb; 1604 1605 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 1606 /* 1607 * We continue despite the error. There is not much we 1608 * can do. If we don't clean it up we loop forever. If 1609 * we skip the TRB then it gets overwritten after a 1610 * while since we use them in a ring buffer. A BUG() 1611 * would help. Lets hope that if this occurs, someone 1612 * fixes the root cause instead of looking away :) 1613 */ 1614 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1615 dep->name, req->trb); 1616 count = trb->size & DWC3_TRB_SIZE_MASK; 1617 1618 if (dep->direction) { 1619 if (count) { 1620 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1621 dep->name); 1622 status = -ECONNRESET; 1623 } 1624 } else { 1625 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1626 s_pkt = 1; 1627 } 1628 1629 /* 1630 * We assume here we will always receive the entire data block 1631 * which we should receive. Meaning, if we program RX to 1632 * receive 4K but we receive only 2K, we assume that's all we 1633 * should receive and we simply bounce the request back to the 1634 * gadget driver for further processing. 1635 */ 1636 req->request.actual += req->request.length - count; 1637 dwc3_gadget_giveback(dep, req, status); 1638 if (s_pkt) 1639 break; 1640 if ((event->status & DEPEVT_STATUS_LST) && 1641 (trb->ctrl & DWC3_TRB_CTRL_LST)) 1642 break; 1643 if ((event->status & DEPEVT_STATUS_IOC) && 1644 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1645 break; 1646 } while (1); 1647 1648 if ((event->status & DEPEVT_STATUS_IOC) && 1649 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1650 return 0; 1651 return 1; 1652} 1653 1654static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1655 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1656 int start_new) 1657{ 1658 unsigned status = 0; 1659 int clean_busy; 1660 1661 if (event->status & DEPEVT_STATUS_BUSERR) 1662 status = -ECONNRESET; 1663 1664 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1665 if (clean_busy) 1666 dep->flags &= ~DWC3_EP_BUSY; 1667 1668 /* 1669 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1670 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1671 */ 1672 if (dwc->revision < DWC3_REVISION_183A) { 1673 u32 reg; 1674 int i; 1675 1676 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1677 struct dwc3_ep *dep = dwc->eps[i]; 1678 1679 if (!(dep->flags & DWC3_EP_ENABLED)) 1680 continue; 1681 1682 if (!list_empty(&dep->req_queued)) 1683 return; 1684 } 1685 1686 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1687 reg |= dwc->u1u2; 1688 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1689 1690 dwc->u1u2 = 0; 1691 } 1692} 1693 1694static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1695 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1696{ 1697 u32 uf, mask; 1698 1699 if (list_empty(&dep->request_list)) { 1700 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1701 dep->name); 1702 return; 1703 } 1704 1705 mask = ~(dep->interval - 1); 1706 uf = event->parameters & mask; 1707 /* 4 micro frames in the future */ 1708 uf += dep->interval * 4; 1709 1710 __dwc3_gadget_kick_transfer(dep, uf, 1); 1711} 1712 1713static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep, 1714 const struct dwc3_event_depevt *event) 1715{ 1716 struct dwc3 *dwc = dep->dwc; 1717 struct dwc3_event_depevt mod_ev = *event; 1718 1719 /* 1720 * We were asked to remove one request. It is possible that this 1721 * request and a few others were started together and have the same 1722 * transfer index. Since we stopped the complete endpoint we don't 1723 * know how many requests were already completed (and not yet) 1724 * reported and how could be done (later). We purge them all until 1725 * the end of the list. 1726 */ 1727 mod_ev.status = DEPEVT_STATUS_LST; 1728 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN); 1729 dep->flags &= ~DWC3_EP_BUSY; 1730 /* pending requests are ignored and are queued on XferNotReady */ 1731} 1732 1733static void dwc3_ep_cmd_compl(struct dwc3_ep *dep, 1734 const struct dwc3_event_depevt *event) 1735{ 1736 u32 param = event->parameters; 1737 u32 cmd_type = (param >> 8) & ((1 << 5) - 1); 1738 1739 switch (cmd_type) { 1740 case DWC3_DEPCMD_ENDTRANSFER: 1741 dwc3_process_ep_cmd_complete(dep, event); 1742 break; 1743 case DWC3_DEPCMD_STARTTRANSFER: 1744 dep->res_trans_idx = param & 0x7f; 1745 break; 1746 default: 1747 printk(KERN_ERR "%s() unknown /unexpected type: %d\n", 1748 __func__, cmd_type); 1749 break; 1750 }; 1751} 1752 1753static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1754 const struct dwc3_event_depevt *event) 1755{ 1756 struct dwc3_ep *dep; 1757 u8 epnum = event->endpoint_number; 1758 1759 dep = dwc->eps[epnum]; 1760 1761 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1762 dwc3_ep_event_string(event->endpoint_event)); 1763 1764 if (epnum == 0 || epnum == 1) { 1765 dwc3_ep0_interrupt(dwc, event); 1766 return; 1767 } 1768 1769 switch (event->endpoint_event) { 1770 case DWC3_DEPEVT_XFERCOMPLETE: 1771 dep->res_trans_idx = 0; 1772 1773 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1774 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1775 dep->name); 1776 return; 1777 } 1778 1779 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1780 break; 1781 case DWC3_DEPEVT_XFERINPROGRESS: 1782 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1783 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1784 dep->name); 1785 return; 1786 } 1787 1788 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1789 break; 1790 case DWC3_DEPEVT_XFERNOTREADY: 1791 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1792 dwc3_gadget_start_isoc(dwc, dep, event); 1793 } else { 1794 int ret; 1795 1796 dev_vdbg(dwc->dev, "%s: reason %s\n", 1797 dep->name, event->status & 1798 DEPEVT_STATUS_TRANSFER_ACTIVE 1799 ? "Transfer Active" 1800 : "Transfer Not Active"); 1801 1802 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1803 if (!ret || ret == -EBUSY) 1804 return; 1805 1806 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1807 dep->name); 1808 } 1809 1810 break; 1811 case DWC3_DEPEVT_STREAMEVT: 1812 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { 1813 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1814 dep->name); 1815 return; 1816 } 1817 1818 switch (event->status) { 1819 case DEPEVT_STREAMEVT_FOUND: 1820 dev_vdbg(dwc->dev, "Stream %d found and started\n", 1821 event->parameters); 1822 1823 break; 1824 case DEPEVT_STREAMEVT_NOTFOUND: 1825 /* FALLTHROUGH */ 1826 default: 1827 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 1828 } 1829 break; 1830 case DWC3_DEPEVT_RXTXFIFOEVT: 1831 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 1832 break; 1833 case DWC3_DEPEVT_EPCMDCMPLT: 1834 dwc3_ep_cmd_compl(dep, event); 1835 break; 1836 } 1837} 1838 1839static void dwc3_disconnect_gadget(struct dwc3 *dwc) 1840{ 1841 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 1842 spin_unlock(&dwc->lock); 1843 dwc->gadget_driver->disconnect(&dwc->gadget); 1844 spin_lock(&dwc->lock); 1845 } 1846} 1847 1848static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) 1849{ 1850 struct dwc3_ep *dep; 1851 struct dwc3_gadget_ep_cmd_params params; 1852 u32 cmd; 1853 int ret; 1854 1855 dep = dwc->eps[epnum]; 1856 1857 WARN_ON(!dep->res_trans_idx); 1858 if (dep->res_trans_idx) { 1859 cmd = DWC3_DEPCMD_ENDTRANSFER; 1860 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; 1861 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx); 1862 memset(¶ms, 0, sizeof(params)); 1863 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1864 WARN_ON_ONCE(ret); 1865 dep->res_trans_idx = 0; 1866 } 1867} 1868 1869static void dwc3_stop_active_transfers(struct dwc3 *dwc) 1870{ 1871 u32 epnum; 1872 1873 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1874 struct dwc3_ep *dep; 1875 1876 dep = dwc->eps[epnum]; 1877 if (!(dep->flags & DWC3_EP_ENABLED)) 1878 continue; 1879 1880 dwc3_remove_requests(dwc, dep); 1881 } 1882} 1883 1884static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 1885{ 1886 u32 epnum; 1887 1888 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1889 struct dwc3_ep *dep; 1890 struct dwc3_gadget_ep_cmd_params params; 1891 int ret; 1892 1893 dep = dwc->eps[epnum]; 1894 1895 if (!(dep->flags & DWC3_EP_STALL)) 1896 continue; 1897 1898 dep->flags &= ~DWC3_EP_STALL; 1899 1900 memset(¶ms, 0, sizeof(params)); 1901 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1902 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1903 WARN_ON_ONCE(ret); 1904 } 1905} 1906 1907static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 1908{ 1909 int reg; 1910 1911 dev_vdbg(dwc->dev, "%s\n", __func__); 1912 1913 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1914 reg &= ~DWC3_DCTL_INITU1ENA; 1915 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1916 1917 reg &= ~DWC3_DCTL_INITU2ENA; 1918 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1919 1920 dwc3_stop_active_transfers(dwc); 1921 dwc3_disconnect_gadget(dwc); 1922 dwc->start_config_issued = false; 1923 1924 dwc->gadget.speed = USB_SPEED_UNKNOWN; 1925 dwc->setup_packet_pending = false; 1926} 1927 1928static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend) 1929{ 1930 u32 reg; 1931 1932 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1933 1934 if (suspend) 1935 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1936 else 1937 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 1938 1939 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1940} 1941 1942static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend) 1943{ 1944 u32 reg; 1945 1946 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1947 1948 if (suspend) 1949 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1950 else 1951 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1952 1953 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1954} 1955 1956static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 1957{ 1958 u32 reg; 1959 1960 dev_vdbg(dwc->dev, "%s\n", __func__); 1961 1962 /* 1963 * WORKAROUND: DWC3 revisions <1.88a have an issue which 1964 * would cause a missing Disconnect Event if there's a 1965 * pending Setup Packet in the FIFO. 1966 * 1967 * There's no suggested workaround on the official Bug 1968 * report, which states that "unless the driver/application 1969 * is doing any special handling of a disconnect event, 1970 * there is no functional issue". 1971 * 1972 * Unfortunately, it turns out that we _do_ some special 1973 * handling of a disconnect event, namely complete all 1974 * pending transfers, notify gadget driver of the 1975 * disconnection, and so on. 1976 * 1977 * Our suggested workaround is to follow the Disconnect 1978 * Event steps here, instead, based on a setup_packet_pending 1979 * flag. Such flag gets set whenever we have a XferNotReady 1980 * event on EP0 and gets cleared on XferComplete for the 1981 * same endpoint. 1982 * 1983 * Refers to: 1984 * 1985 * STAR#9000466709: RTL: Device : Disconnect event not 1986 * generated if setup packet pending in FIFO 1987 */ 1988 if (dwc->revision < DWC3_REVISION_188A) { 1989 if (dwc->setup_packet_pending) 1990 dwc3_gadget_disconnect_interrupt(dwc); 1991 } 1992 1993 /* after reset -> Default State */ 1994 dwc->dev_state = DWC3_DEFAULT_STATE; 1995 1996 /* Recent versions support automatic phy suspend and don't need this */ 1997 if (dwc->revision < DWC3_REVISION_194A) { 1998 /* Resume PHYs */ 1999 dwc3_gadget_usb2_phy_suspend(dwc, false); 2000 dwc3_gadget_usb3_phy_suspend(dwc, false); 2001 } 2002 2003 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 2004 dwc3_disconnect_gadget(dwc); 2005 2006 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2007 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2008 reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA); 2009 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2010 dwc->test_mode = false; 2011 2012 dwc3_stop_active_transfers(dwc); 2013 dwc3_clear_stall_all_ep(dwc); 2014 dwc->start_config_issued = false; 2015 2016 /* Reset device address to zero */ 2017 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2018 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2019 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2020} 2021 2022static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 2023{ 2024 u32 reg; 2025 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 2026 2027 /* 2028 * We change the clock only at SS but I dunno why I would want to do 2029 * this. Maybe it becomes part of the power saving plan. 2030 */ 2031 2032 if (speed != DWC3_DSTS_SUPERSPEED) 2033 return; 2034 2035 /* 2036 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2037 * each time on Connect Done. 2038 */ 2039 if (!usb30_clock) 2040 return; 2041 2042 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 2043 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 2044 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 2045} 2046 2047static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed) 2048{ 2049 switch (speed) { 2050 case USB_SPEED_SUPER: 2051 dwc3_gadget_usb2_phy_suspend(dwc, true); 2052 break; 2053 case USB_SPEED_HIGH: 2054 case USB_SPEED_FULL: 2055 case USB_SPEED_LOW: 2056 dwc3_gadget_usb3_phy_suspend(dwc, true); 2057 break; 2058 } 2059} 2060 2061static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2062{ 2063 struct dwc3_gadget_ep_cmd_params params; 2064 struct dwc3_ep *dep; 2065 int ret; 2066 u32 reg; 2067 u8 speed; 2068 2069 dev_vdbg(dwc->dev, "%s\n", __func__); 2070 2071 memset(¶ms, 0x00, sizeof(params)); 2072 2073 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2074 speed = reg & DWC3_DSTS_CONNECTSPD; 2075 dwc->speed = speed; 2076 2077 dwc3_update_ram_clk_sel(dwc, speed); 2078 2079 switch (speed) { 2080 case DWC3_DCFG_SUPERSPEED: 2081 /* 2082 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2083 * would cause a missing USB3 Reset event. 2084 * 2085 * In such situations, we should force a USB3 Reset 2086 * event by calling our dwc3_gadget_reset_interrupt() 2087 * routine. 2088 * 2089 * Refers to: 2090 * 2091 * STAR#9000483510: RTL: SS : USB3 reset event may 2092 * not be generated always when the link enters poll 2093 */ 2094 if (dwc->revision < DWC3_REVISION_190A) 2095 dwc3_gadget_reset_interrupt(dwc); 2096 2097 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2098 dwc->gadget.ep0->maxpacket = 512; 2099 dwc->gadget.speed = USB_SPEED_SUPER; 2100 break; 2101 case DWC3_DCFG_HIGHSPEED: 2102 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2103 dwc->gadget.ep0->maxpacket = 64; 2104 dwc->gadget.speed = USB_SPEED_HIGH; 2105 break; 2106 case DWC3_DCFG_FULLSPEED2: 2107 case DWC3_DCFG_FULLSPEED1: 2108 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2109 dwc->gadget.ep0->maxpacket = 64; 2110 dwc->gadget.speed = USB_SPEED_FULL; 2111 break; 2112 case DWC3_DCFG_LOWSPEED: 2113 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2114 dwc->gadget.ep0->maxpacket = 8; 2115 dwc->gadget.speed = USB_SPEED_LOW; 2116 break; 2117 } 2118 2119 /* Recent versions support automatic phy suspend and don't need this */ 2120 if (dwc->revision < DWC3_REVISION_194A) { 2121 /* Suspend unneeded PHY */ 2122 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed); 2123 } 2124 2125 dep = dwc->eps[0]; 2126 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 2127 if (ret) { 2128 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2129 return; 2130 } 2131 2132 dep = dwc->eps[1]; 2133 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 2134 if (ret) { 2135 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2136 return; 2137 } 2138 2139 /* 2140 * Configure PHY via GUSB3PIPECTLn if required. 2141 * 2142 * Update GTXFIFOSIZn 2143 * 2144 * In both cases reset values should be sufficient. 2145 */ 2146} 2147 2148static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2149{ 2150 dev_vdbg(dwc->dev, "%s\n", __func__); 2151 2152 /* 2153 * TODO take core out of low power mode when that's 2154 * implemented. 2155 */ 2156 2157 dwc->gadget_driver->resume(&dwc->gadget); 2158} 2159 2160static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2161 unsigned int evtinfo) 2162{ 2163 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2164 2165 /* 2166 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2167 * on the link partner, the USB session might do multiple entry/exit 2168 * of low power states before a transfer takes place. 2169 * 2170 * Due to this problem, we might experience lower throughput. The 2171 * suggested workaround is to disable DCTL[12:9] bits if we're 2172 * transitioning from U1/U2 to U0 and enable those bits again 2173 * after a transfer completes and there are no pending transfers 2174 * on any of the enabled endpoints. 2175 * 2176 * This is the first half of that workaround. 2177 * 2178 * Refers to: 2179 * 2180 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2181 * core send LGO_Ux entering U0 2182 */ 2183 if (dwc->revision < DWC3_REVISION_183A) { 2184 if (next == DWC3_LINK_STATE_U0) { 2185 u32 u1u2; 2186 u32 reg; 2187 2188 switch (dwc->link_state) { 2189 case DWC3_LINK_STATE_U1: 2190 case DWC3_LINK_STATE_U2: 2191 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2192 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2193 | DWC3_DCTL_ACCEPTU2ENA 2194 | DWC3_DCTL_INITU1ENA 2195 | DWC3_DCTL_ACCEPTU1ENA); 2196 2197 if (!dwc->u1u2) 2198 dwc->u1u2 = reg & u1u2; 2199 2200 reg &= ~u1u2; 2201 2202 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2203 break; 2204 default: 2205 /* do nothing */ 2206 break; 2207 } 2208 } 2209 } 2210 2211 dwc->link_state = next; 2212 2213 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 2214} 2215 2216static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2217 const struct dwc3_event_devt *event) 2218{ 2219 switch (event->type) { 2220 case DWC3_DEVICE_EVENT_DISCONNECT: 2221 dwc3_gadget_disconnect_interrupt(dwc); 2222 break; 2223 case DWC3_DEVICE_EVENT_RESET: 2224 dwc3_gadget_reset_interrupt(dwc); 2225 break; 2226 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2227 dwc3_gadget_conndone_interrupt(dwc); 2228 break; 2229 case DWC3_DEVICE_EVENT_WAKEUP: 2230 dwc3_gadget_wakeup_interrupt(dwc); 2231 break; 2232 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2233 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2234 break; 2235 case DWC3_DEVICE_EVENT_EOPF: 2236 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2237 break; 2238 case DWC3_DEVICE_EVENT_SOF: 2239 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2240 break; 2241 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2242 dev_vdbg(dwc->dev, "Erratic Error\n"); 2243 break; 2244 case DWC3_DEVICE_EVENT_CMD_CMPL: 2245 dev_vdbg(dwc->dev, "Command Complete\n"); 2246 break; 2247 case DWC3_DEVICE_EVENT_OVERFLOW: 2248 dev_vdbg(dwc->dev, "Overflow\n"); 2249 break; 2250 default: 2251 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2252 } 2253} 2254 2255static void dwc3_process_event_entry(struct dwc3 *dwc, 2256 const union dwc3_event *event) 2257{ 2258 /* Endpoint IRQ, handle it and return early */ 2259 if (event->type.is_devspec == 0) { 2260 /* depevt */ 2261 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2262 } 2263 2264 switch (event->type.type) { 2265 case DWC3_EVENT_TYPE_DEV: 2266 dwc3_gadget_interrupt(dwc, &event->devt); 2267 break; 2268 /* REVISIT what to do with Carkit and I2C events ? */ 2269 default: 2270 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2271 } 2272} 2273 2274static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2275{ 2276 struct dwc3_event_buffer *evt; 2277 int left; 2278 u32 count; 2279 2280 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2281 count &= DWC3_GEVNTCOUNT_MASK; 2282 if (!count) 2283 return IRQ_NONE; 2284 2285 evt = dwc->ev_buffs[buf]; 2286 left = count; 2287 2288 while (left > 0) { 2289 union dwc3_event event; 2290 2291 event.raw = *(u32 *) (evt->buf + evt->lpos); 2292 2293 dwc3_process_event_entry(dwc, &event); 2294 /* 2295 * XXX we wrap around correctly to the next entry as almost all 2296 * entries are 4 bytes in size. There is one entry which has 12 2297 * bytes which is a regular entry followed by 8 bytes data. ATM 2298 * I don't know how things are organized if were get next to the 2299 * a boundary so I worry about that once we try to handle that. 2300 */ 2301 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2302 left -= 4; 2303 2304 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2305 } 2306 2307 return IRQ_HANDLED; 2308} 2309 2310static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2311{ 2312 struct dwc3 *dwc = _dwc; 2313 int i; 2314 irqreturn_t ret = IRQ_NONE; 2315 2316 spin_lock(&dwc->lock); 2317 2318 for (i = 0; i < dwc->num_event_buffers; i++) { 2319 irqreturn_t status; 2320 2321 status = dwc3_process_event_buf(dwc, i); 2322 if (status == IRQ_HANDLED) 2323 ret = status; 2324 } 2325 2326 spin_unlock(&dwc->lock); 2327 2328 return ret; 2329} 2330 2331/** 2332 * dwc3_gadget_init - Initializes gadget related registers 2333 * @dwc: pointer to our controller context structure 2334 * 2335 * Returns 0 on success otherwise negative errno. 2336 */ 2337int __devinit dwc3_gadget_init(struct dwc3 *dwc) 2338{ 2339 u32 reg; 2340 int ret; 2341 int irq; 2342 2343 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2344 &dwc->ctrl_req_addr, GFP_KERNEL); 2345 if (!dwc->ctrl_req) { 2346 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2347 ret = -ENOMEM; 2348 goto err0; 2349 } 2350 2351 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2352 &dwc->ep0_trb_addr, GFP_KERNEL); 2353 if (!dwc->ep0_trb) { 2354 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2355 ret = -ENOMEM; 2356 goto err1; 2357 } 2358 2359 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); 2360 if (!dwc->setup_buf) { 2361 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2362 ret = -ENOMEM; 2363 goto err2; 2364 } 2365 2366 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2367 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, 2368 GFP_KERNEL); 2369 if (!dwc->ep0_bounce) { 2370 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2371 ret = -ENOMEM; 2372 goto err3; 2373 } 2374 2375 dev_set_name(&dwc->gadget.dev, "gadget"); 2376 2377 dwc->gadget.ops = &dwc3_gadget_ops; 2378 dwc->gadget.max_speed = USB_SPEED_SUPER; 2379 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2380 dwc->gadget.dev.parent = dwc->dev; 2381 dwc->gadget.sg_supported = true; 2382 2383 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); 2384 2385 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; 2386 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; 2387 dwc->gadget.dev.release = dwc3_gadget_release; 2388 dwc->gadget.name = "dwc3-gadget"; 2389 2390 /* 2391 * REVISIT: Here we should clear all pending IRQs to be 2392 * sure we're starting from a well known location. 2393 */ 2394 2395 ret = dwc3_gadget_init_endpoints(dwc); 2396 if (ret) 2397 goto err4; 2398 2399 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2400 2401 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, 2402 "dwc3", dwc); 2403 if (ret) { 2404 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 2405 irq, ret); 2406 goto err5; 2407 } 2408 2409 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2410 reg |= DWC3_DCFG_LPM_CAP; 2411 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2412 2413 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2414 reg |= DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA; 2415 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2416 2417 /* Enable all but Start and End of Frame IRQs */ 2418 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 2419 DWC3_DEVTEN_EVNTOVERFLOWEN | 2420 DWC3_DEVTEN_CMDCMPLTEN | 2421 DWC3_DEVTEN_ERRTICERREN | 2422 DWC3_DEVTEN_WKUPEVTEN | 2423 DWC3_DEVTEN_ULSTCNGEN | 2424 DWC3_DEVTEN_CONNECTDONEEN | 2425 DWC3_DEVTEN_USBRSTEN | 2426 DWC3_DEVTEN_DISCONNEVTEN); 2427 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 2428 2429 /* Enable USB2 LPM and automatic phy suspend only on recent versions */ 2430 if (dwc->revision >= DWC3_REVISION_194A) { 2431 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2432 reg |= DWC3_DCFG_LPM_CAP; 2433 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2434 2435 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2436 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2437 2438 /* TODO: This should be configurable */ 2439 reg |= DWC3_DCTL_HIRD_THRES(31); 2440 2441 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2442 2443 dwc3_gadget_usb2_phy_suspend(dwc, true); 2444 dwc3_gadget_usb3_phy_suspend(dwc, true); 2445 } 2446 2447 ret = device_register(&dwc->gadget.dev); 2448 if (ret) { 2449 dev_err(dwc->dev, "failed to register gadget device\n"); 2450 put_device(&dwc->gadget.dev); 2451 goto err6; 2452 } 2453 2454 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2455 if (ret) { 2456 dev_err(dwc->dev, "failed to register udc\n"); 2457 goto err7; 2458 } 2459 2460 return 0; 2461 2462err7: 2463 device_unregister(&dwc->gadget.dev); 2464 2465err6: 2466 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2467 free_irq(irq, dwc); 2468 2469err5: 2470 dwc3_gadget_free_endpoints(dwc); 2471 2472err4: 2473 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2474 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2475 2476err3: 2477 kfree(dwc->setup_buf); 2478 2479err2: 2480 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2481 dwc->ep0_trb, dwc->ep0_trb_addr); 2482 2483err1: 2484 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2485 dwc->ctrl_req, dwc->ctrl_req_addr); 2486 2487err0: 2488 return ret; 2489} 2490 2491void dwc3_gadget_exit(struct dwc3 *dwc) 2492{ 2493 int irq; 2494 2495 usb_del_gadget_udc(&dwc->gadget); 2496 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2497 2498 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2499 free_irq(irq, dwc); 2500 2501 dwc3_gadget_free_endpoints(dwc); 2502 2503 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2504 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2505 2506 kfree(dwc->setup_buf); 2507 2508 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2509 dwc->ep0_trb, dwc->ep0_trb_addr); 2510 2511 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2512 dwc->ctrl_req, dwc->ctrl_req_addr); 2513 2514 device_unregister(&dwc->gadget.dev); 2515} 2516