gadget.c revision c6f83f386c2f7987a344368e33e55840c12bd38f
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <linux/kernel.h> 40#include <linux/delay.h> 41#include <linux/slab.h> 42#include <linux/spinlock.h> 43#include <linux/platform_device.h> 44#include <linux/pm_runtime.h> 45#include <linux/interrupt.h> 46#include <linux/io.h> 47#include <linux/list.h> 48#include <linux/dma-mapping.h> 49 50#include <linux/usb/ch9.h> 51#include <linux/usb/gadget.h> 52 53#include "core.h" 54#include "gadget.h" 55#include "io.h" 56 57/** 58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 59 * @dwc: pointer to our context structure 60 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 61 * 62 * Caller should take care of locking. This function will 63 * return 0 on success or -EINVAL if wrong Test Selector 64 * is passed 65 */ 66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 67{ 68 u32 reg; 69 70 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 71 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 72 73 switch (mode) { 74 case TEST_J: 75 case TEST_K: 76 case TEST_SE0_NAK: 77 case TEST_PACKET: 78 case TEST_FORCE_EN: 79 reg |= mode << 1; 80 break; 81 default: 82 return -EINVAL; 83 } 84 85 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 86 87 return 0; 88} 89 90/** 91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 92 * @dwc: pointer to our context structure 93 * @state: the state to put link into 94 * 95 * Caller should take care of locking. This function will 96 * return 0 on success or -ETIMEDOUT. 97 */ 98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 99{ 100 int retries = 10000; 101 u32 reg; 102 103 /* 104 * Wait until device controller is ready. Only applies to 1.94a and 105 * later RTL. 106 */ 107 if (dwc->revision >= DWC3_REVISION_194A) { 108 while (--retries) { 109 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 110 if (reg & DWC3_DSTS_DCNRD) 111 udelay(5); 112 else 113 break; 114 } 115 116 if (retries <= 0) 117 return -ETIMEDOUT; 118 } 119 120 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 122 123 /* set requested state */ 124 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 125 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 126 127 /* 128 * The following code is racy when called from dwc3_gadget_wakeup, 129 * and is not needed, at least on newer versions 130 */ 131 if (dwc->revision >= DWC3_REVISION_194A) 132 return 0; 133 134 /* wait for a change in DSTS */ 135 retries = 10000; 136 while (--retries) { 137 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 138 139 if (DWC3_DSTS_USBLNKST(reg) == state) 140 return 0; 141 142 udelay(5); 143 } 144 145 dev_vdbg(dwc->dev, "link state change request timed out\n"); 146 147 return -ETIMEDOUT; 148} 149 150/** 151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 152 * @dwc: pointer to our context structure 153 * 154 * This function will a best effort FIFO allocation in order 155 * to improve FIFO usage and throughput, while still allowing 156 * us to enable as many endpoints as possible. 157 * 158 * Keep in mind that this operation will be highly dependent 159 * on the configured size for RAM1 - which contains TxFifo -, 160 * the amount of endpoints enabled on coreConsultant tool, and 161 * the width of the Master Bus. 162 * 163 * In the ideal world, we would always be able to satisfy the 164 * following equation: 165 * 166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 168 * 169 * Unfortunately, due to many variables that's not always the case. 170 */ 171int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 172{ 173 int last_fifo_depth = 0; 174 int ram1_depth; 175 int fifo_size; 176 int mdwidth; 177 int num; 178 179 if (!dwc->needs_fifo_resize) 180 return 0; 181 182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 184 185 /* MDWIDTH is represented in bits, we need it in bytes */ 186 mdwidth >>= 3; 187 188 /* 189 * FIXME For now we will only allocate 1 wMaxPacketSize space 190 * for each enabled endpoint, later patches will come to 191 * improve this algorithm so that we better use the internal 192 * FIFO space 193 */ 194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { 195 struct dwc3_ep *dep = dwc->eps[num]; 196 int fifo_number = dep->number >> 1; 197 int mult = 1; 198 int tmp; 199 200 if (!(dep->number & 1)) 201 continue; 202 203 if (!(dep->flags & DWC3_EP_ENABLED)) 204 continue; 205 206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) 207 || usb_endpoint_xfer_isoc(dep->endpoint.desc)) 208 mult = 3; 209 210 /* 211 * REVISIT: the following assumes we will always have enough 212 * space available on the FIFO RAM for all possible use cases. 213 * Make sure that's true somehow and change FIFO allocation 214 * accordingly. 215 * 216 * If we have Bulk or Isochronous endpoints, we want 217 * them to be able to be very, very fast. So we're giving 218 * those endpoints a fifo_size which is enough for 3 full 219 * packets 220 */ 221 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 222 tmp += mdwidth; 223 224 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 225 226 fifo_size |= (last_fifo_depth << 16); 227 228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 229 dep->name, last_fifo_depth, fifo_size & 0xffff); 230 231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), 232 fifo_size); 233 234 last_fifo_depth += (fifo_size & 0xffff); 235 } 236 237 return 0; 238} 239 240void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 241 int status) 242{ 243 struct dwc3 *dwc = dep->dwc; 244 245 if (req->queued) { 246 if (req->request.num_mapped_sgs) 247 dep->busy_slot += req->request.num_mapped_sgs; 248 else 249 dep->busy_slot++; 250 251 /* 252 * Skip LINK TRB. We can't use req->trb and check for 253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just 254 * completed (not the LINK TRB). 255 */ 256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 257 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 258 dep->busy_slot++; 259 } 260 list_del(&req->list); 261 req->trb = NULL; 262 263 if (req->request.status == -EINPROGRESS) 264 req->request.status = status; 265 266 usb_gadget_unmap_request(&dwc->gadget, &req->request, 267 req->direction); 268 269 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 270 req, dep->name, req->request.actual, 271 req->request.length, status); 272 273 spin_unlock(&dwc->lock); 274 req->request.complete(&dep->endpoint, &req->request); 275 spin_lock(&dwc->lock); 276} 277 278static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 279{ 280 switch (cmd) { 281 case DWC3_DEPCMD_DEPSTARTCFG: 282 return "Start New Configuration"; 283 case DWC3_DEPCMD_ENDTRANSFER: 284 return "End Transfer"; 285 case DWC3_DEPCMD_UPDATETRANSFER: 286 return "Update Transfer"; 287 case DWC3_DEPCMD_STARTTRANSFER: 288 return "Start Transfer"; 289 case DWC3_DEPCMD_CLEARSTALL: 290 return "Clear Stall"; 291 case DWC3_DEPCMD_SETSTALL: 292 return "Set Stall"; 293 case DWC3_DEPCMD_GETEPSTATE: 294 return "Get Endpoint State"; 295 case DWC3_DEPCMD_SETTRANSFRESOURCE: 296 return "Set Endpoint Transfer Resource"; 297 case DWC3_DEPCMD_SETEPCONFIG: 298 return "Set Endpoint Configuration"; 299 default: 300 return "UNKNOWN command"; 301 } 302} 303 304int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) 305{ 306 u32 timeout = 500; 307 u32 reg; 308 309 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 310 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 311 312 do { 313 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 314 if (!(reg & DWC3_DGCMD_CMDACT)) { 315 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 316 DWC3_DGCMD_STATUS(reg)); 317 return 0; 318 } 319 320 /* 321 * We can't sleep here, because it's also called from 322 * interrupt context. 323 */ 324 timeout--; 325 if (!timeout) 326 return -ETIMEDOUT; 327 udelay(1); 328 } while (1); 329} 330 331int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 332 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 333{ 334 struct dwc3_ep *dep = dwc->eps[ep]; 335 u32 timeout = 500; 336 u32 reg; 337 338 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 339 dep->name, 340 dwc3_gadget_ep_cmd_string(cmd), params->param0, 341 params->param1, params->param2); 342 343 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 346 347 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 348 do { 349 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 350 if (!(reg & DWC3_DEPCMD_CMDACT)) { 351 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 352 DWC3_DEPCMD_STATUS(reg)); 353 return 0; 354 } 355 356 /* 357 * We can't sleep here, because it is also called from 358 * interrupt context. 359 */ 360 timeout--; 361 if (!timeout) 362 return -ETIMEDOUT; 363 364 udelay(1); 365 } while (1); 366} 367 368static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 369 struct dwc3_trb *trb) 370{ 371 u32 offset = (char *) trb - (char *) dep->trb_pool; 372 373 return dep->trb_pool_dma + offset; 374} 375 376static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 377{ 378 struct dwc3 *dwc = dep->dwc; 379 380 if (dep->trb_pool) 381 return 0; 382 383 if (dep->number == 0 || dep->number == 1) 384 return 0; 385 386 dep->trb_pool = dma_alloc_coherent(dwc->dev, 387 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 388 &dep->trb_pool_dma, GFP_KERNEL); 389 if (!dep->trb_pool) { 390 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 391 dep->name); 392 return -ENOMEM; 393 } 394 395 return 0; 396} 397 398static void dwc3_free_trb_pool(struct dwc3_ep *dep) 399{ 400 struct dwc3 *dwc = dep->dwc; 401 402 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 403 dep->trb_pool, dep->trb_pool_dma); 404 405 dep->trb_pool = NULL; 406 dep->trb_pool_dma = 0; 407} 408 409static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 410{ 411 struct dwc3_gadget_ep_cmd_params params; 412 u32 cmd; 413 414 memset(¶ms, 0x00, sizeof(params)); 415 416 if (dep->number != 1) { 417 cmd = DWC3_DEPCMD_DEPSTARTCFG; 418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 419 if (dep->number > 1) { 420 if (dwc->start_config_issued) 421 return 0; 422 dwc->start_config_issued = true; 423 cmd |= DWC3_DEPCMD_PARAM(2); 424 } 425 426 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 427 } 428 429 return 0; 430} 431 432static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 433 const struct usb_endpoint_descriptor *desc, 434 const struct usb_ss_ep_comp_descriptor *comp_desc, 435 bool ignore) 436{ 437 struct dwc3_gadget_ep_cmd_params params; 438 439 memset(¶ms, 0x00, sizeof(params)); 440 441 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 442 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) 443 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst - 1); 444 445 if (ignore) 446 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; 447 448 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 449 | DWC3_DEPCFG_XFER_NOT_READY_EN; 450 451 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 452 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 453 | DWC3_DEPCFG_STREAM_EVENT_EN; 454 dep->stream_capable = true; 455 } 456 457 if (usb_endpoint_xfer_isoc(desc)) 458 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 459 460 /* 461 * We are doing 1:1 mapping for endpoints, meaning 462 * Physical Endpoints 2 maps to Logical Endpoint 2 and 463 * so on. We consider the direction bit as part of the physical 464 * endpoint number. So USB endpoint 0x81 is 0x03. 465 */ 466 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 467 468 /* 469 * We must use the lower 16 TX FIFOs even though 470 * HW might have more 471 */ 472 if (dep->direction) 473 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 474 475 if (desc->bInterval) { 476 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 477 dep->interval = 1 << (desc->bInterval - 1); 478 } 479 480 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 481 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 482} 483 484static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 485{ 486 struct dwc3_gadget_ep_cmd_params params; 487 488 memset(¶ms, 0x00, sizeof(params)); 489 490 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 491 492 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 493 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 494} 495 496/** 497 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 498 * @dep: endpoint to be initialized 499 * @desc: USB Endpoint Descriptor 500 * 501 * Caller should take care of locking 502 */ 503static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 504 const struct usb_endpoint_descriptor *desc, 505 const struct usb_ss_ep_comp_descriptor *comp_desc, 506 bool ignore) 507{ 508 struct dwc3 *dwc = dep->dwc; 509 u32 reg; 510 int ret = -ENOMEM; 511 512 if (!(dep->flags & DWC3_EP_ENABLED)) { 513 ret = dwc3_gadget_start_config(dwc, dep); 514 if (ret) 515 return ret; 516 } 517 518 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore); 519 if (ret) 520 return ret; 521 522 if (!(dep->flags & DWC3_EP_ENABLED)) { 523 struct dwc3_trb *trb_st_hw; 524 struct dwc3_trb *trb_link; 525 526 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 527 if (ret) 528 return ret; 529 530 dep->endpoint.desc = desc; 531 dep->comp_desc = comp_desc; 532 dep->type = usb_endpoint_type(desc); 533 dep->flags |= DWC3_EP_ENABLED; 534 535 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 536 reg |= DWC3_DALEPENA_EP(dep->number); 537 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 538 539 if (!usb_endpoint_xfer_isoc(desc)) 540 return 0; 541 542 memset(&trb_link, 0, sizeof(trb_link)); 543 544 /* Link TRB for ISOC. The HWO bit is never reset */ 545 trb_st_hw = &dep->trb_pool[0]; 546 547 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 548 549 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 550 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 551 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 552 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 553 } 554 555 return 0; 556} 557 558static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); 559static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 560{ 561 struct dwc3_request *req; 562 563 if (!list_empty(&dep->req_queued)) { 564 dwc3_stop_active_transfer(dwc, dep->number); 565 566 /* - giveback all requests to gadget driver */ 567 while (!list_empty(&dep->req_queued)) { 568 req = next_request(&dep->req_queued); 569 570 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 571 } 572 } 573 574 while (!list_empty(&dep->request_list)) { 575 req = next_request(&dep->request_list); 576 577 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 578 } 579} 580 581/** 582 * __dwc3_gadget_ep_disable - Disables a HW endpoint 583 * @dep: the endpoint to disable 584 * 585 * This function also removes requests which are currently processed ny the 586 * hardware and those which are not yet scheduled. 587 * Caller should take care of locking. 588 */ 589static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 590{ 591 struct dwc3 *dwc = dep->dwc; 592 u32 reg; 593 594 dwc3_remove_requests(dwc, dep); 595 596 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 597 reg &= ~DWC3_DALEPENA_EP(dep->number); 598 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 599 600 dep->stream_capable = false; 601 dep->endpoint.desc = NULL; 602 dep->comp_desc = NULL; 603 dep->type = 0; 604 dep->flags = 0; 605 606 return 0; 607} 608 609/* -------------------------------------------------------------------------- */ 610 611static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 612 const struct usb_endpoint_descriptor *desc) 613{ 614 return -EINVAL; 615} 616 617static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 618{ 619 return -EINVAL; 620} 621 622/* -------------------------------------------------------------------------- */ 623 624static int dwc3_gadget_ep_enable(struct usb_ep *ep, 625 const struct usb_endpoint_descriptor *desc) 626{ 627 struct dwc3_ep *dep; 628 struct dwc3 *dwc; 629 unsigned long flags; 630 int ret; 631 632 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 633 pr_debug("dwc3: invalid parameters\n"); 634 return -EINVAL; 635 } 636 637 if (!desc->wMaxPacketSize) { 638 pr_debug("dwc3: missing wMaxPacketSize\n"); 639 return -EINVAL; 640 } 641 642 dep = to_dwc3_ep(ep); 643 dwc = dep->dwc; 644 645 if (dep->flags & DWC3_EP_ENABLED) { 646 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 647 dep->name); 648 return 0; 649 } 650 651 switch (usb_endpoint_type(desc)) { 652 case USB_ENDPOINT_XFER_CONTROL: 653 strlcat(dep->name, "-control", sizeof(dep->name)); 654 break; 655 case USB_ENDPOINT_XFER_ISOC: 656 strlcat(dep->name, "-isoc", sizeof(dep->name)); 657 break; 658 case USB_ENDPOINT_XFER_BULK: 659 strlcat(dep->name, "-bulk", sizeof(dep->name)); 660 break; 661 case USB_ENDPOINT_XFER_INT: 662 strlcat(dep->name, "-int", sizeof(dep->name)); 663 break; 664 default: 665 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 666 } 667 668 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 669 670 spin_lock_irqsave(&dwc->lock, flags); 671 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false); 672 spin_unlock_irqrestore(&dwc->lock, flags); 673 674 return ret; 675} 676 677static int dwc3_gadget_ep_disable(struct usb_ep *ep) 678{ 679 struct dwc3_ep *dep; 680 struct dwc3 *dwc; 681 unsigned long flags; 682 int ret; 683 684 if (!ep) { 685 pr_debug("dwc3: invalid parameters\n"); 686 return -EINVAL; 687 } 688 689 dep = to_dwc3_ep(ep); 690 dwc = dep->dwc; 691 692 if (!(dep->flags & DWC3_EP_ENABLED)) { 693 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 694 dep->name); 695 return 0; 696 } 697 698 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 699 dep->number >> 1, 700 (dep->number & 1) ? "in" : "out"); 701 702 spin_lock_irqsave(&dwc->lock, flags); 703 ret = __dwc3_gadget_ep_disable(dep); 704 spin_unlock_irqrestore(&dwc->lock, flags); 705 706 return ret; 707} 708 709static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 710 gfp_t gfp_flags) 711{ 712 struct dwc3_request *req; 713 struct dwc3_ep *dep = to_dwc3_ep(ep); 714 struct dwc3 *dwc = dep->dwc; 715 716 req = kzalloc(sizeof(*req), gfp_flags); 717 if (!req) { 718 dev_err(dwc->dev, "not enough memory\n"); 719 return NULL; 720 } 721 722 req->epnum = dep->number; 723 req->dep = dep; 724 725 return &req->request; 726} 727 728static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 729 struct usb_request *request) 730{ 731 struct dwc3_request *req = to_dwc3_request(request); 732 733 kfree(req); 734} 735 736/** 737 * dwc3_prepare_one_trb - setup one TRB from one request 738 * @dep: endpoint for which this request is prepared 739 * @req: dwc3_request pointer 740 */ 741static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 742 struct dwc3_request *req, dma_addr_t dma, 743 unsigned length, unsigned last, unsigned chain) 744{ 745 struct dwc3 *dwc = dep->dwc; 746 struct dwc3_trb *trb; 747 748 unsigned int cur_slot; 749 750 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 751 dep->name, req, (unsigned long long) dma, 752 length, last ? " last" : "", 753 chain ? " chain" : ""); 754 755 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 756 cur_slot = dep->free_slot; 757 dep->free_slot++; 758 759 /* Skip the LINK-TRB on ISOC */ 760 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 761 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 762 return; 763 764 if (!req->trb) { 765 dwc3_gadget_move_request_queued(req); 766 req->trb = trb; 767 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 768 } 769 770 trb->size = DWC3_TRB_SIZE_LENGTH(length); 771 trb->bpl = lower_32_bits(dma); 772 trb->bph = upper_32_bits(dma); 773 774 switch (usb_endpoint_type(dep->endpoint.desc)) { 775 case USB_ENDPOINT_XFER_CONTROL: 776 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 777 break; 778 779 case USB_ENDPOINT_XFER_ISOC: 780 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 781 782 if (!req->request.no_interrupt) 783 trb->ctrl |= DWC3_TRB_CTRL_IOC; 784 break; 785 786 case USB_ENDPOINT_XFER_BULK: 787 case USB_ENDPOINT_XFER_INT: 788 trb->ctrl = DWC3_TRBCTL_NORMAL; 789 break; 790 default: 791 /* 792 * This is only possible with faulty memory because we 793 * checked it already :) 794 */ 795 BUG(); 796 } 797 798 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 799 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 800 trb->ctrl |= DWC3_TRB_CTRL_CSP; 801 } else { 802 if (chain) 803 trb->ctrl |= DWC3_TRB_CTRL_CHN; 804 805 if (last) 806 trb->ctrl |= DWC3_TRB_CTRL_LST; 807 } 808 809 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 810 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); 811 812 trb->ctrl |= DWC3_TRB_CTRL_HWO; 813} 814 815/* 816 * dwc3_prepare_trbs - setup TRBs from requests 817 * @dep: endpoint for which requests are being prepared 818 * @starting: true if the endpoint is idle and no requests are queued. 819 * 820 * The function goes through the requests list and sets up TRBs for the 821 * transfers. The function returns once there are no more TRBs available or 822 * it runs out of requests. 823 */ 824static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 825{ 826 struct dwc3_request *req, *n; 827 u32 trbs_left; 828 u32 max; 829 unsigned int last_one = 0; 830 831 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 832 833 /* the first request must not be queued */ 834 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 835 836 /* Can't wrap around on a non-isoc EP since there's no link TRB */ 837 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 838 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); 839 if (trbs_left > max) 840 trbs_left = max; 841 } 842 843 /* 844 * If busy & slot are equal than it is either full or empty. If we are 845 * starting to process requests then we are empty. Otherwise we are 846 * full and don't do anything 847 */ 848 if (!trbs_left) { 849 if (!starting) 850 return; 851 trbs_left = DWC3_TRB_NUM; 852 /* 853 * In case we start from scratch, we queue the ISOC requests 854 * starting from slot 1. This is done because we use ring 855 * buffer and have no LST bit to stop us. Instead, we place 856 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt 857 * after the first request so we start at slot 1 and have 858 * 7 requests proceed before we hit the first IOC. 859 * Other transfer types don't use the ring buffer and are 860 * processed from the first TRB until the last one. Since we 861 * don't wrap around we have to start at the beginning. 862 */ 863 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 864 dep->busy_slot = 1; 865 dep->free_slot = 1; 866 } else { 867 dep->busy_slot = 0; 868 dep->free_slot = 0; 869 } 870 } 871 872 /* The last TRB is a link TRB, not used for xfer */ 873 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) 874 return; 875 876 list_for_each_entry_safe(req, n, &dep->request_list, list) { 877 unsigned length; 878 dma_addr_t dma; 879 880 if (req->request.num_mapped_sgs > 0) { 881 struct usb_request *request = &req->request; 882 struct scatterlist *sg = request->sg; 883 struct scatterlist *s; 884 int i; 885 886 for_each_sg(sg, s, request->num_mapped_sgs, i) { 887 unsigned chain = true; 888 889 length = sg_dma_len(s); 890 dma = sg_dma_address(s); 891 892 if (i == (request->num_mapped_sgs - 1) || 893 sg_is_last(s)) { 894 last_one = true; 895 chain = false; 896 } 897 898 trbs_left--; 899 if (!trbs_left) 900 last_one = true; 901 902 if (last_one) 903 chain = false; 904 905 dwc3_prepare_one_trb(dep, req, dma, length, 906 last_one, chain); 907 908 if (last_one) 909 break; 910 } 911 } else { 912 dma = req->request.dma; 913 length = req->request.length; 914 trbs_left--; 915 916 if (!trbs_left) 917 last_one = 1; 918 919 /* Is this the last request? */ 920 if (list_is_last(&req->list, &dep->request_list)) 921 last_one = 1; 922 923 dwc3_prepare_one_trb(dep, req, dma, length, 924 last_one, false); 925 926 if (last_one) 927 break; 928 } 929 } 930} 931 932static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 933 int start_new) 934{ 935 struct dwc3_gadget_ep_cmd_params params; 936 struct dwc3_request *req; 937 struct dwc3 *dwc = dep->dwc; 938 int ret; 939 u32 cmd; 940 941 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 942 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 943 return -EBUSY; 944 } 945 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 946 947 /* 948 * If we are getting here after a short-out-packet we don't enqueue any 949 * new requests as we try to set the IOC bit only on the last request. 950 */ 951 if (start_new) { 952 if (list_empty(&dep->req_queued)) 953 dwc3_prepare_trbs(dep, start_new); 954 955 /* req points to the first request which will be sent */ 956 req = next_request(&dep->req_queued); 957 } else { 958 dwc3_prepare_trbs(dep, start_new); 959 960 /* 961 * req points to the first request where HWO changed from 0 to 1 962 */ 963 req = next_request(&dep->req_queued); 964 } 965 if (!req) { 966 dep->flags |= DWC3_EP_PENDING_REQUEST; 967 return 0; 968 } 969 970 memset(¶ms, 0, sizeof(params)); 971 params.param0 = upper_32_bits(req->trb_dma); 972 params.param1 = lower_32_bits(req->trb_dma); 973 974 if (start_new) 975 cmd = DWC3_DEPCMD_STARTTRANSFER; 976 else 977 cmd = DWC3_DEPCMD_UPDATETRANSFER; 978 979 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 980 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 981 if (ret < 0) { 982 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 983 984 /* 985 * FIXME we need to iterate over the list of requests 986 * here and stop, unmap, free and del each of the linked 987 * requests instead of what we do now. 988 */ 989 usb_gadget_unmap_request(&dwc->gadget, &req->request, 990 req->direction); 991 list_del(&req->list); 992 return ret; 993 } 994 995 dep->flags |= DWC3_EP_BUSY; 996 997 if (start_new) { 998 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 999 dep->number); 1000 WARN_ON_ONCE(!dep->resource_index); 1001 } 1002 1003 return 0; 1004} 1005 1006static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, 1007 struct dwc3_ep *dep, u32 cur_uf) 1008{ 1009 u32 uf; 1010 1011 if (list_empty(&dep->request_list)) { 1012 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1013 dep->name); 1014 return; 1015 } 1016 1017 /* 4 micro frames in the future */ 1018 uf = cur_uf + dep->interval * 4; 1019 1020 __dwc3_gadget_kick_transfer(dep, uf, 1); 1021} 1022 1023static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1024 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1025{ 1026 u32 cur_uf, mask; 1027 1028 mask = ~(dep->interval - 1); 1029 cur_uf = event->parameters & mask; 1030 1031 __dwc3_gadget_start_isoc(dwc, dep, cur_uf); 1032} 1033 1034static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 1035{ 1036 struct dwc3 *dwc = dep->dwc; 1037 int ret; 1038 1039 req->request.actual = 0; 1040 req->request.status = -EINPROGRESS; 1041 req->direction = dep->direction; 1042 req->epnum = dep->number; 1043 1044 /* 1045 * We only add to our list of requests now and 1046 * start consuming the list once we get XferNotReady 1047 * IRQ. 1048 * 1049 * That way, we avoid doing anything that we don't need 1050 * to do now and defer it until the point we receive a 1051 * particular token from the Host side. 1052 * 1053 * This will also avoid Host cancelling URBs due to too 1054 * many NAKs. 1055 */ 1056 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1057 dep->direction); 1058 if (ret) 1059 return ret; 1060 1061 list_add_tail(&req->list, &dep->request_list); 1062 1063 /* 1064 * There are a few special cases: 1065 * 1066 * 1. XferNotReady with empty list of requests. We need to kick the 1067 * transfer here in that situation, otherwise we will be NAKing 1068 * forever. If we get XferNotReady before gadget driver has a 1069 * chance to queue a request, we will ACK the IRQ but won't be 1070 * able to receive the data until the next request is queued. 1071 * The following code is handling exactly that. 1072 * 1073 */ 1074 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1075 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1076 if (ret && ret != -EBUSY) 1077 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1078 dep->name); 1079 } 1080 1081 /* 1082 * 2. XferInProgress on Isoc EP with an active transfer. We need to 1083 * kick the transfer here after queuing a request, otherwise the 1084 * core may not see the modified TRB(s). 1085 */ 1086 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1087 (dep->flags & DWC3_EP_BUSY) && 1088 !(dep->flags & DWC3_EP_MISSED_ISOC)) { 1089 WARN_ON_ONCE(!dep->resource_index); 1090 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, 1091 false); 1092 if (ret && ret != -EBUSY) 1093 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1094 dep->name); 1095 } 1096 1097 /* 1098 * 3. Missed ISOC Handling. We need to start isoc transfer on the saved 1099 * uframe number. 1100 */ 1101 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1102 (dep->flags & DWC3_EP_MISSED_ISOC)) { 1103 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf); 1104 dep->flags &= ~DWC3_EP_MISSED_ISOC; 1105 } 1106 1107 return 0; 1108} 1109 1110static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1111 gfp_t gfp_flags) 1112{ 1113 struct dwc3_request *req = to_dwc3_request(request); 1114 struct dwc3_ep *dep = to_dwc3_ep(ep); 1115 struct dwc3 *dwc = dep->dwc; 1116 1117 unsigned long flags; 1118 1119 int ret; 1120 1121 if (!dep->endpoint.desc) { 1122 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1123 request, ep->name); 1124 return -ESHUTDOWN; 1125 } 1126 1127 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1128 request, ep->name, request->length); 1129 1130 spin_lock_irqsave(&dwc->lock, flags); 1131 ret = __dwc3_gadget_ep_queue(dep, req); 1132 spin_unlock_irqrestore(&dwc->lock, flags); 1133 1134 return ret; 1135} 1136 1137static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1138 struct usb_request *request) 1139{ 1140 struct dwc3_request *req = to_dwc3_request(request); 1141 struct dwc3_request *r = NULL; 1142 1143 struct dwc3_ep *dep = to_dwc3_ep(ep); 1144 struct dwc3 *dwc = dep->dwc; 1145 1146 unsigned long flags; 1147 int ret = 0; 1148 1149 spin_lock_irqsave(&dwc->lock, flags); 1150 1151 list_for_each_entry(r, &dep->request_list, list) { 1152 if (r == req) 1153 break; 1154 } 1155 1156 if (r != req) { 1157 list_for_each_entry(r, &dep->req_queued, list) { 1158 if (r == req) 1159 break; 1160 } 1161 if (r == req) { 1162 /* wait until it is processed */ 1163 dwc3_stop_active_transfer(dwc, dep->number); 1164 goto out1; 1165 } 1166 dev_err(dwc->dev, "request %p was not queued to %s\n", 1167 request, ep->name); 1168 ret = -EINVAL; 1169 goto out0; 1170 } 1171 1172out1: 1173 /* giveback the request */ 1174 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1175 1176out0: 1177 spin_unlock_irqrestore(&dwc->lock, flags); 1178 1179 return ret; 1180} 1181 1182int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1183{ 1184 struct dwc3_gadget_ep_cmd_params params; 1185 struct dwc3 *dwc = dep->dwc; 1186 int ret; 1187 1188 memset(¶ms, 0x00, sizeof(params)); 1189 1190 if (value) { 1191 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1192 DWC3_DEPCMD_SETSTALL, ¶ms); 1193 if (ret) 1194 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1195 value ? "set" : "clear", 1196 dep->name); 1197 else 1198 dep->flags |= DWC3_EP_STALL; 1199 } else { 1200 if (dep->flags & DWC3_EP_WEDGE) 1201 return 0; 1202 1203 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1204 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1205 if (ret) 1206 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1207 value ? "set" : "clear", 1208 dep->name); 1209 else 1210 dep->flags &= ~DWC3_EP_STALL; 1211 } 1212 1213 return ret; 1214} 1215 1216static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1217{ 1218 struct dwc3_ep *dep = to_dwc3_ep(ep); 1219 struct dwc3 *dwc = dep->dwc; 1220 1221 unsigned long flags; 1222 1223 int ret; 1224 1225 spin_lock_irqsave(&dwc->lock, flags); 1226 1227 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1228 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1229 ret = -EINVAL; 1230 goto out; 1231 } 1232 1233 ret = __dwc3_gadget_ep_set_halt(dep, value); 1234out: 1235 spin_unlock_irqrestore(&dwc->lock, flags); 1236 1237 return ret; 1238} 1239 1240static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1241{ 1242 struct dwc3_ep *dep = to_dwc3_ep(ep); 1243 struct dwc3 *dwc = dep->dwc; 1244 unsigned long flags; 1245 1246 spin_lock_irqsave(&dwc->lock, flags); 1247 dep->flags |= DWC3_EP_WEDGE; 1248 spin_unlock_irqrestore(&dwc->lock, flags); 1249 1250 if (dep->number == 0 || dep->number == 1) 1251 return dwc3_gadget_ep0_set_halt(ep, 1); 1252 else 1253 return dwc3_gadget_ep_set_halt(ep, 1); 1254} 1255 1256/* -------------------------------------------------------------------------- */ 1257 1258static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1259 .bLength = USB_DT_ENDPOINT_SIZE, 1260 .bDescriptorType = USB_DT_ENDPOINT, 1261 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1262}; 1263 1264static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1265 .enable = dwc3_gadget_ep0_enable, 1266 .disable = dwc3_gadget_ep0_disable, 1267 .alloc_request = dwc3_gadget_ep_alloc_request, 1268 .free_request = dwc3_gadget_ep_free_request, 1269 .queue = dwc3_gadget_ep0_queue, 1270 .dequeue = dwc3_gadget_ep_dequeue, 1271 .set_halt = dwc3_gadget_ep0_set_halt, 1272 .set_wedge = dwc3_gadget_ep_set_wedge, 1273}; 1274 1275static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1276 .enable = dwc3_gadget_ep_enable, 1277 .disable = dwc3_gadget_ep_disable, 1278 .alloc_request = dwc3_gadget_ep_alloc_request, 1279 .free_request = dwc3_gadget_ep_free_request, 1280 .queue = dwc3_gadget_ep_queue, 1281 .dequeue = dwc3_gadget_ep_dequeue, 1282 .set_halt = dwc3_gadget_ep_set_halt, 1283 .set_wedge = dwc3_gadget_ep_set_wedge, 1284}; 1285 1286/* -------------------------------------------------------------------------- */ 1287 1288static int dwc3_gadget_get_frame(struct usb_gadget *g) 1289{ 1290 struct dwc3 *dwc = gadget_to_dwc(g); 1291 u32 reg; 1292 1293 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1294 return DWC3_DSTS_SOFFN(reg); 1295} 1296 1297static int dwc3_gadget_wakeup(struct usb_gadget *g) 1298{ 1299 struct dwc3 *dwc = gadget_to_dwc(g); 1300 1301 unsigned long timeout; 1302 unsigned long flags; 1303 1304 u32 reg; 1305 1306 int ret = 0; 1307 1308 u8 link_state; 1309 u8 speed; 1310 1311 spin_lock_irqsave(&dwc->lock, flags); 1312 1313 /* 1314 * According to the Databook Remote wakeup request should 1315 * be issued only when the device is in early suspend state. 1316 * 1317 * We can check that via USB Link State bits in DSTS register. 1318 */ 1319 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1320 1321 speed = reg & DWC3_DSTS_CONNECTSPD; 1322 if (speed == DWC3_DSTS_SUPERSPEED) { 1323 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1324 ret = -EINVAL; 1325 goto out; 1326 } 1327 1328 link_state = DWC3_DSTS_USBLNKST(reg); 1329 1330 switch (link_state) { 1331 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1332 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1333 break; 1334 default: 1335 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1336 link_state); 1337 ret = -EINVAL; 1338 goto out; 1339 } 1340 1341 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1342 if (ret < 0) { 1343 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1344 goto out; 1345 } 1346 1347 /* Recent versions do this automatically */ 1348 if (dwc->revision < DWC3_REVISION_194A) { 1349 /* write zeroes to Link Change Request */ 1350 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1351 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1352 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1353 } 1354 1355 /* poll until Link State changes to ON */ 1356 timeout = jiffies + msecs_to_jiffies(100); 1357 1358 while (!time_after(jiffies, timeout)) { 1359 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1360 1361 /* in HS, means ON */ 1362 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1363 break; 1364 } 1365 1366 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1367 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1368 ret = -EINVAL; 1369 } 1370 1371out: 1372 spin_unlock_irqrestore(&dwc->lock, flags); 1373 1374 return ret; 1375} 1376 1377static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1378 int is_selfpowered) 1379{ 1380 struct dwc3 *dwc = gadget_to_dwc(g); 1381 unsigned long flags; 1382 1383 spin_lock_irqsave(&dwc->lock, flags); 1384 dwc->is_selfpowered = !!is_selfpowered; 1385 spin_unlock_irqrestore(&dwc->lock, flags); 1386 1387 return 0; 1388} 1389 1390static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) 1391{ 1392 u32 reg; 1393 u32 timeout = 500; 1394 1395 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1396 if (is_on) { 1397 if (dwc->revision <= DWC3_REVISION_187A) { 1398 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1399 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1400 } 1401 1402 if (dwc->revision >= DWC3_REVISION_194A) 1403 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1404 reg |= DWC3_DCTL_RUN_STOP; 1405 } else { 1406 reg &= ~DWC3_DCTL_RUN_STOP; 1407 } 1408 1409 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1410 1411 do { 1412 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1413 if (is_on) { 1414 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1415 break; 1416 } else { 1417 if (reg & DWC3_DSTS_DEVCTRLHLT) 1418 break; 1419 } 1420 timeout--; 1421 if (!timeout) 1422 return -ETIMEDOUT; 1423 udelay(1); 1424 } while (1); 1425 1426 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1427 dwc->gadget_driver 1428 ? dwc->gadget_driver->function : "no-function", 1429 is_on ? "connect" : "disconnect"); 1430 1431 return 0; 1432} 1433 1434static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1435{ 1436 struct dwc3 *dwc = gadget_to_dwc(g); 1437 unsigned long flags; 1438 int ret; 1439 1440 is_on = !!is_on; 1441 1442 spin_lock_irqsave(&dwc->lock, flags); 1443 ret = dwc3_gadget_run_stop(dwc, is_on); 1444 spin_unlock_irqrestore(&dwc->lock, flags); 1445 1446 return ret; 1447} 1448 1449static int dwc3_gadget_start(struct usb_gadget *g, 1450 struct usb_gadget_driver *driver) 1451{ 1452 struct dwc3 *dwc = gadget_to_dwc(g); 1453 struct dwc3_ep *dep; 1454 unsigned long flags; 1455 int ret = 0; 1456 u32 reg; 1457 1458 spin_lock_irqsave(&dwc->lock, flags); 1459 1460 if (dwc->gadget_driver) { 1461 dev_err(dwc->dev, "%s is already bound to %s\n", 1462 dwc->gadget.name, 1463 dwc->gadget_driver->driver.name); 1464 ret = -EBUSY; 1465 goto err0; 1466 } 1467 1468 dwc->gadget_driver = driver; 1469 dwc->gadget.dev.driver = &driver->driver; 1470 1471 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1472 reg &= ~(DWC3_DCFG_SPEED_MASK); 1473 1474 /** 1475 * WORKAROUND: DWC3 revision < 2.20a have an issue 1476 * which would cause metastability state on Run/Stop 1477 * bit if we try to force the IP to USB2-only mode. 1478 * 1479 * Because of that, we cannot configure the IP to any 1480 * speed other than the SuperSpeed 1481 * 1482 * Refers to: 1483 * 1484 * STAR#9000525659: Clock Domain Crossing on DCTL in 1485 * USB 2.0 Mode 1486 */ 1487 if (dwc->revision < DWC3_REVISION_220A) 1488 reg |= DWC3_DCFG_SUPERSPEED; 1489 else 1490 reg |= dwc->maximum_speed; 1491 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1492 1493 dwc->start_config_issued = false; 1494 1495 /* Start with SuperSpeed Default */ 1496 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1497 1498 dep = dwc->eps[0]; 1499 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); 1500 if (ret) { 1501 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1502 goto err0; 1503 } 1504 1505 dep = dwc->eps[1]; 1506 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false); 1507 if (ret) { 1508 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1509 goto err1; 1510 } 1511 1512 /* begin to receive SETUP packets */ 1513 dwc->ep0state = EP0_SETUP_PHASE; 1514 dwc3_ep0_out_start(dwc); 1515 1516 spin_unlock_irqrestore(&dwc->lock, flags); 1517 1518 return 0; 1519 1520err1: 1521 __dwc3_gadget_ep_disable(dwc->eps[0]); 1522 1523err0: 1524 spin_unlock_irqrestore(&dwc->lock, flags); 1525 1526 return ret; 1527} 1528 1529static int dwc3_gadget_stop(struct usb_gadget *g, 1530 struct usb_gadget_driver *driver) 1531{ 1532 struct dwc3 *dwc = gadget_to_dwc(g); 1533 unsigned long flags; 1534 1535 spin_lock_irqsave(&dwc->lock, flags); 1536 1537 __dwc3_gadget_ep_disable(dwc->eps[0]); 1538 __dwc3_gadget_ep_disable(dwc->eps[1]); 1539 1540 dwc->gadget_driver = NULL; 1541 dwc->gadget.dev.driver = NULL; 1542 1543 spin_unlock_irqrestore(&dwc->lock, flags); 1544 1545 return 0; 1546} 1547 1548static const struct usb_gadget_ops dwc3_gadget_ops = { 1549 .get_frame = dwc3_gadget_get_frame, 1550 .wakeup = dwc3_gadget_wakeup, 1551 .set_selfpowered = dwc3_gadget_set_selfpowered, 1552 .pullup = dwc3_gadget_pullup, 1553 .udc_start = dwc3_gadget_start, 1554 .udc_stop = dwc3_gadget_stop, 1555}; 1556 1557/* -------------------------------------------------------------------------- */ 1558 1559static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1560{ 1561 struct dwc3_ep *dep; 1562 u8 epnum; 1563 1564 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1565 1566 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1567 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1568 if (!dep) { 1569 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1570 epnum); 1571 return -ENOMEM; 1572 } 1573 1574 dep->dwc = dwc; 1575 dep->number = epnum; 1576 dwc->eps[epnum] = dep; 1577 1578 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1579 (epnum & 1) ? "in" : "out"); 1580 dep->endpoint.name = dep->name; 1581 dep->direction = (epnum & 1); 1582 1583 if (epnum == 0 || epnum == 1) { 1584 dep->endpoint.maxpacket = 512; 1585 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1586 if (!epnum) 1587 dwc->gadget.ep0 = &dep->endpoint; 1588 } else { 1589 int ret; 1590 1591 dep->endpoint.maxpacket = 1024; 1592 dep->endpoint.max_streams = 15; 1593 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1594 list_add_tail(&dep->endpoint.ep_list, 1595 &dwc->gadget.ep_list); 1596 1597 ret = dwc3_alloc_trb_pool(dep); 1598 if (ret) 1599 return ret; 1600 } 1601 1602 INIT_LIST_HEAD(&dep->request_list); 1603 INIT_LIST_HEAD(&dep->req_queued); 1604 } 1605 1606 return 0; 1607} 1608 1609static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1610{ 1611 struct dwc3_ep *dep; 1612 u8 epnum; 1613 1614 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1615 dep = dwc->eps[epnum]; 1616 dwc3_free_trb_pool(dep); 1617 1618 if (epnum != 0 && epnum != 1) 1619 list_del(&dep->endpoint.ep_list); 1620 1621 kfree(dep); 1622 } 1623} 1624 1625static void dwc3_gadget_release(struct device *dev) 1626{ 1627 dev_dbg(dev, "%s\n", __func__); 1628} 1629 1630/* -------------------------------------------------------------------------- */ 1631static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1632 const struct dwc3_event_depevt *event, int status) 1633{ 1634 struct dwc3_request *req; 1635 struct dwc3_trb *trb; 1636 unsigned int count; 1637 unsigned int s_pkt = 0; 1638 unsigned int trb_status; 1639 1640 do { 1641 req = next_request(&dep->req_queued); 1642 if (!req) { 1643 WARN_ON_ONCE(1); 1644 return 1; 1645 } 1646 1647 trb = req->trb; 1648 1649 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 1650 /* 1651 * We continue despite the error. There is not much we 1652 * can do. If we don't clean it up we loop forever. If 1653 * we skip the TRB then it gets overwritten after a 1654 * while since we use them in a ring buffer. A BUG() 1655 * would help. Lets hope that if this occurs, someone 1656 * fixes the root cause instead of looking away :) 1657 */ 1658 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1659 dep->name, req->trb); 1660 count = trb->size & DWC3_TRB_SIZE_MASK; 1661 1662 if (dep->direction) { 1663 if (count) { 1664 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); 1665 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { 1666 dev_dbg(dwc->dev, "incomplete IN transfer %s\n", 1667 dep->name); 1668 dep->current_uf = event->parameters & 1669 ~(dep->interval - 1); 1670 dep->flags |= DWC3_EP_MISSED_ISOC; 1671 } else { 1672 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1673 dep->name); 1674 status = -ECONNRESET; 1675 } 1676 } 1677 } else { 1678 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1679 s_pkt = 1; 1680 } 1681 1682 /* 1683 * We assume here we will always receive the entire data block 1684 * which we should receive. Meaning, if we program RX to 1685 * receive 4K but we receive only 2K, we assume that's all we 1686 * should receive and we simply bounce the request back to the 1687 * gadget driver for further processing. 1688 */ 1689 req->request.actual += req->request.length - count; 1690 dwc3_gadget_giveback(dep, req, status); 1691 if (s_pkt) 1692 break; 1693 if ((event->status & DEPEVT_STATUS_LST) && 1694 (trb->ctrl & (DWC3_TRB_CTRL_LST | 1695 DWC3_TRB_CTRL_HWO))) 1696 break; 1697 if ((event->status & DEPEVT_STATUS_IOC) && 1698 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1699 break; 1700 } while (1); 1701 1702 if ((event->status & DEPEVT_STATUS_IOC) && 1703 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1704 return 0; 1705 return 1; 1706} 1707 1708static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1709 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1710 int start_new) 1711{ 1712 unsigned status = 0; 1713 int clean_busy; 1714 1715 if (event->status & DEPEVT_STATUS_BUSERR) 1716 status = -ECONNRESET; 1717 1718 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1719 if (clean_busy) 1720 dep->flags &= ~DWC3_EP_BUSY; 1721 1722 /* 1723 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1724 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1725 */ 1726 if (dwc->revision < DWC3_REVISION_183A) { 1727 u32 reg; 1728 int i; 1729 1730 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1731 dep = dwc->eps[i]; 1732 1733 if (!(dep->flags & DWC3_EP_ENABLED)) 1734 continue; 1735 1736 if (!list_empty(&dep->req_queued)) 1737 return; 1738 } 1739 1740 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1741 reg |= dwc->u1u2; 1742 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1743 1744 dwc->u1u2 = 0; 1745 } 1746} 1747 1748static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1749 const struct dwc3_event_depevt *event) 1750{ 1751 struct dwc3_ep *dep; 1752 u8 epnum = event->endpoint_number; 1753 1754 dep = dwc->eps[epnum]; 1755 1756 if (!(dep->flags & DWC3_EP_ENABLED)) 1757 return; 1758 1759 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1760 dwc3_ep_event_string(event->endpoint_event)); 1761 1762 if (epnum == 0 || epnum == 1) { 1763 dwc3_ep0_interrupt(dwc, event); 1764 return; 1765 } 1766 1767 switch (event->endpoint_event) { 1768 case DWC3_DEPEVT_XFERCOMPLETE: 1769 dep->resource_index = 0; 1770 1771 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1772 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1773 dep->name); 1774 return; 1775 } 1776 1777 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1778 break; 1779 case DWC3_DEPEVT_XFERINPROGRESS: 1780 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1781 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1782 dep->name); 1783 return; 1784 } 1785 1786 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1787 break; 1788 case DWC3_DEPEVT_XFERNOTREADY: 1789 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1790 dwc3_gadget_start_isoc(dwc, dep, event); 1791 } else { 1792 int ret; 1793 1794 dev_vdbg(dwc->dev, "%s: reason %s\n", 1795 dep->name, event->status & 1796 DEPEVT_STATUS_TRANSFER_ACTIVE 1797 ? "Transfer Active" 1798 : "Transfer Not Active"); 1799 1800 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1801 if (!ret || ret == -EBUSY) 1802 return; 1803 1804 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1805 dep->name); 1806 } 1807 1808 break; 1809 case DWC3_DEPEVT_STREAMEVT: 1810 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { 1811 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1812 dep->name); 1813 return; 1814 } 1815 1816 switch (event->status) { 1817 case DEPEVT_STREAMEVT_FOUND: 1818 dev_vdbg(dwc->dev, "Stream %d found and started\n", 1819 event->parameters); 1820 1821 break; 1822 case DEPEVT_STREAMEVT_NOTFOUND: 1823 /* FALLTHROUGH */ 1824 default: 1825 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 1826 } 1827 break; 1828 case DWC3_DEPEVT_RXTXFIFOEVT: 1829 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 1830 break; 1831 case DWC3_DEPEVT_EPCMDCMPLT: 1832 dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); 1833 break; 1834 } 1835} 1836 1837static void dwc3_disconnect_gadget(struct dwc3 *dwc) 1838{ 1839 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 1840 spin_unlock(&dwc->lock); 1841 dwc->gadget_driver->disconnect(&dwc->gadget); 1842 spin_lock(&dwc->lock); 1843 } 1844} 1845 1846static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) 1847{ 1848 struct dwc3_ep *dep; 1849 struct dwc3_gadget_ep_cmd_params params; 1850 u32 cmd; 1851 int ret; 1852 1853 dep = dwc->eps[epnum]; 1854 1855 if (!dep->resource_index) 1856 return; 1857 1858 /* 1859 * NOTICE: We are violating what the Databook says about the 1860 * EndTransfer command. Ideally we would _always_ wait for the 1861 * EndTransfer Command Completion IRQ, but that's causing too 1862 * much trouble synchronizing between us and gadget driver. 1863 * 1864 * We have discussed this with the IP Provider and it was 1865 * suggested to giveback all requests here, but give HW some 1866 * extra time to synchronize with the interconnect. We're using 1867 * an arbitraty 100us delay for that. 1868 * 1869 * Note also that a similar handling was tested by Synopsys 1870 * (thanks a lot Paul) and nothing bad has come out of it. 1871 * In short, what we're doing is: 1872 * 1873 * - Issue EndTransfer WITH CMDIOC bit set 1874 * - Wait 100us 1875 */ 1876 1877 cmd = DWC3_DEPCMD_ENDTRANSFER; 1878 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; 1879 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1880 memset(¶ms, 0, sizeof(params)); 1881 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1882 WARN_ON_ONCE(ret); 1883 dep->resource_index = 0; 1884 1885 udelay(100); 1886} 1887 1888static void dwc3_stop_active_transfers(struct dwc3 *dwc) 1889{ 1890 u32 epnum; 1891 1892 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1893 struct dwc3_ep *dep; 1894 1895 dep = dwc->eps[epnum]; 1896 if (!(dep->flags & DWC3_EP_ENABLED)) 1897 continue; 1898 1899 dwc3_remove_requests(dwc, dep); 1900 } 1901} 1902 1903static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 1904{ 1905 u32 epnum; 1906 1907 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1908 struct dwc3_ep *dep; 1909 struct dwc3_gadget_ep_cmd_params params; 1910 int ret; 1911 1912 dep = dwc->eps[epnum]; 1913 1914 if (!(dep->flags & DWC3_EP_STALL)) 1915 continue; 1916 1917 dep->flags &= ~DWC3_EP_STALL; 1918 1919 memset(¶ms, 0, sizeof(params)); 1920 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1921 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1922 WARN_ON_ONCE(ret); 1923 } 1924} 1925 1926static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 1927{ 1928 int reg; 1929 1930 dev_vdbg(dwc->dev, "%s\n", __func__); 1931 1932 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1933 reg &= ~DWC3_DCTL_INITU1ENA; 1934 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1935 1936 reg &= ~DWC3_DCTL_INITU2ENA; 1937 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1938 1939 dwc3_disconnect_gadget(dwc); 1940 dwc->start_config_issued = false; 1941 1942 dwc->gadget.speed = USB_SPEED_UNKNOWN; 1943 dwc->setup_packet_pending = false; 1944} 1945 1946static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend) 1947{ 1948 u32 reg; 1949 1950 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1951 1952 if (suspend) 1953 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1954 else 1955 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 1956 1957 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1958} 1959 1960static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend) 1961{ 1962 u32 reg; 1963 1964 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1965 1966 if (suspend) 1967 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1968 else 1969 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1970 1971 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1972} 1973 1974static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 1975{ 1976 u32 reg; 1977 1978 dev_vdbg(dwc->dev, "%s\n", __func__); 1979 1980 /* 1981 * WORKAROUND: DWC3 revisions <1.88a have an issue which 1982 * would cause a missing Disconnect Event if there's a 1983 * pending Setup Packet in the FIFO. 1984 * 1985 * There's no suggested workaround on the official Bug 1986 * report, which states that "unless the driver/application 1987 * is doing any special handling of a disconnect event, 1988 * there is no functional issue". 1989 * 1990 * Unfortunately, it turns out that we _do_ some special 1991 * handling of a disconnect event, namely complete all 1992 * pending transfers, notify gadget driver of the 1993 * disconnection, and so on. 1994 * 1995 * Our suggested workaround is to follow the Disconnect 1996 * Event steps here, instead, based on a setup_packet_pending 1997 * flag. Such flag gets set whenever we have a XferNotReady 1998 * event on EP0 and gets cleared on XferComplete for the 1999 * same endpoint. 2000 * 2001 * Refers to: 2002 * 2003 * STAR#9000466709: RTL: Device : Disconnect event not 2004 * generated if setup packet pending in FIFO 2005 */ 2006 if (dwc->revision < DWC3_REVISION_188A) { 2007 if (dwc->setup_packet_pending) 2008 dwc3_gadget_disconnect_interrupt(dwc); 2009 } 2010 2011 /* after reset -> Default State */ 2012 dwc->dev_state = DWC3_DEFAULT_STATE; 2013 2014 /* Recent versions support automatic phy suspend and don't need this */ 2015 if (dwc->revision < DWC3_REVISION_194A) { 2016 /* Resume PHYs */ 2017 dwc3_gadget_usb2_phy_suspend(dwc, false); 2018 dwc3_gadget_usb3_phy_suspend(dwc, false); 2019 } 2020 2021 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 2022 dwc3_disconnect_gadget(dwc); 2023 2024 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2025 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2026 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2027 dwc->test_mode = false; 2028 2029 dwc3_stop_active_transfers(dwc); 2030 dwc3_clear_stall_all_ep(dwc); 2031 dwc->start_config_issued = false; 2032 2033 /* Reset device address to zero */ 2034 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2035 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2036 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2037} 2038 2039static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 2040{ 2041 u32 reg; 2042 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 2043 2044 /* 2045 * We change the clock only at SS but I dunno why I would want to do 2046 * this. Maybe it becomes part of the power saving plan. 2047 */ 2048 2049 if (speed != DWC3_DSTS_SUPERSPEED) 2050 return; 2051 2052 /* 2053 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2054 * each time on Connect Done. 2055 */ 2056 if (!usb30_clock) 2057 return; 2058 2059 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 2060 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 2061 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 2062} 2063 2064static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed) 2065{ 2066 switch (speed) { 2067 case USB_SPEED_SUPER: 2068 dwc3_gadget_usb2_phy_suspend(dwc, true); 2069 break; 2070 case USB_SPEED_HIGH: 2071 case USB_SPEED_FULL: 2072 case USB_SPEED_LOW: 2073 dwc3_gadget_usb3_phy_suspend(dwc, true); 2074 break; 2075 } 2076} 2077 2078static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2079{ 2080 struct dwc3_gadget_ep_cmd_params params; 2081 struct dwc3_ep *dep; 2082 int ret; 2083 u32 reg; 2084 u8 speed; 2085 2086 dev_vdbg(dwc->dev, "%s\n", __func__); 2087 2088 memset(¶ms, 0x00, sizeof(params)); 2089 2090 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2091 speed = reg & DWC3_DSTS_CONNECTSPD; 2092 dwc->speed = speed; 2093 2094 dwc3_update_ram_clk_sel(dwc, speed); 2095 2096 switch (speed) { 2097 case DWC3_DCFG_SUPERSPEED: 2098 /* 2099 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2100 * would cause a missing USB3 Reset event. 2101 * 2102 * In such situations, we should force a USB3 Reset 2103 * event by calling our dwc3_gadget_reset_interrupt() 2104 * routine. 2105 * 2106 * Refers to: 2107 * 2108 * STAR#9000483510: RTL: SS : USB3 reset event may 2109 * not be generated always when the link enters poll 2110 */ 2111 if (dwc->revision < DWC3_REVISION_190A) 2112 dwc3_gadget_reset_interrupt(dwc); 2113 2114 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2115 dwc->gadget.ep0->maxpacket = 512; 2116 dwc->gadget.speed = USB_SPEED_SUPER; 2117 break; 2118 case DWC3_DCFG_HIGHSPEED: 2119 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2120 dwc->gadget.ep0->maxpacket = 64; 2121 dwc->gadget.speed = USB_SPEED_HIGH; 2122 break; 2123 case DWC3_DCFG_FULLSPEED2: 2124 case DWC3_DCFG_FULLSPEED1: 2125 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2126 dwc->gadget.ep0->maxpacket = 64; 2127 dwc->gadget.speed = USB_SPEED_FULL; 2128 break; 2129 case DWC3_DCFG_LOWSPEED: 2130 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2131 dwc->gadget.ep0->maxpacket = 8; 2132 dwc->gadget.speed = USB_SPEED_LOW; 2133 break; 2134 } 2135 2136 /* Recent versions support automatic phy suspend and don't need this */ 2137 if (dwc->revision < DWC3_REVISION_194A) { 2138 /* Suspend unneeded PHY */ 2139 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed); 2140 } 2141 2142 dep = dwc->eps[0]; 2143 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true); 2144 if (ret) { 2145 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2146 return; 2147 } 2148 2149 dep = dwc->eps[1]; 2150 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true); 2151 if (ret) { 2152 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2153 return; 2154 } 2155 2156 /* 2157 * Configure PHY via GUSB3PIPECTLn if required. 2158 * 2159 * Update GTXFIFOSIZn 2160 * 2161 * In both cases reset values should be sufficient. 2162 */ 2163} 2164 2165static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2166{ 2167 dev_vdbg(dwc->dev, "%s\n", __func__); 2168 2169 /* 2170 * TODO take core out of low power mode when that's 2171 * implemented. 2172 */ 2173 2174 dwc->gadget_driver->resume(&dwc->gadget); 2175} 2176 2177static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2178 unsigned int evtinfo) 2179{ 2180 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2181 2182 /* 2183 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2184 * on the link partner, the USB session might do multiple entry/exit 2185 * of low power states before a transfer takes place. 2186 * 2187 * Due to this problem, we might experience lower throughput. The 2188 * suggested workaround is to disable DCTL[12:9] bits if we're 2189 * transitioning from U1/U2 to U0 and enable those bits again 2190 * after a transfer completes and there are no pending transfers 2191 * on any of the enabled endpoints. 2192 * 2193 * This is the first half of that workaround. 2194 * 2195 * Refers to: 2196 * 2197 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2198 * core send LGO_Ux entering U0 2199 */ 2200 if (dwc->revision < DWC3_REVISION_183A) { 2201 if (next == DWC3_LINK_STATE_U0) { 2202 u32 u1u2; 2203 u32 reg; 2204 2205 switch (dwc->link_state) { 2206 case DWC3_LINK_STATE_U1: 2207 case DWC3_LINK_STATE_U2: 2208 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2209 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2210 | DWC3_DCTL_ACCEPTU2ENA 2211 | DWC3_DCTL_INITU1ENA 2212 | DWC3_DCTL_ACCEPTU1ENA); 2213 2214 if (!dwc->u1u2) 2215 dwc->u1u2 = reg & u1u2; 2216 2217 reg &= ~u1u2; 2218 2219 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2220 break; 2221 default: 2222 /* do nothing */ 2223 break; 2224 } 2225 } 2226 } 2227 2228 dwc->link_state = next; 2229 2230 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 2231} 2232 2233static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2234 const struct dwc3_event_devt *event) 2235{ 2236 switch (event->type) { 2237 case DWC3_DEVICE_EVENT_DISCONNECT: 2238 dwc3_gadget_disconnect_interrupt(dwc); 2239 break; 2240 case DWC3_DEVICE_EVENT_RESET: 2241 dwc3_gadget_reset_interrupt(dwc); 2242 break; 2243 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2244 dwc3_gadget_conndone_interrupt(dwc); 2245 break; 2246 case DWC3_DEVICE_EVENT_WAKEUP: 2247 dwc3_gadget_wakeup_interrupt(dwc); 2248 break; 2249 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2250 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2251 break; 2252 case DWC3_DEVICE_EVENT_EOPF: 2253 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2254 break; 2255 case DWC3_DEVICE_EVENT_SOF: 2256 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2257 break; 2258 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2259 dev_vdbg(dwc->dev, "Erratic Error\n"); 2260 break; 2261 case DWC3_DEVICE_EVENT_CMD_CMPL: 2262 dev_vdbg(dwc->dev, "Command Complete\n"); 2263 break; 2264 case DWC3_DEVICE_EVENT_OVERFLOW: 2265 dev_vdbg(dwc->dev, "Overflow\n"); 2266 break; 2267 default: 2268 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2269 } 2270} 2271 2272static void dwc3_process_event_entry(struct dwc3 *dwc, 2273 const union dwc3_event *event) 2274{ 2275 /* Endpoint IRQ, handle it and return early */ 2276 if (event->type.is_devspec == 0) { 2277 /* depevt */ 2278 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2279 } 2280 2281 switch (event->type.type) { 2282 case DWC3_EVENT_TYPE_DEV: 2283 dwc3_gadget_interrupt(dwc, &event->devt); 2284 break; 2285 /* REVISIT what to do with Carkit and I2C events ? */ 2286 default: 2287 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2288 } 2289} 2290 2291static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2292{ 2293 struct dwc3_event_buffer *evt; 2294 int left; 2295 u32 count; 2296 2297 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2298 count &= DWC3_GEVNTCOUNT_MASK; 2299 if (!count) 2300 return IRQ_NONE; 2301 2302 evt = dwc->ev_buffs[buf]; 2303 left = count; 2304 2305 while (left > 0) { 2306 union dwc3_event event; 2307 2308 event.raw = *(u32 *) (evt->buf + evt->lpos); 2309 2310 dwc3_process_event_entry(dwc, &event); 2311 /* 2312 * XXX we wrap around correctly to the next entry as almost all 2313 * entries are 4 bytes in size. There is one entry which has 12 2314 * bytes which is a regular entry followed by 8 bytes data. ATM 2315 * I don't know how things are organized if were get next to the 2316 * a boundary so I worry about that once we try to handle that. 2317 */ 2318 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2319 left -= 4; 2320 2321 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2322 } 2323 2324 return IRQ_HANDLED; 2325} 2326 2327static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2328{ 2329 struct dwc3 *dwc = _dwc; 2330 int i; 2331 irqreturn_t ret = IRQ_NONE; 2332 2333 spin_lock(&dwc->lock); 2334 2335 for (i = 0; i < dwc->num_event_buffers; i++) { 2336 irqreturn_t status; 2337 2338 status = dwc3_process_event_buf(dwc, i); 2339 if (status == IRQ_HANDLED) 2340 ret = status; 2341 } 2342 2343 spin_unlock(&dwc->lock); 2344 2345 return ret; 2346} 2347 2348/** 2349 * dwc3_gadget_init - Initializes gadget related registers 2350 * @dwc: pointer to our controller context structure 2351 * 2352 * Returns 0 on success otherwise negative errno. 2353 */ 2354int __devinit dwc3_gadget_init(struct dwc3 *dwc) 2355{ 2356 u32 reg; 2357 int ret; 2358 int irq; 2359 2360 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2361 &dwc->ctrl_req_addr, GFP_KERNEL); 2362 if (!dwc->ctrl_req) { 2363 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2364 ret = -ENOMEM; 2365 goto err0; 2366 } 2367 2368 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2369 &dwc->ep0_trb_addr, GFP_KERNEL); 2370 if (!dwc->ep0_trb) { 2371 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2372 ret = -ENOMEM; 2373 goto err1; 2374 } 2375 2376 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); 2377 if (!dwc->setup_buf) { 2378 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2379 ret = -ENOMEM; 2380 goto err2; 2381 } 2382 2383 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2384 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, 2385 GFP_KERNEL); 2386 if (!dwc->ep0_bounce) { 2387 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2388 ret = -ENOMEM; 2389 goto err3; 2390 } 2391 2392 dev_set_name(&dwc->gadget.dev, "gadget"); 2393 2394 dwc->gadget.ops = &dwc3_gadget_ops; 2395 dwc->gadget.max_speed = USB_SPEED_SUPER; 2396 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2397 dwc->gadget.dev.parent = dwc->dev; 2398 dwc->gadget.sg_supported = true; 2399 2400 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); 2401 2402 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; 2403 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; 2404 dwc->gadget.dev.release = dwc3_gadget_release; 2405 dwc->gadget.name = "dwc3-gadget"; 2406 2407 /* 2408 * REVISIT: Here we should clear all pending IRQs to be 2409 * sure we're starting from a well known location. 2410 */ 2411 2412 ret = dwc3_gadget_init_endpoints(dwc); 2413 if (ret) 2414 goto err4; 2415 2416 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2417 2418 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, 2419 "dwc3", dwc); 2420 if (ret) { 2421 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 2422 irq, ret); 2423 goto err5; 2424 } 2425 2426 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2427 reg |= DWC3_DCFG_LPM_CAP; 2428 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2429 2430 /* Enable all but Start and End of Frame IRQs */ 2431 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 2432 DWC3_DEVTEN_EVNTOVERFLOWEN | 2433 DWC3_DEVTEN_CMDCMPLTEN | 2434 DWC3_DEVTEN_ERRTICERREN | 2435 DWC3_DEVTEN_WKUPEVTEN | 2436 DWC3_DEVTEN_ULSTCNGEN | 2437 DWC3_DEVTEN_CONNECTDONEEN | 2438 DWC3_DEVTEN_USBRSTEN | 2439 DWC3_DEVTEN_DISCONNEVTEN); 2440 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 2441 2442 /* Enable USB2 LPM and automatic phy suspend only on recent versions */ 2443 if (dwc->revision >= DWC3_REVISION_194A) { 2444 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2445 reg |= DWC3_DCFG_LPM_CAP; 2446 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2447 2448 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2449 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2450 2451 /* TODO: This should be configurable */ 2452 reg |= DWC3_DCTL_HIRD_THRES(28); 2453 2454 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2455 2456 dwc3_gadget_usb2_phy_suspend(dwc, false); 2457 dwc3_gadget_usb3_phy_suspend(dwc, false); 2458 } 2459 2460 ret = device_register(&dwc->gadget.dev); 2461 if (ret) { 2462 dev_err(dwc->dev, "failed to register gadget device\n"); 2463 put_device(&dwc->gadget.dev); 2464 goto err6; 2465 } 2466 2467 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2468 if (ret) { 2469 dev_err(dwc->dev, "failed to register udc\n"); 2470 goto err7; 2471 } 2472 2473 return 0; 2474 2475err7: 2476 device_unregister(&dwc->gadget.dev); 2477 2478err6: 2479 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2480 free_irq(irq, dwc); 2481 2482err5: 2483 dwc3_gadget_free_endpoints(dwc); 2484 2485err4: 2486 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2487 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2488 2489err3: 2490 kfree(dwc->setup_buf); 2491 2492err2: 2493 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2494 dwc->ep0_trb, dwc->ep0_trb_addr); 2495 2496err1: 2497 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2498 dwc->ctrl_req, dwc->ctrl_req_addr); 2499 2500err0: 2501 return ret; 2502} 2503 2504void dwc3_gadget_exit(struct dwc3 *dwc) 2505{ 2506 int irq; 2507 2508 usb_del_gadget_udc(&dwc->gadget); 2509 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2510 2511 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2512 free_irq(irq, dwc); 2513 2514 dwc3_gadget_free_endpoints(dwc); 2515 2516 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2517 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2518 2519 kfree(dwc->setup_buf); 2520 2521 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2522 dwc->ep0_trb, dwc->ep0_trb_addr); 2523 2524 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2525 dwc->ctrl_req, dwc->ctrl_req_addr); 2526 2527 device_unregister(&dwc->gadget.dev); 2528} 2529