gadget.c revision c90bfaece97c18d1ad66b9d4c717b1cb55a647ad
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <linux/kernel.h> 40#include <linux/delay.h> 41#include <linux/slab.h> 42#include <linux/spinlock.h> 43#include <linux/platform_device.h> 44#include <linux/pm_runtime.h> 45#include <linux/interrupt.h> 46#include <linux/io.h> 47#include <linux/list.h> 48#include <linux/dma-mapping.h> 49 50#include <linux/usb/ch9.h> 51#include <linux/usb/gadget.h> 52 53#include "core.h" 54#include "gadget.h" 55#include "io.h" 56 57#define DMA_ADDR_INVALID (~(dma_addr_t)0) 58 59void dwc3_map_buffer_to_dma(struct dwc3_request *req) 60{ 61 struct dwc3 *dwc = req->dep->dwc; 62 63 if (req->request.length == 0) { 64 /* req->request.dma = dwc->setup_buf_addr; */ 65 return; 66 } 67 68 if (req->request.dma == DMA_ADDR_INVALID) { 69 req->request.dma = dma_map_single(dwc->dev, req->request.buf, 70 req->request.length, req->direction 71 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 72 req->mapped = true; 73 } 74} 75 76void dwc3_unmap_buffer_from_dma(struct dwc3_request *req) 77{ 78 struct dwc3 *dwc = req->dep->dwc; 79 80 if (req->request.length == 0) { 81 req->request.dma = DMA_ADDR_INVALID; 82 return; 83 } 84 85 if (req->mapped) { 86 dma_unmap_single(dwc->dev, req->request.dma, 87 req->request.length, req->direction 88 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 89 req->mapped = 0; 90 req->request.dma = DMA_ADDR_INVALID; 91 } 92} 93 94void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 95 int status) 96{ 97 struct dwc3 *dwc = dep->dwc; 98 99 if (req->queued) { 100 dep->busy_slot++; 101 /* 102 * Skip LINK TRB. We can't use req->trb and check for 103 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just 104 * completed (not the LINK TRB). 105 */ 106 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 107 usb_endpoint_xfer_isoc(dep->desc)) 108 dep->busy_slot++; 109 } 110 list_del(&req->list); 111 112 if (req->request.status == -EINPROGRESS) 113 req->request.status = status; 114 115 dwc3_unmap_buffer_from_dma(req); 116 117 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 118 req, dep->name, req->request.actual, 119 req->request.length, status); 120 121 spin_unlock(&dwc->lock); 122 req->request.complete(&req->dep->endpoint, &req->request); 123 spin_lock(&dwc->lock); 124} 125 126static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 127{ 128 switch (cmd) { 129 case DWC3_DEPCMD_DEPSTARTCFG: 130 return "Start New Configuration"; 131 case DWC3_DEPCMD_ENDTRANSFER: 132 return "End Transfer"; 133 case DWC3_DEPCMD_UPDATETRANSFER: 134 return "Update Transfer"; 135 case DWC3_DEPCMD_STARTTRANSFER: 136 return "Start Transfer"; 137 case DWC3_DEPCMD_CLEARSTALL: 138 return "Clear Stall"; 139 case DWC3_DEPCMD_SETSTALL: 140 return "Set Stall"; 141 case DWC3_DEPCMD_GETSEQNUMBER: 142 return "Get Data Sequence Number"; 143 case DWC3_DEPCMD_SETTRANSFRESOURCE: 144 return "Set Endpoint Transfer Resource"; 145 case DWC3_DEPCMD_SETEPCONFIG: 146 return "Set Endpoint Configuration"; 147 default: 148 return "UNKNOWN command"; 149 } 150} 151 152int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 153 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 154{ 155 struct dwc3_ep *dep = dwc->eps[ep]; 156 u32 timeout = 500; 157 u32 reg; 158 159 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 160 dep->name, 161 dwc3_gadget_ep_cmd_string(cmd), params->param0, 162 params->param1, params->param2); 163 164 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 165 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 166 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 167 168 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 169 do { 170 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 171 if (!(reg & DWC3_DEPCMD_CMDACT)) { 172 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 173 DWC3_DEPCMD_STATUS(reg)); 174 return 0; 175 } 176 177 /* 178 * We can't sleep here, because it is also called from 179 * interrupt context. 180 */ 181 timeout--; 182 if (!timeout) 183 return -ETIMEDOUT; 184 185 udelay(1); 186 } while (1); 187} 188 189static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 190 struct dwc3_trb_hw *trb) 191{ 192 u32 offset = (char *) trb - (char *) dep->trb_pool; 193 194 return dep->trb_pool_dma + offset; 195} 196 197static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 198{ 199 struct dwc3 *dwc = dep->dwc; 200 201 if (dep->trb_pool) 202 return 0; 203 204 if (dep->number == 0 || dep->number == 1) 205 return 0; 206 207 dep->trb_pool = dma_alloc_coherent(dwc->dev, 208 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 209 &dep->trb_pool_dma, GFP_KERNEL); 210 if (!dep->trb_pool) { 211 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 212 dep->name); 213 return -ENOMEM; 214 } 215 216 return 0; 217} 218 219static void dwc3_free_trb_pool(struct dwc3_ep *dep) 220{ 221 struct dwc3 *dwc = dep->dwc; 222 223 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 224 dep->trb_pool, dep->trb_pool_dma); 225 226 dep->trb_pool = NULL; 227 dep->trb_pool_dma = 0; 228} 229 230static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 231{ 232 struct dwc3_gadget_ep_cmd_params params; 233 u32 cmd; 234 235 memset(¶ms, 0x00, sizeof(params)); 236 237 if (dep->number != 1) { 238 cmd = DWC3_DEPCMD_DEPSTARTCFG; 239 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 240 if (dep->number > 1) { 241 if (dwc->start_config_issued) 242 return 0; 243 dwc->start_config_issued = true; 244 cmd |= DWC3_DEPCMD_PARAM(2); 245 } 246 247 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 248 } 249 250 return 0; 251} 252 253static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 254 const struct usb_endpoint_descriptor *desc, 255 const struct usb_ss_ep_comp_descriptor *comp_desc) 256{ 257 struct dwc3_gadget_ep_cmd_params params; 258 259 memset(¶ms, 0x00, sizeof(params)); 260 261 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 262 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) 263 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst); 264 265 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 266 | DWC3_DEPCFG_XFER_NOT_READY_EN; 267 268 if (comp_desc && USB_SS_MAX_STREAMS(comp_desc->bmAttributes) 269 && usb_endpoint_xfer_bulk(desc)) { 270 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 271 | DWC3_DEPCFG_STREAM_EVENT_EN; 272 dep->stream_capable = true; 273 } 274 275 if (usb_endpoint_xfer_isoc(desc)) 276 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 277 278 /* 279 * We are doing 1:1 mapping for endpoints, meaning 280 * Physical Endpoints 2 maps to Logical Endpoint 2 and 281 * so on. We consider the direction bit as part of the physical 282 * endpoint number. So USB endpoint 0x81 is 0x03. 283 */ 284 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 285 286 /* 287 * We must use the lower 16 TX FIFOs even though 288 * HW might have more 289 */ 290 if (dep->direction) 291 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 292 293 if (desc->bInterval) { 294 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 295 dep->interval = 1 << (desc->bInterval - 1); 296 } 297 298 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 299 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 300} 301 302static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 303{ 304 struct dwc3_gadget_ep_cmd_params params; 305 306 memset(¶ms, 0x00, sizeof(params)); 307 308 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 309 310 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 311 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 312} 313 314/** 315 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 316 * @dep: endpoint to be initialized 317 * @desc: USB Endpoint Descriptor 318 * 319 * Caller should take care of locking 320 */ 321static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 322 const struct usb_endpoint_descriptor *desc, 323 const struct usb_ss_ep_comp_descriptor *comp_desc) 324{ 325 struct dwc3 *dwc = dep->dwc; 326 u32 reg; 327 int ret = -ENOMEM; 328 329 if (!(dep->flags & DWC3_EP_ENABLED)) { 330 ret = dwc3_gadget_start_config(dwc, dep); 331 if (ret) 332 return ret; 333 } 334 335 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc); 336 if (ret) 337 return ret; 338 339 if (!(dep->flags & DWC3_EP_ENABLED)) { 340 struct dwc3_trb_hw *trb_st_hw; 341 struct dwc3_trb_hw *trb_link_hw; 342 struct dwc3_trb trb_link; 343 344 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 345 if (ret) 346 return ret; 347 348 dep->desc = desc; 349 dep->comp_desc = comp_desc; 350 dep->type = usb_endpoint_type(desc); 351 dep->flags |= DWC3_EP_ENABLED; 352 353 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 354 reg |= DWC3_DALEPENA_EP(dep->number); 355 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 356 357 if (!usb_endpoint_xfer_isoc(desc)) 358 return 0; 359 360 memset(&trb_link, 0, sizeof(trb_link)); 361 362 /* Link TRB for ISOC. The HWO but is never reset */ 363 trb_st_hw = &dep->trb_pool[0]; 364 365 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw); 366 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB; 367 trb_link.hwo = true; 368 369 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1]; 370 dwc3_trb_to_hw(&trb_link, trb_link_hw); 371 } 372 373 return 0; 374} 375 376static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); 377static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 378{ 379 struct dwc3_request *req; 380 381 if (!list_empty(&dep->req_queued)) 382 dwc3_stop_active_transfer(dwc, dep->number); 383 384 while (!list_empty(&dep->request_list)) { 385 req = next_request(&dep->request_list); 386 387 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 388 } 389} 390 391/** 392 * __dwc3_gadget_ep_disable - Disables a HW endpoint 393 * @dep: the endpoint to disable 394 * 395 * This function also removes requests which are currently processed ny the 396 * hardware and those which are not yet scheduled. 397 * Caller should take care of locking. 398 */ 399static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 400{ 401 struct dwc3 *dwc = dep->dwc; 402 u32 reg; 403 404 dwc3_remove_requests(dwc, dep); 405 406 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 407 reg &= ~DWC3_DALEPENA_EP(dep->number); 408 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 409 410 dep->stream_capable = false; 411 dep->desc = NULL; 412 dep->comp_desc = NULL; 413 dep->type = 0; 414 dep->flags = 0; 415 416 return 0; 417} 418 419/* -------------------------------------------------------------------------- */ 420 421static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 422 const struct usb_endpoint_descriptor *desc) 423{ 424 return -EINVAL; 425} 426 427static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 428{ 429 return -EINVAL; 430} 431 432/* -------------------------------------------------------------------------- */ 433 434static int dwc3_gadget_ep_enable(struct usb_ep *ep, 435 const struct usb_endpoint_descriptor *desc) 436{ 437 struct dwc3_ep *dep; 438 struct dwc3 *dwc; 439 unsigned long flags; 440 int ret; 441 442 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 443 pr_debug("dwc3: invalid parameters\n"); 444 return -EINVAL; 445 } 446 447 if (!desc->wMaxPacketSize) { 448 pr_debug("dwc3: missing wMaxPacketSize\n"); 449 return -EINVAL; 450 } 451 452 dep = to_dwc3_ep(ep); 453 dwc = dep->dwc; 454 455 switch (usb_endpoint_type(desc)) { 456 case USB_ENDPOINT_XFER_CONTROL: 457 strncat(dep->name, "-control", sizeof(dep->name)); 458 break; 459 case USB_ENDPOINT_XFER_ISOC: 460 strncat(dep->name, "-isoc", sizeof(dep->name)); 461 break; 462 case USB_ENDPOINT_XFER_BULK: 463 strncat(dep->name, "-bulk", sizeof(dep->name)); 464 break; 465 case USB_ENDPOINT_XFER_INT: 466 strncat(dep->name, "-int", sizeof(dep->name)); 467 break; 468 default: 469 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 470 } 471 472 if (dep->flags & DWC3_EP_ENABLED) { 473 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 474 dep->name); 475 return 0; 476 } 477 478 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 479 480 spin_lock_irqsave(&dwc->lock, flags); 481 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc); 482 spin_unlock_irqrestore(&dwc->lock, flags); 483 484 return ret; 485} 486 487static int dwc3_gadget_ep_disable(struct usb_ep *ep) 488{ 489 struct dwc3_ep *dep; 490 struct dwc3 *dwc; 491 unsigned long flags; 492 int ret; 493 494 if (!ep) { 495 pr_debug("dwc3: invalid parameters\n"); 496 return -EINVAL; 497 } 498 499 dep = to_dwc3_ep(ep); 500 dwc = dep->dwc; 501 502 if (!(dep->flags & DWC3_EP_ENABLED)) { 503 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 504 dep->name); 505 return 0; 506 } 507 508 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 509 dep->number >> 1, 510 (dep->number & 1) ? "in" : "out"); 511 512 spin_lock_irqsave(&dwc->lock, flags); 513 ret = __dwc3_gadget_ep_disable(dep); 514 spin_unlock_irqrestore(&dwc->lock, flags); 515 516 return ret; 517} 518 519static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 520 gfp_t gfp_flags) 521{ 522 struct dwc3_request *req; 523 struct dwc3_ep *dep = to_dwc3_ep(ep); 524 struct dwc3 *dwc = dep->dwc; 525 526 req = kzalloc(sizeof(*req), gfp_flags); 527 if (!req) { 528 dev_err(dwc->dev, "not enough memory\n"); 529 return NULL; 530 } 531 532 req->epnum = dep->number; 533 req->dep = dep; 534 req->request.dma = DMA_ADDR_INVALID; 535 536 return &req->request; 537} 538 539static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 540 struct usb_request *request) 541{ 542 struct dwc3_request *req = to_dwc3_request(request); 543 544 kfree(req); 545} 546 547/* 548 * dwc3_prepare_trbs - setup TRBs from requests 549 * @dep: endpoint for which requests are being prepared 550 * @starting: true if the endpoint is idle and no requests are queued. 551 * 552 * The functions goes through the requests list and setups TRBs for the 553 * transfers. The functions returns once there are not more TRBs available or 554 * it run out of requests. 555 */ 556static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep, 557 bool starting) 558{ 559 struct dwc3_request *req, *n, *ret = NULL; 560 struct dwc3_trb_hw *trb_hw; 561 struct dwc3_trb trb; 562 u32 trbs_left; 563 564 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 565 566 /* the first request must not be queued */ 567 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 568 /* 569 * if busy & slot are equal than it is either full or empty. If we are 570 * starting to proceed requests then we are empty. Otherwise we ar 571 * full and don't do anything 572 */ 573 if (!trbs_left) { 574 if (!starting) 575 return NULL; 576 trbs_left = DWC3_TRB_NUM; 577 /* 578 * In case we start from scratch, we queue the ISOC requests 579 * starting from slot 1. This is done because we use ring 580 * buffer and have no LST bit to stop us. Instead, we place 581 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt 582 * after the first request so we start at slot 1 and have 583 * 7 requests proceed before we hit the first IOC. 584 * Other transfer types don't use the ring buffer and are 585 * processed from the first TRB until the last one. Since we 586 * don't wrap around we have to start at the beginning. 587 */ 588 if (usb_endpoint_xfer_isoc(dep->desc)) { 589 dep->busy_slot = 1; 590 dep->free_slot = 1; 591 } else { 592 dep->busy_slot = 0; 593 dep->free_slot = 0; 594 } 595 } 596 597 /* The last TRB is a link TRB, not used for xfer */ 598 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc)) 599 return NULL; 600 601 list_for_each_entry_safe(req, n, &dep->request_list, list) { 602 unsigned int last_one = 0; 603 unsigned int cur_slot; 604 605 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 606 cur_slot = dep->free_slot; 607 dep->free_slot++; 608 609 /* Skip the LINK-TRB on ISOC */ 610 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 611 usb_endpoint_xfer_isoc(dep->desc)) 612 continue; 613 614 dwc3_gadget_move_request_queued(req); 615 memset(&trb, 0, sizeof(trb)); 616 trbs_left--; 617 618 /* Is our TRB pool empty? */ 619 if (!trbs_left) 620 last_one = 1; 621 /* Is this the last request? */ 622 if (list_empty(&dep->request_list)) 623 last_one = 1; 624 625 /* 626 * FIXME we shouldn't need to set LST bit always but we are 627 * facing some weird problem with the Hardware where it doesn't 628 * complete even though it has been previously started. 629 * 630 * While we're debugging the problem, as a workaround to 631 * multiple TRBs handling, use only one TRB at a time. 632 */ 633 last_one = 1; 634 635 req->trb = trb_hw; 636 if (!ret) 637 ret = req; 638 639 trb.bplh = req->request.dma; 640 641 if (usb_endpoint_xfer_isoc(dep->desc)) { 642 trb.isp_imi = true; 643 trb.csp = true; 644 } else { 645 trb.lst = last_one; 646 } 647 648 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable) 649 trb.sid_sofn = req->request.stream_id; 650 651 switch (usb_endpoint_type(dep->desc)) { 652 case USB_ENDPOINT_XFER_CONTROL: 653 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP; 654 break; 655 656 case USB_ENDPOINT_XFER_ISOC: 657 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 658 659 /* IOC every DWC3_TRB_NUM / 4 so we can refill */ 660 if (!(cur_slot % (DWC3_TRB_NUM / 4))) 661 trb.ioc = last_one; 662 break; 663 664 case USB_ENDPOINT_XFER_BULK: 665 case USB_ENDPOINT_XFER_INT: 666 trb.trbctl = DWC3_TRBCTL_NORMAL; 667 break; 668 default: 669 /* 670 * This is only possible with faulty memory because we 671 * checked it already :) 672 */ 673 BUG(); 674 } 675 676 trb.length = req->request.length; 677 trb.hwo = true; 678 679 dwc3_trb_to_hw(&trb, trb_hw); 680 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw); 681 682 if (last_one) 683 break; 684 } 685 686 return ret; 687} 688 689static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 690 int start_new) 691{ 692 struct dwc3_gadget_ep_cmd_params params; 693 struct dwc3_request *req; 694 struct dwc3 *dwc = dep->dwc; 695 int ret; 696 u32 cmd; 697 698 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 699 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 700 return -EBUSY; 701 } 702 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 703 704 /* 705 * If we are getting here after a short-out-packet we don't enqueue any 706 * new requests as we try to set the IOC bit only on the last request. 707 */ 708 if (start_new) { 709 if (list_empty(&dep->req_queued)) 710 dwc3_prepare_trbs(dep, start_new); 711 712 /* req points to the first request which will be sent */ 713 req = next_request(&dep->req_queued); 714 } else { 715 /* 716 * req points to the first request where HWO changed 717 * from 0 to 1 718 */ 719 req = dwc3_prepare_trbs(dep, start_new); 720 } 721 if (!req) { 722 dep->flags |= DWC3_EP_PENDING_REQUEST; 723 return 0; 724 } 725 726 memset(¶ms, 0, sizeof(params)); 727 params.param0 = upper_32_bits(req->trb_dma); 728 params.param1 = lower_32_bits(req->trb_dma); 729 730 if (start_new) 731 cmd = DWC3_DEPCMD_STARTTRANSFER; 732 else 733 cmd = DWC3_DEPCMD_UPDATETRANSFER; 734 735 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 736 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 737 if (ret < 0) { 738 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 739 740 /* 741 * FIXME we need to iterate over the list of requests 742 * here and stop, unmap, free and del each of the linked 743 * requests instead of we do now. 744 */ 745 dwc3_unmap_buffer_from_dma(req); 746 list_del(&req->list); 747 return ret; 748 } 749 750 dep->flags |= DWC3_EP_BUSY; 751 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, 752 dep->number); 753 754 WARN_ON_ONCE(!dep->res_trans_idx); 755 756 return 0; 757} 758 759static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 760{ 761 req->request.actual = 0; 762 req->request.status = -EINPROGRESS; 763 req->direction = dep->direction; 764 req->epnum = dep->number; 765 766 /* 767 * We only add to our list of requests now and 768 * start consuming the list once we get XferNotReady 769 * IRQ. 770 * 771 * That way, we avoid doing anything that we don't need 772 * to do now and defer it until the point we receive a 773 * particular token from the Host side. 774 * 775 * This will also avoid Host cancelling URBs due to too 776 * many NACKs. 777 */ 778 dwc3_map_buffer_to_dma(req); 779 list_add_tail(&req->list, &dep->request_list); 780 781 /* 782 * There is one special case: XferNotReady with 783 * empty list of requests. We need to kick the 784 * transfer here in that situation, otherwise 785 * we will be NAKing forever. 786 * 787 * If we get XferNotReady before gadget driver 788 * has a chance to queue a request, we will ACK 789 * the IRQ but won't be able to receive the data 790 * until the next request is queued. The following 791 * code is handling exactly that. 792 */ 793 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 794 int ret; 795 int start_trans; 796 797 start_trans = 1; 798 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 799 dep->flags & DWC3_EP_BUSY) 800 start_trans = 0; 801 802 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans); 803 if (ret && ret != -EBUSY) { 804 struct dwc3 *dwc = dep->dwc; 805 806 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 807 dep->name); 808 } 809 }; 810 811 return 0; 812} 813 814static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 815 gfp_t gfp_flags) 816{ 817 struct dwc3_request *req = to_dwc3_request(request); 818 struct dwc3_ep *dep = to_dwc3_ep(ep); 819 struct dwc3 *dwc = dep->dwc; 820 821 unsigned long flags; 822 823 int ret; 824 825 if (!dep->desc) { 826 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 827 request, ep->name); 828 return -ESHUTDOWN; 829 } 830 831 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 832 request, ep->name, request->length); 833 834 spin_lock_irqsave(&dwc->lock, flags); 835 ret = __dwc3_gadget_ep_queue(dep, req); 836 spin_unlock_irqrestore(&dwc->lock, flags); 837 838 return ret; 839} 840 841static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 842 struct usb_request *request) 843{ 844 struct dwc3_request *req = to_dwc3_request(request); 845 struct dwc3_request *r = NULL; 846 847 struct dwc3_ep *dep = to_dwc3_ep(ep); 848 struct dwc3 *dwc = dep->dwc; 849 850 unsigned long flags; 851 int ret = 0; 852 853 spin_lock_irqsave(&dwc->lock, flags); 854 855 list_for_each_entry(r, &dep->request_list, list) { 856 if (r == req) 857 break; 858 } 859 860 if (r != req) { 861 list_for_each_entry(r, &dep->req_queued, list) { 862 if (r == req) 863 break; 864 } 865 if (r == req) { 866 /* wait until it is processed */ 867 dwc3_stop_active_transfer(dwc, dep->number); 868 goto out0; 869 } 870 dev_err(dwc->dev, "request %p was not queued to %s\n", 871 request, ep->name); 872 ret = -EINVAL; 873 goto out0; 874 } 875 876 /* giveback the request */ 877 dwc3_gadget_giveback(dep, req, -ECONNRESET); 878 879out0: 880 spin_unlock_irqrestore(&dwc->lock, flags); 881 882 return ret; 883} 884 885int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 886{ 887 struct dwc3_gadget_ep_cmd_params params; 888 struct dwc3 *dwc = dep->dwc; 889 int ret; 890 891 memset(¶ms, 0x00, sizeof(params)); 892 893 if (value) { 894 if (dep->number == 0 || dep->number == 1) { 895 /* 896 * Whenever EP0 is stalled, we will restart 897 * the state machine, thus moving back to 898 * Setup Phase 899 */ 900 dwc->ep0state = EP0_SETUP_PHASE; 901 } 902 903 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 904 DWC3_DEPCMD_SETSTALL, ¶ms); 905 if (ret) 906 dev_err(dwc->dev, "failed to %s STALL on %s\n", 907 value ? "set" : "clear", 908 dep->name); 909 else 910 dep->flags |= DWC3_EP_STALL; 911 } else { 912 if (dep->flags & DWC3_EP_WEDGE) 913 return 0; 914 915 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 916 DWC3_DEPCMD_CLEARSTALL, ¶ms); 917 if (ret) 918 dev_err(dwc->dev, "failed to %s STALL on %s\n", 919 value ? "set" : "clear", 920 dep->name); 921 else 922 dep->flags &= ~DWC3_EP_STALL; 923 } 924 925 return ret; 926} 927 928static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 929{ 930 struct dwc3_ep *dep = to_dwc3_ep(ep); 931 struct dwc3 *dwc = dep->dwc; 932 933 unsigned long flags; 934 935 int ret; 936 937 spin_lock_irqsave(&dwc->lock, flags); 938 939 if (usb_endpoint_xfer_isoc(dep->desc)) { 940 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 941 ret = -EINVAL; 942 goto out; 943 } 944 945 ret = __dwc3_gadget_ep_set_halt(dep, value); 946out: 947 spin_unlock_irqrestore(&dwc->lock, flags); 948 949 return ret; 950} 951 952static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 953{ 954 struct dwc3_ep *dep = to_dwc3_ep(ep); 955 956 dep->flags |= DWC3_EP_WEDGE; 957 958 return dwc3_gadget_ep_set_halt(ep, 1); 959} 960 961/* -------------------------------------------------------------------------- */ 962 963static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 964 .bLength = USB_DT_ENDPOINT_SIZE, 965 .bDescriptorType = USB_DT_ENDPOINT, 966 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 967}; 968 969static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 970 .enable = dwc3_gadget_ep0_enable, 971 .disable = dwc3_gadget_ep0_disable, 972 .alloc_request = dwc3_gadget_ep_alloc_request, 973 .free_request = dwc3_gadget_ep_free_request, 974 .queue = dwc3_gadget_ep0_queue, 975 .dequeue = dwc3_gadget_ep_dequeue, 976 .set_halt = dwc3_gadget_ep_set_halt, 977 .set_wedge = dwc3_gadget_ep_set_wedge, 978}; 979 980static const struct usb_ep_ops dwc3_gadget_ep_ops = { 981 .enable = dwc3_gadget_ep_enable, 982 .disable = dwc3_gadget_ep_disable, 983 .alloc_request = dwc3_gadget_ep_alloc_request, 984 .free_request = dwc3_gadget_ep_free_request, 985 .queue = dwc3_gadget_ep_queue, 986 .dequeue = dwc3_gadget_ep_dequeue, 987 .set_halt = dwc3_gadget_ep_set_halt, 988 .set_wedge = dwc3_gadget_ep_set_wedge, 989}; 990 991/* -------------------------------------------------------------------------- */ 992 993static int dwc3_gadget_get_frame(struct usb_gadget *g) 994{ 995 struct dwc3 *dwc = gadget_to_dwc(g); 996 u32 reg; 997 998 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 999 return DWC3_DSTS_SOFFN(reg); 1000} 1001 1002static int dwc3_gadget_wakeup(struct usb_gadget *g) 1003{ 1004 struct dwc3 *dwc = gadget_to_dwc(g); 1005 1006 unsigned long timeout; 1007 unsigned long flags; 1008 1009 u32 reg; 1010 1011 int ret = 0; 1012 1013 u8 link_state; 1014 u8 speed; 1015 1016 spin_lock_irqsave(&dwc->lock, flags); 1017 1018 /* 1019 * According to the Databook Remote wakeup request should 1020 * be issued only when the device is in early suspend state. 1021 * 1022 * We can check that via USB Link State bits in DSTS register. 1023 */ 1024 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1025 1026 speed = reg & DWC3_DSTS_CONNECTSPD; 1027 if (speed == DWC3_DSTS_SUPERSPEED) { 1028 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1029 ret = -EINVAL; 1030 goto out; 1031 } 1032 1033 link_state = DWC3_DSTS_USBLNKST(reg); 1034 1035 switch (link_state) { 1036 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1037 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1038 break; 1039 default: 1040 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1041 link_state); 1042 ret = -EINVAL; 1043 goto out; 1044 } 1045 1046 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1047 1048 /* 1049 * Switch link state to Recovery. In HS/FS/LS this means 1050 * RemoteWakeup Request 1051 */ 1052 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY; 1053 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1054 1055 /* wait for at least 2000us */ 1056 usleep_range(2000, 2500); 1057 1058 /* write zeroes to Link Change Request */ 1059 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1060 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1061 1062 /* pool until Link State change to ON */ 1063 timeout = jiffies + msecs_to_jiffies(100); 1064 1065 while (!(time_after(jiffies, timeout))) { 1066 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1067 1068 /* in HS, means ON */ 1069 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1070 break; 1071 } 1072 1073 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1074 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1075 ret = -EINVAL; 1076 } 1077 1078out: 1079 spin_unlock_irqrestore(&dwc->lock, flags); 1080 1081 return ret; 1082} 1083 1084static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1085 int is_selfpowered) 1086{ 1087 struct dwc3 *dwc = gadget_to_dwc(g); 1088 1089 dwc->is_selfpowered = !!is_selfpowered; 1090 1091 return 0; 1092} 1093 1094static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) 1095{ 1096 u32 reg; 1097 u32 timeout = 500; 1098 1099 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1100 if (is_on) 1101 reg |= DWC3_DCTL_RUN_STOP; 1102 else 1103 reg &= ~DWC3_DCTL_RUN_STOP; 1104 1105 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1106 1107 do { 1108 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1109 if (is_on) { 1110 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1111 break; 1112 } else { 1113 if (reg & DWC3_DSTS_DEVCTRLHLT) 1114 break; 1115 } 1116 timeout--; 1117 if (!timeout) 1118 break; 1119 udelay(1); 1120 } while (1); 1121 1122 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1123 dwc->gadget_driver 1124 ? dwc->gadget_driver->function : "no-function", 1125 is_on ? "connect" : "disconnect"); 1126} 1127 1128static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1129{ 1130 struct dwc3 *dwc = gadget_to_dwc(g); 1131 unsigned long flags; 1132 1133 is_on = !!is_on; 1134 1135 spin_lock_irqsave(&dwc->lock, flags); 1136 dwc3_gadget_run_stop(dwc, is_on); 1137 spin_unlock_irqrestore(&dwc->lock, flags); 1138 1139 return 0; 1140} 1141 1142static int dwc3_gadget_start(struct usb_gadget *g, 1143 struct usb_gadget_driver *driver) 1144{ 1145 struct dwc3 *dwc = gadget_to_dwc(g); 1146 struct dwc3_ep *dep; 1147 unsigned long flags; 1148 int ret = 0; 1149 u32 reg; 1150 1151 spin_lock_irqsave(&dwc->lock, flags); 1152 1153 if (dwc->gadget_driver) { 1154 dev_err(dwc->dev, "%s is already bound to %s\n", 1155 dwc->gadget.name, 1156 dwc->gadget_driver->driver.name); 1157 ret = -EBUSY; 1158 goto err0; 1159 } 1160 1161 dwc->gadget_driver = driver; 1162 dwc->gadget.dev.driver = &driver->driver; 1163 1164 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1165 reg &= ~(DWC3_DCFG_SPEED_MASK); 1166 reg |= dwc->maximum_speed; 1167 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1168 1169 dwc->start_config_issued = false; 1170 1171 /* Start with SuperSpeed Default */ 1172 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1173 1174 dep = dwc->eps[0]; 1175 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1176 if (ret) { 1177 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1178 goto err0; 1179 } 1180 1181 dep = dwc->eps[1]; 1182 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1183 if (ret) { 1184 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1185 goto err1; 1186 } 1187 1188 /* begin to receive SETUP packets */ 1189 dwc->ep0state = EP0_SETUP_PHASE; 1190 dwc3_ep0_out_start(dwc); 1191 1192 spin_unlock_irqrestore(&dwc->lock, flags); 1193 1194 return 0; 1195 1196err1: 1197 __dwc3_gadget_ep_disable(dwc->eps[0]); 1198 1199err0: 1200 spin_unlock_irqrestore(&dwc->lock, flags); 1201 1202 return ret; 1203} 1204 1205static int dwc3_gadget_stop(struct usb_gadget *g, 1206 struct usb_gadget_driver *driver) 1207{ 1208 struct dwc3 *dwc = gadget_to_dwc(g); 1209 unsigned long flags; 1210 1211 spin_lock_irqsave(&dwc->lock, flags); 1212 1213 __dwc3_gadget_ep_disable(dwc->eps[0]); 1214 __dwc3_gadget_ep_disable(dwc->eps[1]); 1215 1216 dwc->gadget_driver = NULL; 1217 dwc->gadget.dev.driver = NULL; 1218 1219 spin_unlock_irqrestore(&dwc->lock, flags); 1220 1221 return 0; 1222} 1223static const struct usb_gadget_ops dwc3_gadget_ops = { 1224 .get_frame = dwc3_gadget_get_frame, 1225 .wakeup = dwc3_gadget_wakeup, 1226 .set_selfpowered = dwc3_gadget_set_selfpowered, 1227 .pullup = dwc3_gadget_pullup, 1228 .udc_start = dwc3_gadget_start, 1229 .udc_stop = dwc3_gadget_stop, 1230}; 1231 1232/* -------------------------------------------------------------------------- */ 1233 1234static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1235{ 1236 struct dwc3_ep *dep; 1237 u8 epnum; 1238 1239 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1240 1241 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1242 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1243 if (!dep) { 1244 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1245 epnum); 1246 return -ENOMEM; 1247 } 1248 1249 dep->dwc = dwc; 1250 dep->number = epnum; 1251 dwc->eps[epnum] = dep; 1252 1253 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1254 (epnum & 1) ? "in" : "out"); 1255 dep->endpoint.name = dep->name; 1256 dep->direction = (epnum & 1); 1257 1258 if (epnum == 0 || epnum == 1) { 1259 dep->endpoint.maxpacket = 512; 1260 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1261 if (!epnum) 1262 dwc->gadget.ep0 = &dep->endpoint; 1263 } else { 1264 int ret; 1265 1266 dep->endpoint.maxpacket = 1024; 1267 dep->endpoint.max_streams = 15; 1268 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1269 list_add_tail(&dep->endpoint.ep_list, 1270 &dwc->gadget.ep_list); 1271 1272 ret = dwc3_alloc_trb_pool(dep); 1273 if (ret) 1274 return ret; 1275 } 1276 1277 INIT_LIST_HEAD(&dep->request_list); 1278 INIT_LIST_HEAD(&dep->req_queued); 1279 } 1280 1281 return 0; 1282} 1283 1284static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1285{ 1286 struct dwc3_ep *dep; 1287 u8 epnum; 1288 1289 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1290 dep = dwc->eps[epnum]; 1291 dwc3_free_trb_pool(dep); 1292 1293 if (epnum != 0 && epnum != 1) 1294 list_del(&dep->endpoint.ep_list); 1295 1296 kfree(dep); 1297 } 1298} 1299 1300static void dwc3_gadget_release(struct device *dev) 1301{ 1302 dev_dbg(dev, "%s\n", __func__); 1303} 1304 1305/* -------------------------------------------------------------------------- */ 1306static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1307 const struct dwc3_event_depevt *event, int status) 1308{ 1309 struct dwc3_request *req; 1310 struct dwc3_trb trb; 1311 unsigned int count; 1312 unsigned int s_pkt = 0; 1313 1314 do { 1315 req = next_request(&dep->req_queued); 1316 if (!req) { 1317 WARN_ON_ONCE(1); 1318 return 1; 1319 } 1320 1321 dwc3_trb_to_nat(req->trb, &trb); 1322 1323 if (trb.hwo && status != -ESHUTDOWN) 1324 /* 1325 * We continue despite the error. There is not much we 1326 * can do. If we don't clean in up we loop for ever. If 1327 * we skip the TRB than it gets overwritten reused after 1328 * a while since we use them in a ring buffer. a BUG() 1329 * would help. Lets hope that if this occures, someone 1330 * fixes the root cause instead of looking away :) 1331 */ 1332 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1333 dep->name, req->trb); 1334 count = trb.length; 1335 1336 if (dep->direction) { 1337 if (count) { 1338 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1339 dep->name); 1340 status = -ECONNRESET; 1341 } 1342 } else { 1343 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1344 s_pkt = 1; 1345 } 1346 1347 /* 1348 * We assume here we will always receive the entire data block 1349 * which we should receive. Meaning, if we program RX to 1350 * receive 4K but we receive only 2K, we assume that's all we 1351 * should receive and we simply bounce the request back to the 1352 * gadget driver for further processing. 1353 */ 1354 req->request.actual += req->request.length - count; 1355 dwc3_gadget_giveback(dep, req, status); 1356 if (s_pkt) 1357 break; 1358 if ((event->status & DEPEVT_STATUS_LST) && trb.lst) 1359 break; 1360 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc) 1361 break; 1362 } while (1); 1363 1364 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc) 1365 return 0; 1366 return 1; 1367} 1368 1369static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1370 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1371 int start_new) 1372{ 1373 unsigned status = 0; 1374 int clean_busy; 1375 1376 if (event->status & DEPEVT_STATUS_BUSERR) 1377 status = -ECONNRESET; 1378 1379 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1380 if (clean_busy) { 1381 dep->flags &= ~DWC3_EP_BUSY; 1382 dep->res_trans_idx = 0; 1383 } 1384 1385 /* 1386 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1387 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1388 */ 1389 if (dwc->revision < DWC3_REVISION_183A) { 1390 u32 reg; 1391 int i; 1392 1393 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1394 struct dwc3_ep *dep = dwc->eps[i]; 1395 1396 if (!(dep->flags & DWC3_EP_ENABLED)) 1397 continue; 1398 1399 if (!list_empty(&dep->req_queued)) 1400 return; 1401 } 1402 1403 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1404 reg |= dwc->u1u2; 1405 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1406 1407 dwc->u1u2 = 0; 1408 } 1409} 1410 1411static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1412 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1413{ 1414 u32 uf; 1415 1416 if (list_empty(&dep->request_list)) { 1417 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1418 dep->name); 1419 return; 1420 } 1421 1422 if (event->parameters) { 1423 u32 mask; 1424 1425 mask = ~(dep->interval - 1); 1426 uf = event->parameters & mask; 1427 /* 4 micro frames in the future */ 1428 uf += dep->interval * 4; 1429 } else { 1430 uf = 0; 1431 } 1432 1433 __dwc3_gadget_kick_transfer(dep, uf, 1); 1434} 1435 1436static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep, 1437 const struct dwc3_event_depevt *event) 1438{ 1439 struct dwc3 *dwc = dep->dwc; 1440 struct dwc3_event_depevt mod_ev = *event; 1441 1442 /* 1443 * We were asked to remove one requests. It is possible that this 1444 * request and a few other were started together and have the same 1445 * transfer index. Since we stopped the complete endpoint we don't 1446 * know how many requests were already completed (and not yet) 1447 * reported and how could be done (later). We purge them all until 1448 * the end of the list. 1449 */ 1450 mod_ev.status = DEPEVT_STATUS_LST; 1451 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN); 1452 dep->flags &= ~DWC3_EP_BUSY; 1453 /* pending requets are ignored and are queued on XferNotReady */ 1454} 1455 1456static void dwc3_ep_cmd_compl(struct dwc3_ep *dep, 1457 const struct dwc3_event_depevt *event) 1458{ 1459 u32 param = event->parameters; 1460 u32 cmd_type = (param >> 8) & ((1 << 5) - 1); 1461 1462 switch (cmd_type) { 1463 case DWC3_DEPCMD_ENDTRANSFER: 1464 dwc3_process_ep_cmd_complete(dep, event); 1465 break; 1466 case DWC3_DEPCMD_STARTTRANSFER: 1467 dep->res_trans_idx = param & 0x7f; 1468 break; 1469 default: 1470 printk(KERN_ERR "%s() unknown /unexpected type: %d\n", 1471 __func__, cmd_type); 1472 break; 1473 }; 1474} 1475 1476static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1477 const struct dwc3_event_depevt *event) 1478{ 1479 struct dwc3_ep *dep; 1480 u8 epnum = event->endpoint_number; 1481 1482 dep = dwc->eps[epnum]; 1483 1484 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1485 dwc3_ep_event_string(event->endpoint_event)); 1486 1487 if (epnum == 0 || epnum == 1) { 1488 dwc3_ep0_interrupt(dwc, event); 1489 return; 1490 } 1491 1492 switch (event->endpoint_event) { 1493 case DWC3_DEPEVT_XFERCOMPLETE: 1494 if (usb_endpoint_xfer_isoc(dep->desc)) { 1495 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1496 dep->name); 1497 return; 1498 } 1499 1500 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1501 break; 1502 case DWC3_DEPEVT_XFERINPROGRESS: 1503 if (!usb_endpoint_xfer_isoc(dep->desc)) { 1504 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1505 dep->name); 1506 return; 1507 } 1508 1509 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1510 break; 1511 case DWC3_DEPEVT_XFERNOTREADY: 1512 if (usb_endpoint_xfer_isoc(dep->desc)) { 1513 dwc3_gadget_start_isoc(dwc, dep, event); 1514 } else { 1515 int ret; 1516 1517 dev_vdbg(dwc->dev, "%s: reason %s\n", 1518 dep->name, event->status 1519 ? "Transfer Active" 1520 : "Transfer Not Active"); 1521 1522 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1523 if (!ret || ret == -EBUSY) 1524 return; 1525 1526 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1527 dep->name); 1528 } 1529 1530 break; 1531 case DWC3_DEPEVT_STREAMEVT: 1532 if (!usb_endpoint_xfer_bulk(dep->desc)) { 1533 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1534 dep->name); 1535 return; 1536 } 1537 1538 switch (event->status) { 1539 case DEPEVT_STREAMEVT_FOUND: 1540 dev_vdbg(dwc->dev, "Stream %d found and started\n", 1541 event->parameters); 1542 1543 break; 1544 case DEPEVT_STREAMEVT_NOTFOUND: 1545 /* FALLTHROUGH */ 1546 default: 1547 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 1548 } 1549 break; 1550 case DWC3_DEPEVT_RXTXFIFOEVT: 1551 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 1552 break; 1553 case DWC3_DEPEVT_EPCMDCMPLT: 1554 dwc3_ep_cmd_compl(dep, event); 1555 break; 1556 } 1557} 1558 1559static void dwc3_disconnect_gadget(struct dwc3 *dwc) 1560{ 1561 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 1562 spin_unlock(&dwc->lock); 1563 dwc->gadget_driver->disconnect(&dwc->gadget); 1564 spin_lock(&dwc->lock); 1565 } 1566} 1567 1568static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) 1569{ 1570 struct dwc3_ep *dep; 1571 struct dwc3_gadget_ep_cmd_params params; 1572 u32 cmd; 1573 int ret; 1574 1575 dep = dwc->eps[epnum]; 1576 1577 WARN_ON(!dep->res_trans_idx); 1578 if (dep->res_trans_idx) { 1579 cmd = DWC3_DEPCMD_ENDTRANSFER; 1580 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; 1581 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx); 1582 memset(¶ms, 0, sizeof(params)); 1583 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1584 WARN_ON_ONCE(ret); 1585 dep->res_trans_idx = 0; 1586 } 1587} 1588 1589static void dwc3_stop_active_transfers(struct dwc3 *dwc) 1590{ 1591 u32 epnum; 1592 1593 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1594 struct dwc3_ep *dep; 1595 1596 dep = dwc->eps[epnum]; 1597 if (!(dep->flags & DWC3_EP_ENABLED)) 1598 continue; 1599 1600 dwc3_remove_requests(dwc, dep); 1601 } 1602} 1603 1604static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 1605{ 1606 u32 epnum; 1607 1608 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1609 struct dwc3_ep *dep; 1610 struct dwc3_gadget_ep_cmd_params params; 1611 int ret; 1612 1613 dep = dwc->eps[epnum]; 1614 1615 if (!(dep->flags & DWC3_EP_STALL)) 1616 continue; 1617 1618 dep->flags &= ~DWC3_EP_STALL; 1619 1620 memset(¶ms, 0, sizeof(params)); 1621 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1622 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1623 WARN_ON_ONCE(ret); 1624 } 1625} 1626 1627static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 1628{ 1629 dev_vdbg(dwc->dev, "%s\n", __func__); 1630#if 0 1631 XXX 1632 U1/U2 is powersave optimization. Skip it for now. Anyway we need to 1633 enable it before we can disable it. 1634 1635 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1636 reg &= ~DWC3_DCTL_INITU1ENA; 1637 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1638 1639 reg &= ~DWC3_DCTL_INITU2ENA; 1640 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1641#endif 1642 1643 dwc3_stop_active_transfers(dwc); 1644 dwc3_disconnect_gadget(dwc); 1645 dwc->start_config_issued = false; 1646 1647 dwc->gadget.speed = USB_SPEED_UNKNOWN; 1648 dwc->setup_packet_pending = false; 1649} 1650 1651static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on) 1652{ 1653 u32 reg; 1654 1655 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1656 1657 if (on) 1658 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 1659 else 1660 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1661 1662 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1663} 1664 1665static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on) 1666{ 1667 u32 reg; 1668 1669 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1670 1671 if (on) 1672 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1673 else 1674 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1675 1676 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1677} 1678 1679static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 1680{ 1681 u32 reg; 1682 1683 dev_vdbg(dwc->dev, "%s\n", __func__); 1684 1685 /* 1686 * WORKAROUND: DWC3 revisions <1.88a have an issue which 1687 * would cause a missing Disconnect Event if there's a 1688 * pending Setup Packet in the FIFO. 1689 * 1690 * There's no suggested workaround on the official Bug 1691 * report, which states that "unless the driver/application 1692 * is doing any special handling of a disconnect event, 1693 * there is no functional issue". 1694 * 1695 * Unfortunately, it turns out that we _do_ some special 1696 * handling of a disconnect event, namely complete all 1697 * pending transfers, notify gadget driver of the 1698 * disconnection, and so on. 1699 * 1700 * Our suggested workaround is to follow the Disconnect 1701 * Event steps here, instead, based on a setup_packet_pending 1702 * flag. Such flag gets set whenever we have a XferNotReady 1703 * event on EP0 and gets cleared on XferComplete for the 1704 * same endpoint. 1705 * 1706 * Refers to: 1707 * 1708 * STAR#9000466709: RTL: Device : Disconnect event not 1709 * generated if setup packet pending in FIFO 1710 */ 1711 if (dwc->revision < DWC3_REVISION_188A) { 1712 if (dwc->setup_packet_pending) 1713 dwc3_gadget_disconnect_interrupt(dwc); 1714 } 1715 1716 /* Enable PHYs */ 1717 dwc3_gadget_usb2_phy_power(dwc, true); 1718 dwc3_gadget_usb3_phy_power(dwc, true); 1719 1720 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 1721 dwc3_disconnect_gadget(dwc); 1722 1723 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1724 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 1725 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1726 1727 dwc3_stop_active_transfers(dwc); 1728 dwc3_clear_stall_all_ep(dwc); 1729 dwc->start_config_issued = false; 1730 1731 /* Reset device address to zero */ 1732 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1733 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 1734 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1735} 1736 1737static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 1738{ 1739 u32 reg; 1740 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 1741 1742 /* 1743 * We change the clock only at SS but I dunno why I would want to do 1744 * this. Maybe it becomes part of the power saving plan. 1745 */ 1746 1747 if (speed != DWC3_DSTS_SUPERSPEED) 1748 return; 1749 1750 /* 1751 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 1752 * each time on Connect Done. 1753 */ 1754 if (!usb30_clock) 1755 return; 1756 1757 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1758 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 1759 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1760} 1761 1762static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed) 1763{ 1764 switch (speed) { 1765 case USB_SPEED_SUPER: 1766 dwc3_gadget_usb2_phy_power(dwc, false); 1767 break; 1768 case USB_SPEED_HIGH: 1769 case USB_SPEED_FULL: 1770 case USB_SPEED_LOW: 1771 dwc3_gadget_usb3_phy_power(dwc, false); 1772 break; 1773 } 1774} 1775 1776static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 1777{ 1778 struct dwc3_gadget_ep_cmd_params params; 1779 struct dwc3_ep *dep; 1780 int ret; 1781 u32 reg; 1782 u8 speed; 1783 1784 dev_vdbg(dwc->dev, "%s\n", __func__); 1785 1786 memset(¶ms, 0x00, sizeof(params)); 1787 1788 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1789 speed = reg & DWC3_DSTS_CONNECTSPD; 1790 dwc->speed = speed; 1791 1792 dwc3_update_ram_clk_sel(dwc, speed); 1793 1794 switch (speed) { 1795 case DWC3_DCFG_SUPERSPEED: 1796 /* 1797 * WORKAROUND: DWC3 revisions <1.90a have an issue which 1798 * would cause a missing USB3 Reset event. 1799 * 1800 * In such situations, we should force a USB3 Reset 1801 * event by calling our dwc3_gadget_reset_interrupt() 1802 * routine. 1803 * 1804 * Refers to: 1805 * 1806 * STAR#9000483510: RTL: SS : USB3 reset event may 1807 * not be generated always when the link enters poll 1808 */ 1809 if (dwc->revision < DWC3_REVISION_190A) 1810 dwc3_gadget_reset_interrupt(dwc); 1811 1812 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1813 dwc->gadget.ep0->maxpacket = 512; 1814 dwc->gadget.speed = USB_SPEED_SUPER; 1815 break; 1816 case DWC3_DCFG_HIGHSPEED: 1817 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 1818 dwc->gadget.ep0->maxpacket = 64; 1819 dwc->gadget.speed = USB_SPEED_HIGH; 1820 break; 1821 case DWC3_DCFG_FULLSPEED2: 1822 case DWC3_DCFG_FULLSPEED1: 1823 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 1824 dwc->gadget.ep0->maxpacket = 64; 1825 dwc->gadget.speed = USB_SPEED_FULL; 1826 break; 1827 case DWC3_DCFG_LOWSPEED: 1828 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 1829 dwc->gadget.ep0->maxpacket = 8; 1830 dwc->gadget.speed = USB_SPEED_LOW; 1831 break; 1832 } 1833 1834 /* Disable unneded PHY */ 1835 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed); 1836 1837 dep = dwc->eps[0]; 1838 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1839 if (ret) { 1840 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1841 return; 1842 } 1843 1844 dep = dwc->eps[1]; 1845 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1846 if (ret) { 1847 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1848 return; 1849 } 1850 1851 /* 1852 * Configure PHY via GUSB3PIPECTLn if required. 1853 * 1854 * Update GTXFIFOSIZn 1855 * 1856 * In both cases reset values should be sufficient. 1857 */ 1858} 1859 1860static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 1861{ 1862 dev_vdbg(dwc->dev, "%s\n", __func__); 1863 1864 /* 1865 * TODO take core out of low power mode when that's 1866 * implemented. 1867 */ 1868 1869 dwc->gadget_driver->resume(&dwc->gadget); 1870} 1871 1872static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 1873 unsigned int evtinfo) 1874{ 1875 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 1876 1877 /* 1878 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 1879 * on the link partner, the USB session might do multiple entry/exit 1880 * of low power states before a transfer takes place. 1881 * 1882 * Due to this problem, we might experience lower throughput. The 1883 * suggested workaround is to disable DCTL[12:9] bits if we're 1884 * transitioning from U1/U2 to U0 and enable those bits again 1885 * after a transfer completes and there are no pending transfers 1886 * on any of the enabled endpoints. 1887 * 1888 * This is the first half of that workaround. 1889 * 1890 * Refers to: 1891 * 1892 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 1893 * core send LGO_Ux entering U0 1894 */ 1895 if (dwc->revision < DWC3_REVISION_183A) { 1896 if (next == DWC3_LINK_STATE_U0) { 1897 u32 u1u2; 1898 u32 reg; 1899 1900 switch (dwc->link_state) { 1901 case DWC3_LINK_STATE_U1: 1902 case DWC3_LINK_STATE_U2: 1903 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1904 u1u2 = reg & (DWC3_DCTL_INITU2ENA 1905 | DWC3_DCTL_ACCEPTU2ENA 1906 | DWC3_DCTL_INITU1ENA 1907 | DWC3_DCTL_ACCEPTU1ENA); 1908 1909 if (!dwc->u1u2) 1910 dwc->u1u2 = reg & u1u2; 1911 1912 reg &= ~u1u2; 1913 1914 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1915 break; 1916 default: 1917 /* do nothing */ 1918 break; 1919 } 1920 } 1921 } 1922 1923 dwc->link_state = next; 1924 1925 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 1926} 1927 1928static void dwc3_gadget_interrupt(struct dwc3 *dwc, 1929 const struct dwc3_event_devt *event) 1930{ 1931 switch (event->type) { 1932 case DWC3_DEVICE_EVENT_DISCONNECT: 1933 dwc3_gadget_disconnect_interrupt(dwc); 1934 break; 1935 case DWC3_DEVICE_EVENT_RESET: 1936 dwc3_gadget_reset_interrupt(dwc); 1937 break; 1938 case DWC3_DEVICE_EVENT_CONNECT_DONE: 1939 dwc3_gadget_conndone_interrupt(dwc); 1940 break; 1941 case DWC3_DEVICE_EVENT_WAKEUP: 1942 dwc3_gadget_wakeup_interrupt(dwc); 1943 break; 1944 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 1945 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 1946 break; 1947 case DWC3_DEVICE_EVENT_EOPF: 1948 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 1949 break; 1950 case DWC3_DEVICE_EVENT_SOF: 1951 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 1952 break; 1953 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 1954 dev_vdbg(dwc->dev, "Erratic Error\n"); 1955 break; 1956 case DWC3_DEVICE_EVENT_CMD_CMPL: 1957 dev_vdbg(dwc->dev, "Command Complete\n"); 1958 break; 1959 case DWC3_DEVICE_EVENT_OVERFLOW: 1960 dev_vdbg(dwc->dev, "Overflow\n"); 1961 break; 1962 default: 1963 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 1964 } 1965} 1966 1967static void dwc3_process_event_entry(struct dwc3 *dwc, 1968 const union dwc3_event *event) 1969{ 1970 /* Endpoint IRQ, handle it and return early */ 1971 if (event->type.is_devspec == 0) { 1972 /* depevt */ 1973 return dwc3_endpoint_interrupt(dwc, &event->depevt); 1974 } 1975 1976 switch (event->type.type) { 1977 case DWC3_EVENT_TYPE_DEV: 1978 dwc3_gadget_interrupt(dwc, &event->devt); 1979 break; 1980 /* REVISIT what to do with Carkit and I2C events ? */ 1981 default: 1982 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 1983 } 1984} 1985 1986static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 1987{ 1988 struct dwc3_event_buffer *evt; 1989 int left; 1990 u32 count; 1991 1992 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 1993 count &= DWC3_GEVNTCOUNT_MASK; 1994 if (!count) 1995 return IRQ_NONE; 1996 1997 evt = dwc->ev_buffs[buf]; 1998 left = count; 1999 2000 while (left > 0) { 2001 union dwc3_event event; 2002 2003 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw)); 2004 dwc3_process_event_entry(dwc, &event); 2005 /* 2006 * XXX we wrap around correctly to the next entry as almost all 2007 * entries are 4 bytes in size. There is one entry which has 12 2008 * bytes which is a regular entry followed by 8 bytes data. ATM 2009 * I don't know how things are organized if were get next to the 2010 * a boundary so I worry about that once we try to handle that. 2011 */ 2012 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2013 left -= 4; 2014 2015 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2016 } 2017 2018 return IRQ_HANDLED; 2019} 2020 2021static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2022{ 2023 struct dwc3 *dwc = _dwc; 2024 int i; 2025 irqreturn_t ret = IRQ_NONE; 2026 2027 spin_lock(&dwc->lock); 2028 2029 for (i = 0; i < dwc->num_event_buffers; i++) { 2030 irqreturn_t status; 2031 2032 status = dwc3_process_event_buf(dwc, i); 2033 if (status == IRQ_HANDLED) 2034 ret = status; 2035 } 2036 2037 spin_unlock(&dwc->lock); 2038 2039 return ret; 2040} 2041 2042/** 2043 * dwc3_gadget_init - Initializes gadget related registers 2044 * @dwc: Pointer to out controller context structure 2045 * 2046 * Returns 0 on success otherwise negative errno. 2047 */ 2048int __devinit dwc3_gadget_init(struct dwc3 *dwc) 2049{ 2050 u32 reg; 2051 int ret; 2052 int irq; 2053 2054 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2055 &dwc->ctrl_req_addr, GFP_KERNEL); 2056 if (!dwc->ctrl_req) { 2057 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2058 ret = -ENOMEM; 2059 goto err0; 2060 } 2061 2062 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2063 &dwc->ep0_trb_addr, GFP_KERNEL); 2064 if (!dwc->ep0_trb) { 2065 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2066 ret = -ENOMEM; 2067 goto err1; 2068 } 2069 2070 dwc->setup_buf = dma_alloc_coherent(dwc->dev, 2071 sizeof(*dwc->setup_buf) * 2, 2072 &dwc->setup_buf_addr, GFP_KERNEL); 2073 if (!dwc->setup_buf) { 2074 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2075 ret = -ENOMEM; 2076 goto err2; 2077 } 2078 2079 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2080 512, &dwc->ep0_bounce_addr, GFP_KERNEL); 2081 if (!dwc->ep0_bounce) { 2082 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2083 ret = -ENOMEM; 2084 goto err3; 2085 } 2086 2087 dev_set_name(&dwc->gadget.dev, "gadget"); 2088 2089 dwc->gadget.ops = &dwc3_gadget_ops; 2090 dwc->gadget.is_dualspeed = true; 2091 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2092 dwc->gadget.dev.parent = dwc->dev; 2093 2094 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); 2095 2096 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; 2097 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; 2098 dwc->gadget.dev.release = dwc3_gadget_release; 2099 dwc->gadget.name = "dwc3-gadget"; 2100 2101 /* 2102 * REVISIT: Here we should clear all pending IRQs to be 2103 * sure we're starting from a well known location. 2104 */ 2105 2106 ret = dwc3_gadget_init_endpoints(dwc); 2107 if (ret) 2108 goto err4; 2109 2110 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2111 2112 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, 2113 "dwc3", dwc); 2114 if (ret) { 2115 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 2116 irq, ret); 2117 goto err5; 2118 } 2119 2120 /* Enable all but Start and End of Frame IRQs */ 2121 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 2122 DWC3_DEVTEN_EVNTOVERFLOWEN | 2123 DWC3_DEVTEN_CMDCMPLTEN | 2124 DWC3_DEVTEN_ERRTICERREN | 2125 DWC3_DEVTEN_WKUPEVTEN | 2126 DWC3_DEVTEN_ULSTCNGEN | 2127 DWC3_DEVTEN_CONNECTDONEEN | 2128 DWC3_DEVTEN_USBRSTEN | 2129 DWC3_DEVTEN_DISCONNEVTEN); 2130 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 2131 2132 ret = device_register(&dwc->gadget.dev); 2133 if (ret) { 2134 dev_err(dwc->dev, "failed to register gadget device\n"); 2135 put_device(&dwc->gadget.dev); 2136 goto err6; 2137 } 2138 2139 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2140 if (ret) { 2141 dev_err(dwc->dev, "failed to register udc\n"); 2142 goto err7; 2143 } 2144 2145 return 0; 2146 2147err7: 2148 device_unregister(&dwc->gadget.dev); 2149 2150err6: 2151 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2152 free_irq(irq, dwc); 2153 2154err5: 2155 dwc3_gadget_free_endpoints(dwc); 2156 2157err4: 2158 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce, 2159 dwc->ep0_bounce_addr); 2160 2161err3: 2162 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2, 2163 dwc->setup_buf, dwc->setup_buf_addr); 2164 2165err2: 2166 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2167 dwc->ep0_trb, dwc->ep0_trb_addr); 2168 2169err1: 2170 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2171 dwc->ctrl_req, dwc->ctrl_req_addr); 2172 2173err0: 2174 return ret; 2175} 2176 2177void dwc3_gadget_exit(struct dwc3 *dwc) 2178{ 2179 int irq; 2180 2181 usb_del_gadget_udc(&dwc->gadget); 2182 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2183 2184 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2185 free_irq(irq, dwc); 2186 2187 dwc3_gadget_free_endpoints(dwc); 2188 2189 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce, 2190 dwc->ep0_bounce_addr); 2191 2192 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2, 2193 dwc->setup_buf, dwc->setup_buf_addr); 2194 2195 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2196 dwc->ep0_trb, dwc->ep0_trb_addr); 2197 2198 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2199 dwc->ctrl_req, dwc->ctrl_req_addr); 2200 2201 device_unregister(&dwc->gadget.dev); 2202} 2203