gadget.c revision df62df56e13d73cb0dd4c54649d4fe13557128f8
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <linux/kernel.h> 40#include <linux/delay.h> 41#include <linux/slab.h> 42#include <linux/spinlock.h> 43#include <linux/platform_device.h> 44#include <linux/pm_runtime.h> 45#include <linux/interrupt.h> 46#include <linux/io.h> 47#include <linux/list.h> 48#include <linux/dma-mapping.h> 49 50#include <linux/usb/ch9.h> 51#include <linux/usb/gadget.h> 52 53#include "core.h" 54#include "gadget.h" 55#include "io.h" 56 57#define DMA_ADDR_INVALID (~(dma_addr_t)0) 58 59void dwc3_map_buffer_to_dma(struct dwc3_request *req) 60{ 61 struct dwc3 *dwc = req->dep->dwc; 62 63 if (req->request.length == 0) { 64 /* req->request.dma = dwc->setup_buf_addr; */ 65 return; 66 } 67 68 if (req->request.dma == DMA_ADDR_INVALID) { 69 req->request.dma = dma_map_single(dwc->dev, req->request.buf, 70 req->request.length, req->direction 71 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 72 req->mapped = true; 73 } 74} 75 76void dwc3_unmap_buffer_from_dma(struct dwc3_request *req) 77{ 78 struct dwc3 *dwc = req->dep->dwc; 79 80 if (req->request.length == 0) { 81 req->request.dma = DMA_ADDR_INVALID; 82 return; 83 } 84 85 if (req->mapped) { 86 dma_unmap_single(dwc->dev, req->request.dma, 87 req->request.length, req->direction 88 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 89 req->mapped = 0; 90 req->request.dma = DMA_ADDR_INVALID; 91 } 92} 93 94void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 95 int status) 96{ 97 struct dwc3 *dwc = dep->dwc; 98 99 if (req->queued) { 100 dep->busy_slot++; 101 /* 102 * Skip LINK TRB. We can't use req->trb and check for 103 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just 104 * completed (not the LINK TRB). 105 */ 106 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 107 usb_endpoint_xfer_isoc(dep->desc)) 108 dep->busy_slot++; 109 } 110 list_del(&req->list); 111 112 if (req->request.status == -EINPROGRESS) 113 req->request.status = status; 114 115 dwc3_unmap_buffer_from_dma(req); 116 117 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 118 req, dep->name, req->request.actual, 119 req->request.length, status); 120 121 spin_unlock(&dwc->lock); 122 req->request.complete(&req->dep->endpoint, &req->request); 123 spin_lock(&dwc->lock); 124} 125 126static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 127{ 128 switch (cmd) { 129 case DWC3_DEPCMD_DEPSTARTCFG: 130 return "Start New Configuration"; 131 case DWC3_DEPCMD_ENDTRANSFER: 132 return "End Transfer"; 133 case DWC3_DEPCMD_UPDATETRANSFER: 134 return "Update Transfer"; 135 case DWC3_DEPCMD_STARTTRANSFER: 136 return "Start Transfer"; 137 case DWC3_DEPCMD_CLEARSTALL: 138 return "Clear Stall"; 139 case DWC3_DEPCMD_SETSTALL: 140 return "Set Stall"; 141 case DWC3_DEPCMD_GETSEQNUMBER: 142 return "Get Data Sequence Number"; 143 case DWC3_DEPCMD_SETTRANSFRESOURCE: 144 return "Set Endpoint Transfer Resource"; 145 case DWC3_DEPCMD_SETEPCONFIG: 146 return "Set Endpoint Configuration"; 147 default: 148 return "UNKNOWN command"; 149 } 150} 151 152int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 153 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 154{ 155 struct dwc3_ep *dep = dwc->eps[ep]; 156 u32 timeout = 500; 157 u32 reg; 158 159 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 160 dep->name, 161 dwc3_gadget_ep_cmd_string(cmd), params->param0, 162 params->param1, params->param2); 163 164 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 165 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 166 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 167 168 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 169 do { 170 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 171 if (!(reg & DWC3_DEPCMD_CMDACT)) { 172 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 173 DWC3_DEPCMD_STATUS(reg)); 174 return 0; 175 } 176 177 /* 178 * We can't sleep here, because it is also called from 179 * interrupt context. 180 */ 181 timeout--; 182 if (!timeout) 183 return -ETIMEDOUT; 184 185 udelay(1); 186 } while (1); 187} 188 189static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 190 struct dwc3_trb_hw *trb) 191{ 192 u32 offset = (char *) trb - (char *) dep->trb_pool; 193 194 return dep->trb_pool_dma + offset; 195} 196 197static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 198{ 199 struct dwc3 *dwc = dep->dwc; 200 201 if (dep->trb_pool) 202 return 0; 203 204 if (dep->number == 0 || dep->number == 1) 205 return 0; 206 207 dep->trb_pool = dma_alloc_coherent(dwc->dev, 208 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 209 &dep->trb_pool_dma, GFP_KERNEL); 210 if (!dep->trb_pool) { 211 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 212 dep->name); 213 return -ENOMEM; 214 } 215 216 return 0; 217} 218 219static void dwc3_free_trb_pool(struct dwc3_ep *dep) 220{ 221 struct dwc3 *dwc = dep->dwc; 222 223 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 224 dep->trb_pool, dep->trb_pool_dma); 225 226 dep->trb_pool = NULL; 227 dep->trb_pool_dma = 0; 228} 229 230static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 231{ 232 struct dwc3_gadget_ep_cmd_params params; 233 u32 cmd; 234 235 memset(¶ms, 0x00, sizeof(params)); 236 237 if (dep->number != 1) { 238 cmd = DWC3_DEPCMD_DEPSTARTCFG; 239 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 240 if (dep->number > 1) { 241 if (dwc->start_config_issued) 242 return 0; 243 dwc->start_config_issued = true; 244 cmd |= DWC3_DEPCMD_PARAM(2); 245 } 246 247 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 248 } 249 250 return 0; 251} 252 253static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 254 const struct usb_endpoint_descriptor *desc) 255{ 256 struct dwc3_gadget_ep_cmd_params params; 257 258 memset(¶ms, 0x00, sizeof(params)); 259 260 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 261 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) 262 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst); 263 264 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 265 | DWC3_DEPCFG_XFER_NOT_READY_EN; 266 267 if (usb_endpoint_xfer_bulk(desc) && dep->endpoint.max_streams) { 268 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 269 | DWC3_DEPCFG_STREAM_EVENT_EN; 270 dep->stream_capable = true; 271 } 272 273 if (usb_endpoint_xfer_isoc(desc)) 274 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 275 276 /* 277 * We are doing 1:1 mapping for endpoints, meaning 278 * Physical Endpoints 2 maps to Logical Endpoint 2 and 279 * so on. We consider the direction bit as part of the physical 280 * endpoint number. So USB endpoint 0x81 is 0x03. 281 */ 282 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 283 284 /* 285 * We must use the lower 16 TX FIFOs even though 286 * HW might have more 287 */ 288 if (dep->direction) 289 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 290 291 if (desc->bInterval) { 292 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 293 dep->interval = 1 << (desc->bInterval - 1); 294 } 295 296 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 297 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 298} 299 300static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 301{ 302 struct dwc3_gadget_ep_cmd_params params; 303 304 memset(¶ms, 0x00, sizeof(params)); 305 306 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 307 308 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 309 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 310} 311 312/** 313 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 314 * @dep: endpoint to be initialized 315 * @desc: USB Endpoint Descriptor 316 * 317 * Caller should take care of locking 318 */ 319static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 320 const struct usb_endpoint_descriptor *desc) 321{ 322 struct dwc3 *dwc = dep->dwc; 323 u32 reg; 324 int ret = -ENOMEM; 325 326 if (!(dep->flags & DWC3_EP_ENABLED)) { 327 ret = dwc3_gadget_start_config(dwc, dep); 328 if (ret) 329 return ret; 330 } 331 332 ret = dwc3_gadget_set_ep_config(dwc, dep, desc); 333 if (ret) 334 return ret; 335 336 if (!(dep->flags & DWC3_EP_ENABLED)) { 337 struct dwc3_trb_hw *trb_st_hw; 338 struct dwc3_trb_hw *trb_link_hw; 339 struct dwc3_trb trb_link; 340 341 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 342 if (ret) 343 return ret; 344 345 dep->desc = desc; 346 dep->type = usb_endpoint_type(desc); 347 dep->flags |= DWC3_EP_ENABLED; 348 349 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 350 reg |= DWC3_DALEPENA_EP(dep->number); 351 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 352 353 if (!usb_endpoint_xfer_isoc(desc)) 354 return 0; 355 356 memset(&trb_link, 0, sizeof(trb_link)); 357 358 /* Link TRB for ISOC. The HWO but is never reset */ 359 trb_st_hw = &dep->trb_pool[0]; 360 361 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw); 362 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB; 363 trb_link.hwo = true; 364 365 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1]; 366 dwc3_trb_to_hw(&trb_link, trb_link_hw); 367 } 368 369 return 0; 370} 371 372static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); 373static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 374{ 375 struct dwc3_request *req; 376 377 if (!list_empty(&dep->req_queued)) 378 dwc3_stop_active_transfer(dwc, dep->number); 379 380 while (!list_empty(&dep->request_list)) { 381 req = next_request(&dep->request_list); 382 383 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 384 } 385} 386 387/** 388 * __dwc3_gadget_ep_disable - Disables a HW endpoint 389 * @dep: the endpoint to disable 390 * 391 * This function also removes requests which are currently processed ny the 392 * hardware and those which are not yet scheduled. 393 * Caller should take care of locking. 394 */ 395static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 396{ 397 struct dwc3 *dwc = dep->dwc; 398 u32 reg; 399 400 dwc3_remove_requests(dwc, dep); 401 402 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 403 reg &= ~DWC3_DALEPENA_EP(dep->number); 404 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 405 406 dep->stream_capable = false; 407 dep->desc = NULL; 408 dep->type = 0; 409 dep->flags = 0; 410 411 return 0; 412} 413 414/* -------------------------------------------------------------------------- */ 415 416static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 417 const struct usb_endpoint_descriptor *desc) 418{ 419 return -EINVAL; 420} 421 422static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 423{ 424 return -EINVAL; 425} 426 427/* -------------------------------------------------------------------------- */ 428 429static int dwc3_gadget_ep_enable(struct usb_ep *ep, 430 const struct usb_endpoint_descriptor *desc) 431{ 432 struct dwc3_ep *dep; 433 struct dwc3 *dwc; 434 unsigned long flags; 435 int ret; 436 437 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 438 pr_debug("dwc3: invalid parameters\n"); 439 return -EINVAL; 440 } 441 442 if (!desc->wMaxPacketSize) { 443 pr_debug("dwc3: missing wMaxPacketSize\n"); 444 return -EINVAL; 445 } 446 447 dep = to_dwc3_ep(ep); 448 dwc = dep->dwc; 449 450 switch (usb_endpoint_type(desc)) { 451 case USB_ENDPOINT_XFER_CONTROL: 452 strncat(dep->name, "-control", sizeof(dep->name)); 453 break; 454 case USB_ENDPOINT_XFER_ISOC: 455 strncat(dep->name, "-isoc", sizeof(dep->name)); 456 break; 457 case USB_ENDPOINT_XFER_BULK: 458 strncat(dep->name, "-bulk", sizeof(dep->name)); 459 break; 460 case USB_ENDPOINT_XFER_INT: 461 strncat(dep->name, "-int", sizeof(dep->name)); 462 break; 463 default: 464 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 465 } 466 467 if (dep->flags & DWC3_EP_ENABLED) { 468 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 469 dep->name); 470 return 0; 471 } 472 473 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 474 475 spin_lock_irqsave(&dwc->lock, flags); 476 ret = __dwc3_gadget_ep_enable(dep, desc); 477 spin_unlock_irqrestore(&dwc->lock, flags); 478 479 return ret; 480} 481 482static int dwc3_gadget_ep_disable(struct usb_ep *ep) 483{ 484 struct dwc3_ep *dep; 485 struct dwc3 *dwc; 486 unsigned long flags; 487 int ret; 488 489 if (!ep) { 490 pr_debug("dwc3: invalid parameters\n"); 491 return -EINVAL; 492 } 493 494 dep = to_dwc3_ep(ep); 495 dwc = dep->dwc; 496 497 if (!(dep->flags & DWC3_EP_ENABLED)) { 498 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 499 dep->name); 500 return 0; 501 } 502 503 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 504 dep->number >> 1, 505 (dep->number & 1) ? "in" : "out"); 506 507 spin_lock_irqsave(&dwc->lock, flags); 508 ret = __dwc3_gadget_ep_disable(dep); 509 spin_unlock_irqrestore(&dwc->lock, flags); 510 511 return ret; 512} 513 514static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 515 gfp_t gfp_flags) 516{ 517 struct dwc3_request *req; 518 struct dwc3_ep *dep = to_dwc3_ep(ep); 519 struct dwc3 *dwc = dep->dwc; 520 521 req = kzalloc(sizeof(*req), gfp_flags); 522 if (!req) { 523 dev_err(dwc->dev, "not enough memory\n"); 524 return NULL; 525 } 526 527 req->epnum = dep->number; 528 req->dep = dep; 529 req->request.dma = DMA_ADDR_INVALID; 530 531 return &req->request; 532} 533 534static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 535 struct usb_request *request) 536{ 537 struct dwc3_request *req = to_dwc3_request(request); 538 539 kfree(req); 540} 541 542/* 543 * dwc3_prepare_trbs - setup TRBs from requests 544 * @dep: endpoint for which requests are being prepared 545 * @starting: true if the endpoint is idle and no requests are queued. 546 * 547 * The functions goes through the requests list and setups TRBs for the 548 * transfers. The functions returns once there are not more TRBs available or 549 * it run out of requests. 550 */ 551static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep, 552 bool starting) 553{ 554 struct dwc3_request *req, *n, *ret = NULL; 555 struct dwc3_trb_hw *trb_hw; 556 struct dwc3_trb trb; 557 u32 trbs_left; 558 559 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 560 561 /* the first request must not be queued */ 562 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 563 /* 564 * if busy & slot are equal than it is either full or empty. If we are 565 * starting to proceed requests then we are empty. Otherwise we ar 566 * full and don't do anything 567 */ 568 if (!trbs_left) { 569 if (!starting) 570 return NULL; 571 trbs_left = DWC3_TRB_NUM; 572 /* 573 * In case we start from scratch, we queue the ISOC requests 574 * starting from slot 1. This is done because we use ring 575 * buffer and have no LST bit to stop us. Instead, we place 576 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt 577 * after the first request so we start at slot 1 and have 578 * 7 requests proceed before we hit the first IOC. 579 * Other transfer types don't use the ring buffer and are 580 * processed from the first TRB until the last one. Since we 581 * don't wrap around we have to start at the beginning. 582 */ 583 if (usb_endpoint_xfer_isoc(dep->desc)) { 584 dep->busy_slot = 1; 585 dep->free_slot = 1; 586 } else { 587 dep->busy_slot = 0; 588 dep->free_slot = 0; 589 } 590 } 591 592 /* The last TRB is a link TRB, not used for xfer */ 593 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc)) 594 return NULL; 595 596 list_for_each_entry_safe(req, n, &dep->request_list, list) { 597 unsigned int last_one = 0; 598 unsigned int cur_slot; 599 600 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 601 cur_slot = dep->free_slot; 602 dep->free_slot++; 603 604 /* Skip the LINK-TRB on ISOC */ 605 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 606 usb_endpoint_xfer_isoc(dep->desc)) 607 continue; 608 609 dwc3_gadget_move_request_queued(req); 610 memset(&trb, 0, sizeof(trb)); 611 trbs_left--; 612 613 /* Is our TRB pool empty? */ 614 if (!trbs_left) 615 last_one = 1; 616 /* Is this the last request? */ 617 if (list_empty(&dep->request_list)) 618 last_one = 1; 619 620 /* 621 * FIXME we shouldn't need to set LST bit always but we are 622 * facing some weird problem with the Hardware where it doesn't 623 * complete even though it has been previously started. 624 * 625 * While we're debugging the problem, as a workaround to 626 * multiple TRBs handling, use only one TRB at a time. 627 */ 628 last_one = 1; 629 630 req->trb = trb_hw; 631 if (!ret) 632 ret = req; 633 634 trb.bplh = req->request.dma; 635 636 if (usb_endpoint_xfer_isoc(dep->desc)) { 637 trb.isp_imi = true; 638 trb.csp = true; 639 } else { 640 trb.lst = last_one; 641 } 642 643 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable) 644 trb.sid_sofn = req->request.stream_id; 645 646 switch (usb_endpoint_type(dep->desc)) { 647 case USB_ENDPOINT_XFER_CONTROL: 648 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP; 649 break; 650 651 case USB_ENDPOINT_XFER_ISOC: 652 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 653 654 /* IOC every DWC3_TRB_NUM / 4 so we can refill */ 655 if (!(cur_slot % (DWC3_TRB_NUM / 4))) 656 trb.ioc = last_one; 657 break; 658 659 case USB_ENDPOINT_XFER_BULK: 660 case USB_ENDPOINT_XFER_INT: 661 trb.trbctl = DWC3_TRBCTL_NORMAL; 662 break; 663 default: 664 /* 665 * This is only possible with faulty memory because we 666 * checked it already :) 667 */ 668 BUG(); 669 } 670 671 trb.length = req->request.length; 672 trb.hwo = true; 673 674 dwc3_trb_to_hw(&trb, trb_hw); 675 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw); 676 677 if (last_one) 678 break; 679 } 680 681 return ret; 682} 683 684static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 685 int start_new) 686{ 687 struct dwc3_gadget_ep_cmd_params params; 688 struct dwc3_request *req; 689 struct dwc3 *dwc = dep->dwc; 690 int ret; 691 u32 cmd; 692 693 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 694 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 695 return -EBUSY; 696 } 697 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 698 699 /* 700 * If we are getting here after a short-out-packet we don't enqueue any 701 * new requests as we try to set the IOC bit only on the last request. 702 */ 703 if (start_new) { 704 if (list_empty(&dep->req_queued)) 705 dwc3_prepare_trbs(dep, start_new); 706 707 /* req points to the first request which will be sent */ 708 req = next_request(&dep->req_queued); 709 } else { 710 /* 711 * req points to the first request where HWO changed 712 * from 0 to 1 713 */ 714 req = dwc3_prepare_trbs(dep, start_new); 715 } 716 if (!req) { 717 dep->flags |= DWC3_EP_PENDING_REQUEST; 718 return 0; 719 } 720 721 memset(¶ms, 0, sizeof(params)); 722 params.param0 = upper_32_bits(req->trb_dma); 723 params.param1 = lower_32_bits(req->trb_dma); 724 725 if (start_new) 726 cmd = DWC3_DEPCMD_STARTTRANSFER; 727 else 728 cmd = DWC3_DEPCMD_UPDATETRANSFER; 729 730 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 731 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 732 if (ret < 0) { 733 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 734 735 /* 736 * FIXME we need to iterate over the list of requests 737 * here and stop, unmap, free and del each of the linked 738 * requests instead of we do now. 739 */ 740 dwc3_unmap_buffer_from_dma(req); 741 list_del(&req->list); 742 return ret; 743 } 744 745 dep->flags |= DWC3_EP_BUSY; 746 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, 747 dep->number); 748 749 WARN_ON_ONCE(!dep->res_trans_idx); 750 751 return 0; 752} 753 754static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 755{ 756 req->request.actual = 0; 757 req->request.status = -EINPROGRESS; 758 req->direction = dep->direction; 759 req->epnum = dep->number; 760 761 /* 762 * We only add to our list of requests now and 763 * start consuming the list once we get XferNotReady 764 * IRQ. 765 * 766 * That way, we avoid doing anything that we don't need 767 * to do now and defer it until the point we receive a 768 * particular token from the Host side. 769 * 770 * This will also avoid Host cancelling URBs due to too 771 * many NACKs. 772 */ 773 dwc3_map_buffer_to_dma(req); 774 list_add_tail(&req->list, &dep->request_list); 775 776 /* 777 * There is one special case: XferNotReady with 778 * empty list of requests. We need to kick the 779 * transfer here in that situation, otherwise 780 * we will be NAKing forever. 781 * 782 * If we get XferNotReady before gadget driver 783 * has a chance to queue a request, we will ACK 784 * the IRQ but won't be able to receive the data 785 * until the next request is queued. The following 786 * code is handling exactly that. 787 */ 788 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 789 int ret; 790 int start_trans; 791 792 start_trans = 1; 793 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 794 dep->flags & DWC3_EP_BUSY) 795 start_trans = 0; 796 797 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans); 798 if (ret && ret != -EBUSY) { 799 struct dwc3 *dwc = dep->dwc; 800 801 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 802 dep->name); 803 } 804 }; 805 806 return 0; 807} 808 809static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 810 gfp_t gfp_flags) 811{ 812 struct dwc3_request *req = to_dwc3_request(request); 813 struct dwc3_ep *dep = to_dwc3_ep(ep); 814 struct dwc3 *dwc = dep->dwc; 815 816 unsigned long flags; 817 818 int ret; 819 820 if (!dep->desc) { 821 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 822 request, ep->name); 823 return -ESHUTDOWN; 824 } 825 826 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 827 request, ep->name, request->length); 828 829 spin_lock_irqsave(&dwc->lock, flags); 830 ret = __dwc3_gadget_ep_queue(dep, req); 831 spin_unlock_irqrestore(&dwc->lock, flags); 832 833 return ret; 834} 835 836static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 837 struct usb_request *request) 838{ 839 struct dwc3_request *req = to_dwc3_request(request); 840 struct dwc3_request *r = NULL; 841 842 struct dwc3_ep *dep = to_dwc3_ep(ep); 843 struct dwc3 *dwc = dep->dwc; 844 845 unsigned long flags; 846 int ret = 0; 847 848 spin_lock_irqsave(&dwc->lock, flags); 849 850 list_for_each_entry(r, &dep->request_list, list) { 851 if (r == req) 852 break; 853 } 854 855 if (r != req) { 856 list_for_each_entry(r, &dep->req_queued, list) { 857 if (r == req) 858 break; 859 } 860 if (r == req) { 861 /* wait until it is processed */ 862 dwc3_stop_active_transfer(dwc, dep->number); 863 goto out0; 864 } 865 dev_err(dwc->dev, "request %p was not queued to %s\n", 866 request, ep->name); 867 ret = -EINVAL; 868 goto out0; 869 } 870 871 /* giveback the request */ 872 dwc3_gadget_giveback(dep, req, -ECONNRESET); 873 874out0: 875 spin_unlock_irqrestore(&dwc->lock, flags); 876 877 return ret; 878} 879 880int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 881{ 882 struct dwc3_gadget_ep_cmd_params params; 883 struct dwc3 *dwc = dep->dwc; 884 int ret; 885 886 memset(¶ms, 0x00, sizeof(params)); 887 888 if (value) { 889 if (dep->number == 0 || dep->number == 1) { 890 /* 891 * Whenever EP0 is stalled, we will restart 892 * the state machine, thus moving back to 893 * Setup Phase 894 */ 895 dwc->ep0state = EP0_SETUP_PHASE; 896 } 897 898 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 899 DWC3_DEPCMD_SETSTALL, ¶ms); 900 if (ret) 901 dev_err(dwc->dev, "failed to %s STALL on %s\n", 902 value ? "set" : "clear", 903 dep->name); 904 else 905 dep->flags |= DWC3_EP_STALL; 906 } else { 907 if (dep->flags & DWC3_EP_WEDGE) 908 return 0; 909 910 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 911 DWC3_DEPCMD_CLEARSTALL, ¶ms); 912 if (ret) 913 dev_err(dwc->dev, "failed to %s STALL on %s\n", 914 value ? "set" : "clear", 915 dep->name); 916 else 917 dep->flags &= ~DWC3_EP_STALL; 918 } 919 920 return ret; 921} 922 923static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 924{ 925 struct dwc3_ep *dep = to_dwc3_ep(ep); 926 struct dwc3 *dwc = dep->dwc; 927 928 unsigned long flags; 929 930 int ret; 931 932 spin_lock_irqsave(&dwc->lock, flags); 933 934 if (usb_endpoint_xfer_isoc(dep->desc)) { 935 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 936 ret = -EINVAL; 937 goto out; 938 } 939 940 ret = __dwc3_gadget_ep_set_halt(dep, value); 941out: 942 spin_unlock_irqrestore(&dwc->lock, flags); 943 944 return ret; 945} 946 947static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 948{ 949 struct dwc3_ep *dep = to_dwc3_ep(ep); 950 951 dep->flags |= DWC3_EP_WEDGE; 952 953 return dwc3_gadget_ep_set_halt(ep, 1); 954} 955 956/* -------------------------------------------------------------------------- */ 957 958static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 959 .bLength = USB_DT_ENDPOINT_SIZE, 960 .bDescriptorType = USB_DT_ENDPOINT, 961 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 962}; 963 964static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 965 .enable = dwc3_gadget_ep0_enable, 966 .disable = dwc3_gadget_ep0_disable, 967 .alloc_request = dwc3_gadget_ep_alloc_request, 968 .free_request = dwc3_gadget_ep_free_request, 969 .queue = dwc3_gadget_ep0_queue, 970 .dequeue = dwc3_gadget_ep_dequeue, 971 .set_halt = dwc3_gadget_ep_set_halt, 972 .set_wedge = dwc3_gadget_ep_set_wedge, 973}; 974 975static const struct usb_ep_ops dwc3_gadget_ep_ops = { 976 .enable = dwc3_gadget_ep_enable, 977 .disable = dwc3_gadget_ep_disable, 978 .alloc_request = dwc3_gadget_ep_alloc_request, 979 .free_request = dwc3_gadget_ep_free_request, 980 .queue = dwc3_gadget_ep_queue, 981 .dequeue = dwc3_gadget_ep_dequeue, 982 .set_halt = dwc3_gadget_ep_set_halt, 983 .set_wedge = dwc3_gadget_ep_set_wedge, 984}; 985 986/* -------------------------------------------------------------------------- */ 987 988static int dwc3_gadget_get_frame(struct usb_gadget *g) 989{ 990 struct dwc3 *dwc = gadget_to_dwc(g); 991 u32 reg; 992 993 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 994 return DWC3_DSTS_SOFFN(reg); 995} 996 997static int dwc3_gadget_wakeup(struct usb_gadget *g) 998{ 999 struct dwc3 *dwc = gadget_to_dwc(g); 1000 1001 unsigned long timeout; 1002 unsigned long flags; 1003 1004 u32 reg; 1005 1006 int ret = 0; 1007 1008 u8 link_state; 1009 u8 speed; 1010 1011 spin_lock_irqsave(&dwc->lock, flags); 1012 1013 /* 1014 * According to the Databook Remote wakeup request should 1015 * be issued only when the device is in early suspend state. 1016 * 1017 * We can check that via USB Link State bits in DSTS register. 1018 */ 1019 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1020 1021 speed = reg & DWC3_DSTS_CONNECTSPD; 1022 if (speed == DWC3_DSTS_SUPERSPEED) { 1023 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1024 ret = -EINVAL; 1025 goto out; 1026 } 1027 1028 link_state = DWC3_DSTS_USBLNKST(reg); 1029 1030 switch (link_state) { 1031 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1032 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1033 break; 1034 default: 1035 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1036 link_state); 1037 ret = -EINVAL; 1038 goto out; 1039 } 1040 1041 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1042 1043 /* 1044 * Switch link state to Recovery. In HS/FS/LS this means 1045 * RemoteWakeup Request 1046 */ 1047 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY; 1048 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1049 1050 /* wait for at least 2000us */ 1051 usleep_range(2000, 2500); 1052 1053 /* write zeroes to Link Change Request */ 1054 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1055 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1056 1057 /* pool until Link State change to ON */ 1058 timeout = jiffies + msecs_to_jiffies(100); 1059 1060 while (!(time_after(jiffies, timeout))) { 1061 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1062 1063 /* in HS, means ON */ 1064 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1065 break; 1066 } 1067 1068 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1069 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1070 ret = -EINVAL; 1071 } 1072 1073out: 1074 spin_unlock_irqrestore(&dwc->lock, flags); 1075 1076 return ret; 1077} 1078 1079static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1080 int is_selfpowered) 1081{ 1082 struct dwc3 *dwc = gadget_to_dwc(g); 1083 1084 dwc->is_selfpowered = !!is_selfpowered; 1085 1086 return 0; 1087} 1088 1089static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) 1090{ 1091 u32 reg; 1092 u32 timeout = 500; 1093 1094 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1095 if (is_on) 1096 reg |= DWC3_DCTL_RUN_STOP; 1097 else 1098 reg &= ~DWC3_DCTL_RUN_STOP; 1099 1100 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1101 1102 do { 1103 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1104 if (is_on) { 1105 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1106 break; 1107 } else { 1108 if (reg & DWC3_DSTS_DEVCTRLHLT) 1109 break; 1110 } 1111 timeout--; 1112 if (!timeout) 1113 break; 1114 udelay(1); 1115 } while (1); 1116 1117 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1118 dwc->gadget_driver 1119 ? dwc->gadget_driver->function : "no-function", 1120 is_on ? "connect" : "disconnect"); 1121} 1122 1123static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1124{ 1125 struct dwc3 *dwc = gadget_to_dwc(g); 1126 unsigned long flags; 1127 1128 is_on = !!is_on; 1129 1130 spin_lock_irqsave(&dwc->lock, flags); 1131 dwc3_gadget_run_stop(dwc, is_on); 1132 spin_unlock_irqrestore(&dwc->lock, flags); 1133 1134 return 0; 1135} 1136 1137static int dwc3_gadget_start(struct usb_gadget *g, 1138 struct usb_gadget_driver *driver) 1139{ 1140 struct dwc3 *dwc = gadget_to_dwc(g); 1141 struct dwc3_ep *dep; 1142 unsigned long flags; 1143 int ret = 0; 1144 u32 reg; 1145 1146 spin_lock_irqsave(&dwc->lock, flags); 1147 1148 if (dwc->gadget_driver) { 1149 dev_err(dwc->dev, "%s is already bound to %s\n", 1150 dwc->gadget.name, 1151 dwc->gadget_driver->driver.name); 1152 ret = -EBUSY; 1153 goto err0; 1154 } 1155 1156 dwc->gadget_driver = driver; 1157 dwc->gadget.dev.driver = &driver->driver; 1158 1159 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1160 reg &= ~(DWC3_DCFG_SPEED_MASK); 1161 reg |= dwc->maximum_speed; 1162 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1163 1164 dwc->start_config_issued = false; 1165 1166 /* Start with SuperSpeed Default */ 1167 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1168 1169 dep = dwc->eps[0]; 1170 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc); 1171 if (ret) { 1172 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1173 goto err0; 1174 } 1175 1176 dep = dwc->eps[1]; 1177 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc); 1178 if (ret) { 1179 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1180 goto err1; 1181 } 1182 1183 /* begin to receive SETUP packets */ 1184 dwc->ep0state = EP0_SETUP_PHASE; 1185 dwc3_ep0_out_start(dwc); 1186 1187 spin_unlock_irqrestore(&dwc->lock, flags); 1188 1189 return 0; 1190 1191err1: 1192 __dwc3_gadget_ep_disable(dwc->eps[0]); 1193 1194err0: 1195 spin_unlock_irqrestore(&dwc->lock, flags); 1196 1197 return ret; 1198} 1199 1200static int dwc3_gadget_stop(struct usb_gadget *g, 1201 struct usb_gadget_driver *driver) 1202{ 1203 struct dwc3 *dwc = gadget_to_dwc(g); 1204 unsigned long flags; 1205 1206 spin_lock_irqsave(&dwc->lock, flags); 1207 1208 __dwc3_gadget_ep_disable(dwc->eps[0]); 1209 __dwc3_gadget_ep_disable(dwc->eps[1]); 1210 1211 dwc->gadget_driver = NULL; 1212 dwc->gadget.dev.driver = NULL; 1213 1214 spin_unlock_irqrestore(&dwc->lock, flags); 1215 1216 return 0; 1217} 1218static const struct usb_gadget_ops dwc3_gadget_ops = { 1219 .get_frame = dwc3_gadget_get_frame, 1220 .wakeup = dwc3_gadget_wakeup, 1221 .set_selfpowered = dwc3_gadget_set_selfpowered, 1222 .pullup = dwc3_gadget_pullup, 1223 .udc_start = dwc3_gadget_start, 1224 .udc_stop = dwc3_gadget_stop, 1225}; 1226 1227/* -------------------------------------------------------------------------- */ 1228 1229static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1230{ 1231 struct dwc3_ep *dep; 1232 u8 epnum; 1233 1234 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1235 1236 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1237 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1238 if (!dep) { 1239 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1240 epnum); 1241 return -ENOMEM; 1242 } 1243 1244 dep->dwc = dwc; 1245 dep->number = epnum; 1246 dwc->eps[epnum] = dep; 1247 1248 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1249 (epnum & 1) ? "in" : "out"); 1250 dep->endpoint.name = dep->name; 1251 dep->direction = (epnum & 1); 1252 1253 if (epnum == 0 || epnum == 1) { 1254 dep->endpoint.maxpacket = 512; 1255 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1256 if (!epnum) 1257 dwc->gadget.ep0 = &dep->endpoint; 1258 } else { 1259 int ret; 1260 1261 dep->endpoint.maxpacket = 1024; 1262 dep->endpoint.max_streams = 15; 1263 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1264 list_add_tail(&dep->endpoint.ep_list, 1265 &dwc->gadget.ep_list); 1266 1267 ret = dwc3_alloc_trb_pool(dep); 1268 if (ret) 1269 return ret; 1270 } 1271 1272 INIT_LIST_HEAD(&dep->request_list); 1273 INIT_LIST_HEAD(&dep->req_queued); 1274 } 1275 1276 return 0; 1277} 1278 1279static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1280{ 1281 struct dwc3_ep *dep; 1282 u8 epnum; 1283 1284 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1285 dep = dwc->eps[epnum]; 1286 dwc3_free_trb_pool(dep); 1287 1288 if (epnum != 0 && epnum != 1) 1289 list_del(&dep->endpoint.ep_list); 1290 1291 kfree(dep); 1292 } 1293} 1294 1295static void dwc3_gadget_release(struct device *dev) 1296{ 1297 dev_dbg(dev, "%s\n", __func__); 1298} 1299 1300/* -------------------------------------------------------------------------- */ 1301static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1302 const struct dwc3_event_depevt *event, int status) 1303{ 1304 struct dwc3_request *req; 1305 struct dwc3_trb trb; 1306 unsigned int count; 1307 unsigned int s_pkt = 0; 1308 1309 do { 1310 req = next_request(&dep->req_queued); 1311 if (!req) { 1312 WARN_ON_ONCE(1); 1313 return 1; 1314 } 1315 1316 dwc3_trb_to_nat(req->trb, &trb); 1317 1318 if (trb.hwo && status != -ESHUTDOWN) 1319 /* 1320 * We continue despite the error. There is not much we 1321 * can do. If we don't clean in up we loop for ever. If 1322 * we skip the TRB than it gets overwritten reused after 1323 * a while since we use them in a ring buffer. a BUG() 1324 * would help. Lets hope that if this occures, someone 1325 * fixes the root cause instead of looking away :) 1326 */ 1327 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1328 dep->name, req->trb); 1329 count = trb.length; 1330 1331 if (dep->direction) { 1332 if (count) { 1333 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1334 dep->name); 1335 status = -ECONNRESET; 1336 } 1337 } else { 1338 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1339 s_pkt = 1; 1340 } 1341 1342 /* 1343 * We assume here we will always receive the entire data block 1344 * which we should receive. Meaning, if we program RX to 1345 * receive 4K but we receive only 2K, we assume that's all we 1346 * should receive and we simply bounce the request back to the 1347 * gadget driver for further processing. 1348 */ 1349 req->request.actual += req->request.length - count; 1350 dwc3_gadget_giveback(dep, req, status); 1351 if (s_pkt) 1352 break; 1353 if ((event->status & DEPEVT_STATUS_LST) && trb.lst) 1354 break; 1355 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc) 1356 break; 1357 } while (1); 1358 1359 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc) 1360 return 0; 1361 return 1; 1362} 1363 1364static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1365 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1366 int start_new) 1367{ 1368 unsigned status = 0; 1369 int clean_busy; 1370 1371 if (event->status & DEPEVT_STATUS_BUSERR) 1372 status = -ECONNRESET; 1373 1374 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1375 if (clean_busy) { 1376 dep->flags &= ~DWC3_EP_BUSY; 1377 dep->res_trans_idx = 0; 1378 } 1379 1380 /* 1381 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1382 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1383 */ 1384 if (dwc->revision < DWC3_REVISION_183A) { 1385 u32 reg; 1386 int i; 1387 1388 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1389 struct dwc3_ep *dep = dwc->eps[i]; 1390 1391 if (!(dep->flags & DWC3_EP_ENABLED)) 1392 continue; 1393 1394 if (!list_empty(&dep->req_queued)) 1395 return; 1396 } 1397 1398 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1399 reg |= dwc->u1u2; 1400 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1401 1402 dwc->u1u2 = 0; 1403 } 1404} 1405 1406static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1407 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1408{ 1409 u32 uf; 1410 1411 if (list_empty(&dep->request_list)) { 1412 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1413 dep->name); 1414 return; 1415 } 1416 1417 if (event->parameters) { 1418 u32 mask; 1419 1420 mask = ~(dep->interval - 1); 1421 uf = event->parameters & mask; 1422 /* 4 micro frames in the future */ 1423 uf += dep->interval * 4; 1424 } else { 1425 uf = 0; 1426 } 1427 1428 __dwc3_gadget_kick_transfer(dep, uf, 1); 1429} 1430 1431static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep, 1432 const struct dwc3_event_depevt *event) 1433{ 1434 struct dwc3 *dwc = dep->dwc; 1435 struct dwc3_event_depevt mod_ev = *event; 1436 1437 /* 1438 * We were asked to remove one requests. It is possible that this 1439 * request and a few other were started together and have the same 1440 * transfer index. Since we stopped the complete endpoint we don't 1441 * know how many requests were already completed (and not yet) 1442 * reported and how could be done (later). We purge them all until 1443 * the end of the list. 1444 */ 1445 mod_ev.status = DEPEVT_STATUS_LST; 1446 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN); 1447 dep->flags &= ~DWC3_EP_BUSY; 1448 /* pending requets are ignored and are queued on XferNotReady */ 1449} 1450 1451static void dwc3_ep_cmd_compl(struct dwc3_ep *dep, 1452 const struct dwc3_event_depevt *event) 1453{ 1454 u32 param = event->parameters; 1455 u32 cmd_type = (param >> 8) & ((1 << 5) - 1); 1456 1457 switch (cmd_type) { 1458 case DWC3_DEPCMD_ENDTRANSFER: 1459 dwc3_process_ep_cmd_complete(dep, event); 1460 break; 1461 case DWC3_DEPCMD_STARTTRANSFER: 1462 dep->res_trans_idx = param & 0x7f; 1463 break; 1464 default: 1465 printk(KERN_ERR "%s() unknown /unexpected type: %d\n", 1466 __func__, cmd_type); 1467 break; 1468 }; 1469} 1470 1471static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1472 const struct dwc3_event_depevt *event) 1473{ 1474 struct dwc3_ep *dep; 1475 u8 epnum = event->endpoint_number; 1476 1477 dep = dwc->eps[epnum]; 1478 1479 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1480 dwc3_ep_event_string(event->endpoint_event)); 1481 1482 if (epnum == 0 || epnum == 1) { 1483 dwc3_ep0_interrupt(dwc, event); 1484 return; 1485 } 1486 1487 switch (event->endpoint_event) { 1488 case DWC3_DEPEVT_XFERCOMPLETE: 1489 if (usb_endpoint_xfer_isoc(dep->desc)) { 1490 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1491 dep->name); 1492 return; 1493 } 1494 1495 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1496 break; 1497 case DWC3_DEPEVT_XFERINPROGRESS: 1498 if (!usb_endpoint_xfer_isoc(dep->desc)) { 1499 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1500 dep->name); 1501 return; 1502 } 1503 1504 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1505 break; 1506 case DWC3_DEPEVT_XFERNOTREADY: 1507 if (usb_endpoint_xfer_isoc(dep->desc)) { 1508 dwc3_gadget_start_isoc(dwc, dep, event); 1509 } else { 1510 int ret; 1511 1512 dev_vdbg(dwc->dev, "%s: reason %s\n", 1513 dep->name, event->status 1514 ? "Transfer Active" 1515 : "Transfer Not Active"); 1516 1517 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1518 if (!ret || ret == -EBUSY) 1519 return; 1520 1521 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1522 dep->name); 1523 } 1524 1525 break; 1526 case DWC3_DEPEVT_STREAMEVT: 1527 if (!usb_endpoint_xfer_bulk(dep->desc)) { 1528 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1529 dep->name); 1530 return; 1531 } 1532 1533 switch (event->status) { 1534 case DEPEVT_STREAMEVT_FOUND: 1535 dev_vdbg(dwc->dev, "Stream %d found and started\n", 1536 event->parameters); 1537 1538 break; 1539 case DEPEVT_STREAMEVT_NOTFOUND: 1540 /* FALLTHROUGH */ 1541 default: 1542 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 1543 } 1544 break; 1545 case DWC3_DEPEVT_RXTXFIFOEVT: 1546 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 1547 break; 1548 case DWC3_DEPEVT_EPCMDCMPLT: 1549 dwc3_ep_cmd_compl(dep, event); 1550 break; 1551 } 1552} 1553 1554static void dwc3_disconnect_gadget(struct dwc3 *dwc) 1555{ 1556 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 1557 spin_unlock(&dwc->lock); 1558 dwc->gadget_driver->disconnect(&dwc->gadget); 1559 spin_lock(&dwc->lock); 1560 } 1561} 1562 1563static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) 1564{ 1565 struct dwc3_ep *dep; 1566 struct dwc3_gadget_ep_cmd_params params; 1567 u32 cmd; 1568 int ret; 1569 1570 dep = dwc->eps[epnum]; 1571 1572 WARN_ON(!dep->res_trans_idx); 1573 if (dep->res_trans_idx) { 1574 cmd = DWC3_DEPCMD_ENDTRANSFER; 1575 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; 1576 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx); 1577 memset(¶ms, 0, sizeof(params)); 1578 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1579 WARN_ON_ONCE(ret); 1580 dep->res_trans_idx = 0; 1581 } 1582} 1583 1584static void dwc3_stop_active_transfers(struct dwc3 *dwc) 1585{ 1586 u32 epnum; 1587 1588 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1589 struct dwc3_ep *dep; 1590 1591 dep = dwc->eps[epnum]; 1592 if (!(dep->flags & DWC3_EP_ENABLED)) 1593 continue; 1594 1595 dwc3_remove_requests(dwc, dep); 1596 } 1597} 1598 1599static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 1600{ 1601 u32 epnum; 1602 1603 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1604 struct dwc3_ep *dep; 1605 struct dwc3_gadget_ep_cmd_params params; 1606 int ret; 1607 1608 dep = dwc->eps[epnum]; 1609 1610 if (!(dep->flags & DWC3_EP_STALL)) 1611 continue; 1612 1613 dep->flags &= ~DWC3_EP_STALL; 1614 1615 memset(¶ms, 0, sizeof(params)); 1616 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1617 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1618 WARN_ON_ONCE(ret); 1619 } 1620} 1621 1622static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 1623{ 1624 dev_vdbg(dwc->dev, "%s\n", __func__); 1625#if 0 1626 XXX 1627 U1/U2 is powersave optimization. Skip it for now. Anyway we need to 1628 enable it before we can disable it. 1629 1630 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1631 reg &= ~DWC3_DCTL_INITU1ENA; 1632 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1633 1634 reg &= ~DWC3_DCTL_INITU2ENA; 1635 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1636#endif 1637 1638 dwc3_stop_active_transfers(dwc); 1639 dwc3_disconnect_gadget(dwc); 1640 dwc->start_config_issued = false; 1641 1642 dwc->gadget.speed = USB_SPEED_UNKNOWN; 1643 dwc->setup_packet_pending = false; 1644} 1645 1646static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on) 1647{ 1648 u32 reg; 1649 1650 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1651 1652 if (on) 1653 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 1654 else 1655 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1656 1657 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1658} 1659 1660static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on) 1661{ 1662 u32 reg; 1663 1664 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1665 1666 if (on) 1667 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1668 else 1669 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1670 1671 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1672} 1673 1674static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 1675{ 1676 u32 reg; 1677 1678 dev_vdbg(dwc->dev, "%s\n", __func__); 1679 1680 /* 1681 * WORKAROUND: DWC3 revisions <1.88a have an issue which 1682 * would cause a missing Disconnect Event if there's a 1683 * pending Setup Packet in the FIFO. 1684 * 1685 * There's no suggested workaround on the official Bug 1686 * report, which states that "unless the driver/application 1687 * is doing any special handling of a disconnect event, 1688 * there is no functional issue". 1689 * 1690 * Unfortunately, it turns out that we _do_ some special 1691 * handling of a disconnect event, namely complete all 1692 * pending transfers, notify gadget driver of the 1693 * disconnection, and so on. 1694 * 1695 * Our suggested workaround is to follow the Disconnect 1696 * Event steps here, instead, based on a setup_packet_pending 1697 * flag. Such flag gets set whenever we have a XferNotReady 1698 * event on EP0 and gets cleared on XferComplete for the 1699 * same endpoint. 1700 * 1701 * Refers to: 1702 * 1703 * STAR#9000466709: RTL: Device : Disconnect event not 1704 * generated if setup packet pending in FIFO 1705 */ 1706 if (dwc->revision < DWC3_REVISION_188A) { 1707 if (dwc->setup_packet_pending) 1708 dwc3_gadget_disconnect_interrupt(dwc); 1709 } 1710 1711 /* Enable PHYs */ 1712 dwc3_gadget_usb2_phy_power(dwc, true); 1713 dwc3_gadget_usb3_phy_power(dwc, true); 1714 1715 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 1716 dwc3_disconnect_gadget(dwc); 1717 1718 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1719 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 1720 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1721 1722 dwc3_stop_active_transfers(dwc); 1723 dwc3_clear_stall_all_ep(dwc); 1724 dwc->start_config_issued = false; 1725 1726 /* Reset device address to zero */ 1727 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1728 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 1729 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1730} 1731 1732static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 1733{ 1734 u32 reg; 1735 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 1736 1737 /* 1738 * We change the clock only at SS but I dunno why I would want to do 1739 * this. Maybe it becomes part of the power saving plan. 1740 */ 1741 1742 if (speed != DWC3_DSTS_SUPERSPEED) 1743 return; 1744 1745 /* 1746 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 1747 * each time on Connect Done. 1748 */ 1749 if (!usb30_clock) 1750 return; 1751 1752 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1753 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 1754 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 1755} 1756 1757static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed) 1758{ 1759 switch (speed) { 1760 case USB_SPEED_SUPER: 1761 dwc3_gadget_usb2_phy_power(dwc, false); 1762 break; 1763 case USB_SPEED_HIGH: 1764 case USB_SPEED_FULL: 1765 case USB_SPEED_LOW: 1766 dwc3_gadget_usb3_phy_power(dwc, false); 1767 break; 1768 } 1769} 1770 1771static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 1772{ 1773 struct dwc3_gadget_ep_cmd_params params; 1774 struct dwc3_ep *dep; 1775 int ret; 1776 u32 reg; 1777 u8 speed; 1778 1779 dev_vdbg(dwc->dev, "%s\n", __func__); 1780 1781 memset(¶ms, 0x00, sizeof(params)); 1782 1783 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1784 speed = reg & DWC3_DSTS_CONNECTSPD; 1785 dwc->speed = speed; 1786 1787 dwc3_update_ram_clk_sel(dwc, speed); 1788 1789 switch (speed) { 1790 case DWC3_DCFG_SUPERSPEED: 1791 /* 1792 * WORKAROUND: DWC3 revisions <1.90a have an issue which 1793 * would cause a missing USB3 Reset event. 1794 * 1795 * In such situations, we should force a USB3 Reset 1796 * event by calling our dwc3_gadget_reset_interrupt() 1797 * routine. 1798 * 1799 * Refers to: 1800 * 1801 * STAR#9000483510: RTL: SS : USB3 reset event may 1802 * not be generated always when the link enters poll 1803 */ 1804 if (dwc->revision < DWC3_REVISION_190A) 1805 dwc3_gadget_reset_interrupt(dwc); 1806 1807 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1808 dwc->gadget.ep0->maxpacket = 512; 1809 dwc->gadget.speed = USB_SPEED_SUPER; 1810 break; 1811 case DWC3_DCFG_HIGHSPEED: 1812 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 1813 dwc->gadget.ep0->maxpacket = 64; 1814 dwc->gadget.speed = USB_SPEED_HIGH; 1815 break; 1816 case DWC3_DCFG_FULLSPEED2: 1817 case DWC3_DCFG_FULLSPEED1: 1818 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 1819 dwc->gadget.ep0->maxpacket = 64; 1820 dwc->gadget.speed = USB_SPEED_FULL; 1821 break; 1822 case DWC3_DCFG_LOWSPEED: 1823 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 1824 dwc->gadget.ep0->maxpacket = 8; 1825 dwc->gadget.speed = USB_SPEED_LOW; 1826 break; 1827 } 1828 1829 /* Disable unneded PHY */ 1830 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed); 1831 1832 dep = dwc->eps[0]; 1833 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc); 1834 if (ret) { 1835 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1836 return; 1837 } 1838 1839 dep = dwc->eps[1]; 1840 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc); 1841 if (ret) { 1842 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1843 return; 1844 } 1845 1846 /* 1847 * Configure PHY via GUSB3PIPECTLn if required. 1848 * 1849 * Update GTXFIFOSIZn 1850 * 1851 * In both cases reset values should be sufficient. 1852 */ 1853} 1854 1855static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 1856{ 1857 dev_vdbg(dwc->dev, "%s\n", __func__); 1858 1859 /* 1860 * TODO take core out of low power mode when that's 1861 * implemented. 1862 */ 1863 1864 dwc->gadget_driver->resume(&dwc->gadget); 1865} 1866 1867static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 1868 unsigned int evtinfo) 1869{ 1870 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 1871 1872 /* 1873 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 1874 * on the link partner, the USB session might do multiple entry/exit 1875 * of low power states before a transfer takes place. 1876 * 1877 * Due to this problem, we might experience lower throughput. The 1878 * suggested workaround is to disable DCTL[12:9] bits if we're 1879 * transitioning from U1/U2 to U0 and enable those bits again 1880 * after a transfer completes and there are no pending transfers 1881 * on any of the enabled endpoints. 1882 * 1883 * This is the first half of that workaround. 1884 * 1885 * Refers to: 1886 * 1887 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 1888 * core send LGO_Ux entering U0 1889 */ 1890 if (dwc->revision < DWC3_REVISION_183A) { 1891 if (next == DWC3_LINK_STATE_U0) { 1892 u32 u1u2; 1893 u32 reg; 1894 1895 switch (dwc->link_state) { 1896 case DWC3_LINK_STATE_U1: 1897 case DWC3_LINK_STATE_U2: 1898 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1899 u1u2 = reg & (DWC3_DCTL_INITU2ENA 1900 | DWC3_DCTL_ACCEPTU2ENA 1901 | DWC3_DCTL_INITU1ENA 1902 | DWC3_DCTL_ACCEPTU1ENA); 1903 1904 if (!dwc->u1u2) 1905 dwc->u1u2 = reg & u1u2; 1906 1907 reg &= ~u1u2; 1908 1909 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1910 break; 1911 default: 1912 /* do nothing */ 1913 break; 1914 } 1915 } 1916 } 1917 1918 dwc->link_state = next; 1919 1920 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 1921} 1922 1923static void dwc3_gadget_interrupt(struct dwc3 *dwc, 1924 const struct dwc3_event_devt *event) 1925{ 1926 switch (event->type) { 1927 case DWC3_DEVICE_EVENT_DISCONNECT: 1928 dwc3_gadget_disconnect_interrupt(dwc); 1929 break; 1930 case DWC3_DEVICE_EVENT_RESET: 1931 dwc3_gadget_reset_interrupt(dwc); 1932 break; 1933 case DWC3_DEVICE_EVENT_CONNECT_DONE: 1934 dwc3_gadget_conndone_interrupt(dwc); 1935 break; 1936 case DWC3_DEVICE_EVENT_WAKEUP: 1937 dwc3_gadget_wakeup_interrupt(dwc); 1938 break; 1939 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 1940 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 1941 break; 1942 case DWC3_DEVICE_EVENT_EOPF: 1943 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 1944 break; 1945 case DWC3_DEVICE_EVENT_SOF: 1946 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 1947 break; 1948 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 1949 dev_vdbg(dwc->dev, "Erratic Error\n"); 1950 break; 1951 case DWC3_DEVICE_EVENT_CMD_CMPL: 1952 dev_vdbg(dwc->dev, "Command Complete\n"); 1953 break; 1954 case DWC3_DEVICE_EVENT_OVERFLOW: 1955 dev_vdbg(dwc->dev, "Overflow\n"); 1956 break; 1957 default: 1958 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 1959 } 1960} 1961 1962static void dwc3_process_event_entry(struct dwc3 *dwc, 1963 const union dwc3_event *event) 1964{ 1965 /* Endpoint IRQ, handle it and return early */ 1966 if (event->type.is_devspec == 0) { 1967 /* depevt */ 1968 return dwc3_endpoint_interrupt(dwc, &event->depevt); 1969 } 1970 1971 switch (event->type.type) { 1972 case DWC3_EVENT_TYPE_DEV: 1973 dwc3_gadget_interrupt(dwc, &event->devt); 1974 break; 1975 /* REVISIT what to do with Carkit and I2C events ? */ 1976 default: 1977 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 1978 } 1979} 1980 1981static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 1982{ 1983 struct dwc3_event_buffer *evt; 1984 int left; 1985 u32 count; 1986 1987 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 1988 count &= DWC3_GEVNTCOUNT_MASK; 1989 if (!count) 1990 return IRQ_NONE; 1991 1992 evt = dwc->ev_buffs[buf]; 1993 left = count; 1994 1995 while (left > 0) { 1996 union dwc3_event event; 1997 1998 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw)); 1999 dwc3_process_event_entry(dwc, &event); 2000 /* 2001 * XXX we wrap around correctly to the next entry as almost all 2002 * entries are 4 bytes in size. There is one entry which has 12 2003 * bytes which is a regular entry followed by 8 bytes data. ATM 2004 * I don't know how things are organized if were get next to the 2005 * a boundary so I worry about that once we try to handle that. 2006 */ 2007 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2008 left -= 4; 2009 2010 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2011 } 2012 2013 return IRQ_HANDLED; 2014} 2015 2016static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2017{ 2018 struct dwc3 *dwc = _dwc; 2019 int i; 2020 irqreturn_t ret = IRQ_NONE; 2021 2022 spin_lock(&dwc->lock); 2023 2024 for (i = 0; i < dwc->num_event_buffers; i++) { 2025 irqreturn_t status; 2026 2027 status = dwc3_process_event_buf(dwc, i); 2028 if (status == IRQ_HANDLED) 2029 ret = status; 2030 } 2031 2032 spin_unlock(&dwc->lock); 2033 2034 return ret; 2035} 2036 2037/** 2038 * dwc3_gadget_init - Initializes gadget related registers 2039 * @dwc: Pointer to out controller context structure 2040 * 2041 * Returns 0 on success otherwise negative errno. 2042 */ 2043int __devinit dwc3_gadget_init(struct dwc3 *dwc) 2044{ 2045 u32 reg; 2046 int ret; 2047 int irq; 2048 2049 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2050 &dwc->ctrl_req_addr, GFP_KERNEL); 2051 if (!dwc->ctrl_req) { 2052 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2053 ret = -ENOMEM; 2054 goto err0; 2055 } 2056 2057 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2058 &dwc->ep0_trb_addr, GFP_KERNEL); 2059 if (!dwc->ep0_trb) { 2060 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2061 ret = -ENOMEM; 2062 goto err1; 2063 } 2064 2065 dwc->setup_buf = dma_alloc_coherent(dwc->dev, 2066 sizeof(*dwc->setup_buf) * 2, 2067 &dwc->setup_buf_addr, GFP_KERNEL); 2068 if (!dwc->setup_buf) { 2069 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2070 ret = -ENOMEM; 2071 goto err2; 2072 } 2073 2074 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2075 512, &dwc->ep0_bounce_addr, GFP_KERNEL); 2076 if (!dwc->ep0_bounce) { 2077 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2078 ret = -ENOMEM; 2079 goto err3; 2080 } 2081 2082 dev_set_name(&dwc->gadget.dev, "gadget"); 2083 2084 dwc->gadget.ops = &dwc3_gadget_ops; 2085 dwc->gadget.is_dualspeed = true; 2086 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2087 dwc->gadget.dev.parent = dwc->dev; 2088 2089 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); 2090 2091 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; 2092 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; 2093 dwc->gadget.dev.release = dwc3_gadget_release; 2094 dwc->gadget.name = "dwc3-gadget"; 2095 2096 /* 2097 * REVISIT: Here we should clear all pending IRQs to be 2098 * sure we're starting from a well known location. 2099 */ 2100 2101 ret = dwc3_gadget_init_endpoints(dwc); 2102 if (ret) 2103 goto err4; 2104 2105 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2106 2107 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, 2108 "dwc3", dwc); 2109 if (ret) { 2110 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 2111 irq, ret); 2112 goto err5; 2113 } 2114 2115 /* Enable all but Start and End of Frame IRQs */ 2116 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 2117 DWC3_DEVTEN_EVNTOVERFLOWEN | 2118 DWC3_DEVTEN_CMDCMPLTEN | 2119 DWC3_DEVTEN_ERRTICERREN | 2120 DWC3_DEVTEN_WKUPEVTEN | 2121 DWC3_DEVTEN_ULSTCNGEN | 2122 DWC3_DEVTEN_CONNECTDONEEN | 2123 DWC3_DEVTEN_USBRSTEN | 2124 DWC3_DEVTEN_DISCONNEVTEN); 2125 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 2126 2127 ret = device_register(&dwc->gadget.dev); 2128 if (ret) { 2129 dev_err(dwc->dev, "failed to register gadget device\n"); 2130 put_device(&dwc->gadget.dev); 2131 goto err6; 2132 } 2133 2134 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2135 if (ret) { 2136 dev_err(dwc->dev, "failed to register udc\n"); 2137 goto err7; 2138 } 2139 2140 return 0; 2141 2142err7: 2143 device_unregister(&dwc->gadget.dev); 2144 2145err6: 2146 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2147 free_irq(irq, dwc); 2148 2149err5: 2150 dwc3_gadget_free_endpoints(dwc); 2151 2152err4: 2153 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce, 2154 dwc->ep0_bounce_addr); 2155 2156err3: 2157 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2, 2158 dwc->setup_buf, dwc->setup_buf_addr); 2159 2160err2: 2161 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2162 dwc->ep0_trb, dwc->ep0_trb_addr); 2163 2164err1: 2165 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2166 dwc->ctrl_req, dwc->ctrl_req_addr); 2167 2168err0: 2169 return ret; 2170} 2171 2172void dwc3_gadget_exit(struct dwc3 *dwc) 2173{ 2174 int irq; 2175 2176 usb_del_gadget_udc(&dwc->gadget); 2177 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2178 2179 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2180 free_irq(irq, dwc); 2181 2182 dwc3_gadget_free_endpoints(dwc); 2183 2184 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce, 2185 dwc->ep0_bounce_addr); 2186 2187 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2, 2188 dwc->setup_buf, dwc->setup_buf_addr); 2189 2190 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2191 dwc->ep0_trb, dwc->ep0_trb_addr); 2192 2193 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2194 dwc->ctrl_req, dwc->ctrl_req_addr); 2195 2196 device_unregister(&dwc->gadget.dev); 2197} 2198