gadget.c revision ea53b8828c50b7a5138a8931c41b2671682c86b5
1/** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#include <linux/kernel.h> 40#include <linux/delay.h> 41#include <linux/slab.h> 42#include <linux/spinlock.h> 43#include <linux/platform_device.h> 44#include <linux/pm_runtime.h> 45#include <linux/interrupt.h> 46#include <linux/io.h> 47#include <linux/list.h> 48#include <linux/dma-mapping.h> 49 50#include <linux/usb/ch9.h> 51#include <linux/usb/gadget.h> 52 53#include "core.h" 54#include "gadget.h" 55#include "io.h" 56 57/** 58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 59 * @dwc: pointer to our context structure 60 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 61 * 62 * Caller should take care of locking. This function will 63 * return 0 on success or -EINVAL if wrong Test Selector 64 * is passed 65 */ 66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 67{ 68 u32 reg; 69 70 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 71 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 72 73 switch (mode) { 74 case TEST_J: 75 case TEST_K: 76 case TEST_SE0_NAK: 77 case TEST_PACKET: 78 case TEST_FORCE_EN: 79 reg |= mode << 1; 80 break; 81 default: 82 return -EINVAL; 83 } 84 85 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 86 87 return 0; 88} 89 90/** 91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 92 * @dwc: pointer to our context structure 93 * @state: the state to put link into 94 * 95 * Caller should take care of locking. This function will 96 * return 0 on success or -ETIMEDOUT. 97 */ 98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 99{ 100 int retries = 10000; 101 u32 reg; 102 103 /* 104 * Wait until device controller is ready. Only applies to 1.94a and 105 * later RTL. 106 */ 107 if (dwc->revision >= DWC3_REVISION_194A) { 108 while (--retries) { 109 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 110 if (reg & DWC3_DSTS_DCNRD) 111 udelay(5); 112 else 113 break; 114 } 115 116 if (retries <= 0) 117 return -ETIMEDOUT; 118 } 119 120 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 122 123 /* set requested state */ 124 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 125 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 126 127 /* 128 * The following code is racy when called from dwc3_gadget_wakeup, 129 * and is not needed, at least on newer versions 130 */ 131 if (dwc->revision >= DWC3_REVISION_194A) 132 return 0; 133 134 /* wait for a change in DSTS */ 135 retries = 10000; 136 while (--retries) { 137 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 138 139 if (DWC3_DSTS_USBLNKST(reg) == state) 140 return 0; 141 142 udelay(5); 143 } 144 145 dev_vdbg(dwc->dev, "link state change request timed out\n"); 146 147 return -ETIMEDOUT; 148} 149 150/** 151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 152 * @dwc: pointer to our context structure 153 * 154 * This function will a best effort FIFO allocation in order 155 * to improve FIFO usage and throughput, while still allowing 156 * us to enable as many endpoints as possible. 157 * 158 * Keep in mind that this operation will be highly dependent 159 * on the configured size for RAM1 - which contains TxFifo -, 160 * the amount of endpoints enabled on coreConsultant tool, and 161 * the width of the Master Bus. 162 * 163 * In the ideal world, we would always be able to satisfy the 164 * following equation: 165 * 166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 168 * 169 * Unfortunately, due to many variables that's not always the case. 170 */ 171int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 172{ 173 int last_fifo_depth = 0; 174 int ram1_depth; 175 int fifo_size; 176 int mdwidth; 177 int num; 178 179 if (!dwc->needs_fifo_resize) 180 return 0; 181 182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 184 185 /* MDWIDTH is represented in bits, we need it in bytes */ 186 mdwidth >>= 3; 187 188 /* 189 * FIXME For now we will only allocate 1 wMaxPacketSize space 190 * for each enabled endpoint, later patches will come to 191 * improve this algorithm so that we better use the internal 192 * FIFO space 193 */ 194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { 195 struct dwc3_ep *dep = dwc->eps[num]; 196 int fifo_number = dep->number >> 1; 197 int mult = 1; 198 int tmp; 199 200 if (!(dep->number & 1)) 201 continue; 202 203 if (!(dep->flags & DWC3_EP_ENABLED)) 204 continue; 205 206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) 207 || usb_endpoint_xfer_isoc(dep->endpoint.desc)) 208 mult = 3; 209 210 /* 211 * REVISIT: the following assumes we will always have enough 212 * space available on the FIFO RAM for all possible use cases. 213 * Make sure that's true somehow and change FIFO allocation 214 * accordingly. 215 * 216 * If we have Bulk or Isochronous endpoints, we want 217 * them to be able to be very, very fast. So we're giving 218 * those endpoints a fifo_size which is enough for 3 full 219 * packets 220 */ 221 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 222 tmp += mdwidth; 223 224 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 225 226 fifo_size |= (last_fifo_depth << 16); 227 228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 229 dep->name, last_fifo_depth, fifo_size & 0xffff); 230 231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), 232 fifo_size); 233 234 last_fifo_depth += (fifo_size & 0xffff); 235 } 236 237 return 0; 238} 239 240void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 241 int status) 242{ 243 struct dwc3 *dwc = dep->dwc; 244 245 if (req->queued) { 246 if (req->request.num_mapped_sgs) 247 dep->busy_slot += req->request.num_mapped_sgs; 248 else 249 dep->busy_slot++; 250 251 /* 252 * Skip LINK TRB. We can't use req->trb and check for 253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just 254 * completed (not the LINK TRB). 255 */ 256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 257 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 258 dep->busy_slot++; 259 } 260 list_del(&req->list); 261 req->trb = NULL; 262 263 if (req->request.status == -EINPROGRESS) 264 req->request.status = status; 265 266 usb_gadget_unmap_request(&dwc->gadget, &req->request, 267 req->direction); 268 269 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 270 req, dep->name, req->request.actual, 271 req->request.length, status); 272 273 spin_unlock(&dwc->lock); 274 req->request.complete(&dep->endpoint, &req->request); 275 spin_lock(&dwc->lock); 276} 277 278static const char *dwc3_gadget_ep_cmd_string(u8 cmd) 279{ 280 switch (cmd) { 281 case DWC3_DEPCMD_DEPSTARTCFG: 282 return "Start New Configuration"; 283 case DWC3_DEPCMD_ENDTRANSFER: 284 return "End Transfer"; 285 case DWC3_DEPCMD_UPDATETRANSFER: 286 return "Update Transfer"; 287 case DWC3_DEPCMD_STARTTRANSFER: 288 return "Start Transfer"; 289 case DWC3_DEPCMD_CLEARSTALL: 290 return "Clear Stall"; 291 case DWC3_DEPCMD_SETSTALL: 292 return "Set Stall"; 293 case DWC3_DEPCMD_GETEPSTATE: 294 return "Get Endpoint State"; 295 case DWC3_DEPCMD_SETTRANSFRESOURCE: 296 return "Set Endpoint Transfer Resource"; 297 case DWC3_DEPCMD_SETEPCONFIG: 298 return "Set Endpoint Configuration"; 299 default: 300 return "UNKNOWN command"; 301 } 302} 303 304int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) 305{ 306 u32 timeout = 500; 307 u32 reg; 308 309 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 310 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 311 312 do { 313 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 314 if (!(reg & DWC3_DGCMD_CMDACT)) { 315 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 316 DWC3_DGCMD_STATUS(reg)); 317 return 0; 318 } 319 320 /* 321 * We can't sleep here, because it's also called from 322 * interrupt context. 323 */ 324 timeout--; 325 if (!timeout) 326 return -ETIMEDOUT; 327 udelay(1); 328 } while (1); 329} 330 331int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 332 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 333{ 334 struct dwc3_ep *dep = dwc->eps[ep]; 335 u32 timeout = 500; 336 u32 reg; 337 338 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", 339 dep->name, 340 dwc3_gadget_ep_cmd_string(cmd), params->param0, 341 params->param1, params->param2); 342 343 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 346 347 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 348 do { 349 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 350 if (!(reg & DWC3_DEPCMD_CMDACT)) { 351 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 352 DWC3_DEPCMD_STATUS(reg)); 353 return 0; 354 } 355 356 /* 357 * We can't sleep here, because it is also called from 358 * interrupt context. 359 */ 360 timeout--; 361 if (!timeout) 362 return -ETIMEDOUT; 363 364 udelay(1); 365 } while (1); 366} 367 368static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 369 struct dwc3_trb *trb) 370{ 371 u32 offset = (char *) trb - (char *) dep->trb_pool; 372 373 return dep->trb_pool_dma + offset; 374} 375 376static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 377{ 378 struct dwc3 *dwc = dep->dwc; 379 380 if (dep->trb_pool) 381 return 0; 382 383 if (dep->number == 0 || dep->number == 1) 384 return 0; 385 386 dep->trb_pool = dma_alloc_coherent(dwc->dev, 387 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 388 &dep->trb_pool_dma, GFP_KERNEL); 389 if (!dep->trb_pool) { 390 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 391 dep->name); 392 return -ENOMEM; 393 } 394 395 return 0; 396} 397 398static void dwc3_free_trb_pool(struct dwc3_ep *dep) 399{ 400 struct dwc3 *dwc = dep->dwc; 401 402 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 403 dep->trb_pool, dep->trb_pool_dma); 404 405 dep->trb_pool = NULL; 406 dep->trb_pool_dma = 0; 407} 408 409static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 410{ 411 struct dwc3_gadget_ep_cmd_params params; 412 u32 cmd; 413 414 memset(¶ms, 0x00, sizeof(params)); 415 416 if (dep->number != 1) { 417 cmd = DWC3_DEPCMD_DEPSTARTCFG; 418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 419 if (dep->number > 1) { 420 if (dwc->start_config_issued) 421 return 0; 422 dwc->start_config_issued = true; 423 cmd |= DWC3_DEPCMD_PARAM(2); 424 } 425 426 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 427 } 428 429 return 0; 430} 431 432static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 433 const struct usb_endpoint_descriptor *desc, 434 const struct usb_ss_ep_comp_descriptor *comp_desc) 435{ 436 struct dwc3_gadget_ep_cmd_params params; 437 438 memset(¶ms, 0x00, sizeof(params)); 439 440 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 441 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) 442 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst); 443 444 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 445 | DWC3_DEPCFG_XFER_NOT_READY_EN; 446 447 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 448 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 449 | DWC3_DEPCFG_STREAM_EVENT_EN; 450 dep->stream_capable = true; 451 } 452 453 if (usb_endpoint_xfer_isoc(desc)) 454 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 455 456 /* 457 * We are doing 1:1 mapping for endpoints, meaning 458 * Physical Endpoints 2 maps to Logical Endpoint 2 and 459 * so on. We consider the direction bit as part of the physical 460 * endpoint number. So USB endpoint 0x81 is 0x03. 461 */ 462 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 463 464 /* 465 * We must use the lower 16 TX FIFOs even though 466 * HW might have more 467 */ 468 if (dep->direction) 469 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 470 471 if (desc->bInterval) { 472 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 473 dep->interval = 1 << (desc->bInterval - 1); 474 } 475 476 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 477 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 478} 479 480static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 481{ 482 struct dwc3_gadget_ep_cmd_params params; 483 484 memset(¶ms, 0x00, sizeof(params)); 485 486 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 487 488 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 489 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 490} 491 492/** 493 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 494 * @dep: endpoint to be initialized 495 * @desc: USB Endpoint Descriptor 496 * 497 * Caller should take care of locking 498 */ 499static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 500 const struct usb_endpoint_descriptor *desc, 501 const struct usb_ss_ep_comp_descriptor *comp_desc) 502{ 503 struct dwc3 *dwc = dep->dwc; 504 u32 reg; 505 int ret = -ENOMEM; 506 507 if (!(dep->flags & DWC3_EP_ENABLED)) { 508 ret = dwc3_gadget_start_config(dwc, dep); 509 if (ret) 510 return ret; 511 } 512 513 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc); 514 if (ret) 515 return ret; 516 517 if (!(dep->flags & DWC3_EP_ENABLED)) { 518 struct dwc3_trb *trb_st_hw; 519 struct dwc3_trb *trb_link; 520 521 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 522 if (ret) 523 return ret; 524 525 dep->endpoint.desc = desc; 526 dep->comp_desc = comp_desc; 527 dep->type = usb_endpoint_type(desc); 528 dep->flags |= DWC3_EP_ENABLED; 529 530 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 531 reg |= DWC3_DALEPENA_EP(dep->number); 532 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 533 534 if (!usb_endpoint_xfer_isoc(desc)) 535 return 0; 536 537 memset(&trb_link, 0, sizeof(trb_link)); 538 539 /* Link TRB for ISOC. The HWO bit is never reset */ 540 trb_st_hw = &dep->trb_pool[0]; 541 542 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 543 544 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 545 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 546 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 547 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 548 } 549 550 return 0; 551} 552 553static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); 554static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 555{ 556 struct dwc3_request *req; 557 558 if (!list_empty(&dep->req_queued)) { 559 dwc3_stop_active_transfer(dwc, dep->number); 560 561 /* 562 * NOTICE: We are violating what the Databook says about the 563 * EndTransfer command. Ideally we would _always_ wait for the 564 * EndTransfer Command Completion IRQ, but that's causing too 565 * much trouble synchronizing between us and gadget driver. 566 * 567 * We have discussed this with the IP Provider and it was 568 * suggested to giveback all requests here, but give HW some 569 * extra time to synchronize with the interconnect. We're using 570 * an arbitraty 100us delay for that. 571 * 572 * Note also that a similar handling was tested by Synopsys 573 * (thanks a lot Paul) and nothing bad has come out of it. 574 * In short, what we're doing is: 575 * 576 * - Issue EndTransfer WITH CMDIOC bit set 577 * - Wait 100us 578 * - giveback all requests to gadget driver 579 */ 580 udelay(100); 581 582 req = next_request(&dep->req_queued); 583 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 584 } 585 586 while (!list_empty(&dep->request_list)) { 587 req = next_request(&dep->request_list); 588 589 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 590 } 591} 592 593/** 594 * __dwc3_gadget_ep_disable - Disables a HW endpoint 595 * @dep: the endpoint to disable 596 * 597 * This function also removes requests which are currently processed ny the 598 * hardware and those which are not yet scheduled. 599 * Caller should take care of locking. 600 */ 601static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 602{ 603 struct dwc3 *dwc = dep->dwc; 604 u32 reg; 605 606 dwc3_remove_requests(dwc, dep); 607 608 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 609 reg &= ~DWC3_DALEPENA_EP(dep->number); 610 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 611 612 dep->stream_capable = false; 613 dep->endpoint.desc = NULL; 614 dep->comp_desc = NULL; 615 dep->type = 0; 616 dep->flags = 0; 617 618 return 0; 619} 620 621/* -------------------------------------------------------------------------- */ 622 623static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 624 const struct usb_endpoint_descriptor *desc) 625{ 626 return -EINVAL; 627} 628 629static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 630{ 631 return -EINVAL; 632} 633 634/* -------------------------------------------------------------------------- */ 635 636static int dwc3_gadget_ep_enable(struct usb_ep *ep, 637 const struct usb_endpoint_descriptor *desc) 638{ 639 struct dwc3_ep *dep; 640 struct dwc3 *dwc; 641 unsigned long flags; 642 int ret; 643 644 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 645 pr_debug("dwc3: invalid parameters\n"); 646 return -EINVAL; 647 } 648 649 if (!desc->wMaxPacketSize) { 650 pr_debug("dwc3: missing wMaxPacketSize\n"); 651 return -EINVAL; 652 } 653 654 dep = to_dwc3_ep(ep); 655 dwc = dep->dwc; 656 657 switch (usb_endpoint_type(desc)) { 658 case USB_ENDPOINT_XFER_CONTROL: 659 strlcat(dep->name, "-control", sizeof(dep->name)); 660 break; 661 case USB_ENDPOINT_XFER_ISOC: 662 strlcat(dep->name, "-isoc", sizeof(dep->name)); 663 break; 664 case USB_ENDPOINT_XFER_BULK: 665 strlcat(dep->name, "-bulk", sizeof(dep->name)); 666 break; 667 case USB_ENDPOINT_XFER_INT: 668 strlcat(dep->name, "-int", sizeof(dep->name)); 669 break; 670 default: 671 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 672 } 673 674 if (dep->flags & DWC3_EP_ENABLED) { 675 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 676 dep->name); 677 return 0; 678 } 679 680 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 681 682 spin_lock_irqsave(&dwc->lock, flags); 683 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc); 684 spin_unlock_irqrestore(&dwc->lock, flags); 685 686 return ret; 687} 688 689static int dwc3_gadget_ep_disable(struct usb_ep *ep) 690{ 691 struct dwc3_ep *dep; 692 struct dwc3 *dwc; 693 unsigned long flags; 694 int ret; 695 696 if (!ep) { 697 pr_debug("dwc3: invalid parameters\n"); 698 return -EINVAL; 699 } 700 701 dep = to_dwc3_ep(ep); 702 dwc = dep->dwc; 703 704 if (!(dep->flags & DWC3_EP_ENABLED)) { 705 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 706 dep->name); 707 return 0; 708 } 709 710 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 711 dep->number >> 1, 712 (dep->number & 1) ? "in" : "out"); 713 714 spin_lock_irqsave(&dwc->lock, flags); 715 ret = __dwc3_gadget_ep_disable(dep); 716 spin_unlock_irqrestore(&dwc->lock, flags); 717 718 return ret; 719} 720 721static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 722 gfp_t gfp_flags) 723{ 724 struct dwc3_request *req; 725 struct dwc3_ep *dep = to_dwc3_ep(ep); 726 struct dwc3 *dwc = dep->dwc; 727 728 req = kzalloc(sizeof(*req), gfp_flags); 729 if (!req) { 730 dev_err(dwc->dev, "not enough memory\n"); 731 return NULL; 732 } 733 734 req->epnum = dep->number; 735 req->dep = dep; 736 737 return &req->request; 738} 739 740static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 741 struct usb_request *request) 742{ 743 struct dwc3_request *req = to_dwc3_request(request); 744 745 kfree(req); 746} 747 748/** 749 * dwc3_prepare_one_trb - setup one TRB from one request 750 * @dep: endpoint for which this request is prepared 751 * @req: dwc3_request pointer 752 */ 753static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 754 struct dwc3_request *req, dma_addr_t dma, 755 unsigned length, unsigned last, unsigned chain) 756{ 757 struct dwc3 *dwc = dep->dwc; 758 struct dwc3_trb *trb; 759 760 unsigned int cur_slot; 761 762 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 763 dep->name, req, (unsigned long long) dma, 764 length, last ? " last" : "", 765 chain ? " chain" : ""); 766 767 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 768 cur_slot = dep->free_slot; 769 dep->free_slot++; 770 771 /* Skip the LINK-TRB on ISOC */ 772 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 773 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 774 return; 775 776 if (!req->trb) { 777 dwc3_gadget_move_request_queued(req); 778 req->trb = trb; 779 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 780 } 781 782 trb->size = DWC3_TRB_SIZE_LENGTH(length); 783 trb->bpl = lower_32_bits(dma); 784 trb->bph = upper_32_bits(dma); 785 786 switch (usb_endpoint_type(dep->endpoint.desc)) { 787 case USB_ENDPOINT_XFER_CONTROL: 788 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 789 break; 790 791 case USB_ENDPOINT_XFER_ISOC: 792 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 793 794 if (!req->request.no_interrupt) 795 trb->ctrl |= DWC3_TRB_CTRL_IOC; 796 break; 797 798 case USB_ENDPOINT_XFER_BULK: 799 case USB_ENDPOINT_XFER_INT: 800 trb->ctrl = DWC3_TRBCTL_NORMAL; 801 break; 802 default: 803 /* 804 * This is only possible with faulty memory because we 805 * checked it already :) 806 */ 807 BUG(); 808 } 809 810 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 811 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 812 trb->ctrl |= DWC3_TRB_CTRL_CSP; 813 } else { 814 if (chain) 815 trb->ctrl |= DWC3_TRB_CTRL_CHN; 816 817 if (last) 818 trb->ctrl |= DWC3_TRB_CTRL_LST; 819 } 820 821 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 822 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); 823 824 trb->ctrl |= DWC3_TRB_CTRL_HWO; 825} 826 827/* 828 * dwc3_prepare_trbs - setup TRBs from requests 829 * @dep: endpoint for which requests are being prepared 830 * @starting: true if the endpoint is idle and no requests are queued. 831 * 832 * The function goes through the requests list and sets up TRBs for the 833 * transfers. The function returns once there are no more TRBs available or 834 * it runs out of requests. 835 */ 836static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 837{ 838 struct dwc3_request *req, *n; 839 u32 trbs_left; 840 u32 max; 841 unsigned int last_one = 0; 842 843 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 844 845 /* the first request must not be queued */ 846 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 847 848 /* Can't wrap around on a non-isoc EP since there's no link TRB */ 849 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 850 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); 851 if (trbs_left > max) 852 trbs_left = max; 853 } 854 855 /* 856 * If busy & slot are equal than it is either full or empty. If we are 857 * starting to process requests then we are empty. Otherwise we are 858 * full and don't do anything 859 */ 860 if (!trbs_left) { 861 if (!starting) 862 return; 863 trbs_left = DWC3_TRB_NUM; 864 /* 865 * In case we start from scratch, we queue the ISOC requests 866 * starting from slot 1. This is done because we use ring 867 * buffer and have no LST bit to stop us. Instead, we place 868 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt 869 * after the first request so we start at slot 1 and have 870 * 7 requests proceed before we hit the first IOC. 871 * Other transfer types don't use the ring buffer and are 872 * processed from the first TRB until the last one. Since we 873 * don't wrap around we have to start at the beginning. 874 */ 875 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 876 dep->busy_slot = 1; 877 dep->free_slot = 1; 878 } else { 879 dep->busy_slot = 0; 880 dep->free_slot = 0; 881 } 882 } 883 884 /* The last TRB is a link TRB, not used for xfer */ 885 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) 886 return; 887 888 list_for_each_entry_safe(req, n, &dep->request_list, list) { 889 unsigned length; 890 dma_addr_t dma; 891 892 if (req->request.num_mapped_sgs > 0) { 893 struct usb_request *request = &req->request; 894 struct scatterlist *sg = request->sg; 895 struct scatterlist *s; 896 int i; 897 898 for_each_sg(sg, s, request->num_mapped_sgs, i) { 899 unsigned chain = true; 900 901 length = sg_dma_len(s); 902 dma = sg_dma_address(s); 903 904 if (i == (request->num_mapped_sgs - 1) || 905 sg_is_last(s)) { 906 last_one = true; 907 chain = false; 908 } 909 910 trbs_left--; 911 if (!trbs_left) 912 last_one = true; 913 914 if (last_one) 915 chain = false; 916 917 dwc3_prepare_one_trb(dep, req, dma, length, 918 last_one, chain); 919 920 if (last_one) 921 break; 922 } 923 } else { 924 dma = req->request.dma; 925 length = req->request.length; 926 trbs_left--; 927 928 if (!trbs_left) 929 last_one = 1; 930 931 /* Is this the last request? */ 932 if (list_is_last(&req->list, &dep->request_list)) 933 last_one = 1; 934 935 dwc3_prepare_one_trb(dep, req, dma, length, 936 last_one, false); 937 938 if (last_one) 939 break; 940 } 941 } 942} 943 944static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 945 int start_new) 946{ 947 struct dwc3_gadget_ep_cmd_params params; 948 struct dwc3_request *req; 949 struct dwc3 *dwc = dep->dwc; 950 int ret; 951 u32 cmd; 952 953 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 954 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 955 return -EBUSY; 956 } 957 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 958 959 /* 960 * If we are getting here after a short-out-packet we don't enqueue any 961 * new requests as we try to set the IOC bit only on the last request. 962 */ 963 if (start_new) { 964 if (list_empty(&dep->req_queued)) 965 dwc3_prepare_trbs(dep, start_new); 966 967 /* req points to the first request which will be sent */ 968 req = next_request(&dep->req_queued); 969 } else { 970 dwc3_prepare_trbs(dep, start_new); 971 972 /* 973 * req points to the first request where HWO changed from 0 to 1 974 */ 975 req = next_request(&dep->req_queued); 976 } 977 if (!req) { 978 dep->flags |= DWC3_EP_PENDING_REQUEST; 979 return 0; 980 } 981 982 memset(¶ms, 0, sizeof(params)); 983 params.param0 = upper_32_bits(req->trb_dma); 984 params.param1 = lower_32_bits(req->trb_dma); 985 986 if (start_new) 987 cmd = DWC3_DEPCMD_STARTTRANSFER; 988 else 989 cmd = DWC3_DEPCMD_UPDATETRANSFER; 990 991 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 992 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 993 if (ret < 0) { 994 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 995 996 /* 997 * FIXME we need to iterate over the list of requests 998 * here and stop, unmap, free and del each of the linked 999 * requests instead of what we do now. 1000 */ 1001 usb_gadget_unmap_request(&dwc->gadget, &req->request, 1002 req->direction); 1003 list_del(&req->list); 1004 return ret; 1005 } 1006 1007 dep->flags |= DWC3_EP_BUSY; 1008 1009 if (start_new) { 1010 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, 1011 dep->number); 1012 WARN_ON_ONCE(!dep->res_trans_idx); 1013 } 1014 1015 return 0; 1016} 1017 1018static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, 1019 struct dwc3_ep *dep, u32 cur_uf) 1020{ 1021 u32 uf; 1022 1023 if (list_empty(&dep->request_list)) { 1024 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1025 dep->name); 1026 return; 1027 } 1028 1029 /* 4 micro frames in the future */ 1030 uf = cur_uf + dep->interval * 4; 1031 1032 __dwc3_gadget_kick_transfer(dep, uf, 1); 1033} 1034 1035static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1036 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1037{ 1038 u32 cur_uf, mask; 1039 1040 mask = ~(dep->interval - 1); 1041 cur_uf = event->parameters & mask; 1042 1043 __dwc3_gadget_start_isoc(dwc, dep, cur_uf); 1044} 1045 1046static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 1047{ 1048 struct dwc3 *dwc = dep->dwc; 1049 int ret; 1050 1051 req->request.actual = 0; 1052 req->request.status = -EINPROGRESS; 1053 req->direction = dep->direction; 1054 req->epnum = dep->number; 1055 1056 /* 1057 * We only add to our list of requests now and 1058 * start consuming the list once we get XferNotReady 1059 * IRQ. 1060 * 1061 * That way, we avoid doing anything that we don't need 1062 * to do now and defer it until the point we receive a 1063 * particular token from the Host side. 1064 * 1065 * This will also avoid Host cancelling URBs due to too 1066 * many NAKs. 1067 */ 1068 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1069 dep->direction); 1070 if (ret) 1071 return ret; 1072 1073 list_add_tail(&req->list, &dep->request_list); 1074 1075 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1076 if (dep->flags & DWC3_EP_BUSY) { 1077 dep->flags |= DWC3_EP_PENDING_REQUEST; 1078 } else if (dep->flags & DWC3_EP_MISSED_ISOC) { 1079 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf); 1080 dep->flags &= ~DWC3_EP_MISSED_ISOC; 1081 } 1082 } 1083 1084 /* 1085 * There are two special cases: 1086 * 1087 * 1. XferNotReady with empty list of requests. We need to kick the 1088 * transfer here in that situation, otherwise we will be NAKing 1089 * forever. If we get XferNotReady before gadget driver has a 1090 * chance to queue a request, we will ACK the IRQ but won't be 1091 * able to receive the data until the next request is queued. 1092 * The following code is handling exactly that. 1093 * 1094 * 2. XferInProgress on Isoc EP with an active transfer. We need to 1095 * kick the transfer here after queuing a request, otherwise the 1096 * core may not see the modified TRB(s). 1097 */ 1098 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1099 int ret; 1100 int start_trans = 1; 1101 u8 trans_idx = dep->res_trans_idx; 1102 1103 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1104 (dep->flags & DWC3_EP_BUSY)) { 1105 start_trans = 0; 1106 WARN_ON_ONCE(!trans_idx); 1107 } else { 1108 trans_idx = 0; 1109 } 1110 1111 ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans); 1112 if (ret && ret != -EBUSY) { 1113 struct dwc3 *dwc = dep->dwc; 1114 1115 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1116 dep->name); 1117 } 1118 } 1119 1120 return 0; 1121} 1122 1123static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1124 gfp_t gfp_flags) 1125{ 1126 struct dwc3_request *req = to_dwc3_request(request); 1127 struct dwc3_ep *dep = to_dwc3_ep(ep); 1128 struct dwc3 *dwc = dep->dwc; 1129 1130 unsigned long flags; 1131 1132 int ret; 1133 1134 if (!dep->endpoint.desc) { 1135 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1136 request, ep->name); 1137 return -ESHUTDOWN; 1138 } 1139 1140 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1141 request, ep->name, request->length); 1142 1143 spin_lock_irqsave(&dwc->lock, flags); 1144 ret = __dwc3_gadget_ep_queue(dep, req); 1145 spin_unlock_irqrestore(&dwc->lock, flags); 1146 1147 return ret; 1148} 1149 1150static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1151 struct usb_request *request) 1152{ 1153 struct dwc3_request *req = to_dwc3_request(request); 1154 struct dwc3_request *r = NULL; 1155 1156 struct dwc3_ep *dep = to_dwc3_ep(ep); 1157 struct dwc3 *dwc = dep->dwc; 1158 1159 unsigned long flags; 1160 int ret = 0; 1161 1162 spin_lock_irqsave(&dwc->lock, flags); 1163 1164 list_for_each_entry(r, &dep->request_list, list) { 1165 if (r == req) 1166 break; 1167 } 1168 1169 if (r != req) { 1170 list_for_each_entry(r, &dep->req_queued, list) { 1171 if (r == req) 1172 break; 1173 } 1174 if (r == req) { 1175 /* wait until it is processed */ 1176 dwc3_stop_active_transfer(dwc, dep->number); 1177 goto out0; 1178 } 1179 dev_err(dwc->dev, "request %p was not queued to %s\n", 1180 request, ep->name); 1181 ret = -EINVAL; 1182 goto out0; 1183 } 1184 1185 /* giveback the request */ 1186 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1187 1188out0: 1189 spin_unlock_irqrestore(&dwc->lock, flags); 1190 1191 return ret; 1192} 1193 1194int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1195{ 1196 struct dwc3_gadget_ep_cmd_params params; 1197 struct dwc3 *dwc = dep->dwc; 1198 int ret; 1199 1200 memset(¶ms, 0x00, sizeof(params)); 1201 1202 if (value) { 1203 if (dep->number == 0 || dep->number == 1) { 1204 /* 1205 * Whenever EP0 is stalled, we will restart 1206 * the state machine, thus moving back to 1207 * Setup Phase 1208 */ 1209 dwc->ep0state = EP0_SETUP_PHASE; 1210 } 1211 1212 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1213 DWC3_DEPCMD_SETSTALL, ¶ms); 1214 if (ret) 1215 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1216 value ? "set" : "clear", 1217 dep->name); 1218 else 1219 dep->flags |= DWC3_EP_STALL; 1220 } else { 1221 if (dep->flags & DWC3_EP_WEDGE) 1222 return 0; 1223 1224 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1225 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1226 if (ret) 1227 dev_err(dwc->dev, "failed to %s STALL on %s\n", 1228 value ? "set" : "clear", 1229 dep->name); 1230 else 1231 dep->flags &= ~DWC3_EP_STALL; 1232 } 1233 1234 return ret; 1235} 1236 1237static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1238{ 1239 struct dwc3_ep *dep = to_dwc3_ep(ep); 1240 struct dwc3 *dwc = dep->dwc; 1241 1242 unsigned long flags; 1243 1244 int ret; 1245 1246 spin_lock_irqsave(&dwc->lock, flags); 1247 1248 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1249 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1250 ret = -EINVAL; 1251 goto out; 1252 } 1253 1254 ret = __dwc3_gadget_ep_set_halt(dep, value); 1255out: 1256 spin_unlock_irqrestore(&dwc->lock, flags); 1257 1258 return ret; 1259} 1260 1261static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1262{ 1263 struct dwc3_ep *dep = to_dwc3_ep(ep); 1264 struct dwc3 *dwc = dep->dwc; 1265 unsigned long flags; 1266 1267 spin_lock_irqsave(&dwc->lock, flags); 1268 dep->flags |= DWC3_EP_WEDGE; 1269 spin_unlock_irqrestore(&dwc->lock, flags); 1270 1271 return dwc3_gadget_ep_set_halt(ep, 1); 1272} 1273 1274/* -------------------------------------------------------------------------- */ 1275 1276static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1277 .bLength = USB_DT_ENDPOINT_SIZE, 1278 .bDescriptorType = USB_DT_ENDPOINT, 1279 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1280}; 1281 1282static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1283 .enable = dwc3_gadget_ep0_enable, 1284 .disable = dwc3_gadget_ep0_disable, 1285 .alloc_request = dwc3_gadget_ep_alloc_request, 1286 .free_request = dwc3_gadget_ep_free_request, 1287 .queue = dwc3_gadget_ep0_queue, 1288 .dequeue = dwc3_gadget_ep_dequeue, 1289 .set_halt = dwc3_gadget_ep_set_halt, 1290 .set_wedge = dwc3_gadget_ep_set_wedge, 1291}; 1292 1293static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1294 .enable = dwc3_gadget_ep_enable, 1295 .disable = dwc3_gadget_ep_disable, 1296 .alloc_request = dwc3_gadget_ep_alloc_request, 1297 .free_request = dwc3_gadget_ep_free_request, 1298 .queue = dwc3_gadget_ep_queue, 1299 .dequeue = dwc3_gadget_ep_dequeue, 1300 .set_halt = dwc3_gadget_ep_set_halt, 1301 .set_wedge = dwc3_gadget_ep_set_wedge, 1302}; 1303 1304/* -------------------------------------------------------------------------- */ 1305 1306static int dwc3_gadget_get_frame(struct usb_gadget *g) 1307{ 1308 struct dwc3 *dwc = gadget_to_dwc(g); 1309 u32 reg; 1310 1311 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1312 return DWC3_DSTS_SOFFN(reg); 1313} 1314 1315static int dwc3_gadget_wakeup(struct usb_gadget *g) 1316{ 1317 struct dwc3 *dwc = gadget_to_dwc(g); 1318 1319 unsigned long timeout; 1320 unsigned long flags; 1321 1322 u32 reg; 1323 1324 int ret = 0; 1325 1326 u8 link_state; 1327 u8 speed; 1328 1329 spin_lock_irqsave(&dwc->lock, flags); 1330 1331 /* 1332 * According to the Databook Remote wakeup request should 1333 * be issued only when the device is in early suspend state. 1334 * 1335 * We can check that via USB Link State bits in DSTS register. 1336 */ 1337 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1338 1339 speed = reg & DWC3_DSTS_CONNECTSPD; 1340 if (speed == DWC3_DSTS_SUPERSPEED) { 1341 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1342 ret = -EINVAL; 1343 goto out; 1344 } 1345 1346 link_state = DWC3_DSTS_USBLNKST(reg); 1347 1348 switch (link_state) { 1349 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1350 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1351 break; 1352 default: 1353 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1354 link_state); 1355 ret = -EINVAL; 1356 goto out; 1357 } 1358 1359 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1360 if (ret < 0) { 1361 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1362 goto out; 1363 } 1364 1365 /* Recent versions do this automatically */ 1366 if (dwc->revision < DWC3_REVISION_194A) { 1367 /* write zeroes to Link Change Request */ 1368 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1369 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1370 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1371 } 1372 1373 /* poll until Link State changes to ON */ 1374 timeout = jiffies + msecs_to_jiffies(100); 1375 1376 while (!time_after(jiffies, timeout)) { 1377 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1378 1379 /* in HS, means ON */ 1380 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1381 break; 1382 } 1383 1384 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1385 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1386 ret = -EINVAL; 1387 } 1388 1389out: 1390 spin_unlock_irqrestore(&dwc->lock, flags); 1391 1392 return ret; 1393} 1394 1395static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1396 int is_selfpowered) 1397{ 1398 struct dwc3 *dwc = gadget_to_dwc(g); 1399 unsigned long flags; 1400 1401 spin_lock_irqsave(&dwc->lock, flags); 1402 dwc->is_selfpowered = !!is_selfpowered; 1403 spin_unlock_irqrestore(&dwc->lock, flags); 1404 1405 return 0; 1406} 1407 1408static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) 1409{ 1410 u32 reg; 1411 u32 timeout = 500; 1412 1413 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1414 if (is_on) { 1415 if (dwc->revision <= DWC3_REVISION_187A) { 1416 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1417 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1418 } 1419 1420 if (dwc->revision >= DWC3_REVISION_194A) 1421 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1422 reg |= DWC3_DCTL_RUN_STOP; 1423 } else { 1424 reg &= ~DWC3_DCTL_RUN_STOP; 1425 } 1426 1427 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1428 1429 do { 1430 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1431 if (is_on) { 1432 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1433 break; 1434 } else { 1435 if (reg & DWC3_DSTS_DEVCTRLHLT) 1436 break; 1437 } 1438 timeout--; 1439 if (!timeout) 1440 break; 1441 udelay(1); 1442 } while (1); 1443 1444 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1445 dwc->gadget_driver 1446 ? dwc->gadget_driver->function : "no-function", 1447 is_on ? "connect" : "disconnect"); 1448} 1449 1450static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1451{ 1452 struct dwc3 *dwc = gadget_to_dwc(g); 1453 unsigned long flags; 1454 1455 is_on = !!is_on; 1456 1457 spin_lock_irqsave(&dwc->lock, flags); 1458 dwc3_gadget_run_stop(dwc, is_on); 1459 spin_unlock_irqrestore(&dwc->lock, flags); 1460 1461 return 0; 1462} 1463 1464static int dwc3_gadget_start(struct usb_gadget *g, 1465 struct usb_gadget_driver *driver) 1466{ 1467 struct dwc3 *dwc = gadget_to_dwc(g); 1468 struct dwc3_ep *dep; 1469 unsigned long flags; 1470 int ret = 0; 1471 u32 reg; 1472 1473 spin_lock_irqsave(&dwc->lock, flags); 1474 1475 if (dwc->gadget_driver) { 1476 dev_err(dwc->dev, "%s is already bound to %s\n", 1477 dwc->gadget.name, 1478 dwc->gadget_driver->driver.name); 1479 ret = -EBUSY; 1480 goto err0; 1481 } 1482 1483 dwc->gadget_driver = driver; 1484 dwc->gadget.dev.driver = &driver->driver; 1485 1486 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1487 reg &= ~(DWC3_DCFG_SPEED_MASK); 1488 1489 /** 1490 * WORKAROUND: DWC3 revision < 2.20a have an issue 1491 * which would cause metastability state on Run/Stop 1492 * bit if we try to force the IP to USB2-only mode. 1493 * 1494 * Because of that, we cannot configure the IP to any 1495 * speed other than the SuperSpeed 1496 * 1497 * Refers to: 1498 * 1499 * STAR#9000525659: Clock Domain Crossing on DCTL in 1500 * USB 2.0 Mode 1501 */ 1502 if (dwc->revision < DWC3_REVISION_220A) 1503 reg |= DWC3_DCFG_SUPERSPEED; 1504 else 1505 reg |= dwc->maximum_speed; 1506 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1507 1508 dwc->start_config_issued = false; 1509 1510 /* Start with SuperSpeed Default */ 1511 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1512 1513 dep = dwc->eps[0]; 1514 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1515 if (ret) { 1516 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1517 goto err0; 1518 } 1519 1520 dep = dwc->eps[1]; 1521 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 1522 if (ret) { 1523 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1524 goto err1; 1525 } 1526 1527 /* begin to receive SETUP packets */ 1528 dwc->ep0state = EP0_SETUP_PHASE; 1529 dwc3_ep0_out_start(dwc); 1530 1531 spin_unlock_irqrestore(&dwc->lock, flags); 1532 1533 return 0; 1534 1535err1: 1536 __dwc3_gadget_ep_disable(dwc->eps[0]); 1537 1538err0: 1539 spin_unlock_irqrestore(&dwc->lock, flags); 1540 1541 return ret; 1542} 1543 1544static int dwc3_gadget_stop(struct usb_gadget *g, 1545 struct usb_gadget_driver *driver) 1546{ 1547 struct dwc3 *dwc = gadget_to_dwc(g); 1548 unsigned long flags; 1549 1550 spin_lock_irqsave(&dwc->lock, flags); 1551 1552 __dwc3_gadget_ep_disable(dwc->eps[0]); 1553 __dwc3_gadget_ep_disable(dwc->eps[1]); 1554 1555 dwc->gadget_driver = NULL; 1556 dwc->gadget.dev.driver = NULL; 1557 1558 spin_unlock_irqrestore(&dwc->lock, flags); 1559 1560 return 0; 1561} 1562 1563static const struct usb_gadget_ops dwc3_gadget_ops = { 1564 .get_frame = dwc3_gadget_get_frame, 1565 .wakeup = dwc3_gadget_wakeup, 1566 .set_selfpowered = dwc3_gadget_set_selfpowered, 1567 .pullup = dwc3_gadget_pullup, 1568 .udc_start = dwc3_gadget_start, 1569 .udc_stop = dwc3_gadget_stop, 1570}; 1571 1572/* -------------------------------------------------------------------------- */ 1573 1574static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1575{ 1576 struct dwc3_ep *dep; 1577 u8 epnum; 1578 1579 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1580 1581 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1582 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1583 if (!dep) { 1584 dev_err(dwc->dev, "can't allocate endpoint %d\n", 1585 epnum); 1586 return -ENOMEM; 1587 } 1588 1589 dep->dwc = dwc; 1590 dep->number = epnum; 1591 dwc->eps[epnum] = dep; 1592 1593 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1594 (epnum & 1) ? "in" : "out"); 1595 dep->endpoint.name = dep->name; 1596 dep->direction = (epnum & 1); 1597 1598 if (epnum == 0 || epnum == 1) { 1599 dep->endpoint.maxpacket = 512; 1600 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1601 if (!epnum) 1602 dwc->gadget.ep0 = &dep->endpoint; 1603 } else { 1604 int ret; 1605 1606 dep->endpoint.maxpacket = 1024; 1607 dep->endpoint.max_streams = 15; 1608 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1609 list_add_tail(&dep->endpoint.ep_list, 1610 &dwc->gadget.ep_list); 1611 1612 ret = dwc3_alloc_trb_pool(dep); 1613 if (ret) 1614 return ret; 1615 } 1616 1617 INIT_LIST_HEAD(&dep->request_list); 1618 INIT_LIST_HEAD(&dep->req_queued); 1619 } 1620 1621 return 0; 1622} 1623 1624static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1625{ 1626 struct dwc3_ep *dep; 1627 u8 epnum; 1628 1629 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1630 dep = dwc->eps[epnum]; 1631 dwc3_free_trb_pool(dep); 1632 1633 if (epnum != 0 && epnum != 1) 1634 list_del(&dep->endpoint.ep_list); 1635 1636 kfree(dep); 1637 } 1638} 1639 1640static void dwc3_gadget_release(struct device *dev) 1641{ 1642 dev_dbg(dev, "%s\n", __func__); 1643} 1644 1645/* -------------------------------------------------------------------------- */ 1646static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1647 const struct dwc3_event_depevt *event, int status) 1648{ 1649 struct dwc3_request *req; 1650 struct dwc3_trb *trb; 1651 unsigned int count; 1652 unsigned int s_pkt = 0; 1653 unsigned int trb_status; 1654 1655 do { 1656 req = next_request(&dep->req_queued); 1657 if (!req) { 1658 WARN_ON_ONCE(1); 1659 return 1; 1660 } 1661 1662 trb = req->trb; 1663 1664 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 1665 /* 1666 * We continue despite the error. There is not much we 1667 * can do. If we don't clean it up we loop forever. If 1668 * we skip the TRB then it gets overwritten after a 1669 * while since we use them in a ring buffer. A BUG() 1670 * would help. Lets hope that if this occurs, someone 1671 * fixes the root cause instead of looking away :) 1672 */ 1673 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1674 dep->name, req->trb); 1675 count = trb->size & DWC3_TRB_SIZE_MASK; 1676 1677 if (dep->direction) { 1678 if (count) { 1679 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); 1680 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { 1681 dev_dbg(dwc->dev, "incomplete IN transfer %s\n", 1682 dep->name); 1683 dep->current_uf = event->parameters & 1684 ~(dep->interval - 1); 1685 dep->flags |= DWC3_EP_MISSED_ISOC; 1686 } else { 1687 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1688 dep->name); 1689 status = -ECONNRESET; 1690 } 1691 } 1692 } else { 1693 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1694 s_pkt = 1; 1695 } 1696 1697 /* 1698 * We assume here we will always receive the entire data block 1699 * which we should receive. Meaning, if we program RX to 1700 * receive 4K but we receive only 2K, we assume that's all we 1701 * should receive and we simply bounce the request back to the 1702 * gadget driver for further processing. 1703 */ 1704 req->request.actual += req->request.length - count; 1705 dwc3_gadget_giveback(dep, req, status); 1706 if (s_pkt) 1707 break; 1708 if ((event->status & DEPEVT_STATUS_LST) && 1709 (trb->ctrl & (DWC3_TRB_CTRL_LST | 1710 DWC3_TRB_CTRL_HWO))) 1711 break; 1712 if ((event->status & DEPEVT_STATUS_IOC) && 1713 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1714 break; 1715 } while (1); 1716 1717 if ((event->status & DEPEVT_STATUS_IOC) && 1718 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1719 return 0; 1720 return 1; 1721} 1722 1723static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1724 struct dwc3_ep *dep, const struct dwc3_event_depevt *event, 1725 int start_new) 1726{ 1727 unsigned status = 0; 1728 int clean_busy; 1729 1730 if (event->status & DEPEVT_STATUS_BUSERR) 1731 status = -ECONNRESET; 1732 1733 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1734 if (clean_busy) 1735 dep->flags &= ~DWC3_EP_BUSY; 1736 1737 /* 1738 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1739 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1740 */ 1741 if (dwc->revision < DWC3_REVISION_183A) { 1742 u32 reg; 1743 int i; 1744 1745 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1746 struct dwc3_ep *dep = dwc->eps[i]; 1747 1748 if (!(dep->flags & DWC3_EP_ENABLED)) 1749 continue; 1750 1751 if (!list_empty(&dep->req_queued)) 1752 return; 1753 } 1754 1755 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1756 reg |= dwc->u1u2; 1757 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1758 1759 dwc->u1u2 = 0; 1760 } 1761} 1762 1763static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1764 const struct dwc3_event_depevt *event) 1765{ 1766 struct dwc3_ep *dep; 1767 u8 epnum = event->endpoint_number; 1768 1769 dep = dwc->eps[epnum]; 1770 1771 dev_vdbg(dwc->dev, "%s: %s\n", dep->name, 1772 dwc3_ep_event_string(event->endpoint_event)); 1773 1774 if (epnum == 0 || epnum == 1) { 1775 dwc3_ep0_interrupt(dwc, event); 1776 return; 1777 } 1778 1779 switch (event->endpoint_event) { 1780 case DWC3_DEPEVT_XFERCOMPLETE: 1781 dep->res_trans_idx = 0; 1782 1783 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1784 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1785 dep->name); 1786 return; 1787 } 1788 1789 dwc3_endpoint_transfer_complete(dwc, dep, event, 1); 1790 break; 1791 case DWC3_DEPEVT_XFERINPROGRESS: 1792 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1793 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", 1794 dep->name); 1795 return; 1796 } 1797 1798 dwc3_endpoint_transfer_complete(dwc, dep, event, 0); 1799 break; 1800 case DWC3_DEPEVT_XFERNOTREADY: 1801 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1802 dwc3_gadget_start_isoc(dwc, dep, event); 1803 } else { 1804 int ret; 1805 1806 dev_vdbg(dwc->dev, "%s: reason %s\n", 1807 dep->name, event->status & 1808 DEPEVT_STATUS_TRANSFER_ACTIVE 1809 ? "Transfer Active" 1810 : "Transfer Not Active"); 1811 1812 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1813 if (!ret || ret == -EBUSY) 1814 return; 1815 1816 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1817 dep->name); 1818 } 1819 1820 break; 1821 case DWC3_DEPEVT_STREAMEVT: 1822 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { 1823 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1824 dep->name); 1825 return; 1826 } 1827 1828 switch (event->status) { 1829 case DEPEVT_STREAMEVT_FOUND: 1830 dev_vdbg(dwc->dev, "Stream %d found and started\n", 1831 event->parameters); 1832 1833 break; 1834 case DEPEVT_STREAMEVT_NOTFOUND: 1835 /* FALLTHROUGH */ 1836 default: 1837 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 1838 } 1839 break; 1840 case DWC3_DEPEVT_RXTXFIFOEVT: 1841 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 1842 break; 1843 case DWC3_DEPEVT_EPCMDCMPLT: 1844 dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); 1845 break; 1846 } 1847} 1848 1849static void dwc3_disconnect_gadget(struct dwc3 *dwc) 1850{ 1851 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 1852 spin_unlock(&dwc->lock); 1853 dwc->gadget_driver->disconnect(&dwc->gadget); 1854 spin_lock(&dwc->lock); 1855 } 1856} 1857 1858static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) 1859{ 1860 struct dwc3_ep *dep; 1861 struct dwc3_gadget_ep_cmd_params params; 1862 u32 cmd; 1863 int ret; 1864 1865 dep = dwc->eps[epnum]; 1866 1867 WARN_ON(!dep->res_trans_idx); 1868 if (dep->res_trans_idx) { 1869 cmd = DWC3_DEPCMD_ENDTRANSFER; 1870 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; 1871 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx); 1872 memset(¶ms, 0, sizeof(params)); 1873 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1874 WARN_ON_ONCE(ret); 1875 dep->res_trans_idx = 0; 1876 } 1877} 1878 1879static void dwc3_stop_active_transfers(struct dwc3 *dwc) 1880{ 1881 u32 epnum; 1882 1883 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1884 struct dwc3_ep *dep; 1885 1886 dep = dwc->eps[epnum]; 1887 if (!(dep->flags & DWC3_EP_ENABLED)) 1888 continue; 1889 1890 dwc3_remove_requests(dwc, dep); 1891 } 1892} 1893 1894static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 1895{ 1896 u32 epnum; 1897 1898 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1899 struct dwc3_ep *dep; 1900 struct dwc3_gadget_ep_cmd_params params; 1901 int ret; 1902 1903 dep = dwc->eps[epnum]; 1904 1905 if (!(dep->flags & DWC3_EP_STALL)) 1906 continue; 1907 1908 dep->flags &= ~DWC3_EP_STALL; 1909 1910 memset(¶ms, 0, sizeof(params)); 1911 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1912 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1913 WARN_ON_ONCE(ret); 1914 } 1915} 1916 1917static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 1918{ 1919 int reg; 1920 1921 dev_vdbg(dwc->dev, "%s\n", __func__); 1922 1923 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1924 reg &= ~DWC3_DCTL_INITU1ENA; 1925 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1926 1927 reg &= ~DWC3_DCTL_INITU2ENA; 1928 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1929 1930 dwc3_stop_active_transfers(dwc); 1931 dwc3_disconnect_gadget(dwc); 1932 dwc->start_config_issued = false; 1933 1934 dwc->gadget.speed = USB_SPEED_UNKNOWN; 1935 dwc->setup_packet_pending = false; 1936} 1937 1938static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend) 1939{ 1940 u32 reg; 1941 1942 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 1943 1944 if (suspend) 1945 reg |= DWC3_GUSB3PIPECTL_SUSPHY; 1946 else 1947 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 1948 1949 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 1950} 1951 1952static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend) 1953{ 1954 u32 reg; 1955 1956 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1957 1958 if (suspend) 1959 reg |= DWC3_GUSB2PHYCFG_SUSPHY; 1960 else 1961 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1962 1963 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1964} 1965 1966static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 1967{ 1968 u32 reg; 1969 1970 dev_vdbg(dwc->dev, "%s\n", __func__); 1971 1972 /* 1973 * WORKAROUND: DWC3 revisions <1.88a have an issue which 1974 * would cause a missing Disconnect Event if there's a 1975 * pending Setup Packet in the FIFO. 1976 * 1977 * There's no suggested workaround on the official Bug 1978 * report, which states that "unless the driver/application 1979 * is doing any special handling of a disconnect event, 1980 * there is no functional issue". 1981 * 1982 * Unfortunately, it turns out that we _do_ some special 1983 * handling of a disconnect event, namely complete all 1984 * pending transfers, notify gadget driver of the 1985 * disconnection, and so on. 1986 * 1987 * Our suggested workaround is to follow the Disconnect 1988 * Event steps here, instead, based on a setup_packet_pending 1989 * flag. Such flag gets set whenever we have a XferNotReady 1990 * event on EP0 and gets cleared on XferComplete for the 1991 * same endpoint. 1992 * 1993 * Refers to: 1994 * 1995 * STAR#9000466709: RTL: Device : Disconnect event not 1996 * generated if setup packet pending in FIFO 1997 */ 1998 if (dwc->revision < DWC3_REVISION_188A) { 1999 if (dwc->setup_packet_pending) 2000 dwc3_gadget_disconnect_interrupt(dwc); 2001 } 2002 2003 /* after reset -> Default State */ 2004 dwc->dev_state = DWC3_DEFAULT_STATE; 2005 2006 /* Recent versions support automatic phy suspend and don't need this */ 2007 if (dwc->revision < DWC3_REVISION_194A) { 2008 /* Resume PHYs */ 2009 dwc3_gadget_usb2_phy_suspend(dwc, false); 2010 dwc3_gadget_usb3_phy_suspend(dwc, false); 2011 } 2012 2013 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 2014 dwc3_disconnect_gadget(dwc); 2015 2016 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2017 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2018 reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA); 2019 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 2020 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2021 dwc->test_mode = false; 2022 2023 dwc3_stop_active_transfers(dwc); 2024 dwc3_clear_stall_all_ep(dwc); 2025 dwc->start_config_issued = false; 2026 2027 /* Reset device address to zero */ 2028 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2029 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2030 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2031} 2032 2033static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 2034{ 2035 u32 reg; 2036 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 2037 2038 /* 2039 * We change the clock only at SS but I dunno why I would want to do 2040 * this. Maybe it becomes part of the power saving plan. 2041 */ 2042 2043 if (speed != DWC3_DSTS_SUPERSPEED) 2044 return; 2045 2046 /* 2047 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2048 * each time on Connect Done. 2049 */ 2050 if (!usb30_clock) 2051 return; 2052 2053 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 2054 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 2055 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 2056} 2057 2058static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed) 2059{ 2060 switch (speed) { 2061 case USB_SPEED_SUPER: 2062 dwc3_gadget_usb2_phy_suspend(dwc, true); 2063 break; 2064 case USB_SPEED_HIGH: 2065 case USB_SPEED_FULL: 2066 case USB_SPEED_LOW: 2067 dwc3_gadget_usb3_phy_suspend(dwc, true); 2068 break; 2069 } 2070} 2071 2072static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2073{ 2074 struct dwc3_gadget_ep_cmd_params params; 2075 struct dwc3_ep *dep; 2076 int ret; 2077 u32 reg; 2078 u8 speed; 2079 2080 dev_vdbg(dwc->dev, "%s\n", __func__); 2081 2082 memset(¶ms, 0x00, sizeof(params)); 2083 2084 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2085 speed = reg & DWC3_DSTS_CONNECTSPD; 2086 dwc->speed = speed; 2087 2088 dwc3_update_ram_clk_sel(dwc, speed); 2089 2090 switch (speed) { 2091 case DWC3_DCFG_SUPERSPEED: 2092 /* 2093 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2094 * would cause a missing USB3 Reset event. 2095 * 2096 * In such situations, we should force a USB3 Reset 2097 * event by calling our dwc3_gadget_reset_interrupt() 2098 * routine. 2099 * 2100 * Refers to: 2101 * 2102 * STAR#9000483510: RTL: SS : USB3 reset event may 2103 * not be generated always when the link enters poll 2104 */ 2105 if (dwc->revision < DWC3_REVISION_190A) 2106 dwc3_gadget_reset_interrupt(dwc); 2107 2108 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2109 dwc->gadget.ep0->maxpacket = 512; 2110 dwc->gadget.speed = USB_SPEED_SUPER; 2111 break; 2112 case DWC3_DCFG_HIGHSPEED: 2113 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2114 dwc->gadget.ep0->maxpacket = 64; 2115 dwc->gadget.speed = USB_SPEED_HIGH; 2116 break; 2117 case DWC3_DCFG_FULLSPEED2: 2118 case DWC3_DCFG_FULLSPEED1: 2119 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2120 dwc->gadget.ep0->maxpacket = 64; 2121 dwc->gadget.speed = USB_SPEED_FULL; 2122 break; 2123 case DWC3_DCFG_LOWSPEED: 2124 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2125 dwc->gadget.ep0->maxpacket = 8; 2126 dwc->gadget.speed = USB_SPEED_LOW; 2127 break; 2128 } 2129 2130 /* Recent versions support automatic phy suspend and don't need this */ 2131 if (dwc->revision < DWC3_REVISION_194A) { 2132 /* Suspend unneeded PHY */ 2133 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed); 2134 } 2135 2136 dep = dwc->eps[0]; 2137 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 2138 if (ret) { 2139 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2140 return; 2141 } 2142 2143 dep = dwc->eps[1]; 2144 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); 2145 if (ret) { 2146 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2147 return; 2148 } 2149 2150 /* 2151 * Configure PHY via GUSB3PIPECTLn if required. 2152 * 2153 * Update GTXFIFOSIZn 2154 * 2155 * In both cases reset values should be sufficient. 2156 */ 2157} 2158 2159static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2160{ 2161 dev_vdbg(dwc->dev, "%s\n", __func__); 2162 2163 /* 2164 * TODO take core out of low power mode when that's 2165 * implemented. 2166 */ 2167 2168 dwc->gadget_driver->resume(&dwc->gadget); 2169} 2170 2171static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2172 unsigned int evtinfo) 2173{ 2174 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2175 2176 /* 2177 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2178 * on the link partner, the USB session might do multiple entry/exit 2179 * of low power states before a transfer takes place. 2180 * 2181 * Due to this problem, we might experience lower throughput. The 2182 * suggested workaround is to disable DCTL[12:9] bits if we're 2183 * transitioning from U1/U2 to U0 and enable those bits again 2184 * after a transfer completes and there are no pending transfers 2185 * on any of the enabled endpoints. 2186 * 2187 * This is the first half of that workaround. 2188 * 2189 * Refers to: 2190 * 2191 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2192 * core send LGO_Ux entering U0 2193 */ 2194 if (dwc->revision < DWC3_REVISION_183A) { 2195 if (next == DWC3_LINK_STATE_U0) { 2196 u32 u1u2; 2197 u32 reg; 2198 2199 switch (dwc->link_state) { 2200 case DWC3_LINK_STATE_U1: 2201 case DWC3_LINK_STATE_U2: 2202 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2203 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2204 | DWC3_DCTL_ACCEPTU2ENA 2205 | DWC3_DCTL_INITU1ENA 2206 | DWC3_DCTL_ACCEPTU1ENA); 2207 2208 if (!dwc->u1u2) 2209 dwc->u1u2 = reg & u1u2; 2210 2211 reg &= ~u1u2; 2212 2213 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2214 break; 2215 default: 2216 /* do nothing */ 2217 break; 2218 } 2219 } 2220 } 2221 2222 dwc->link_state = next; 2223 2224 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); 2225} 2226 2227static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2228 const struct dwc3_event_devt *event) 2229{ 2230 switch (event->type) { 2231 case DWC3_DEVICE_EVENT_DISCONNECT: 2232 dwc3_gadget_disconnect_interrupt(dwc); 2233 break; 2234 case DWC3_DEVICE_EVENT_RESET: 2235 dwc3_gadget_reset_interrupt(dwc); 2236 break; 2237 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2238 dwc3_gadget_conndone_interrupt(dwc); 2239 break; 2240 case DWC3_DEVICE_EVENT_WAKEUP: 2241 dwc3_gadget_wakeup_interrupt(dwc); 2242 break; 2243 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2244 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2245 break; 2246 case DWC3_DEVICE_EVENT_EOPF: 2247 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2248 break; 2249 case DWC3_DEVICE_EVENT_SOF: 2250 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2251 break; 2252 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2253 dev_vdbg(dwc->dev, "Erratic Error\n"); 2254 break; 2255 case DWC3_DEVICE_EVENT_CMD_CMPL: 2256 dev_vdbg(dwc->dev, "Command Complete\n"); 2257 break; 2258 case DWC3_DEVICE_EVENT_OVERFLOW: 2259 dev_vdbg(dwc->dev, "Overflow\n"); 2260 break; 2261 default: 2262 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2263 } 2264} 2265 2266static void dwc3_process_event_entry(struct dwc3 *dwc, 2267 const union dwc3_event *event) 2268{ 2269 /* Endpoint IRQ, handle it and return early */ 2270 if (event->type.is_devspec == 0) { 2271 /* depevt */ 2272 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2273 } 2274 2275 switch (event->type.type) { 2276 case DWC3_EVENT_TYPE_DEV: 2277 dwc3_gadget_interrupt(dwc, &event->devt); 2278 break; 2279 /* REVISIT what to do with Carkit and I2C events ? */ 2280 default: 2281 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2282 } 2283} 2284 2285static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2286{ 2287 struct dwc3_event_buffer *evt; 2288 int left; 2289 u32 count; 2290 2291 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2292 count &= DWC3_GEVNTCOUNT_MASK; 2293 if (!count) 2294 return IRQ_NONE; 2295 2296 evt = dwc->ev_buffs[buf]; 2297 left = count; 2298 2299 while (left > 0) { 2300 union dwc3_event event; 2301 2302 event.raw = *(u32 *) (evt->buf + evt->lpos); 2303 2304 dwc3_process_event_entry(dwc, &event); 2305 /* 2306 * XXX we wrap around correctly to the next entry as almost all 2307 * entries are 4 bytes in size. There is one entry which has 12 2308 * bytes which is a regular entry followed by 8 bytes data. ATM 2309 * I don't know how things are organized if were get next to the 2310 * a boundary so I worry about that once we try to handle that. 2311 */ 2312 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2313 left -= 4; 2314 2315 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2316 } 2317 2318 return IRQ_HANDLED; 2319} 2320 2321static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2322{ 2323 struct dwc3 *dwc = _dwc; 2324 int i; 2325 irqreturn_t ret = IRQ_NONE; 2326 2327 spin_lock(&dwc->lock); 2328 2329 for (i = 0; i < dwc->num_event_buffers; i++) { 2330 irqreturn_t status; 2331 2332 status = dwc3_process_event_buf(dwc, i); 2333 if (status == IRQ_HANDLED) 2334 ret = status; 2335 } 2336 2337 spin_unlock(&dwc->lock); 2338 2339 return ret; 2340} 2341 2342/** 2343 * dwc3_gadget_init - Initializes gadget related registers 2344 * @dwc: pointer to our controller context structure 2345 * 2346 * Returns 0 on success otherwise negative errno. 2347 */ 2348int __devinit dwc3_gadget_init(struct dwc3 *dwc) 2349{ 2350 u32 reg; 2351 int ret; 2352 int irq; 2353 2354 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2355 &dwc->ctrl_req_addr, GFP_KERNEL); 2356 if (!dwc->ctrl_req) { 2357 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2358 ret = -ENOMEM; 2359 goto err0; 2360 } 2361 2362 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2363 &dwc->ep0_trb_addr, GFP_KERNEL); 2364 if (!dwc->ep0_trb) { 2365 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2366 ret = -ENOMEM; 2367 goto err1; 2368 } 2369 2370 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); 2371 if (!dwc->setup_buf) { 2372 dev_err(dwc->dev, "failed to allocate setup buffer\n"); 2373 ret = -ENOMEM; 2374 goto err2; 2375 } 2376 2377 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2378 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, 2379 GFP_KERNEL); 2380 if (!dwc->ep0_bounce) { 2381 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2382 ret = -ENOMEM; 2383 goto err3; 2384 } 2385 2386 dev_set_name(&dwc->gadget.dev, "gadget"); 2387 2388 dwc->gadget.ops = &dwc3_gadget_ops; 2389 dwc->gadget.max_speed = USB_SPEED_SUPER; 2390 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2391 dwc->gadget.dev.parent = dwc->dev; 2392 dwc->gadget.sg_supported = true; 2393 2394 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); 2395 2396 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; 2397 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; 2398 dwc->gadget.dev.release = dwc3_gadget_release; 2399 dwc->gadget.name = "dwc3-gadget"; 2400 2401 /* 2402 * REVISIT: Here we should clear all pending IRQs to be 2403 * sure we're starting from a well known location. 2404 */ 2405 2406 ret = dwc3_gadget_init_endpoints(dwc); 2407 if (ret) 2408 goto err4; 2409 2410 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2411 2412 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, 2413 "dwc3", dwc); 2414 if (ret) { 2415 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 2416 irq, ret); 2417 goto err5; 2418 } 2419 2420 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2421 reg |= DWC3_DCFG_LPM_CAP; 2422 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2423 2424 /* Enable all but Start and End of Frame IRQs */ 2425 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 2426 DWC3_DEVTEN_EVNTOVERFLOWEN | 2427 DWC3_DEVTEN_CMDCMPLTEN | 2428 DWC3_DEVTEN_ERRTICERREN | 2429 DWC3_DEVTEN_WKUPEVTEN | 2430 DWC3_DEVTEN_ULSTCNGEN | 2431 DWC3_DEVTEN_CONNECTDONEEN | 2432 DWC3_DEVTEN_USBRSTEN | 2433 DWC3_DEVTEN_DISCONNEVTEN); 2434 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 2435 2436 /* Enable USB2 LPM and automatic phy suspend only on recent versions */ 2437 if (dwc->revision >= DWC3_REVISION_194A) { 2438 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2439 reg |= DWC3_DCFG_LPM_CAP; 2440 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2441 2442 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2443 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2444 2445 /* TODO: This should be configurable */ 2446 reg |= DWC3_DCTL_HIRD_THRES(31); 2447 2448 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2449 2450 dwc3_gadget_usb2_phy_suspend(dwc, true); 2451 dwc3_gadget_usb3_phy_suspend(dwc, true); 2452 } 2453 2454 ret = device_register(&dwc->gadget.dev); 2455 if (ret) { 2456 dev_err(dwc->dev, "failed to register gadget device\n"); 2457 put_device(&dwc->gadget.dev); 2458 goto err6; 2459 } 2460 2461 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2462 if (ret) { 2463 dev_err(dwc->dev, "failed to register udc\n"); 2464 goto err7; 2465 } 2466 2467 return 0; 2468 2469err7: 2470 device_unregister(&dwc->gadget.dev); 2471 2472err6: 2473 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2474 free_irq(irq, dwc); 2475 2476err5: 2477 dwc3_gadget_free_endpoints(dwc); 2478 2479err4: 2480 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2481 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2482 2483err3: 2484 kfree(dwc->setup_buf); 2485 2486err2: 2487 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2488 dwc->ep0_trb, dwc->ep0_trb_addr); 2489 2490err1: 2491 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2492 dwc->ctrl_req, dwc->ctrl_req_addr); 2493 2494err0: 2495 return ret; 2496} 2497 2498void dwc3_gadget_exit(struct dwc3 *dwc) 2499{ 2500 int irq; 2501 2502 usb_del_gadget_udc(&dwc->gadget); 2503 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 2504 2505 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 2506 free_irq(irq, dwc); 2507 2508 dwc3_gadget_free_endpoints(dwc); 2509 2510 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2511 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2512 2513 kfree(dwc->setup_buf); 2514 2515 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2516 dwc->ep0_trb, dwc->ep0_trb_addr); 2517 2518 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2519 dwc->ctrl_req, dwc->ctrl_req_addr); 2520 2521 device_unregister(&dwc->gadget.dev); 2522} 2523