ehci.h revision 55934eb3b9fa52eb53b9d7342267fc73c38206aa
1/* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#ifndef __LINUX_EHCI_HCD_H 20#define __LINUX_EHCI_HCD_H 21 22/* definitions used for the EHCI driver */ 23 24/* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33typedef __u32 __bitwise __hc32; 34typedef __u16 __bitwise __hc16; 35#else 36#define __hc32 __le32 37#define __hc16 __le16 38#endif 39 40/* statistics can be kept for tuning/monitoring */ 41struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long iaa; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51}; 52 53/* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, unlink, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65/* 66 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the 67 * controller may be doing DMA. Lower values mean there's no DMA. 68 */ 69enum ehci_rh_state { 70 EHCI_RH_HALTED, 71 EHCI_RH_SUSPENDED, 72 EHCI_RH_RUNNING, 73 EHCI_RH_STOPPING 74}; 75 76/* 77 * Timer events, ordered by increasing delay length. 78 * Always update event_delays_ns[] and event_handlers[] (defined in 79 * ehci-timer.c) in parallel with this list. 80 */ 81enum ehci_hrtimer_event { 82 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ 83 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ 84 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ 85 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ 86 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ 87 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ 88 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ 89 EHCI_HRTIMER_NUM_EVENTS /* Must come last */ 90}; 91#define EHCI_HRTIMER_NO_EVENT 99 92 93struct ehci_hcd { /* one per controller */ 94 /* timing support */ 95 enum ehci_hrtimer_event next_hrtimer_event; 96 unsigned enabled_hrtimer_events; 97 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; 98 struct hrtimer hrtimer; 99 100 int PSS_poll_count; 101 int ASS_poll_count; 102 int died_poll_count; 103 104 /* glue to PCI and HCD framework */ 105 struct ehci_caps __iomem *caps; 106 struct ehci_regs __iomem *regs; 107 struct ehci_dbg_port __iomem *debug; 108 109 __u32 hcs_params; /* cached register copy */ 110 spinlock_t lock; 111 enum ehci_rh_state rh_state; 112 113 /* general schedule support */ 114 unsigned scanning:1; 115 bool intr_unlinking:1; 116 117 /* async schedule support */ 118 struct ehci_qh *async; 119 struct ehci_qh *dummy; /* For AMD quirk use */ 120 struct ehci_qh *async_unlink; 121 struct ehci_qh *async_unlink_last; 122 struct ehci_qh *qh_scan_next; 123 unsigned async_count; /* async activity count */ 124 125 /* periodic schedule support */ 126#define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 127 unsigned periodic_size; 128 __hc32 *periodic; /* hw periodic table */ 129 dma_addr_t periodic_dma; 130 unsigned i_thresh; /* uframes HC might cache */ 131 132 union ehci_shadow *pshadow; /* mirror hw periodic table */ 133 struct ehci_qh *intr_unlink; 134 struct ehci_qh *intr_unlink_last; 135 unsigned intr_unlink_cycle; 136 int next_uframe; /* scan periodic, start here */ 137 unsigned periodic_count; /* periodic activity count */ 138 unsigned uframe_periodic_max; /* max periodic time per uframe */ 139 140 141 /* list of itds & sitds completed while clock_frame was still active */ 142 struct list_head cached_itd_list; 143 struct ehci_itd *last_itd_to_free; 144 struct list_head cached_sitd_list; 145 struct ehci_sitd *last_sitd_to_free; 146 unsigned clock_frame; 147 148 /* per root hub port */ 149 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 150 151 /* bit vectors (one bit per port) */ 152 unsigned long bus_suspended; /* which ports were 153 already suspended at the start of a bus suspend */ 154 unsigned long companion_ports; /* which ports are 155 dedicated to the companion controller */ 156 unsigned long owned_ports; /* which ports are 157 owned by the companion during a bus suspend */ 158 unsigned long port_c_suspend; /* which ports have 159 the change-suspend feature turned on */ 160 unsigned long suspended_ports; /* which ports are 161 suspended */ 162 unsigned long resuming_ports; /* which ports have 163 started to resume */ 164 165 /* per-HC memory pools (could be per-bus, but ...) */ 166 struct dma_pool *qh_pool; /* qh per active urb */ 167 struct dma_pool *qtd_pool; /* one or more per qh */ 168 struct dma_pool *itd_pool; /* itd per iso urb */ 169 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 170 171 struct timer_list iaa_watchdog; 172 struct timer_list watchdog; 173 unsigned long actions; 174 unsigned periodic_stamp; 175 unsigned random_frame; 176 unsigned long next_statechange; 177 ktime_t last_periodic_enable; 178 u32 command; 179 180 /* SILICON QUIRKS */ 181 unsigned no_selective_suspend:1; 182 unsigned has_fsl_port_bug:1; /* FreeScale */ 183 unsigned big_endian_mmio:1; 184 unsigned big_endian_desc:1; 185 unsigned big_endian_capbase:1; 186 unsigned has_amcc_usb23:1; 187 unsigned need_io_watchdog:1; 188 unsigned amd_pll_fix:1; 189 unsigned fs_i_thresh:1; /* Intel iso scheduling */ 190 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 191 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 192 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ 193 194 /* required for usb32 quirk */ 195 #define OHCI_CTRL_HCFS (3 << 6) 196 #define OHCI_USB_OPER (2 << 6) 197 #define OHCI_USB_SUSPEND (3 << 6) 198 199 #define OHCI_HCCTRL_OFFSET 0x4 200 #define OHCI_HCCTRL_LEN 0x4 201 __hc32 *ohci_hcctrl_reg; 202 unsigned has_hostpc:1; 203 unsigned has_lpm:1; /* support link power management */ 204 unsigned has_ppcd:1; /* support per-port change bits */ 205 u8 sbrn; /* packed release number */ 206 207 /* irq statistics */ 208#ifdef EHCI_STATS 209 struct ehci_stats stats; 210# define COUNT(x) do { (x)++; } while (0) 211#else 212# define COUNT(x) do {} while (0) 213#endif 214 215 /* debug files */ 216#ifdef DEBUG 217 struct dentry *debug_dir; 218#endif 219}; 220 221/* convert between an HCD pointer and the corresponding EHCI_HCD */ 222static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 223{ 224 return (struct ehci_hcd *) (hcd->hcd_priv); 225} 226static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 227{ 228 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 229} 230 231 232static inline void 233iaa_watchdog_start(struct ehci_hcd *ehci) 234{ 235 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 236 mod_timer(&ehci->iaa_watchdog, 237 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 238} 239 240static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 241{ 242 del_timer(&ehci->iaa_watchdog); 243} 244 245enum ehci_timer_action { 246 TIMER_IO_WATCHDOG, 247 TIMER_ASYNC_SHRINK, 248}; 249 250static inline void 251timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 252{ 253 clear_bit (action, &ehci->actions); 254} 255 256/*-------------------------------------------------------------------------*/ 257 258#include <linux/usb/ehci_def.h> 259 260/*-------------------------------------------------------------------------*/ 261 262#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 263 264/* 265 * EHCI Specification 0.95 Section 3.5 266 * QTD: describe data transfer components (buffer, direction, ...) 267 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 268 * 269 * These are associated only with "QH" (Queue Head) structures, 270 * used with control, bulk, and interrupt transfers. 271 */ 272struct ehci_qtd { 273 /* first part defined by EHCI spec */ 274 __hc32 hw_next; /* see EHCI 3.5.1 */ 275 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 276 __hc32 hw_token; /* see EHCI 3.5.3 */ 277#define QTD_TOGGLE (1 << 31) /* data toggle */ 278#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 279#define QTD_IOC (1 << 15) /* interrupt on complete */ 280#define QTD_CERR(tok) (((tok)>>10) & 0x3) 281#define QTD_PID(tok) (((tok)>>8) & 0x3) 282#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 283#define QTD_STS_HALT (1 << 6) /* halted on error */ 284#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 285#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 286#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 287#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 288#define QTD_STS_STS (1 << 1) /* split transaction state */ 289#define QTD_STS_PING (1 << 0) /* issue PING? */ 290 291#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 292#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 293#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 294 295 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 296 __hc32 hw_buf_hi [5]; /* Appendix B */ 297 298 /* the rest is HCD-private */ 299 dma_addr_t qtd_dma; /* qtd address */ 300 struct list_head qtd_list; /* sw qtd list */ 301 struct urb *urb; /* qtd's urb */ 302 size_t length; /* length of buffer */ 303} __attribute__ ((aligned (32))); 304 305/* mask NakCnt+T in qh->hw_alt_next */ 306#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 307 308#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 309 310/*-------------------------------------------------------------------------*/ 311 312/* type tag from {qh,itd,sitd,fstn}->hw_next */ 313#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 314 315/* 316 * Now the following defines are not converted using the 317 * cpu_to_le32() macro anymore, since we have to support 318 * "dynamic" switching between be and le support, so that the driver 319 * can be used on one system with SoC EHCI controller using big-endian 320 * descriptors as well as a normal little-endian PCI EHCI controller. 321 */ 322/* values for that type tag */ 323#define Q_TYPE_ITD (0 << 1) 324#define Q_TYPE_QH (1 << 1) 325#define Q_TYPE_SITD (2 << 1) 326#define Q_TYPE_FSTN (3 << 1) 327 328/* next async queue entry, or pointer to interrupt/periodic QH */ 329#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 330 331/* for periodic/async schedules and qtd lists, mark end of list */ 332#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 333 334/* 335 * Entries in periodic shadow table are pointers to one of four kinds 336 * of data structure. That's dictated by the hardware; a type tag is 337 * encoded in the low bits of the hardware's periodic schedule. Use 338 * Q_NEXT_TYPE to get the tag. 339 * 340 * For entries in the async schedule, the type tag always says "qh". 341 */ 342union ehci_shadow { 343 struct ehci_qh *qh; /* Q_TYPE_QH */ 344 struct ehci_itd *itd; /* Q_TYPE_ITD */ 345 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 346 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 347 __hc32 *hw_next; /* (all types) */ 348 void *ptr; 349}; 350 351/*-------------------------------------------------------------------------*/ 352 353/* 354 * EHCI Specification 0.95 Section 3.6 355 * QH: describes control/bulk/interrupt endpoints 356 * See Fig 3-7 "Queue Head Structure Layout". 357 * 358 * These appear in both the async and (for interrupt) periodic schedules. 359 */ 360 361/* first part defined by EHCI spec */ 362struct ehci_qh_hw { 363 __hc32 hw_next; /* see EHCI 3.6.1 */ 364 __hc32 hw_info1; /* see EHCI 3.6.2 */ 365#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ 366#define QH_HEAD (1 << 15) /* Head of async reclamation list */ 367#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ 368#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ 369#define QH_LOW_SPEED (1 << 12) 370#define QH_FULL_SPEED (0 << 12) 371#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ 372 __hc32 hw_info2; /* see EHCI 3.6.2 */ 373#define QH_SMASK 0x000000ff 374#define QH_CMASK 0x0000ff00 375#define QH_HUBADDR 0x007f0000 376#define QH_HUBPORT 0x3f800000 377#define QH_MULT 0xc0000000 378 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 379 380 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 381 __hc32 hw_qtd_next; 382 __hc32 hw_alt_next; 383 __hc32 hw_token; 384 __hc32 hw_buf [5]; 385 __hc32 hw_buf_hi [5]; 386} __attribute__ ((aligned(32))); 387 388struct ehci_qh { 389 struct ehci_qh_hw *hw; 390 /* the rest is HCD-private */ 391 dma_addr_t qh_dma; /* address of qh */ 392 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 393 struct list_head qtd_list; /* sw qtd list */ 394 struct ehci_qtd *dummy; 395 struct ehci_qh *unlink_next; /* next on unlink list */ 396 397 unsigned long unlink_time; 398 unsigned unlink_cycle; 399 unsigned stamp; 400 401 u8 needs_rescan; /* Dequeue during giveback */ 402 u8 qh_state; 403#define QH_STATE_LINKED 1 /* HC sees this */ 404#define QH_STATE_UNLINK 2 /* HC may still see this */ 405#define QH_STATE_IDLE 3 /* HC doesn't see this */ 406#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ 407#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 408 409 u8 xacterrs; /* XactErr retry counter */ 410#define QH_XACTERR_MAX 32 /* XactErr retry limit */ 411 412 /* periodic schedule info */ 413 u8 usecs; /* intr bandwidth */ 414 u8 gap_uf; /* uframes split/csplit gap */ 415 u8 c_usecs; /* ... split completion bw */ 416 u16 tt_usecs; /* tt downstream bandwidth */ 417 unsigned short period; /* polling interval */ 418 unsigned short start; /* where polling starts */ 419#define NO_FRAME ((unsigned short)~0) /* pick new start */ 420 421 struct usb_device *dev; /* access to TT */ 422 unsigned is_out:1; /* bulk or intr OUT */ 423 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 424}; 425 426/*-------------------------------------------------------------------------*/ 427 428/* description of one iso transaction (up to 3 KB data if highspeed) */ 429struct ehci_iso_packet { 430 /* These will be copied to iTD when scheduling */ 431 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 432 __hc32 transaction; /* itd->hw_transaction[i] |= */ 433 u8 cross; /* buf crosses pages */ 434 /* for full speed OUT splits */ 435 u32 buf1; 436}; 437 438/* temporary schedule data for packets from iso urbs (both speeds) 439 * each packet is one logical usb transaction to the device (not TT), 440 * beginning at stream->next_uframe 441 */ 442struct ehci_iso_sched { 443 struct list_head td_list; 444 unsigned span; 445 struct ehci_iso_packet packet [0]; 446}; 447 448/* 449 * ehci_iso_stream - groups all (s)itds for this endpoint. 450 * acts like a qh would, if EHCI had them for ISO. 451 */ 452struct ehci_iso_stream { 453 /* first field matches ehci_hq, but is NULL */ 454 struct ehci_qh_hw *hw; 455 456 u32 refcount; 457 u8 bEndpointAddress; 458 u8 highspeed; 459 struct list_head td_list; /* queued itds/sitds */ 460 struct list_head free_list; /* list of unused itds/sitds */ 461 struct usb_device *udev; 462 struct usb_host_endpoint *ep; 463 464 /* output of (re)scheduling */ 465 int next_uframe; 466 __hc32 splits; 467 468 /* the rest is derived from the endpoint descriptor, 469 * trusting urb->interval == f(epdesc->bInterval) and 470 * including the extra info for hw_bufp[0..2] 471 */ 472 u8 usecs, c_usecs; 473 u16 interval; 474 u16 tt_usecs; 475 u16 maxp; 476 u16 raw_mask; 477 unsigned bandwidth; 478 479 /* This is used to initialize iTD's hw_bufp fields */ 480 __hc32 buf0; 481 __hc32 buf1; 482 __hc32 buf2; 483 484 /* this is used to initialize sITD's tt info */ 485 __hc32 address; 486}; 487 488/*-------------------------------------------------------------------------*/ 489 490/* 491 * EHCI Specification 0.95 Section 3.3 492 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 493 * 494 * Schedule records for high speed iso xfers 495 */ 496struct ehci_itd { 497 /* first part defined by EHCI spec */ 498 __hc32 hw_next; /* see EHCI 3.3.1 */ 499 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 500#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 501#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 502#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 503#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 504#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 505#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 506 507#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 508 509 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 510 __hc32 hw_bufp_hi [7]; /* Appendix B */ 511 512 /* the rest is HCD-private */ 513 dma_addr_t itd_dma; /* for this itd */ 514 union ehci_shadow itd_next; /* ptr to periodic q entry */ 515 516 struct urb *urb; 517 struct ehci_iso_stream *stream; /* endpoint's queue */ 518 struct list_head itd_list; /* list of stream's itds */ 519 520 /* any/all hw_transactions here may be used by that urb */ 521 unsigned frame; /* where scheduled */ 522 unsigned pg; 523 unsigned index[8]; /* in urb->iso_frame_desc */ 524} __attribute__ ((aligned (32))); 525 526/*-------------------------------------------------------------------------*/ 527 528/* 529 * EHCI Specification 0.95 Section 3.4 530 * siTD, aka split-transaction isochronous Transfer Descriptor 531 * ... describe full speed iso xfers through TT in hubs 532 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 533 */ 534struct ehci_sitd { 535 /* first part defined by EHCI spec */ 536 __hc32 hw_next; 537/* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 538 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 539 __hc32 hw_uframe; /* EHCI table 3-10 */ 540 __hc32 hw_results; /* EHCI table 3-11 */ 541#define SITD_IOC (1 << 31) /* interrupt on completion */ 542#define SITD_PAGE (1 << 30) /* buffer 0/1 */ 543#define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 544#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 545#define SITD_STS_ERR (1 << 6) /* error from TT */ 546#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 547#define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 548#define SITD_STS_XACT (1 << 3) /* illegal IN response */ 549#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 550#define SITD_STS_STS (1 << 1) /* split transaction state */ 551 552#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 553 554 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 555 __hc32 hw_backpointer; /* EHCI table 3-13 */ 556 __hc32 hw_buf_hi [2]; /* Appendix B */ 557 558 /* the rest is HCD-private */ 559 dma_addr_t sitd_dma; 560 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 561 562 struct urb *urb; 563 struct ehci_iso_stream *stream; /* endpoint's queue */ 564 struct list_head sitd_list; /* list of stream's sitds */ 565 unsigned frame; 566 unsigned index; 567} __attribute__ ((aligned (32))); 568 569/*-------------------------------------------------------------------------*/ 570 571/* 572 * EHCI Specification 0.96 Section 3.7 573 * Periodic Frame Span Traversal Node (FSTN) 574 * 575 * Manages split interrupt transactions (using TT) that span frame boundaries 576 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 577 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 578 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 579 */ 580struct ehci_fstn { 581 __hc32 hw_next; /* any periodic q entry */ 582 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 583 584 /* the rest is HCD-private */ 585 dma_addr_t fstn_dma; 586 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 587} __attribute__ ((aligned (32))); 588 589/*-------------------------------------------------------------------------*/ 590 591/* Prepare the PORTSC wakeup flags during controller suspend/resume */ 592 593#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 594 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 595 596#define ehci_prepare_ports_for_controller_resume(ehci) \ 597 ehci_adjust_port_wakeup_flags(ehci, false, false); 598 599/*-------------------------------------------------------------------------*/ 600 601#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 602 603/* 604 * Some EHCI controllers have a Transaction Translator built into the 605 * root hub. This is a non-standard feature. Each controller will need 606 * to add code to the following inline functions, and call them as 607 * needed (mostly in root hub code). 608 */ 609 610#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 611 612/* Returns the speed of a device attached to a port on the root hub. */ 613static inline unsigned int 614ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 615{ 616 if (ehci_is_TDI(ehci)) { 617 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 618 case 0: 619 return 0; 620 case 1: 621 return USB_PORT_STAT_LOW_SPEED; 622 case 2: 623 default: 624 return USB_PORT_STAT_HIGH_SPEED; 625 } 626 } 627 return USB_PORT_STAT_HIGH_SPEED; 628} 629 630#else 631 632#define ehci_is_TDI(e) (0) 633 634#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 635#endif 636 637/*-------------------------------------------------------------------------*/ 638 639#ifdef CONFIG_PPC_83xx 640/* Some Freescale processors have an erratum in which the TT 641 * port number in the queue head was 0..N-1 instead of 1..N. 642 */ 643#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 644#else 645#define ehci_has_fsl_portno_bug(e) (0) 646#endif 647 648/* 649 * While most USB host controllers implement their registers in 650 * little-endian format, a minority (celleb companion chip) implement 651 * them in big endian format. 652 * 653 * This attempts to support either format at compile time without a 654 * runtime penalty, or both formats with the additional overhead 655 * of checking a flag bit. 656 * 657 * ehci_big_endian_capbase is a special quirk for controllers that 658 * implement the HC capability registers as separate registers and not 659 * as fields of a 32-bit register. 660 */ 661 662#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 663#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 664#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 665#else 666#define ehci_big_endian_mmio(e) 0 667#define ehci_big_endian_capbase(e) 0 668#endif 669 670/* 671 * Big-endian read/write functions are arch-specific. 672 * Other arches can be added if/when they're needed. 673 */ 674#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 675#define readl_be(addr) __raw_readl((__force unsigned *)addr) 676#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 677#endif 678 679static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 680 __u32 __iomem * regs) 681{ 682#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 683 return ehci_big_endian_mmio(ehci) ? 684 readl_be(regs) : 685 readl(regs); 686#else 687 return readl(regs); 688#endif 689} 690 691static inline void ehci_writel(const struct ehci_hcd *ehci, 692 const unsigned int val, __u32 __iomem *regs) 693{ 694#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 695 ehci_big_endian_mmio(ehci) ? 696 writel_be(val, regs) : 697 writel(val, regs); 698#else 699 writel(val, regs); 700#endif 701} 702 703/* 704 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 705 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 706 * Other common bits are dependent on has_amcc_usb23 quirk flag. 707 */ 708#ifdef CONFIG_44x 709static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 710{ 711 u32 hc_control; 712 713 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 714 if (operational) 715 hc_control |= OHCI_USB_OPER; 716 else 717 hc_control |= OHCI_USB_SUSPEND; 718 719 writel_be(hc_control, ehci->ohci_hcctrl_reg); 720 (void) readl_be(ehci->ohci_hcctrl_reg); 721} 722#else 723static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 724{ } 725#endif 726 727/*-------------------------------------------------------------------------*/ 728 729/* 730 * The AMCC 440EPx not only implements its EHCI registers in big-endian 731 * format, but also its DMA data structures (descriptors). 732 * 733 * EHCI controllers accessed through PCI work normally (little-endian 734 * everywhere), so we won't bother supporting a BE-only mode for now. 735 */ 736#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 737#define ehci_big_endian_desc(e) ((e)->big_endian_desc) 738 739/* cpu to ehci */ 740static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 741{ 742 return ehci_big_endian_desc(ehci) 743 ? (__force __hc32)cpu_to_be32(x) 744 : (__force __hc32)cpu_to_le32(x); 745} 746 747/* ehci to cpu */ 748static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 749{ 750 return ehci_big_endian_desc(ehci) 751 ? be32_to_cpu((__force __be32)x) 752 : le32_to_cpu((__force __le32)x); 753} 754 755static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 756{ 757 return ehci_big_endian_desc(ehci) 758 ? be32_to_cpup((__force __be32 *)x) 759 : le32_to_cpup((__force __le32 *)x); 760} 761 762#else 763 764/* cpu to ehci */ 765static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 766{ 767 return cpu_to_le32(x); 768} 769 770/* ehci to cpu */ 771static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 772{ 773 return le32_to_cpu(x); 774} 775 776static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 777{ 778 return le32_to_cpup(x); 779} 780 781#endif 782 783/*-------------------------------------------------------------------------*/ 784 785#ifdef CONFIG_PCI 786 787/* For working around the MosChip frame-index-register bug */ 788static unsigned ehci_read_frame_index(struct ehci_hcd *ehci); 789 790#else 791 792static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci) 793{ 794 return ehci_readl(ehci, &ehci->regs->frame_index); 795} 796 797#endif 798 799/*-------------------------------------------------------------------------*/ 800 801#ifndef DEBUG 802#define STUB_DEBUG_FILES 803#endif /* DEBUG */ 804 805/*-------------------------------------------------------------------------*/ 806 807#endif /* __LINUX_EHCI_HCD_H */ 808