ehci.h revision 9be0392989306361d4a63a06a8ee281efbead548
1/* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#ifndef __LINUX_EHCI_HCD_H 20#define __LINUX_EHCI_HCD_H 21 22/* definitions used for the EHCI driver */ 23 24/* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33typedef __u32 __bitwise __hc32; 34typedef __u16 __bitwise __hc16; 35#else 36#define __hc32 __le32 37#define __hc16 __le16 38#endif 39 40/* statistics can be kept for tuning/monitoring */ 41struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long reclaim; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51}; 52 53/* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, reclaim, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65struct ehci_hcd { /* one per controller */ 66 /* glue to PCI and HCD framework */ 67 struct ehci_caps __iomem *caps; 68 struct ehci_regs __iomem *regs; 69 struct ehci_dbg_port __iomem *debug; 70 71 __u32 hcs_params; /* cached register copy */ 72 spinlock_t lock; 73 74 /* async schedule support */ 75 struct ehci_qh *async; 76 struct ehci_qh *dummy; /* For AMD quirk use */ 77 struct ehci_qh *reclaim; 78 unsigned scanning : 1; 79 80 /* periodic schedule support */ 81#define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 82 unsigned periodic_size; 83 __hc32 *periodic; /* hw periodic table */ 84 dma_addr_t periodic_dma; 85 unsigned i_thresh; /* uframes HC might cache */ 86 87 union ehci_shadow *pshadow; /* mirror hw periodic table */ 88 int next_uframe; /* scan periodic, start here */ 89 unsigned periodic_sched; /* periodic activity count */ 90 91 /* list of itds & sitds completed while clock_frame was still active */ 92 struct list_head cached_itd_list; 93 struct list_head cached_sitd_list; 94 unsigned clock_frame; 95 96 /* per root hub port */ 97 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 98 99 /* bit vectors (one bit per port) */ 100 unsigned long bus_suspended; /* which ports were 101 already suspended at the start of a bus suspend */ 102 unsigned long companion_ports; /* which ports are 103 dedicated to the companion controller */ 104 unsigned long owned_ports; /* which ports are 105 owned by the companion during a bus suspend */ 106 unsigned long port_c_suspend; /* which ports have 107 the change-suspend feature turned on */ 108 unsigned long suspended_ports; /* which ports are 109 suspended */ 110 111 /* per-HC memory pools (could be per-bus, but ...) */ 112 struct dma_pool *qh_pool; /* qh per active urb */ 113 struct dma_pool *qtd_pool; /* one or more per qh */ 114 struct dma_pool *itd_pool; /* itd per iso urb */ 115 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 116 117 struct timer_list iaa_watchdog; 118 struct timer_list watchdog; 119 unsigned long actions; 120 unsigned stamp; 121 unsigned random_frame; 122 unsigned long next_statechange; 123 ktime_t last_periodic_enable; 124 u32 command; 125 126 /* SILICON QUIRKS */ 127 unsigned no_selective_suspend:1; 128 unsigned has_fsl_port_bug:1; /* FreeScale */ 129 unsigned big_endian_mmio:1; 130 unsigned big_endian_desc:1; 131 unsigned big_endian_capbase:1; 132 unsigned has_amcc_usb23:1; 133 unsigned need_io_watchdog:1; 134 unsigned broken_periodic:1; 135 unsigned amd_pll_fix:1; 136 unsigned fs_i_thresh:1; /* Intel iso scheduling */ 137 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 138 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 139 140 /* required for usb32 quirk */ 141 #define OHCI_CTRL_HCFS (3 << 6) 142 #define OHCI_USB_OPER (2 << 6) 143 #define OHCI_USB_SUSPEND (3 << 6) 144 145 #define OHCI_HCCTRL_OFFSET 0x4 146 #define OHCI_HCCTRL_LEN 0x4 147 __hc32 *ohci_hcctrl_reg; 148 unsigned has_hostpc:1; 149 unsigned has_lpm:1; /* support link power management */ 150 unsigned has_ppcd:1; /* support per-port change bits */ 151 u8 sbrn; /* packed release number */ 152 153 /* irq statistics */ 154#ifdef EHCI_STATS 155 struct ehci_stats stats; 156# define COUNT(x) do { (x)++; } while (0) 157#else 158# define COUNT(x) do {} while (0) 159#endif 160 161 /* debug files */ 162#ifdef DEBUG 163 struct dentry *debug_dir; 164#endif 165 /* 166 * OTG controllers and transceivers need software interaction 167 */ 168 struct otg_transceiver *transceiver; 169}; 170 171/* convert between an HCD pointer and the corresponding EHCI_HCD */ 172static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 173{ 174 return (struct ehci_hcd *) (hcd->hcd_priv); 175} 176static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 177{ 178 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 179} 180 181 182static inline void 183iaa_watchdog_start(struct ehci_hcd *ehci) 184{ 185 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 186 mod_timer(&ehci->iaa_watchdog, 187 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 188} 189 190static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 191{ 192 del_timer(&ehci->iaa_watchdog); 193} 194 195enum ehci_timer_action { 196 TIMER_IO_WATCHDOG, 197 TIMER_ASYNC_SHRINK, 198 TIMER_ASYNC_OFF, 199}; 200 201static inline void 202timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 203{ 204 clear_bit (action, &ehci->actions); 205} 206 207static void free_cached_lists(struct ehci_hcd *ehci); 208 209/*-------------------------------------------------------------------------*/ 210 211#include <linux/usb/ehci_def.h> 212 213/*-------------------------------------------------------------------------*/ 214 215#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 216 217/* 218 * EHCI Specification 0.95 Section 3.5 219 * QTD: describe data transfer components (buffer, direction, ...) 220 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 221 * 222 * These are associated only with "QH" (Queue Head) structures, 223 * used with control, bulk, and interrupt transfers. 224 */ 225struct ehci_qtd { 226 /* first part defined by EHCI spec */ 227 __hc32 hw_next; /* see EHCI 3.5.1 */ 228 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 229 __hc32 hw_token; /* see EHCI 3.5.3 */ 230#define QTD_TOGGLE (1 << 31) /* data toggle */ 231#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 232#define QTD_IOC (1 << 15) /* interrupt on complete */ 233#define QTD_CERR(tok) (((tok)>>10) & 0x3) 234#define QTD_PID(tok) (((tok)>>8) & 0x3) 235#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 236#define QTD_STS_HALT (1 << 6) /* halted on error */ 237#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 238#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 239#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 240#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 241#define QTD_STS_STS (1 << 1) /* split transaction state */ 242#define QTD_STS_PING (1 << 0) /* issue PING? */ 243 244#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 245#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 246#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 247 248 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 249 __hc32 hw_buf_hi [5]; /* Appendix B */ 250 251 /* the rest is HCD-private */ 252 dma_addr_t qtd_dma; /* qtd address */ 253 struct list_head qtd_list; /* sw qtd list */ 254 struct urb *urb; /* qtd's urb */ 255 size_t length; /* length of buffer */ 256} __attribute__ ((aligned (32))); 257 258/* mask NakCnt+T in qh->hw_alt_next */ 259#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 260 261#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 262 263/*-------------------------------------------------------------------------*/ 264 265/* type tag from {qh,itd,sitd,fstn}->hw_next */ 266#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 267 268/* 269 * Now the following defines are not converted using the 270 * cpu_to_le32() macro anymore, since we have to support 271 * "dynamic" switching between be and le support, so that the driver 272 * can be used on one system with SoC EHCI controller using big-endian 273 * descriptors as well as a normal little-endian PCI EHCI controller. 274 */ 275/* values for that type tag */ 276#define Q_TYPE_ITD (0 << 1) 277#define Q_TYPE_QH (1 << 1) 278#define Q_TYPE_SITD (2 << 1) 279#define Q_TYPE_FSTN (3 << 1) 280 281/* next async queue entry, or pointer to interrupt/periodic QH */ 282#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 283 284/* for periodic/async schedules and qtd lists, mark end of list */ 285#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 286 287/* 288 * Entries in periodic shadow table are pointers to one of four kinds 289 * of data structure. That's dictated by the hardware; a type tag is 290 * encoded in the low bits of the hardware's periodic schedule. Use 291 * Q_NEXT_TYPE to get the tag. 292 * 293 * For entries in the async schedule, the type tag always says "qh". 294 */ 295union ehci_shadow { 296 struct ehci_qh *qh; /* Q_TYPE_QH */ 297 struct ehci_itd *itd; /* Q_TYPE_ITD */ 298 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 299 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 300 __hc32 *hw_next; /* (all types) */ 301 void *ptr; 302}; 303 304/*-------------------------------------------------------------------------*/ 305 306/* 307 * EHCI Specification 0.95 Section 3.6 308 * QH: describes control/bulk/interrupt endpoints 309 * See Fig 3-7 "Queue Head Structure Layout". 310 * 311 * These appear in both the async and (for interrupt) periodic schedules. 312 */ 313 314/* first part defined by EHCI spec */ 315struct ehci_qh_hw { 316 __hc32 hw_next; /* see EHCI 3.6.1 */ 317 __hc32 hw_info1; /* see EHCI 3.6.2 */ 318#define QH_HEAD 0x00008000 319 __hc32 hw_info2; /* see EHCI 3.6.2 */ 320#define QH_SMASK 0x000000ff 321#define QH_CMASK 0x0000ff00 322#define QH_HUBADDR 0x007f0000 323#define QH_HUBPORT 0x3f800000 324#define QH_MULT 0xc0000000 325 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 326 327 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 328 __hc32 hw_qtd_next; 329 __hc32 hw_alt_next; 330 __hc32 hw_token; 331 __hc32 hw_buf [5]; 332 __hc32 hw_buf_hi [5]; 333} __attribute__ ((aligned(32))); 334 335struct ehci_qh { 336 struct ehci_qh_hw *hw; 337 /* the rest is HCD-private */ 338 dma_addr_t qh_dma; /* address of qh */ 339 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 340 struct list_head qtd_list; /* sw qtd list */ 341 struct ehci_qtd *dummy; 342 struct ehci_qh *reclaim; /* next to reclaim */ 343 344 struct ehci_hcd *ehci; 345 346 /* 347 * Do NOT use atomic operations for QH refcounting. On some CPUs 348 * (PPC7448 for example), atomic operations cannot be performed on 349 * memory that is cache-inhibited (i.e. being used for DMA). 350 * Spinlocks are used to protect all QH fields. 351 */ 352 u32 refcount; 353 unsigned stamp; 354 355 u8 needs_rescan; /* Dequeue during giveback */ 356 u8 qh_state; 357#define QH_STATE_LINKED 1 /* HC sees this */ 358#define QH_STATE_UNLINK 2 /* HC may still see this */ 359#define QH_STATE_IDLE 3 /* HC doesn't see this */ 360#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 361#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 362 363 u8 xacterrs; /* XactErr retry counter */ 364#define QH_XACTERR_MAX 32 /* XactErr retry limit */ 365 366 /* periodic schedule info */ 367 u8 usecs; /* intr bandwidth */ 368 u8 gap_uf; /* uframes split/csplit gap */ 369 u8 c_usecs; /* ... split completion bw */ 370 u16 tt_usecs; /* tt downstream bandwidth */ 371 unsigned short period; /* polling interval */ 372 unsigned short start; /* where polling starts */ 373#define NO_FRAME ((unsigned short)~0) /* pick new start */ 374 375 struct usb_device *dev; /* access to TT */ 376 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 377}; 378 379/*-------------------------------------------------------------------------*/ 380 381/* description of one iso transaction (up to 3 KB data if highspeed) */ 382struct ehci_iso_packet { 383 /* These will be copied to iTD when scheduling */ 384 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 385 __hc32 transaction; /* itd->hw_transaction[i] |= */ 386 u8 cross; /* buf crosses pages */ 387 /* for full speed OUT splits */ 388 u32 buf1; 389}; 390 391/* temporary schedule data for packets from iso urbs (both speeds) 392 * each packet is one logical usb transaction to the device (not TT), 393 * beginning at stream->next_uframe 394 */ 395struct ehci_iso_sched { 396 struct list_head td_list; 397 unsigned span; 398 struct ehci_iso_packet packet [0]; 399}; 400 401/* 402 * ehci_iso_stream - groups all (s)itds for this endpoint. 403 * acts like a qh would, if EHCI had them for ISO. 404 */ 405struct ehci_iso_stream { 406 /* first field matches ehci_hq, but is NULL */ 407 struct ehci_qh_hw *hw; 408 409 u32 refcount; 410 u8 bEndpointAddress; 411 u8 highspeed; 412 struct list_head td_list; /* queued itds/sitds */ 413 struct list_head free_list; /* list of unused itds/sitds */ 414 struct usb_device *udev; 415 struct usb_host_endpoint *ep; 416 417 /* output of (re)scheduling */ 418 int next_uframe; 419 __hc32 splits; 420 421 /* the rest is derived from the endpoint descriptor, 422 * trusting urb->interval == f(epdesc->bInterval) and 423 * including the extra info for hw_bufp[0..2] 424 */ 425 u8 usecs, c_usecs; 426 u16 interval; 427 u16 tt_usecs; 428 u16 maxp; 429 u16 raw_mask; 430 unsigned bandwidth; 431 432 /* This is used to initialize iTD's hw_bufp fields */ 433 __hc32 buf0; 434 __hc32 buf1; 435 __hc32 buf2; 436 437 /* this is used to initialize sITD's tt info */ 438 __hc32 address; 439}; 440 441/*-------------------------------------------------------------------------*/ 442 443/* 444 * EHCI Specification 0.95 Section 3.3 445 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 446 * 447 * Schedule records for high speed iso xfers 448 */ 449struct ehci_itd { 450 /* first part defined by EHCI spec */ 451 __hc32 hw_next; /* see EHCI 3.3.1 */ 452 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 453#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 454#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 455#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 456#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 457#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 458#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 459 460#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 461 462 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 463 __hc32 hw_bufp_hi [7]; /* Appendix B */ 464 465 /* the rest is HCD-private */ 466 dma_addr_t itd_dma; /* for this itd */ 467 union ehci_shadow itd_next; /* ptr to periodic q entry */ 468 469 struct urb *urb; 470 struct ehci_iso_stream *stream; /* endpoint's queue */ 471 struct list_head itd_list; /* list of stream's itds */ 472 473 /* any/all hw_transactions here may be used by that urb */ 474 unsigned frame; /* where scheduled */ 475 unsigned pg; 476 unsigned index[8]; /* in urb->iso_frame_desc */ 477} __attribute__ ((aligned (32))); 478 479/*-------------------------------------------------------------------------*/ 480 481/* 482 * EHCI Specification 0.95 Section 3.4 483 * siTD, aka split-transaction isochronous Transfer Descriptor 484 * ... describe full speed iso xfers through TT in hubs 485 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 486 */ 487struct ehci_sitd { 488 /* first part defined by EHCI spec */ 489 __hc32 hw_next; 490/* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 491 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 492 __hc32 hw_uframe; /* EHCI table 3-10 */ 493 __hc32 hw_results; /* EHCI table 3-11 */ 494#define SITD_IOC (1 << 31) /* interrupt on completion */ 495#define SITD_PAGE (1 << 30) /* buffer 0/1 */ 496#define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 497#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 498#define SITD_STS_ERR (1 << 6) /* error from TT */ 499#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 500#define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 501#define SITD_STS_XACT (1 << 3) /* illegal IN response */ 502#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 503#define SITD_STS_STS (1 << 1) /* split transaction state */ 504 505#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 506 507 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 508 __hc32 hw_backpointer; /* EHCI table 3-13 */ 509 __hc32 hw_buf_hi [2]; /* Appendix B */ 510 511 /* the rest is HCD-private */ 512 dma_addr_t sitd_dma; 513 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 514 515 struct urb *urb; 516 struct ehci_iso_stream *stream; /* endpoint's queue */ 517 struct list_head sitd_list; /* list of stream's sitds */ 518 unsigned frame; 519 unsigned index; 520} __attribute__ ((aligned (32))); 521 522/*-------------------------------------------------------------------------*/ 523 524/* 525 * EHCI Specification 0.96 Section 3.7 526 * Periodic Frame Span Traversal Node (FSTN) 527 * 528 * Manages split interrupt transactions (using TT) that span frame boundaries 529 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 530 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 531 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 532 */ 533struct ehci_fstn { 534 __hc32 hw_next; /* any periodic q entry */ 535 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 536 537 /* the rest is HCD-private */ 538 dma_addr_t fstn_dma; 539 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 540} __attribute__ ((aligned (32))); 541 542/*-------------------------------------------------------------------------*/ 543 544/* Prepare the PORTSC wakeup flags during controller suspend/resume */ 545 546#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 547 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 548 549#define ehci_prepare_ports_for_controller_resume(ehci) \ 550 ehci_adjust_port_wakeup_flags(ehci, false, false); 551 552/*-------------------------------------------------------------------------*/ 553 554#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 555 556/* 557 * Some EHCI controllers have a Transaction Translator built into the 558 * root hub. This is a non-standard feature. Each controller will need 559 * to add code to the following inline functions, and call them as 560 * needed (mostly in root hub code). 561 */ 562 563#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 564 565/* Returns the speed of a device attached to a port on the root hub. */ 566static inline unsigned int 567ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 568{ 569 if (ehci_is_TDI(ehci)) { 570 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 571 case 0: 572 return 0; 573 case 1: 574 return USB_PORT_STAT_LOW_SPEED; 575 case 2: 576 default: 577 return USB_PORT_STAT_HIGH_SPEED; 578 } 579 } 580 return USB_PORT_STAT_HIGH_SPEED; 581} 582 583#else 584 585#define ehci_is_TDI(e) (0) 586 587#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 588#endif 589 590/*-------------------------------------------------------------------------*/ 591 592#ifdef CONFIG_PPC_83xx 593/* Some Freescale processors have an erratum in which the TT 594 * port number in the queue head was 0..N-1 instead of 1..N. 595 */ 596#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 597#else 598#define ehci_has_fsl_portno_bug(e) (0) 599#endif 600 601/* 602 * While most USB host controllers implement their registers in 603 * little-endian format, a minority (celleb companion chip) implement 604 * them in big endian format. 605 * 606 * This attempts to support either format at compile time without a 607 * runtime penalty, or both formats with the additional overhead 608 * of checking a flag bit. 609 * 610 * ehci_big_endian_capbase is a special quirk for controllers that 611 * implement the HC capability registers as separate registers and not 612 * as fields of a 32-bit register. 613 */ 614 615#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 616#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 617#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 618#else 619#define ehci_big_endian_mmio(e) 0 620#define ehci_big_endian_capbase(e) 0 621#endif 622 623/* 624 * Big-endian read/write functions are arch-specific. 625 * Other arches can be added if/when they're needed. 626 */ 627#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 628#define readl_be(addr) __raw_readl((__force unsigned *)addr) 629#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 630#elif defined(CONFIG_SPARC_LEON) 631#define readl_be(addr) __raw_readl(addr) 632#define writel_be(val, addr) __raw_writel(val, addr) 633#endif 634 635static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 636 __u32 __iomem * regs) 637{ 638#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 639 return ehci_big_endian_mmio(ehci) ? 640 readl_be(regs) : 641 readl(regs); 642#else 643 return readl(regs); 644#endif 645} 646 647static inline void ehci_writel(const struct ehci_hcd *ehci, 648 const unsigned int val, __u32 __iomem *regs) 649{ 650#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 651 ehci_big_endian_mmio(ehci) ? 652 writel_be(val, regs) : 653 writel(val, regs); 654#else 655 writel(val, regs); 656#endif 657} 658 659/* 660 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 661 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 662 * Other common bits are dependent on has_amcc_usb23 quirk flag. 663 */ 664#ifdef CONFIG_44x 665static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 666{ 667 u32 hc_control; 668 669 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 670 if (operational) 671 hc_control |= OHCI_USB_OPER; 672 else 673 hc_control |= OHCI_USB_SUSPEND; 674 675 writel_be(hc_control, ehci->ohci_hcctrl_reg); 676 (void) readl_be(ehci->ohci_hcctrl_reg); 677} 678#else 679static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 680{ } 681#endif 682 683/*-------------------------------------------------------------------------*/ 684 685/* 686 * The AMCC 440EPx not only implements its EHCI registers in big-endian 687 * format, but also its DMA data structures (descriptors). 688 * 689 * EHCI controllers accessed through PCI work normally (little-endian 690 * everywhere), so we won't bother supporting a BE-only mode for now. 691 */ 692#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 693#define ehci_big_endian_desc(e) ((e)->big_endian_desc) 694 695/* cpu to ehci */ 696static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 697{ 698 return ehci_big_endian_desc(ehci) 699 ? (__force __hc32)cpu_to_be32(x) 700 : (__force __hc32)cpu_to_le32(x); 701} 702 703/* ehci to cpu */ 704static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 705{ 706 return ehci_big_endian_desc(ehci) 707 ? be32_to_cpu((__force __be32)x) 708 : le32_to_cpu((__force __le32)x); 709} 710 711static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 712{ 713 return ehci_big_endian_desc(ehci) 714 ? be32_to_cpup((__force __be32 *)x) 715 : le32_to_cpup((__force __le32 *)x); 716} 717 718#else 719 720/* cpu to ehci */ 721static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 722{ 723 return cpu_to_le32(x); 724} 725 726/* ehci to cpu */ 727static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 728{ 729 return le32_to_cpu(x); 730} 731 732static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 733{ 734 return le32_to_cpup(x); 735} 736 737#endif 738 739/*-------------------------------------------------------------------------*/ 740 741#ifndef DEBUG 742#define STUB_DEBUG_FILES 743#endif /* DEBUG */ 744 745/*-------------------------------------------------------------------------*/ 746 747#endif /* __LINUX_EHCI_HCD_H */ 748