ehci.h revision c06d4dcf5034ee2289a921b9b2c547f3fed2d878
1/* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#ifndef __LINUX_EHCI_HCD_H 20#define __LINUX_EHCI_HCD_H 21 22/* definitions used for the EHCI driver */ 23 24/* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33typedef __u32 __bitwise __hc32; 34typedef __u16 __bitwise __hc16; 35#else 36#define __hc32 __le32 37#define __hc16 __le16 38#endif 39 40/* statistics can be kept for for tuning/monitoring */ 41struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long reclaim; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51}; 52 53/* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, reclaim, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65struct ehci_hcd { /* one per controller */ 66 /* glue to PCI and HCD framework */ 67 struct ehci_caps __iomem *caps; 68 struct ehci_regs __iomem *regs; 69 struct ehci_dbg_port __iomem *debug; 70 71 __u32 hcs_params; /* cached register copy */ 72 spinlock_t lock; 73 74 /* async schedule support */ 75 struct ehci_qh *async; 76 struct ehci_qh *reclaim; 77 unsigned scanning : 1; 78 79 /* periodic schedule support */ 80#define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 81 unsigned periodic_size; 82 __hc32 *periodic; /* hw periodic table */ 83 dma_addr_t periodic_dma; 84 unsigned i_thresh; /* uframes HC might cache */ 85 86 union ehci_shadow *pshadow; /* mirror hw periodic table */ 87 int next_uframe; /* scan periodic, start here */ 88 unsigned periodic_sched; /* periodic activity count */ 89 90 /* per root hub port */ 91 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 92 93 /* bit vectors (one bit per port) */ 94 unsigned long bus_suspended; /* which ports were 95 already suspended at the start of a bus suspend */ 96 unsigned long companion_ports; /* which ports are 97 dedicated to the companion controller */ 98 unsigned long owned_ports; /* which ports are 99 owned by the companion during a bus suspend */ 100 101 /* per-HC memory pools (could be per-bus, but ...) */ 102 struct dma_pool *qh_pool; /* qh per active urb */ 103 struct dma_pool *qtd_pool; /* one or more per qh */ 104 struct dma_pool *itd_pool; /* itd per iso urb */ 105 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 106 107 struct timer_list iaa_watchdog; 108 struct timer_list watchdog; 109 unsigned long actions; 110 unsigned stamp; 111 unsigned long next_statechange; 112 u32 command; 113 114 /* SILICON QUIRKS */ 115 unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */ 116 unsigned no_selective_suspend:1; 117 unsigned has_fsl_port_bug:1; /* FreeScale */ 118 unsigned big_endian_mmio:1; 119 unsigned big_endian_desc:1; 120 121 u8 sbrn; /* packed release number */ 122 123 /* irq statistics */ 124#ifdef EHCI_STATS 125 struct ehci_stats stats; 126# define COUNT(x) do { (x)++; } while (0) 127#else 128# define COUNT(x) do {} while (0) 129#endif 130 131 /* debug files */ 132#ifdef DEBUG 133 struct dentry *debug_dir; 134 struct dentry *debug_async; 135 struct dentry *debug_periodic; 136 struct dentry *debug_registers; 137#endif 138}; 139 140/* convert between an HCD pointer and the corresponding EHCI_HCD */ 141static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 142{ 143 return (struct ehci_hcd *) (hcd->hcd_priv); 144} 145static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 146{ 147 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 148} 149 150 151static inline void 152iaa_watchdog_start(struct ehci_hcd *ehci) 153{ 154 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 155 mod_timer(&ehci->iaa_watchdog, 156 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 157} 158 159static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 160{ 161 del_timer(&ehci->iaa_watchdog); 162} 163 164enum ehci_timer_action { 165 TIMER_IO_WATCHDOG, 166 TIMER_ASYNC_SHRINK, 167 TIMER_ASYNC_OFF, 168}; 169 170static inline void 171timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 172{ 173 clear_bit (action, &ehci->actions); 174} 175 176static inline void 177timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) 178{ 179 if (!test_and_set_bit (action, &ehci->actions)) { 180 unsigned long t; 181 182 switch (action) { 183 case TIMER_IO_WATCHDOG: 184 t = EHCI_IO_JIFFIES; 185 break; 186 case TIMER_ASYNC_OFF: 187 t = EHCI_ASYNC_JIFFIES; 188 break; 189 // case TIMER_ASYNC_SHRINK: 190 default: 191 t = EHCI_SHRINK_JIFFIES; 192 break; 193 } 194 t += jiffies; 195 // all timings except IAA watchdog can be overridden. 196 // async queue SHRINK often precedes IAA. while it's ready 197 // to go OFF neither can matter, and afterwards the IO 198 // watchdog stops unless there's still periodic traffic. 199 if (time_before_eq(t, ehci->watchdog.expires) 200 && timer_pending (&ehci->watchdog)) 201 return; 202 mod_timer (&ehci->watchdog, t); 203 } 204} 205 206/*-------------------------------------------------------------------------*/ 207 208/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ 209 210/* Section 2.2 Host Controller Capability Registers */ 211struct ehci_caps { 212 /* these fields are specified as 8 and 16 bit registers, 213 * but some hosts can't perform 8 or 16 bit PCI accesses. 214 */ 215 u32 hc_capbase; 216#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 217#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ 218 u32 hcs_params; /* HCSPARAMS - offset 0x4 */ 219#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ 220#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 221#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ 222#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ 223#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ 224#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 225#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 226 227 u32 hcc_params; /* HCCPARAMS - offset 0x8 */ 228#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ 229#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 230#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 231#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ 232#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ 233#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ 234 u8 portroute [8]; /* nibbles for routing - offset 0xC */ 235} __attribute__ ((packed)); 236 237 238/* Section 2.3 Host Controller Operational Registers */ 239struct ehci_regs { 240 241 /* USBCMD: offset 0x00 */ 242 u32 command; 243/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ 244#define CMD_PARK (1<<11) /* enable "park" on async qh */ 245#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ 246#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 247#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ 248#define CMD_ASE (1<<5) /* async schedule enable */ 249#define CMD_PSE (1<<4) /* periodic schedule enable */ 250/* 3:2 is periodic frame list size */ 251#define CMD_RESET (1<<1) /* reset HC not bus */ 252#define CMD_RUN (1<<0) /* start/stop HC */ 253 254 /* USBSTS: offset 0x04 */ 255 u32 status; 256#define STS_ASS (1<<15) /* Async Schedule Status */ 257#define STS_PSS (1<<14) /* Periodic Schedule Status */ 258#define STS_RECL (1<<13) /* Reclamation */ 259#define STS_HALT (1<<12) /* Not running (any reason) */ 260/* some bits reserved */ 261 /* these STS_* flags are also intr_enable bits (USBINTR) */ 262#define STS_IAA (1<<5) /* Interrupted on async advance */ 263#define STS_FATAL (1<<4) /* such as some PCI access errors */ 264#define STS_FLR (1<<3) /* frame list rolled over */ 265#define STS_PCD (1<<2) /* port change detect */ 266#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ 267#define STS_INT (1<<0) /* "normal" completion (short, ...) */ 268 269 /* USBINTR: offset 0x08 */ 270 u32 intr_enable; 271 272 /* FRINDEX: offset 0x0C */ 273 u32 frame_index; /* current microframe number */ 274 /* CTRLDSSEGMENT: offset 0x10 */ 275 u32 segment; /* address bits 63:32 if needed */ 276 /* PERIODICLISTBASE: offset 0x14 */ 277 u32 frame_list; /* points to periodic list */ 278 /* ASYNCLISTADDR: offset 0x18 */ 279 u32 async_next; /* address of next async queue head */ 280 281 u32 reserved [9]; 282 283 /* CONFIGFLAG: offset 0x40 */ 284 u32 configured_flag; 285#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 286 287 /* PORTSC: offset 0x44 */ 288 u32 port_status [0]; /* up to N_PORTS */ 289/* 31:23 reserved */ 290#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ 291#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ 292#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ 293/* 19:16 for port testing */ 294#define PORT_LED_OFF (0<<14) 295#define PORT_LED_AMBER (1<<14) 296#define PORT_LED_GREEN (2<<14) 297#define PORT_LED_MASK (3<<14) 298#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 299#define PORT_POWER (1<<12) /* true: has power (see PPC) */ 300#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */ 301/* 11:10 for detecting lowspeed devices (reset vs release ownership) */ 302/* 9 reserved */ 303#define PORT_RESET (1<<8) /* reset port */ 304#define PORT_SUSPEND (1<<7) /* suspend port */ 305#define PORT_RESUME (1<<6) /* resume it */ 306#define PORT_OCC (1<<5) /* over current change */ 307#define PORT_OC (1<<4) /* over current active */ 308#define PORT_PEC (1<<3) /* port enable change */ 309#define PORT_PE (1<<2) /* port enable */ 310#define PORT_CSC (1<<1) /* connect status change */ 311#define PORT_CONNECT (1<<0) /* device connected */ 312#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 313} __attribute__ ((packed)); 314 315#define USBMODE 0x68 /* USB Device mode */ 316#define USBMODE_SDIS (1<<3) /* Stream disable */ 317#define USBMODE_BE (1<<2) /* BE/LE endianness select */ 318#define USBMODE_CM_HC (3<<0) /* host controller mode */ 319#define USBMODE_CM_IDLE (0<<0) /* idle state */ 320 321/* Appendix C, Debug port ... intended for use with special "debug devices" 322 * that can help if there's no serial console. (nonstandard enumeration.) 323 */ 324struct ehci_dbg_port { 325 u32 control; 326#define DBGP_OWNER (1<<30) 327#define DBGP_ENABLED (1<<28) 328#define DBGP_DONE (1<<16) 329#define DBGP_INUSE (1<<10) 330#define DBGP_ERRCODE(x) (((x)>>7)&0x07) 331# define DBGP_ERR_BAD 1 332# define DBGP_ERR_SIGNAL 2 333#define DBGP_ERROR (1<<6) 334#define DBGP_GO (1<<5) 335#define DBGP_OUT (1<<4) 336#define DBGP_LEN(x) (((x)>>0)&0x0f) 337 u32 pids; 338#define DBGP_PID_GET(x) (((x)>>16)&0xff) 339#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)) 340 u32 data03; 341 u32 data47; 342 u32 address; 343#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)) 344} __attribute__ ((packed)); 345 346/*-------------------------------------------------------------------------*/ 347 348#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 349 350/* 351 * EHCI Specification 0.95 Section 3.5 352 * QTD: describe data transfer components (buffer, direction, ...) 353 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 354 * 355 * These are associated only with "QH" (Queue Head) structures, 356 * used with control, bulk, and interrupt transfers. 357 */ 358struct ehci_qtd { 359 /* first part defined by EHCI spec */ 360 __hc32 hw_next; /* see EHCI 3.5.1 */ 361 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 362 __hc32 hw_token; /* see EHCI 3.5.3 */ 363#define QTD_TOGGLE (1 << 31) /* data toggle */ 364#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 365#define QTD_IOC (1 << 15) /* interrupt on complete */ 366#define QTD_CERR(tok) (((tok)>>10) & 0x3) 367#define QTD_PID(tok) (((tok)>>8) & 0x3) 368#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 369#define QTD_STS_HALT (1 << 6) /* halted on error */ 370#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 371#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 372#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 373#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 374#define QTD_STS_STS (1 << 1) /* split transaction state */ 375#define QTD_STS_PING (1 << 0) /* issue PING? */ 376 377#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 378#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 379#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 380 381 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 382 __hc32 hw_buf_hi [5]; /* Appendix B */ 383 384 /* the rest is HCD-private */ 385 dma_addr_t qtd_dma; /* qtd address */ 386 struct list_head qtd_list; /* sw qtd list */ 387 struct urb *urb; /* qtd's urb */ 388 size_t length; /* length of buffer */ 389} __attribute__ ((aligned (32))); 390 391/* mask NakCnt+T in qh->hw_alt_next */ 392#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 393 394#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 395 396/*-------------------------------------------------------------------------*/ 397 398/* type tag from {qh,itd,sitd,fstn}->hw_next */ 399#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 400 401/* 402 * Now the following defines are not converted using the 403 * __constant_cpu_to_le32() macro anymore, since we have to support 404 * "dynamic" switching between be and le support, so that the driver 405 * can be used on one system with SoC EHCI controller using big-endian 406 * descriptors as well as a normal little-endian PCI EHCI controller. 407 */ 408/* values for that type tag */ 409#define Q_TYPE_ITD (0 << 1) 410#define Q_TYPE_QH (1 << 1) 411#define Q_TYPE_SITD (2 << 1) 412#define Q_TYPE_FSTN (3 << 1) 413 414/* next async queue entry, or pointer to interrupt/periodic QH */ 415#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 416 417/* for periodic/async schedules and qtd lists, mark end of list */ 418#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 419 420/* 421 * Entries in periodic shadow table are pointers to one of four kinds 422 * of data structure. That's dictated by the hardware; a type tag is 423 * encoded in the low bits of the hardware's periodic schedule. Use 424 * Q_NEXT_TYPE to get the tag. 425 * 426 * For entries in the async schedule, the type tag always says "qh". 427 */ 428union ehci_shadow { 429 struct ehci_qh *qh; /* Q_TYPE_QH */ 430 struct ehci_itd *itd; /* Q_TYPE_ITD */ 431 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 432 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 433 __hc32 *hw_next; /* (all types) */ 434 void *ptr; 435}; 436 437/*-------------------------------------------------------------------------*/ 438 439/* 440 * EHCI Specification 0.95 Section 3.6 441 * QH: describes control/bulk/interrupt endpoints 442 * See Fig 3-7 "Queue Head Structure Layout". 443 * 444 * These appear in both the async and (for interrupt) periodic schedules. 445 */ 446 447struct ehci_qh { 448 /* first part defined by EHCI spec */ 449 __hc32 hw_next; /* see EHCI 3.6.1 */ 450 __hc32 hw_info1; /* see EHCI 3.6.2 */ 451#define QH_HEAD 0x00008000 452 __hc32 hw_info2; /* see EHCI 3.6.2 */ 453#define QH_SMASK 0x000000ff 454#define QH_CMASK 0x0000ff00 455#define QH_HUBADDR 0x007f0000 456#define QH_HUBPORT 0x3f800000 457#define QH_MULT 0xc0000000 458 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 459 460 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 461 __hc32 hw_qtd_next; 462 __hc32 hw_alt_next; 463 __hc32 hw_token; 464 __hc32 hw_buf [5]; 465 __hc32 hw_buf_hi [5]; 466 467 /* the rest is HCD-private */ 468 dma_addr_t qh_dma; /* address of qh */ 469 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 470 struct list_head qtd_list; /* sw qtd list */ 471 struct ehci_qtd *dummy; 472 struct ehci_qh *reclaim; /* next to reclaim */ 473 474 struct ehci_hcd *ehci; 475 476 /* 477 * Do NOT use atomic operations for QH refcounting. On some CPUs 478 * (PPC7448 for example), atomic operations cannot be performed on 479 * memory that is cache-inhibited (i.e. being used for DMA). 480 * Spinlocks are used to protect all QH fields. 481 */ 482 u32 refcount; 483 unsigned stamp; 484 485 u8 qh_state; 486#define QH_STATE_LINKED 1 /* HC sees this */ 487#define QH_STATE_UNLINK 2 /* HC may still see this */ 488#define QH_STATE_IDLE 3 /* HC doesn't see this */ 489#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 490#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 491 492 /* periodic schedule info */ 493 u8 usecs; /* intr bandwidth */ 494 u8 gap_uf; /* uframes split/csplit gap */ 495 u8 c_usecs; /* ... split completion bw */ 496 u16 tt_usecs; /* tt downstream bandwidth */ 497 unsigned short period; /* polling interval */ 498 unsigned short start; /* where polling starts */ 499#define NO_FRAME ((unsigned short)~0) /* pick new start */ 500 struct usb_device *dev; /* access to TT */ 501} __attribute__ ((aligned (32))); 502 503/*-------------------------------------------------------------------------*/ 504 505/* description of one iso transaction (up to 3 KB data if highspeed) */ 506struct ehci_iso_packet { 507 /* These will be copied to iTD when scheduling */ 508 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 509 __hc32 transaction; /* itd->hw_transaction[i] |= */ 510 u8 cross; /* buf crosses pages */ 511 /* for full speed OUT splits */ 512 u32 buf1; 513}; 514 515/* temporary schedule data for packets from iso urbs (both speeds) 516 * each packet is one logical usb transaction to the device (not TT), 517 * beginning at stream->next_uframe 518 */ 519struct ehci_iso_sched { 520 struct list_head td_list; 521 unsigned span; 522 struct ehci_iso_packet packet [0]; 523}; 524 525/* 526 * ehci_iso_stream - groups all (s)itds for this endpoint. 527 * acts like a qh would, if EHCI had them for ISO. 528 */ 529struct ehci_iso_stream { 530 /* first two fields match QH, but info1 == 0 */ 531 __hc32 hw_next; 532 __hc32 hw_info1; 533 534 u32 refcount; 535 u8 bEndpointAddress; 536 u8 highspeed; 537 u16 depth; /* depth in uframes */ 538 struct list_head td_list; /* queued itds/sitds */ 539 struct list_head free_list; /* list of unused itds/sitds */ 540 struct usb_device *udev; 541 struct usb_host_endpoint *ep; 542 543 /* output of (re)scheduling */ 544 unsigned long start; /* jiffies */ 545 unsigned long rescheduled; 546 int next_uframe; 547 __hc32 splits; 548 549 /* the rest is derived from the endpoint descriptor, 550 * trusting urb->interval == f(epdesc->bInterval) and 551 * including the extra info for hw_bufp[0..2] 552 */ 553 u8 usecs, c_usecs; 554 u16 interval; 555 u16 tt_usecs; 556 u16 maxp; 557 u16 raw_mask; 558 unsigned bandwidth; 559 560 /* This is used to initialize iTD's hw_bufp fields */ 561 __hc32 buf0; 562 __hc32 buf1; 563 __hc32 buf2; 564 565 /* this is used to initialize sITD's tt info */ 566 __hc32 address; 567}; 568 569/*-------------------------------------------------------------------------*/ 570 571/* 572 * EHCI Specification 0.95 Section 3.3 573 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 574 * 575 * Schedule records for high speed iso xfers 576 */ 577struct ehci_itd { 578 /* first part defined by EHCI spec */ 579 __hc32 hw_next; /* see EHCI 3.3.1 */ 580 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 581#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 582#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 583#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 584#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 585#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 586#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 587 588#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 589 590 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 591 __hc32 hw_bufp_hi [7]; /* Appendix B */ 592 593 /* the rest is HCD-private */ 594 dma_addr_t itd_dma; /* for this itd */ 595 union ehci_shadow itd_next; /* ptr to periodic q entry */ 596 597 struct urb *urb; 598 struct ehci_iso_stream *stream; /* endpoint's queue */ 599 struct list_head itd_list; /* list of stream's itds */ 600 601 /* any/all hw_transactions here may be used by that urb */ 602 unsigned frame; /* where scheduled */ 603 unsigned pg; 604 unsigned index[8]; /* in urb->iso_frame_desc */ 605} __attribute__ ((aligned (32))); 606 607/*-------------------------------------------------------------------------*/ 608 609/* 610 * EHCI Specification 0.95 Section 3.4 611 * siTD, aka split-transaction isochronous Transfer Descriptor 612 * ... describe full speed iso xfers through TT in hubs 613 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 614 */ 615struct ehci_sitd { 616 /* first part defined by EHCI spec */ 617 __hc32 hw_next; 618/* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 619 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 620 __hc32 hw_uframe; /* EHCI table 3-10 */ 621 __hc32 hw_results; /* EHCI table 3-11 */ 622#define SITD_IOC (1 << 31) /* interrupt on completion */ 623#define SITD_PAGE (1 << 30) /* buffer 0/1 */ 624#define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 625#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 626#define SITD_STS_ERR (1 << 6) /* error from TT */ 627#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 628#define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 629#define SITD_STS_XACT (1 << 3) /* illegal IN response */ 630#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 631#define SITD_STS_STS (1 << 1) /* split transaction state */ 632 633#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 634 635 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 636 __hc32 hw_backpointer; /* EHCI table 3-13 */ 637 __hc32 hw_buf_hi [2]; /* Appendix B */ 638 639 /* the rest is HCD-private */ 640 dma_addr_t sitd_dma; 641 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 642 643 struct urb *urb; 644 struct ehci_iso_stream *stream; /* endpoint's queue */ 645 struct list_head sitd_list; /* list of stream's sitds */ 646 unsigned frame; 647 unsigned index; 648} __attribute__ ((aligned (32))); 649 650/*-------------------------------------------------------------------------*/ 651 652/* 653 * EHCI Specification 0.96 Section 3.7 654 * Periodic Frame Span Traversal Node (FSTN) 655 * 656 * Manages split interrupt transactions (using TT) that span frame boundaries 657 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 658 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 659 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 660 */ 661struct ehci_fstn { 662 __hc32 hw_next; /* any periodic q entry */ 663 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 664 665 /* the rest is HCD-private */ 666 dma_addr_t fstn_dma; 667 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 668} __attribute__ ((aligned (32))); 669 670/*-------------------------------------------------------------------------*/ 671 672#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 673 674/* 675 * Some EHCI controllers have a Transaction Translator built into the 676 * root hub. This is a non-standard feature. Each controller will need 677 * to add code to the following inline functions, and call them as 678 * needed (mostly in root hub code). 679 */ 680 681#define ehci_is_TDI(e) ((e)->is_tdi_rh_tt) 682 683/* Returns the speed of a device attached to a port on the root hub. */ 684static inline unsigned int 685ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 686{ 687 if (ehci_is_TDI(ehci)) { 688 switch ((portsc>>26)&3) { 689 case 0: 690 return 0; 691 case 1: 692 return (1<<USB_PORT_FEAT_LOWSPEED); 693 case 2: 694 default: 695 return (1<<USB_PORT_FEAT_HIGHSPEED); 696 } 697 } 698 return (1<<USB_PORT_FEAT_HIGHSPEED); 699} 700 701#else 702 703#define ehci_is_TDI(e) (0) 704 705#define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) 706#endif 707 708/*-------------------------------------------------------------------------*/ 709 710#ifdef CONFIG_PPC_83xx 711/* Some Freescale processors have an erratum in which the TT 712 * port number in the queue head was 0..N-1 instead of 1..N. 713 */ 714#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 715#else 716#define ehci_has_fsl_portno_bug(e) (0) 717#endif 718 719/* 720 * While most USB host controllers implement their registers in 721 * little-endian format, a minority (celleb companion chip) implement 722 * them in big endian format. 723 * 724 * This attempts to support either format at compile time without a 725 * runtime penalty, or both formats with the additional overhead 726 * of checking a flag bit. 727 */ 728 729#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 730#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 731#else 732#define ehci_big_endian_mmio(e) 0 733#endif 734 735/* 736 * Big-endian read/write functions are arch-specific. 737 * Other arches can be added if/when they're needed. 738 * 739 * REVISIT: arch/powerpc now has readl/writel_be, so the 740 * definition below can die once the 4xx support is 741 * finally ported over. 742 */ 743#if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE) 744#define readl_be(addr) in_be32((__force unsigned *)addr) 745#define writel_be(val, addr) out_be32((__force unsigned *)addr, val) 746#endif 747 748#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 749#define readl_be(addr) __raw_readl((__force unsigned *)addr) 750#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 751#endif 752 753static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 754 __u32 __iomem * regs) 755{ 756#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 757 return ehci_big_endian_mmio(ehci) ? 758 readl_be(regs) : 759 readl(regs); 760#else 761 return readl(regs); 762#endif 763} 764 765static inline void ehci_writel(const struct ehci_hcd *ehci, 766 const unsigned int val, __u32 __iomem *regs) 767{ 768#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 769 ehci_big_endian_mmio(ehci) ? 770 writel_be(val, regs) : 771 writel(val, regs); 772#else 773 writel(val, regs); 774#endif 775} 776 777/*-------------------------------------------------------------------------*/ 778 779/* 780 * The AMCC 440EPx not only implements its EHCI registers in big-endian 781 * format, but also its DMA data structures (descriptors). 782 * 783 * EHCI controllers accessed through PCI work normally (little-endian 784 * everywhere), so we won't bother supporting a BE-only mode for now. 785 */ 786#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 787#define ehci_big_endian_desc(e) ((e)->big_endian_desc) 788 789/* cpu to ehci */ 790static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 791{ 792 return ehci_big_endian_desc(ehci) 793 ? (__force __hc32)cpu_to_be32(x) 794 : (__force __hc32)cpu_to_le32(x); 795} 796 797/* ehci to cpu */ 798static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 799{ 800 return ehci_big_endian_desc(ehci) 801 ? be32_to_cpu((__force __be32)x) 802 : le32_to_cpu((__force __le32)x); 803} 804 805static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 806{ 807 return ehci_big_endian_desc(ehci) 808 ? be32_to_cpup((__force __be32 *)x) 809 : le32_to_cpup((__force __le32 *)x); 810} 811 812#else 813 814/* cpu to ehci */ 815static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 816{ 817 return cpu_to_le32(x); 818} 819 820/* ehci to cpu */ 821static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 822{ 823 return le32_to_cpu(x); 824} 825 826static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 827{ 828 return le32_to_cpup(x); 829} 830 831#endif 832 833/*-------------------------------------------------------------------------*/ 834 835#ifndef DEBUG 836#define STUB_DEBUG_FILES 837#endif /* DEBUG */ 838 839/*-------------------------------------------------------------------------*/ 840 841#endif /* __LINUX_EHCI_HCD_H */ 842