ehci.h revision df2022553dd8d34d49e16c19d851ea619438f0ef
1/* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#ifndef __LINUX_EHCI_HCD_H 20#define __LINUX_EHCI_HCD_H 21 22/* definitions used for the EHCI driver */ 23 24/* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33typedef __u32 __bitwise __hc32; 34typedef __u16 __bitwise __hc16; 35#else 36#define __hc32 __le32 37#define __hc16 __le16 38#endif 39 40/* statistics can be kept for tuning/monitoring */ 41struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long iaa; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51}; 52 53/* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, unlink, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65/* 66 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the 67 * controller may be doing DMA. Lower values mean there's no DMA. 68 */ 69enum ehci_rh_state { 70 EHCI_RH_HALTED, 71 EHCI_RH_SUSPENDED, 72 EHCI_RH_RUNNING, 73 EHCI_RH_STOPPING 74}; 75 76/* 77 * Timer events, ordered by increasing delay length. 78 * Always update event_delays_ns[] and event_handlers[] (defined in 79 * ehci-timer.c) in parallel with this list. 80 */ 81enum ehci_hrtimer_event { 82 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ 83 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ 84 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ 85 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ 86 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ 87 EHCI_HRTIMER_NUM_EVENTS /* Must come last */ 88}; 89#define EHCI_HRTIMER_NO_EVENT 99 90 91struct ehci_hcd { /* one per controller */ 92 /* timing support */ 93 enum ehci_hrtimer_event next_hrtimer_event; 94 unsigned enabled_hrtimer_events; 95 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; 96 struct hrtimer hrtimer; 97 98 int PSS_poll_count; 99 int ASS_poll_count; 100 101 /* glue to PCI and HCD framework */ 102 struct ehci_caps __iomem *caps; 103 struct ehci_regs __iomem *regs; 104 struct ehci_dbg_port __iomem *debug; 105 106 __u32 hcs_params; /* cached register copy */ 107 spinlock_t lock; 108 enum ehci_rh_state rh_state; 109 110 /* general schedule support */ 111 unsigned scanning:1; 112 bool intr_unlinking:1; 113 114 /* async schedule support */ 115 struct ehci_qh *async; 116 struct ehci_qh *dummy; /* For AMD quirk use */ 117 struct ehci_qh *async_unlink; 118 struct ehci_qh *async_unlink_last; 119 struct ehci_qh *qh_scan_next; 120 unsigned async_count; /* async activity count */ 121 122 /* periodic schedule support */ 123#define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 124 unsigned periodic_size; 125 __hc32 *periodic; /* hw periodic table */ 126 dma_addr_t periodic_dma; 127 unsigned i_thresh; /* uframes HC might cache */ 128 129 union ehci_shadow *pshadow; /* mirror hw periodic table */ 130 struct ehci_qh *intr_unlink; 131 struct ehci_qh *intr_unlink_last; 132 unsigned intr_unlink_cycle; 133 int next_uframe; /* scan periodic, start here */ 134 unsigned periodic_count; /* periodic activity count */ 135 unsigned uframe_periodic_max; /* max periodic time per uframe */ 136 137 138 /* list of itds & sitds completed while clock_frame was still active */ 139 struct list_head cached_itd_list; 140 struct list_head cached_sitd_list; 141 unsigned clock_frame; 142 143 /* per root hub port */ 144 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 145 146 /* bit vectors (one bit per port) */ 147 unsigned long bus_suspended; /* which ports were 148 already suspended at the start of a bus suspend */ 149 unsigned long companion_ports; /* which ports are 150 dedicated to the companion controller */ 151 unsigned long owned_ports; /* which ports are 152 owned by the companion during a bus suspend */ 153 unsigned long port_c_suspend; /* which ports have 154 the change-suspend feature turned on */ 155 unsigned long suspended_ports; /* which ports are 156 suspended */ 157 unsigned long resuming_ports; /* which ports have 158 started to resume */ 159 160 /* per-HC memory pools (could be per-bus, but ...) */ 161 struct dma_pool *qh_pool; /* qh per active urb */ 162 struct dma_pool *qtd_pool; /* one or more per qh */ 163 struct dma_pool *itd_pool; /* itd per iso urb */ 164 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 165 166 struct timer_list iaa_watchdog; 167 struct timer_list watchdog; 168 unsigned long actions; 169 unsigned periodic_stamp; 170 unsigned random_frame; 171 unsigned long next_statechange; 172 ktime_t last_periodic_enable; 173 u32 command; 174 175 /* SILICON QUIRKS */ 176 unsigned no_selective_suspend:1; 177 unsigned has_fsl_port_bug:1; /* FreeScale */ 178 unsigned big_endian_mmio:1; 179 unsigned big_endian_desc:1; 180 unsigned big_endian_capbase:1; 181 unsigned has_amcc_usb23:1; 182 unsigned need_io_watchdog:1; 183 unsigned amd_pll_fix:1; 184 unsigned fs_i_thresh:1; /* Intel iso scheduling */ 185 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 186 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 187 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ 188 189 /* required for usb32 quirk */ 190 #define OHCI_CTRL_HCFS (3 << 6) 191 #define OHCI_USB_OPER (2 << 6) 192 #define OHCI_USB_SUSPEND (3 << 6) 193 194 #define OHCI_HCCTRL_OFFSET 0x4 195 #define OHCI_HCCTRL_LEN 0x4 196 __hc32 *ohci_hcctrl_reg; 197 unsigned has_hostpc:1; 198 unsigned has_lpm:1; /* support link power management */ 199 unsigned has_ppcd:1; /* support per-port change bits */ 200 u8 sbrn; /* packed release number */ 201 202 /* irq statistics */ 203#ifdef EHCI_STATS 204 struct ehci_stats stats; 205# define COUNT(x) do { (x)++; } while (0) 206#else 207# define COUNT(x) do {} while (0) 208#endif 209 210 /* debug files */ 211#ifdef DEBUG 212 struct dentry *debug_dir; 213#endif 214}; 215 216/* convert between an HCD pointer and the corresponding EHCI_HCD */ 217static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 218{ 219 return (struct ehci_hcd *) (hcd->hcd_priv); 220} 221static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 222{ 223 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 224} 225 226 227static inline void 228iaa_watchdog_start(struct ehci_hcd *ehci) 229{ 230 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 231 mod_timer(&ehci->iaa_watchdog, 232 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 233} 234 235static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 236{ 237 del_timer(&ehci->iaa_watchdog); 238} 239 240enum ehci_timer_action { 241 TIMER_IO_WATCHDOG, 242 TIMER_ASYNC_SHRINK, 243}; 244 245static inline void 246timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 247{ 248 clear_bit (action, &ehci->actions); 249} 250 251static void free_cached_lists(struct ehci_hcd *ehci); 252 253/*-------------------------------------------------------------------------*/ 254 255#include <linux/usb/ehci_def.h> 256 257/*-------------------------------------------------------------------------*/ 258 259#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 260 261/* 262 * EHCI Specification 0.95 Section 3.5 263 * QTD: describe data transfer components (buffer, direction, ...) 264 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 265 * 266 * These are associated only with "QH" (Queue Head) structures, 267 * used with control, bulk, and interrupt transfers. 268 */ 269struct ehci_qtd { 270 /* first part defined by EHCI spec */ 271 __hc32 hw_next; /* see EHCI 3.5.1 */ 272 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 273 __hc32 hw_token; /* see EHCI 3.5.3 */ 274#define QTD_TOGGLE (1 << 31) /* data toggle */ 275#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 276#define QTD_IOC (1 << 15) /* interrupt on complete */ 277#define QTD_CERR(tok) (((tok)>>10) & 0x3) 278#define QTD_PID(tok) (((tok)>>8) & 0x3) 279#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 280#define QTD_STS_HALT (1 << 6) /* halted on error */ 281#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 282#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 283#define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 284#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 285#define QTD_STS_STS (1 << 1) /* split transaction state */ 286#define QTD_STS_PING (1 << 0) /* issue PING? */ 287 288#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 289#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 290#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 291 292 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 293 __hc32 hw_buf_hi [5]; /* Appendix B */ 294 295 /* the rest is HCD-private */ 296 dma_addr_t qtd_dma; /* qtd address */ 297 struct list_head qtd_list; /* sw qtd list */ 298 struct urb *urb; /* qtd's urb */ 299 size_t length; /* length of buffer */ 300} __attribute__ ((aligned (32))); 301 302/* mask NakCnt+T in qh->hw_alt_next */ 303#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 304 305#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 306 307/*-------------------------------------------------------------------------*/ 308 309/* type tag from {qh,itd,sitd,fstn}->hw_next */ 310#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 311 312/* 313 * Now the following defines are not converted using the 314 * cpu_to_le32() macro anymore, since we have to support 315 * "dynamic" switching between be and le support, so that the driver 316 * can be used on one system with SoC EHCI controller using big-endian 317 * descriptors as well as a normal little-endian PCI EHCI controller. 318 */ 319/* values for that type tag */ 320#define Q_TYPE_ITD (0 << 1) 321#define Q_TYPE_QH (1 << 1) 322#define Q_TYPE_SITD (2 << 1) 323#define Q_TYPE_FSTN (3 << 1) 324 325/* next async queue entry, or pointer to interrupt/periodic QH */ 326#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 327 328/* for periodic/async schedules and qtd lists, mark end of list */ 329#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 330 331/* 332 * Entries in periodic shadow table are pointers to one of four kinds 333 * of data structure. That's dictated by the hardware; a type tag is 334 * encoded in the low bits of the hardware's periodic schedule. Use 335 * Q_NEXT_TYPE to get the tag. 336 * 337 * For entries in the async schedule, the type tag always says "qh". 338 */ 339union ehci_shadow { 340 struct ehci_qh *qh; /* Q_TYPE_QH */ 341 struct ehci_itd *itd; /* Q_TYPE_ITD */ 342 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 343 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 344 __hc32 *hw_next; /* (all types) */ 345 void *ptr; 346}; 347 348/*-------------------------------------------------------------------------*/ 349 350/* 351 * EHCI Specification 0.95 Section 3.6 352 * QH: describes control/bulk/interrupt endpoints 353 * See Fig 3-7 "Queue Head Structure Layout". 354 * 355 * These appear in both the async and (for interrupt) periodic schedules. 356 */ 357 358/* first part defined by EHCI spec */ 359struct ehci_qh_hw { 360 __hc32 hw_next; /* see EHCI 3.6.1 */ 361 __hc32 hw_info1; /* see EHCI 3.6.2 */ 362#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ 363#define QH_HEAD (1 << 15) /* Head of async reclamation list */ 364#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ 365#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ 366#define QH_LOW_SPEED (1 << 12) 367#define QH_FULL_SPEED (0 << 12) 368#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ 369 __hc32 hw_info2; /* see EHCI 3.6.2 */ 370#define QH_SMASK 0x000000ff 371#define QH_CMASK 0x0000ff00 372#define QH_HUBADDR 0x007f0000 373#define QH_HUBPORT 0x3f800000 374#define QH_MULT 0xc0000000 375 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 376 377 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 378 __hc32 hw_qtd_next; 379 __hc32 hw_alt_next; 380 __hc32 hw_token; 381 __hc32 hw_buf [5]; 382 __hc32 hw_buf_hi [5]; 383} __attribute__ ((aligned(32))); 384 385struct ehci_qh { 386 struct ehci_qh_hw *hw; 387 /* the rest is HCD-private */ 388 dma_addr_t qh_dma; /* address of qh */ 389 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 390 struct list_head qtd_list; /* sw qtd list */ 391 struct ehci_qtd *dummy; 392 struct ehci_qh *unlink_next; /* next on unlink list */ 393 394 unsigned long unlink_time; 395 unsigned unlink_cycle; 396 unsigned stamp; 397 398 u8 needs_rescan; /* Dequeue during giveback */ 399 u8 qh_state; 400#define QH_STATE_LINKED 1 /* HC sees this */ 401#define QH_STATE_UNLINK 2 /* HC may still see this */ 402#define QH_STATE_IDLE 3 /* HC doesn't see this */ 403#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ 404#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 405 406 u8 xacterrs; /* XactErr retry counter */ 407#define QH_XACTERR_MAX 32 /* XactErr retry limit */ 408 409 /* periodic schedule info */ 410 u8 usecs; /* intr bandwidth */ 411 u8 gap_uf; /* uframes split/csplit gap */ 412 u8 c_usecs; /* ... split completion bw */ 413 u16 tt_usecs; /* tt downstream bandwidth */ 414 unsigned short period; /* polling interval */ 415 unsigned short start; /* where polling starts */ 416#define NO_FRAME ((unsigned short)~0) /* pick new start */ 417 418 struct usb_device *dev; /* access to TT */ 419 unsigned is_out:1; /* bulk or intr OUT */ 420 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 421}; 422 423/*-------------------------------------------------------------------------*/ 424 425/* description of one iso transaction (up to 3 KB data if highspeed) */ 426struct ehci_iso_packet { 427 /* These will be copied to iTD when scheduling */ 428 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 429 __hc32 transaction; /* itd->hw_transaction[i] |= */ 430 u8 cross; /* buf crosses pages */ 431 /* for full speed OUT splits */ 432 u32 buf1; 433}; 434 435/* temporary schedule data for packets from iso urbs (both speeds) 436 * each packet is one logical usb transaction to the device (not TT), 437 * beginning at stream->next_uframe 438 */ 439struct ehci_iso_sched { 440 struct list_head td_list; 441 unsigned span; 442 struct ehci_iso_packet packet [0]; 443}; 444 445/* 446 * ehci_iso_stream - groups all (s)itds for this endpoint. 447 * acts like a qh would, if EHCI had them for ISO. 448 */ 449struct ehci_iso_stream { 450 /* first field matches ehci_hq, but is NULL */ 451 struct ehci_qh_hw *hw; 452 453 u32 refcount; 454 u8 bEndpointAddress; 455 u8 highspeed; 456 struct list_head td_list; /* queued itds/sitds */ 457 struct list_head free_list; /* list of unused itds/sitds */ 458 struct usb_device *udev; 459 struct usb_host_endpoint *ep; 460 461 /* output of (re)scheduling */ 462 int next_uframe; 463 __hc32 splits; 464 465 /* the rest is derived from the endpoint descriptor, 466 * trusting urb->interval == f(epdesc->bInterval) and 467 * including the extra info for hw_bufp[0..2] 468 */ 469 u8 usecs, c_usecs; 470 u16 interval; 471 u16 tt_usecs; 472 u16 maxp; 473 u16 raw_mask; 474 unsigned bandwidth; 475 476 /* This is used to initialize iTD's hw_bufp fields */ 477 __hc32 buf0; 478 __hc32 buf1; 479 __hc32 buf2; 480 481 /* this is used to initialize sITD's tt info */ 482 __hc32 address; 483}; 484 485/*-------------------------------------------------------------------------*/ 486 487/* 488 * EHCI Specification 0.95 Section 3.3 489 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 490 * 491 * Schedule records for high speed iso xfers 492 */ 493struct ehci_itd { 494 /* first part defined by EHCI spec */ 495 __hc32 hw_next; /* see EHCI 3.3.1 */ 496 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 497#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 498#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 499#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 500#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 501#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 502#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 503 504#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 505 506 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 507 __hc32 hw_bufp_hi [7]; /* Appendix B */ 508 509 /* the rest is HCD-private */ 510 dma_addr_t itd_dma; /* for this itd */ 511 union ehci_shadow itd_next; /* ptr to periodic q entry */ 512 513 struct urb *urb; 514 struct ehci_iso_stream *stream; /* endpoint's queue */ 515 struct list_head itd_list; /* list of stream's itds */ 516 517 /* any/all hw_transactions here may be used by that urb */ 518 unsigned frame; /* where scheduled */ 519 unsigned pg; 520 unsigned index[8]; /* in urb->iso_frame_desc */ 521} __attribute__ ((aligned (32))); 522 523/*-------------------------------------------------------------------------*/ 524 525/* 526 * EHCI Specification 0.95 Section 3.4 527 * siTD, aka split-transaction isochronous Transfer Descriptor 528 * ... describe full speed iso xfers through TT in hubs 529 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 530 */ 531struct ehci_sitd { 532 /* first part defined by EHCI spec */ 533 __hc32 hw_next; 534/* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 535 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 536 __hc32 hw_uframe; /* EHCI table 3-10 */ 537 __hc32 hw_results; /* EHCI table 3-11 */ 538#define SITD_IOC (1 << 31) /* interrupt on completion */ 539#define SITD_PAGE (1 << 30) /* buffer 0/1 */ 540#define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 541#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 542#define SITD_STS_ERR (1 << 6) /* error from TT */ 543#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 544#define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 545#define SITD_STS_XACT (1 << 3) /* illegal IN response */ 546#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 547#define SITD_STS_STS (1 << 1) /* split transaction state */ 548 549#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 550 551 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 552 __hc32 hw_backpointer; /* EHCI table 3-13 */ 553 __hc32 hw_buf_hi [2]; /* Appendix B */ 554 555 /* the rest is HCD-private */ 556 dma_addr_t sitd_dma; 557 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 558 559 struct urb *urb; 560 struct ehci_iso_stream *stream; /* endpoint's queue */ 561 struct list_head sitd_list; /* list of stream's sitds */ 562 unsigned frame; 563 unsigned index; 564} __attribute__ ((aligned (32))); 565 566/*-------------------------------------------------------------------------*/ 567 568/* 569 * EHCI Specification 0.96 Section 3.7 570 * Periodic Frame Span Traversal Node (FSTN) 571 * 572 * Manages split interrupt transactions (using TT) that span frame boundaries 573 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 574 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 575 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 576 */ 577struct ehci_fstn { 578 __hc32 hw_next; /* any periodic q entry */ 579 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 580 581 /* the rest is HCD-private */ 582 dma_addr_t fstn_dma; 583 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 584} __attribute__ ((aligned (32))); 585 586/*-------------------------------------------------------------------------*/ 587 588/* Prepare the PORTSC wakeup flags during controller suspend/resume */ 589 590#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 591 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 592 593#define ehci_prepare_ports_for_controller_resume(ehci) \ 594 ehci_adjust_port_wakeup_flags(ehci, false, false); 595 596/*-------------------------------------------------------------------------*/ 597 598#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 599 600/* 601 * Some EHCI controllers have a Transaction Translator built into the 602 * root hub. This is a non-standard feature. Each controller will need 603 * to add code to the following inline functions, and call them as 604 * needed (mostly in root hub code). 605 */ 606 607#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 608 609/* Returns the speed of a device attached to a port on the root hub. */ 610static inline unsigned int 611ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 612{ 613 if (ehci_is_TDI(ehci)) { 614 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 615 case 0: 616 return 0; 617 case 1: 618 return USB_PORT_STAT_LOW_SPEED; 619 case 2: 620 default: 621 return USB_PORT_STAT_HIGH_SPEED; 622 } 623 } 624 return USB_PORT_STAT_HIGH_SPEED; 625} 626 627#else 628 629#define ehci_is_TDI(e) (0) 630 631#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 632#endif 633 634/*-------------------------------------------------------------------------*/ 635 636#ifdef CONFIG_PPC_83xx 637/* Some Freescale processors have an erratum in which the TT 638 * port number in the queue head was 0..N-1 instead of 1..N. 639 */ 640#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 641#else 642#define ehci_has_fsl_portno_bug(e) (0) 643#endif 644 645/* 646 * While most USB host controllers implement their registers in 647 * little-endian format, a minority (celleb companion chip) implement 648 * them in big endian format. 649 * 650 * This attempts to support either format at compile time without a 651 * runtime penalty, or both formats with the additional overhead 652 * of checking a flag bit. 653 * 654 * ehci_big_endian_capbase is a special quirk for controllers that 655 * implement the HC capability registers as separate registers and not 656 * as fields of a 32-bit register. 657 */ 658 659#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 660#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 661#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 662#else 663#define ehci_big_endian_mmio(e) 0 664#define ehci_big_endian_capbase(e) 0 665#endif 666 667/* 668 * Big-endian read/write functions are arch-specific. 669 * Other arches can be added if/when they're needed. 670 */ 671#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 672#define readl_be(addr) __raw_readl((__force unsigned *)addr) 673#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 674#endif 675 676static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 677 __u32 __iomem * regs) 678{ 679#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 680 return ehci_big_endian_mmio(ehci) ? 681 readl_be(regs) : 682 readl(regs); 683#else 684 return readl(regs); 685#endif 686} 687 688static inline void ehci_writel(const struct ehci_hcd *ehci, 689 const unsigned int val, __u32 __iomem *regs) 690{ 691#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 692 ehci_big_endian_mmio(ehci) ? 693 writel_be(val, regs) : 694 writel(val, regs); 695#else 696 writel(val, regs); 697#endif 698} 699 700/* 701 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 702 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 703 * Other common bits are dependent on has_amcc_usb23 quirk flag. 704 */ 705#ifdef CONFIG_44x 706static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 707{ 708 u32 hc_control; 709 710 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 711 if (operational) 712 hc_control |= OHCI_USB_OPER; 713 else 714 hc_control |= OHCI_USB_SUSPEND; 715 716 writel_be(hc_control, ehci->ohci_hcctrl_reg); 717 (void) readl_be(ehci->ohci_hcctrl_reg); 718} 719#else 720static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 721{ } 722#endif 723 724/*-------------------------------------------------------------------------*/ 725 726/* 727 * The AMCC 440EPx not only implements its EHCI registers in big-endian 728 * format, but also its DMA data structures (descriptors). 729 * 730 * EHCI controllers accessed through PCI work normally (little-endian 731 * everywhere), so we won't bother supporting a BE-only mode for now. 732 */ 733#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 734#define ehci_big_endian_desc(e) ((e)->big_endian_desc) 735 736/* cpu to ehci */ 737static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 738{ 739 return ehci_big_endian_desc(ehci) 740 ? (__force __hc32)cpu_to_be32(x) 741 : (__force __hc32)cpu_to_le32(x); 742} 743 744/* ehci to cpu */ 745static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 746{ 747 return ehci_big_endian_desc(ehci) 748 ? be32_to_cpu((__force __be32)x) 749 : le32_to_cpu((__force __le32)x); 750} 751 752static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 753{ 754 return ehci_big_endian_desc(ehci) 755 ? be32_to_cpup((__force __be32 *)x) 756 : le32_to_cpup((__force __le32 *)x); 757} 758 759#else 760 761/* cpu to ehci */ 762static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 763{ 764 return cpu_to_le32(x); 765} 766 767/* ehci to cpu */ 768static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 769{ 770 return le32_to_cpu(x); 771} 772 773static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 774{ 775 return le32_to_cpup(x); 776} 777 778#endif 779 780/*-------------------------------------------------------------------------*/ 781 782#ifdef CONFIG_PCI 783 784/* For working around the MosChip frame-index-register bug */ 785static unsigned ehci_read_frame_index(struct ehci_hcd *ehci); 786 787#else 788 789static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci) 790{ 791 return ehci_readl(ehci, &ehci->regs->frame_index); 792} 793 794#endif 795 796/*-------------------------------------------------------------------------*/ 797 798#ifndef DEBUG 799#define STUB_DEBUG_FILES 800#endif /* DEBUG */ 801 802/*-------------------------------------------------------------------------*/ 803 804#endif /* __LINUX_EHCI_HCD_H */ 805