r8a66597.h revision 9424ea29658ce5bcdcf527ddf9617b9507ddf1aa
15d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* 25d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * R8A66597 HCD (Host Controller Driver) 35d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * 45d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * Copyright (C) 2006-2007 Renesas Solutions Corp. 55d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO) 65d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * Portions Copyright (C) 2004-2005 David Brownell 75d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * Portions Copyright (C) 1999 Roman Weissgaerber 85d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * 95d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 105d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * 115d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * This program is free software; you can redistribute it and/or modify 125d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * it under the terms of the GNU General Public License as published by 135d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * the Free Software Foundation; version 2 of the License. 145d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * 155d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * This program is distributed in the hope that it will be useful, 165d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * but WITHOUT ANY WARRANTY; without even the implied warranty of 175d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 185d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * GNU General Public License for more details. 195d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * 205d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * You should have received a copy of the GNU General Public License 215d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * along with this program; if not, write to the Free Software 225d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 235d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda * 245d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda */ 255d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 265d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#ifndef __R8A66597_H__ 275d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define __R8A66597_H__ 285d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 295d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SYSCFG0 0x00 305d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SYSCFG1 0x02 315d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SYSSTS0 0x04 325d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SYSSTS1 0x06 335d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DVSTCTR0 0x08 345d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DVSTCTR1 0x0A 355d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define TESTMODE 0x0C 365d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PINCFG 0x0E 375d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DMA0CFG 0x10 385d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DMA1CFG 0x12 395d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CFIFO 0x14 405d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define D0FIFO 0x18 415d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define D1FIFO 0x1C 425d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CFIFOSEL 0x20 435d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CFIFOCTR 0x22 445d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CFIFOSIE 0x24 455d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define D0FIFOSEL 0x28 465d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define D0FIFOCTR 0x2A 475d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define D1FIFOSEL 0x2C 485d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define D1FIFOCTR 0x2E 495d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define INTENB0 0x30 505d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define INTENB1 0x32 515d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define INTENB2 0x34 525d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDYENB 0x36 535d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDYENB 0x38 545d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMPENB 0x3A 555d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SOFCFG 0x3C 565d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define INTSTS0 0x40 575d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define INTSTS1 0x42 585d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define INTSTS2 0x44 595d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDYSTS 0x46 605d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDYSTS 0x48 615d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMPSTS 0x4A 625d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define FRMNUM 0x4C 635d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define UFRMNUM 0x4E 645d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define USBADDR 0x50 655d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define USBREQ 0x54 665d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define USBVAL 0x56 675d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define USBINDX 0x58 685d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define USBLENG 0x5A 695d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DCPCFG 0x5C 705d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DCPMAXP 0x5E 715d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DCPCTR 0x60 725d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPESEL 0x64 735d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPECFG 0x68 745d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPEBUF 0x6A 755d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPEMAXP 0x6C 765d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPEPERI 0x6E 775d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE1CTR 0x70 785d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE2CTR 0x72 795d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE3CTR 0x74 805d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE4CTR 0x76 815d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE5CTR 0x78 825d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE6CTR 0x7A 835d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE7CTR 0x7C 845d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE8CTR 0x7E 855d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE9CTR 0x80 865d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE1TRE 0x90 875d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE1TRN 0x92 885d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE2TRE 0x94 895d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE2TRN 0x96 905d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE3TRE 0x98 915d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE3TRN 0x9A 925d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE4TRE 0x9C 935d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE4TRN 0x9E 945d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE5TRE 0xA0 955d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE5TRN 0xA2 965d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADD0 0xD0 975d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADD1 0xD2 985d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADD2 0xD4 995d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADD3 0xD6 1005d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADD4 0xD8 1015d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADD5 0xDA 1025d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADD6 0xDC 1035d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADD7 0xDE 1045d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADD8 0xE0 1055d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADD9 0xE2 1065d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DEVADDA 0xE4 1075d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 1085d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* System Configuration Control Register */ 1095d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define XTAL 0xC000 /* b15-14: Crystal selection */ 1105d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define XTAL48 0x8000 /* 48MHz */ 1115d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define XTAL24 0x4000 /* 24MHz */ 1125d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define XTAL12 0x0000 /* 12MHz */ 1135d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define XCKE 0x2000 /* b13: External clock enable */ 1145d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PLLC 0x0800 /* b11: PLL control */ 1155d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SCKE 0x0400 /* b10: USB clock enable */ 1165d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PCSDIS 0x0200 /* b9: not CS wakeup */ 1175d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define LPSME 0x0100 /* b8: Low power sleep mode */ 1185d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define HSE 0x0080 /* b7: Hi-speed enable */ 1195d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DCFM 0x0040 /* b6: Controller function select */ 1205d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DRPD 0x0020 /* b5: D+/- pull down control */ 1215d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DPRPU 0x0010 /* b4: D+ pull up control */ 1225d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define USBE 0x0001 /* b0: USB module operation enable */ 1235d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 1245d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* System Configuration Status Register */ 1255d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define OVCBIT 0x8000 /* b15-14: Over-current bit */ 1265d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define OVCMON 0xC000 /* b15-14: Over-current monitor */ 1275d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SOFEA 0x0020 /* b5: SOF monitor */ 1285d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define IDMON 0x0004 /* b3: ID-pin monitor */ 1295d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define LNST 0x0003 /* b1-0: D+, D- line status */ 1305d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SE1 0x0003 /* SE1 */ 1315d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define FS_KSTS 0x0002 /* Full-Speed K State */ 1325d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define FS_JSTS 0x0001 /* Full-Speed J State */ 1335d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define LS_JSTS 0x0002 /* Low-Speed J State */ 1345d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define LS_KSTS 0x0001 /* Low-Speed K State */ 1355d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SE0 0x0000 /* SE0 */ 1365d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 1375d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Device State Control Register */ 1385d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define EXTLP0 0x0400 /* b10: External port */ 1395d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define VBOUT 0x0200 /* b9: VBUS output */ 1405d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define WKUP 0x0100 /* b8: Remote wakeup */ 1415d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define RWUPE 0x0080 /* b7: Remote wakeup sense */ 1425d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define USBRST 0x0040 /* b6: USB reset enable */ 1435d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define RESUME 0x0020 /* b5: Resume enable */ 1445d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define UACT 0x0010 /* b4: USB bus enable */ 1455d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define RHST 0x0007 /* b1-0: Reset handshake status */ 1465d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define HSPROC 0x0004 /* HS handshake is processing */ 1475d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define HSMODE 0x0003 /* Hi-Speed mode */ 1485d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define FSMODE 0x0002 /* Full-Speed mode */ 1495d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define LSMODE 0x0001 /* Low-Speed mode */ 1505d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define UNDECID 0x0000 /* Undecided */ 1515d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 1525d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Test Mode Register */ 1535d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define UTST 0x000F /* b3-0: Test select */ 1545d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define H_TST_PACKET 0x000C /* HOST TEST Packet */ 1555d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ 1565d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define H_TST_K 0x000A /* HOST TEST K */ 1575d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define H_TST_J 0x0009 /* HOST TEST J */ 1585d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */ 1595d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define P_TST_PACKET 0x0004 /* PERI TEST Packet */ 1605d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ 1615d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define P_TST_K 0x0002 /* PERI TEST K */ 1625d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define P_TST_J 0x0001 /* PERI TEST J */ 1635d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 1645d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 1655d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Data Pin Configuration Register */ 1665d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define LDRV 0x8000 /* b15: Drive Current Adjust */ 1675d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define VIF1 0x0000 /* VIF = 1.8V */ 1685d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define VIF3 0x8000 /* VIF = 3.3V */ 1695d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define INTA 0x0001 /* b1: USB INT-pin active */ 1705d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 1715d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* DMAx Pin Configuration Register */ 1725d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DREQA 0x4000 /* b14: Dreq active select */ 1735d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BURST 0x2000 /* b13: Burst mode */ 1745d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DACKA 0x0400 /* b10: Dack active select */ 1755d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DFORM 0x0380 /* b9-7: DMA mode select */ 1765d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ 1775d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ 1785d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ 1795d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ 1805d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DENDA 0x0040 /* b6: Dend active select */ 1815d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PKTM 0x0020 /* b5: Packet mode */ 1825d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DENDE 0x0010 /* b4: Dend enable */ 1835d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define OBUS 0x0004 /* b2: OUTbus mode */ 1845d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 1855d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* CFIFO/DxFIFO Port Select Register */ 1865d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define RCNT 0x8000 /* b15: Read count mode */ 1875d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define REW 0x4000 /* b14: Buffer rewind */ 1885d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DCLRM 0x2000 /* b13: DMA buffer clear mode */ 1895d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DREQE 0x1000 /* b12: DREQ output enable */ 1909424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) 1919424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#define MBW 0x0800 1929424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#else 1935d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */ 1949424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#endif 1955d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define MBW_8 0x0000 /* 8bit */ 1965d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define MBW_16 0x0400 /* 16bit */ 1975d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BIGEND 0x0100 /* b8: Big endian mode */ 1985d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BYTE_LITTLE 0x0000 /* little dendian */ 1995d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BYTE_BIG 0x0100 /* big endifan */ 2005d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define ISEL 0x0020 /* b5: DCP FIFO port direction select */ 2015d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CURPIPE 0x000F /* b2-0: PIPE select */ 2025d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 2035d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* CFIFO/DxFIFO Port Control Register */ 2045d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BVAL 0x8000 /* b15: Buffer valid flag */ 2055d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BCLR 0x4000 /* b14: Buffer clear */ 2065d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define FRDY 0x2000 /* b13: FIFO ready */ 2075d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DTLN 0x0FFF /* b11-0: FIFO received data length */ 2085d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 2095d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Interrupt Enable Register 0 */ 210e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define VBSE 0x8000 /* b15: VBUS interrupt */ 211e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define RSME 0x4000 /* b14: Resume interrupt */ 212e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define SOFE 0x2000 /* b13: Frame update interrupt */ 213e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define DVSE 0x1000 /* b12: Device state transition interrupt */ 214e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ 215e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define BEMPE 0x0400 /* b10: Buffer empty interrupt */ 216e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ 217e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define BRDYE 0x0100 /* b8: Buffer ready interrupt */ 2185d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 2195d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Interrupt Enable Register 1 */ 2205d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define OVRCRE 0x8000 /* b15: Over-current interrupt */ 2215d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BCHGE 0x4000 /* b14: USB us chenge interrupt */ 2225d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DTCHE 0x1000 /* b12: Detach sense interrupt */ 2235d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define ATTCHE 0x0800 /* b11: Attach sense interrupt */ 2245d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define EOFERRE 0x0040 /* b6: EOF error interrupt */ 2255d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ 2265d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SACKE 0x0010 /* b4: SETUP ACK interrupt */ 2275d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 2285d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* BRDY Interrupt Enable/Status Register */ 2295d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDY9 0x0200 /* b9: PIPE9 */ 2305d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDY8 0x0100 /* b8: PIPE8 */ 2315d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDY7 0x0080 /* b7: PIPE7 */ 2325d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDY6 0x0040 /* b6: PIPE6 */ 2335d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDY5 0x0020 /* b5: PIPE5 */ 2345d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDY4 0x0010 /* b4: PIPE4 */ 2355d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDY3 0x0008 /* b3: PIPE3 */ 2365d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDY2 0x0004 /* b2: PIPE2 */ 2375d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDY1 0x0002 /* b1: PIPE1 */ 2385d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDY0 0x0001 /* b1: PIPE0 */ 2395d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 2405d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* NRDY Interrupt Enable/Status Register */ 2415d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDY9 0x0200 /* b9: PIPE9 */ 2425d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDY8 0x0100 /* b8: PIPE8 */ 2435d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDY7 0x0080 /* b7: PIPE7 */ 2445d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDY6 0x0040 /* b6: PIPE6 */ 2455d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDY5 0x0020 /* b5: PIPE5 */ 2465d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDY4 0x0010 /* b4: PIPE4 */ 2475d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDY3 0x0008 /* b3: PIPE3 */ 2485d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDY2 0x0004 /* b2: PIPE2 */ 2495d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDY1 0x0002 /* b1: PIPE1 */ 2505d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define NRDY0 0x0001 /* b1: PIPE0 */ 2515d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 2525d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* BEMP Interrupt Enable/Status Register */ 2535d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMP9 0x0200 /* b9: PIPE9 */ 2545d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMP8 0x0100 /* b8: PIPE8 */ 2555d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMP7 0x0080 /* b7: PIPE7 */ 2565d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMP6 0x0040 /* b6: PIPE6 */ 2575d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMP5 0x0020 /* b5: PIPE5 */ 2585d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMP4 0x0010 /* b4: PIPE4 */ 2595d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMP3 0x0008 /* b3: PIPE3 */ 2605d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMP2 0x0004 /* b2: PIPE2 */ 2615d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMP1 0x0002 /* b1: PIPE1 */ 2625d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BEMP0 0x0001 /* b0: PIPE0 */ 2635d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 2645d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* SOF Pin Configuration Register */ 2655d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define TRNENSEL 0x0100 /* b8: Select transaction enable period */ 2665d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BRDYM 0x0040 /* b6: BRDY clear timing */ 2675d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define INTL 0x0020 /* b5: Interrupt sense select */ 2685d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define EDGESTS 0x0010 /* b4: */ 2695d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SOFMODE 0x000C /* b3-2: SOF pin select */ 2705d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */ 2715d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ 2725d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SOF_DISABLE 0x0000 /* SOF OUT Disable */ 2735d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 2745d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Interrupt Status Register 0 */ 275e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define VBINT 0x8000 /* b15: VBUS interrupt */ 276e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define RESM 0x4000 /* b14: Resume interrupt */ 277e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define SOFR 0x2000 /* b13: SOF frame update interrupt */ 278e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define DVST 0x1000 /* b12: Device state transition interrupt */ 279e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ 280e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define BEMP 0x0400 /* b10: Buffer empty interrupt */ 281e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define NRDY 0x0200 /* b9: Buffer not ready interrupt */ 282e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define BRDY 0x0100 /* b8: Buffer ready interrupt */ 283e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define VBSTS 0x0080 /* b7: VBUS input port */ 284e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define DVSQ 0x0070 /* b6-4: Device state */ 2855d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DS_SPD_CNFG 0x0070 /* Suspend Configured */ 2865d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DS_SPD_ADDR 0x0060 /* Suspend Address */ 2875d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DS_SPD_DFLT 0x0050 /* Suspend Default */ 2885d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DS_SPD_POWR 0x0040 /* Suspend Powered */ 2895d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DS_SUSP 0x0040 /* Suspend */ 2905d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DS_CNFG 0x0030 /* Configured */ 2915d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DS_ADDS 0x0020 /* Address */ 2925d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DS_DFLT 0x0010 /* Default */ 2935d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DS_POWR 0x0000 /* Powered */ 2945d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DVSQS 0x0030 /* b5-4: Device state */ 2955d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define VALID 0x0008 /* b3: Setup packet detected flag */ 2965d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CTSQ 0x0007 /* b2-0: Control transfer stage */ 2975d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CS_SQER 0x0006 /* Sequence error */ 2985d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CS_WRND 0x0005 /* Control write nodata status stage */ 2995d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CS_WRSS 0x0004 /* Control write status stage */ 3005d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CS_WRDS 0x0003 /* Control write data stage */ 3015d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CS_RDSS 0x0002 /* Control read status stage */ 3025d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CS_RDDS 0x0001 /* Control read data stage */ 3035d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CS_IDST 0x0000 /* Idle or setup stage */ 3045d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3055d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Interrupt Status Register 1 */ 3065d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define OVRCR 0x8000 /* b15: Over-current interrupt */ 3075d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BCHG 0x4000 /* b14: USB bus chenge interrupt */ 3085d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define DTCH 0x1000 /* b12: Detach sense interrupt */ 3095d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define ATTCH 0x0800 /* b11: Attach sense interrupt */ 3105d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define EOFERR 0x0040 /* b6: EOF-error interrupt */ 3115d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SIGN 0x0020 /* b5: Setup ignore interrupt */ 3125d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SACK 0x0010 /* b4: Setup acknowledge interrupt */ 3135d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3145d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Frame Number Register */ 3155d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define OVRN 0x8000 /* b15: Overrun error */ 3165d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CRCE 0x4000 /* b14: Received data error */ 3175d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define FRNM 0x07FF /* b10-0: Frame number */ 3185d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3195d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Micro Frame Number Register */ 3205d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define UFRNM 0x0007 /* b2-0: Micro frame number */ 3215d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3225d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Default Control Pipe Maxpacket Size Register */ 3235d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Pipe Maxpacket Size Register */ 324e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define DEVSEL 0xF000 /* b15-14: Device address select */ 325e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ 3265d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3275d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Default Control Pipe Control Register */ 3285d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BSTS 0x8000 /* b15: Buffer status */ 3295d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SUREQ 0x4000 /* b14: Send USB request */ 3305d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CSCLR 0x2000 /* b13: complete-split status clear */ 3315d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CSSTS 0x1000 /* b12: complete-split status */ 3325d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SUREQCLR 0x0800 /* b11: stop setup request */ 3335d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 3345d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SQSET 0x0080 /* b7: Sequence toggle bit set */ 3355d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 3365d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PBUSY 0x0020 /* b5: pipe busy */ 3375d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PINGE 0x0010 /* b4: ping enable */ 3385d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define CCPL 0x0004 /* b2: Enable control transfer complete */ 3395d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PID 0x0003 /* b1-0: Response PID */ 3405d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PID_STALL11 0x0003 /* STALL */ 3415d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PID_STALL 0x0002 /* STALL */ 3425d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PID_BUF 0x0001 /* BUF */ 3435d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PID_NAK 0x0000 /* NAK */ 3445d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3455d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Pipe Window Select Register */ 3465d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPENM 0x0007 /* b2-0: Pipe select */ 3475d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3485d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Pipe Configuration Register */ 3495d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */ 3505d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_ISO 0xC000 /* Isochronous */ 3515d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_INT 0x8000 /* Interrupt */ 3525d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_BULK 0x4000 /* Bulk */ 3535d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */ 3545d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */ 3555d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */ 3565d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */ 3575d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */ 3585d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */ 3595d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3605d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Pipe Buffer Configuration Register */ 3615d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ 3625d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define BUFNMB 0x007F /* b6-0: Pipe buffer number */ 3635d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPE0BUF 256 3645d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define PIPExBUF 64 3655d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3665d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Pipe Maxpacket Size Register */ 3675d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define MXPS 0x07FF /* b10-0: Maxpacket size */ 3685d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3695d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Pipe Cycle Configuration Register */ 370e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ 371e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define IITV 0x0007 /* b2-0: Isochronous interval */ 3725d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3735d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* Pipex Control Register */ 374e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define BSTS 0x8000 /* b15: Buffer status */ 375e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ 376e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define CSCLR 0x2000 /* b13: complete-split status clear */ 377e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define CSSTS 0x1000 /* b12: complete-split status */ 378e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define ATREPM 0x0400 /* b10: Auto repeat mode */ 379e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ 380e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 381e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define SQSET 0x0080 /* b7: Sequence toggle bit set */ 382e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 383e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define PBUSY 0x0020 /* b5: pipe busy */ 384e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda#define PID 0x0003 /* b1-0: Response PID */ 3855d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3865d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* PIPExTRE */ 3875d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define TRENB 0x0200 /* b9: Transaction counter enable */ 3885d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define TRCLR 0x0100 /* b8: Transaction counter clear */ 3895d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3905d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* PIPExTRN */ 3915d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define TRNCNT 0xFFFF /* b15-0: Transaction counter */ 3925d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3935d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda/* DEVADDx */ 3945d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define UPPHUB 0x7800 3955d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define HUBPORT 0x0700 3965d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define USBSPD 0x00C0 3975d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define RTPORT 0x0001 3985d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 3995d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_MAX_NUM_PIPE 10 4005d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_BUF_BSIZE 8 4015d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_MAX_DEVICE 10 4029424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) 4039424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#define R8A66597_MAX_ROOT_HUB 1 4049424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#else 4055d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_MAX_ROOT_HUB 2 4069424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#endif 40729fab0cd897519be9009ba8c898410ab83b378e9Yoshihiro Shimoda#define R8A66597_MAX_SAMPLING 5 40829fab0cd897519be9009ba8c898410ab83b378e9Yoshihiro Shimoda#define R8A66597_RH_POLL_TIME 10 4095d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_MAX_DMA_CHANNEL 2 4105d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL 4115d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5)) 4125d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9)) 4135d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define make_devsel(addr) (addr << 12) 4145d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4155d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastruct r8a66597_pipe_info { 4166d8791076c7742c65dd796ae0ac260ab22e85517Yoshihiro Shimoda unsigned long timer_interval; 417e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda u16 pipenum; 418dc0d5c1e5c7532e800fff6e313cd4af44af99976Joe Perches u16 address; /* R8A66597 HCD usb address */ 419e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda u16 epnum; 420e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda u16 maxpacket; 421e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda u16 type; 422e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda u16 bufnum; 423e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda u16 buf_bsize; 424e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda u16 interval; 425e294531dc9f2c1f5291373dcdd5013c0cdcbdee2Yoshihiro Shimoda u16 dir_in; 4265d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda}; 4275d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4285d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastruct r8a66597_pipe { 4295d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct r8a66597_pipe_info info; 4305d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4315d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long fifoaddr; 4325d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long fifosel; 4335d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long fifoctr; 4345d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long pipectr; 4355d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long pipetre; 4365d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long pipetrn; 4375d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda}; 4385d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4395d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastruct r8a66597_td { 4405d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct r8a66597_pipe *pipe; 4415d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct urb *urb; 4425d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct list_head queue; 4435d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4445d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 type; 4455d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 pipenum; 4465d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda int iso_cnt; 4475d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4485d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 address; /* R8A66597's USB address */ 4495d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 maxpacket; 4505d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4515d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned zero_packet:1; 4525d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned short_packet:1; 4535d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned set_address:1; 4545d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda}; 4555d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4565d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastruct r8a66597_device { 4575d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 address; /* R8A66597's USB address */ 4585d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 hub_port; 4595d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 root_port; 4605d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4615d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned short ep_in_toggle; 4625d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned short ep_out_toggle; 4635d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE]; 4645d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned char dma_map; 4655d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4665d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda enum usb_device_state state; 4675d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4685d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct usb_device *udev; 4695d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda int usb_address; 4705d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct list_head device_list; 4715d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda}; 4725d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4735d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastruct r8a66597_root_hub { 4745d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u32 port; 4755d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 old_syssts; 4765d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda int scount; 4775d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4785d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct r8a66597_device *dev; 4795d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda}; 4805d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4815d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastruct r8a66597 { 4825d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda spinlock_t lock; 4835d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long reg; 4845d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4855d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct r8a66597_device device0; 4865d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB]; 4875d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE]; 4885d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4895d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct timer_list rh_timer; 4905d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct timer_list td_timer[R8A66597_MAX_NUM_PIPE]; 4916d8791076c7742c65dd796ae0ac260ab22e85517Yoshihiro Shimoda struct timer_list interval_timer[R8A66597_MAX_NUM_PIPE]; 4925d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4935d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned short address_map; 4945d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned short timeout_map; 4956d8791076c7742c65dd796ae0ac260ab22e85517Yoshihiro Shimoda unsigned short interval_map; 4965d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE]; 4975d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned char dma_map; 4985d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 4995d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct list_head child_device; 5005d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long child_connect_map[4]; 5015d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda}; 5025d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5035d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd) 5045d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 5055d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return (struct r8a66597 *)(hcd->hcd_priv); 5065d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 5075d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5085d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597) 5095d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 5105d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return container_of((void *)r8a66597, struct usb_hcd, hcd_priv); 5115d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 5125d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5135d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597, 5145d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 pipenum) 5155d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 5165d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum]))) 5175d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return NULL; 5185d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5195d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return list_entry(r8a66597->pipe_queue[pipenum].next, 5205d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct r8a66597_td, queue); 5215d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 5225d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5235d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597, 5245d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 pipenum) 5255d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 5265d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda struct r8a66597_td *td; 5275d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5285d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda td = r8a66597_get_td(r8a66597, pipenum); 5295d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return (td ? td->urb : NULL); 5305d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 5315d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5325d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset) 5335d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 5345d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return inw(r8a66597->reg + offset); 5355d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 5365d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5375d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline void r8a66597_read_fifo(struct r8a66597 *r8a66597, 5385d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long offset, u16 *buf, 5395d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda int len) 5405d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 5419424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) 5429424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda unsigned long fifoaddr = r8a66597->reg + offset; 5439424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda unsigned long count; 5449424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda 5459424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda count = len / 4; 5469424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda insl(fifoaddr, buf, count); 5479424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda 5489424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda if (len & 0x00000003) { 5499424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda unsigned long tmp = inl(fifoaddr); 5509424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03); 5519424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda } 5529424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#else 5535d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda len = (len + 1) / 2; 5545d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda insw(r8a66597->reg + offset, buf, len); 5559424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#endif 5565d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 5575d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5585d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val, 5595d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long offset) 5605d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 5615d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda outw(val, r8a66597->reg + offset); 5625d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 5635d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5645d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline void r8a66597_write_fifo(struct r8a66597 *r8a66597, 5655d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long offset, u16 *buf, 5665d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda int len) 5675d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 5685d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long fifoaddr = r8a66597->reg + offset; 5699424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) 5709424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda unsigned long count; 5719424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda unsigned char *pb; 5729424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda int i; 5739424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda 5749424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda count = len / 4; 5759424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda outsl(fifoaddr, buf, count); 5769424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda 5779424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda if (len & 0x00000003) { 5789424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda pb = (unsigned char *)buf + count * 4; 5799424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda for (i = 0; i < (len & 0x00000003); i++) { 5809424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND) 5819424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda outb(pb[i], fifoaddr + i); 5829424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda else 5839424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda outb(pb[i], fifoaddr + 3 - i); 5849424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda } 5859424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda } 5869424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#else 5875d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda int odd = len & 0x0001; 5885d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5895d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda len = len / 2; 5905d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda outsw(fifoaddr, buf, len); 5915d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda if (unlikely(odd)) { 5925d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda buf = &buf[len]; 5935d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda outb((unsigned char)*buf, fifoaddr); 5945d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda } 5959424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda#endif 5965d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 5975d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 5985d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline void r8a66597_mdfy(struct r8a66597 *r8a66597, 5995d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 val, u16 pat, unsigned long offset) 6005d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 6015d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda u16 tmp; 6025d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda tmp = r8a66597_read(r8a66597, offset); 6035d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda tmp = tmp & (~pat); 6045d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda tmp = tmp | val; 6055d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda r8a66597_write(r8a66597, tmp, offset); 6065d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 6075d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6085d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define r8a66597_bclr(r8a66597, val, offset) \ 6095d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda r8a66597_mdfy(r8a66597, 0, val, offset) 6105d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define r8a66597_bset(r8a66597, val, offset) \ 6115d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda r8a66597_mdfy(r8a66597, val, 0, offset) 6125d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6135d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline unsigned long get_syscfg_reg(int port) 6145d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 6155d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return port == 0 ? SYSCFG0 : SYSCFG1; 6165d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 6175d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6185d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline unsigned long get_syssts_reg(int port) 6195d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 6205d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return port == 0 ? SYSSTS0 : SYSSTS1; 6215d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 6225d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6235d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline unsigned long get_dvstctr_reg(int port) 6245d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 6255d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return port == 0 ? DVSTCTR0 : DVSTCTR1; 6265d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 6275d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6289424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimodastatic inline unsigned long get_dmacfg_reg(int port) 6299424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda{ 6309424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda return port == 0 ? DMA0CFG : DMA1CFG; 6319424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda} 6329424ea29658ce5bcdcf527ddf9617b9507ddf1aaYoshihiro Shimoda 6335d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline unsigned long get_intenb_reg(int port) 6345d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 6355d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return port == 0 ? INTENB1 : INTENB2; 6365d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 6375d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6385d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline unsigned long get_intsts_reg(int port) 6395d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 6405d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return port == 0 ? INTSTS1 : INTSTS2; 6415d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 6425d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6435d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port) 6445d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 6455d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long dvstctr_reg = get_dvstctr_reg(port); 6465d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6475d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda return r8a66597_read(r8a66597, dvstctr_reg) & RHST; 6485d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 6495d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6505d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimodastatic inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port, 6515d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda int power) 6525d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda{ 6535d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda unsigned long dvstctr_reg = get_dvstctr_reg(port); 6545d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6555d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda if (power) 6565d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda r8a66597_bset(r8a66597, VBOUT, dvstctr_reg); 6575d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda else 6585d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg); 6595d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda} 6605d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6615d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2) 6625d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4) 6635d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4) 6645d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define get_devadd_addr(address) (DEVADD0 + address * 2) 6655d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6665d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define enable_irq_ready(r8a66597, pipenum) \ 6675d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda enable_pipe_irq(r8a66597, pipenum, BRDYENB) 6685d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define disable_irq_ready(r8a66597, pipenum) \ 6695d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda disable_pipe_irq(r8a66597, pipenum, BRDYENB) 6705d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define enable_irq_empty(r8a66597, pipenum) \ 6715d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda enable_pipe_irq(r8a66597, pipenum, BEMPENB) 6725d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define disable_irq_empty(r8a66597, pipenum) \ 6735d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda disable_pipe_irq(r8a66597, pipenum, BEMPENB) 6745d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define enable_irq_nrdy(r8a66597, pipenum) \ 6755d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda enable_pipe_irq(r8a66597, pipenum, NRDYENB) 6765d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#define disable_irq_nrdy(r8a66597, pipenum) \ 6775d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda disable_pipe_irq(r8a66597, pipenum, NRDYENB) 6785d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 6795d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda#endif /* __R8A66597_H__ */ 6805d3043586db428b5b4b3df89fa0c2db9731e934cYoshihiro Shimoda 681