r8a66597.h revision cf4f1e76c49dacfde0680b170b9a9b6a42f296bb 
1/*
2 * R8A66597 HCD (Host Controller Driver)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
6 * Portions Copyright (C) 2004-2005 David Brownell
7 * Portions Copyright (C) 1999 Roman Weissgaerber
8 *
9 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
23 *
24 */
25
26#ifndef __R8A66597_H__
27#define __R8A66597_H__
28
29#ifdef CONFIG_HAVE_CLK
30#include <linux/clk.h>
31#endif
32
33#include <linux/usb/r8a66597.h>
34
35#define R8A66597_MAX_NUM_PIPE		10
36#define R8A66597_BUF_BSIZE		8
37#define R8A66597_MAX_DEVICE		10
38#define R8A66597_MAX_ROOT_HUB		2
39#define R8A66597_MAX_SAMPLING		5
40#define R8A66597_RH_POLL_TIME		10
41#define R8A66597_MAX_DMA_CHANNEL	2
42#define R8A66597_PIPE_NO_DMA		R8A66597_MAX_DMA_CHANNEL
43#define check_bulk_or_isoc(pipenum)	((pipenum >= 1 && pipenum <= 5))
44#define check_interrupt(pipenum)	((pipenum >= 6 && pipenum <= 9))
45#define make_devsel(addr)		(addr << 12)
46
47struct r8a66597_pipe_info {
48	unsigned long timer_interval;
49	u16 pipenum;
50	u16 address;	/* R8A66597 HCD usb address */
51	u16 epnum;
52	u16 maxpacket;
53	u16 type;
54	u16 bufnum;
55	u16 buf_bsize;
56	u16 interval;
57	u16 dir_in;
58};
59
60struct r8a66597_pipe {
61	struct r8a66597_pipe_info info;
62
63	unsigned long fifoaddr;
64	unsigned long fifosel;
65	unsigned long fifoctr;
66	unsigned long pipectr;
67	unsigned long pipetre;
68	unsigned long pipetrn;
69};
70
71struct r8a66597_td {
72	struct r8a66597_pipe *pipe;
73	struct urb *urb;
74	struct list_head queue;
75
76	u16 type;
77	u16 pipenum;
78	int iso_cnt;
79
80	u16 address;		/* R8A66597's USB address */
81	u16 maxpacket;
82
83	unsigned zero_packet:1;
84	unsigned short_packet:1;
85	unsigned set_address:1;
86};
87
88struct r8a66597_device {
89	u16	address;	/* R8A66597's USB address */
90	u16	hub_port;
91	u16	root_port;
92
93	unsigned short ep_in_toggle;
94	unsigned short ep_out_toggle;
95	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
96	unsigned char dma_map;
97
98	enum usb_device_state state;
99
100	struct usb_device *udev;
101	int usb_address;
102	struct list_head device_list;
103};
104
105struct r8a66597_root_hub {
106	u32 port;
107	u16 old_syssts;
108	int scount;
109
110	struct r8a66597_device	*dev;
111};
112
113struct r8a66597 {
114	spinlock_t lock;
115	unsigned long reg;
116#ifdef CONFIG_HAVE_CLK
117	struct clk *clk;
118#endif
119	struct r8a66597_platdata	*pdata;
120	struct r8a66597_device		device0;
121	struct r8a66597_root_hub	root_hub[R8A66597_MAX_ROOT_HUB];
122	struct list_head		pipe_queue[R8A66597_MAX_NUM_PIPE];
123
124	struct timer_list rh_timer;
125	struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
126	struct timer_list interval_timer[R8A66597_MAX_NUM_PIPE];
127
128	unsigned short address_map;
129	unsigned short timeout_map;
130	unsigned short interval_map;
131	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
132	unsigned char dma_map;
133	unsigned int max_root_hub;
134
135	struct list_head child_device;
136	unsigned long child_connect_map[4];
137
138	unsigned bus_suspended:1;
139	unsigned irq_sense_low:1;
140};
141
142static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
143{
144	return (struct r8a66597 *)(hcd->hcd_priv);
145}
146
147static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
148{
149	return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
150}
151
152static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
153						  u16 pipenum)
154{
155	if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
156		return NULL;
157
158	return list_entry(r8a66597->pipe_queue[pipenum].next,
159			  struct r8a66597_td, queue);
160}
161
162static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
163					   u16 pipenum)
164{
165	struct r8a66597_td *td;
166
167	td = r8a66597_get_td(r8a66597, pipenum);
168	return (td ? td->urb : NULL);
169}
170
171static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
172{
173	return inw(r8a66597->reg + offset);
174}
175
176static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
177				      unsigned long offset, u16 *buf,
178				      int len)
179{
180	unsigned long fifoaddr = r8a66597->reg + offset;
181	unsigned long count;
182
183	if (r8a66597->pdata->on_chip) {
184		count = len / 4;
185		insl(fifoaddr, buf, count);
186
187		if (len & 0x00000003) {
188			unsigned long tmp = inl(fifoaddr);
189			memcpy((unsigned char *)buf + count * 4, &tmp,
190			       len & 0x03);
191		}
192	} else {
193		len = (len + 1) / 2;
194		insw(fifoaddr, buf, len);
195	}
196}
197
198static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
199				  unsigned long offset)
200{
201	outw(val, r8a66597->reg + offset);
202}
203
204static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
205				       unsigned long offset, u16 *buf,
206				       int len)
207{
208	unsigned long fifoaddr = r8a66597->reg + offset;
209	unsigned long count;
210	unsigned char *pb;
211	int i;
212
213	if (r8a66597->pdata->on_chip) {
214		count = len / 4;
215		outsl(fifoaddr, buf, count);
216
217		if (len & 0x00000003) {
218			pb = (unsigned char *)buf + count * 4;
219			for (i = 0; i < (len & 0x00000003); i++) {
220				if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
221					outb(pb[i], fifoaddr + i);
222				else
223					outb(pb[i], fifoaddr + 3 - i);
224			}
225		}
226	} else {
227		int odd = len & 0x0001;
228
229		len = len / 2;
230		outsw(fifoaddr, buf, len);
231		if (unlikely(odd)) {
232			buf = &buf[len];
233			outb((unsigned char)*buf, fifoaddr);
234		}
235	}
236}
237
238static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
239				 u16 val, u16 pat, unsigned long offset)
240{
241	u16 tmp;
242	tmp = r8a66597_read(r8a66597, offset);
243	tmp = tmp & (~pat);
244	tmp = tmp | val;
245	r8a66597_write(r8a66597, tmp, offset);
246}
247
248#define r8a66597_bclr(r8a66597, val, offset)	\
249			r8a66597_mdfy(r8a66597, 0, val, offset)
250#define r8a66597_bset(r8a66597, val, offset)	\
251			r8a66597_mdfy(r8a66597, val, 0, offset)
252
253static inline unsigned long get_syscfg_reg(int port)
254{
255	return port == 0 ? SYSCFG0 : SYSCFG1;
256}
257
258static inline unsigned long get_syssts_reg(int port)
259{
260	return port == 0 ? SYSSTS0 : SYSSTS1;
261}
262
263static inline unsigned long get_dvstctr_reg(int port)
264{
265	return port == 0 ? DVSTCTR0 : DVSTCTR1;
266}
267
268static inline unsigned long get_dmacfg_reg(int port)
269{
270	return port == 0 ? DMA0CFG : DMA1CFG;
271}
272
273static inline unsigned long get_intenb_reg(int port)
274{
275	return port == 0 ? INTENB1 : INTENB2;
276}
277
278static inline unsigned long get_intsts_reg(int port)
279{
280	return port == 0 ? INTSTS1 : INTSTS2;
281}
282
283static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
284{
285	unsigned long dvstctr_reg = get_dvstctr_reg(port);
286
287	return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
288}
289
290static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
291				       int power)
292{
293	unsigned long dvstctr_reg = get_dvstctr_reg(port);
294
295	if (r8a66597->pdata->port_power) {
296		r8a66597->pdata->port_power(port, power);
297	} else {
298		if (power)
299			r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
300		else
301			r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
302	}
303}
304
305static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
306{
307	u16 clock = 0;
308
309	switch (pdata->xtal) {
310	case R8A66597_PLATDATA_XTAL_12MHZ:
311		clock = XTAL12;
312		break;
313	case R8A66597_PLATDATA_XTAL_24MHZ:
314		clock = XTAL24;
315		break;
316	case R8A66597_PLATDATA_XTAL_48MHZ:
317		clock = XTAL48;
318		break;
319	default:
320		printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
321		break;
322	}
323
324	return clock;
325}
326
327#define get_pipectr_addr(pipenum)	(PIPE1CTR + (pipenum - 1) * 2)
328#define get_pipetre_addr(pipenum)	(PIPE1TRE + (pipenum - 1) * 4)
329#define get_pipetrn_addr(pipenum)	(PIPE1TRN + (pipenum - 1) * 4)
330#define get_devadd_addr(address)	(DEVADD0 + address * 2)
331
332#define enable_irq_ready(r8a66597, pipenum)	\
333	enable_pipe_irq(r8a66597, pipenum, BRDYENB)
334#define disable_irq_ready(r8a66597, pipenum)	\
335	disable_pipe_irq(r8a66597, pipenum, BRDYENB)
336#define enable_irq_empty(r8a66597, pipenum)	\
337	enable_pipe_irq(r8a66597, pipenum, BEMPENB)
338#define disable_irq_empty(r8a66597, pipenum)	\
339	disable_pipe_irq(r8a66597, pipenum, BEMPENB)
340#define enable_irq_nrdy(r8a66597, pipenum)	\
341	enable_pipe_irq(r8a66597, pipenum, NRDYENB)
342#define disable_irq_nrdy(r8a66597, pipenum)	\
343	disable_pipe_irq(r8a66597, pipenum, NRDYENB)
344
345#endif	/* __R8A66597_H__ */
346
347