1/* 2 * Universal Host Controller Interface driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * (C) Copyright 1999 Linus Torvalds 7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com 8 * (C) Copyright 1999 Randy Dunlap 9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de 10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de 11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch 12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at 13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface 14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). 15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) 16 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu 17 * 18 * Intel documents this fairly well, and as far as I know there 19 * are no royalties or anything like that, but even so there are 20 * people who decided that they want to do the same thing in a 21 * completely different way. 22 * 23 */ 24 25#include <linux/module.h> 26#include <linux/pci.h> 27#include <linux/kernel.h> 28#include <linux/init.h> 29#include <linux/delay.h> 30#include <linux/ioport.h> 31#include <linux/slab.h> 32#include <linux/errno.h> 33#include <linux/unistd.h> 34#include <linux/interrupt.h> 35#include <linux/spinlock.h> 36#include <linux/debugfs.h> 37#include <linux/pm.h> 38#include <linux/dmapool.h> 39#include <linux/dma-mapping.h> 40#include <linux/usb.h> 41#include <linux/usb/hcd.h> 42#include <linux/bitops.h> 43#include <linux/dmi.h> 44 45#include <asm/uaccess.h> 46#include <asm/io.h> 47#include <asm/irq.h> 48 49#include "uhci-hcd.h" 50 51/* 52 * Version Information 53 */ 54#define DRIVER_AUTHOR \ 55 "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, " \ 56 "Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, " \ 57 "Roman Weissgaerber, Alan Stern" 58#define DRIVER_DESC "USB Universal Host Controller Interface driver" 59 60/* for flakey hardware, ignore overcurrent indicators */ 61static bool ignore_oc; 62module_param(ignore_oc, bool, S_IRUGO); 63MODULE_PARM_DESC(ignore_oc, "ignore hardware overcurrent indications"); 64 65/* 66 * debug = 0, no debugging messages 67 * debug = 1, dump failed URBs except for stalls 68 * debug = 2, dump all failed URBs (including stalls) 69 * show all queues in /sys/kernel/debug/uhci/[pci_addr] 70 * debug = 3, show all TDs in URBs when dumping 71 */ 72#ifdef CONFIG_DYNAMIC_DEBUG 73 74static int debug = 1; 75module_param(debug, int, S_IRUGO | S_IWUSR); 76MODULE_PARM_DESC(debug, "Debug level"); 77static char *errbuf; 78 79#else 80 81#define debug 0 82#define errbuf NULL 83 84#endif 85 86 87#define ERRBUF_LEN (32 * 1024) 88 89static struct kmem_cache *uhci_up_cachep; /* urb_priv */ 90 91static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state); 92static void wakeup_rh(struct uhci_hcd *uhci); 93static void uhci_get_current_frame_number(struct uhci_hcd *uhci); 94 95/* 96 * Calculate the link pointer DMA value for the first Skeleton QH in a frame. 97 */ 98static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) 99{ 100 int skelnum; 101 102 /* 103 * The interrupt queues will be interleaved as evenly as possible. 104 * There's not much to be done about period-1 interrupts; they have 105 * to occur in every frame. But we can schedule period-2 interrupts 106 * in odd-numbered frames, period-4 interrupts in frames congruent 107 * to 2 (mod 4), and so on. This way each frame only has two 108 * interrupt QHs, which will help spread out bandwidth utilization. 109 * 110 * ffs (Find First bit Set) does exactly what we need: 111 * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8], 112 * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc. 113 * ffs >= 7 => not on any high-period queue, so use 114 * period-1 QH = skelqh[9]. 115 * Add in UHCI_NUMFRAMES to insure at least one bit is set. 116 */ 117 skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES); 118 if (skelnum <= 1) 119 skelnum = 9; 120 return LINK_TO_QH(uhci, uhci->skelqh[skelnum]); 121} 122 123#include "uhci-debug.c" 124#include "uhci-q.c" 125#include "uhci-hub.c" 126 127/* 128 * Finish up a host controller reset and update the recorded state. 129 */ 130static void finish_reset(struct uhci_hcd *uhci) 131{ 132 int port; 133 134 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect 135 * bits in the port status and control registers. 136 * We have to clear them by hand. 137 */ 138 for (port = 0; port < uhci->rh_numports; ++port) 139 uhci_writew(uhci, 0, USBPORTSC1 + (port * 2)); 140 141 uhci->port_c_suspend = uhci->resuming_ports = 0; 142 uhci->rh_state = UHCI_RH_RESET; 143 uhci->is_stopped = UHCI_IS_STOPPED; 144 clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 145} 146 147/* 148 * Last rites for a defunct/nonfunctional controller 149 * or one we don't want to use any more. 150 */ 151static void uhci_hc_died(struct uhci_hcd *uhci) 152{ 153 uhci_get_current_frame_number(uhci); 154 uhci->reset_hc(uhci); 155 finish_reset(uhci); 156 uhci->dead = 1; 157 158 /* The current frame may already be partway finished */ 159 ++uhci->frame_number; 160} 161 162/* 163 * Initialize a controller that was newly discovered or has lost power 164 * or otherwise been reset while it was suspended. In none of these cases 165 * can we be sure of its previous state. 166 */ 167static void check_and_reset_hc(struct uhci_hcd *uhci) 168{ 169 if (uhci->check_and_reset_hc(uhci)) 170 finish_reset(uhci); 171} 172 173#if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC) 174/* 175 * The two functions below are generic reset functions that are used on systems 176 * that do not have keyboard and mouse legacy support. We assume that we are 177 * running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined. 178 */ 179 180/* 181 * Make sure the controller is completely inactive, unable to 182 * generate interrupts or do DMA. 183 */ 184static void uhci_generic_reset_hc(struct uhci_hcd *uhci) 185{ 186 /* Reset the HC - this will force us to get a 187 * new notification of any already connected 188 * ports due to the virtual disconnect that it 189 * implies. 190 */ 191 uhci_writew(uhci, USBCMD_HCRESET, USBCMD); 192 mb(); 193 udelay(5); 194 if (uhci_readw(uhci, USBCMD) & USBCMD_HCRESET) 195 dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n"); 196 197 /* Just to be safe, disable interrupt requests and 198 * make sure the controller is stopped. 199 */ 200 uhci_writew(uhci, 0, USBINTR); 201 uhci_writew(uhci, 0, USBCMD); 202} 203 204/* 205 * Initialize a controller that was newly discovered or has just been 206 * resumed. In either case we can't be sure of its previous state. 207 * 208 * Returns: 1 if the controller was reset, 0 otherwise. 209 */ 210static int uhci_generic_check_and_reset_hc(struct uhci_hcd *uhci) 211{ 212 unsigned int cmd, intr; 213 214 /* 215 * When restarting a suspended controller, we expect all the 216 * settings to be the same as we left them: 217 * 218 * Controller is stopped and configured with EGSM set; 219 * No interrupts enabled except possibly Resume Detect. 220 * 221 * If any of these conditions are violated we do a complete reset. 222 */ 223 224 cmd = uhci_readw(uhci, USBCMD); 225 if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) { 226 dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n", 227 __func__, cmd); 228 goto reset_needed; 229 } 230 231 intr = uhci_readw(uhci, USBINTR); 232 if (intr & (~USBINTR_RESUME)) { 233 dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n", 234 __func__, intr); 235 goto reset_needed; 236 } 237 return 0; 238 239reset_needed: 240 dev_dbg(uhci_dev(uhci), "Performing full reset\n"); 241 uhci_generic_reset_hc(uhci); 242 return 1; 243} 244#endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ 245 246/* 247 * Store the basic register settings needed by the controller. 248 */ 249static void configure_hc(struct uhci_hcd *uhci) 250{ 251 /* Set the frame length to the default: 1 ms exactly */ 252 uhci_writeb(uhci, USBSOF_DEFAULT, USBSOF); 253 254 /* Store the frame list base address */ 255 uhci_writel(uhci, uhci->frame_dma_handle, USBFLBASEADD); 256 257 /* Set the current frame number */ 258 uhci_writew(uhci, uhci->frame_number & UHCI_MAX_SOF_NUMBER, 259 USBFRNUM); 260 261 /* perform any arch/bus specific configuration */ 262 if (uhci->configure_hc) 263 uhci->configure_hc(uhci); 264} 265 266static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) 267{ 268 /* If we have to ignore overcurrent events then almost by definition 269 * we can't depend on resume-detect interrupts. */ 270 if (ignore_oc) 271 return 1; 272 273 return uhci->resume_detect_interrupts_are_broken ? 274 uhci->resume_detect_interrupts_are_broken(uhci) : 0; 275} 276 277static int global_suspend_mode_is_broken(struct uhci_hcd *uhci) 278{ 279 return uhci->global_suspend_mode_is_broken ? 280 uhci->global_suspend_mode_is_broken(uhci) : 0; 281} 282 283static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) 284__releases(uhci->lock) 285__acquires(uhci->lock) 286{ 287 int auto_stop; 288 int int_enable, egsm_enable, wakeup_enable; 289 struct usb_device *rhdev = uhci_to_hcd(uhci)->self.root_hub; 290 291 auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); 292 dev_dbg(&rhdev->dev, "%s%s\n", __func__, 293 (auto_stop ? " (auto-stop)" : "")); 294 295 /* Start off by assuming Resume-Detect interrupts and EGSM work 296 * and that remote wakeups should be enabled. 297 */ 298 egsm_enable = USBCMD_EGSM; 299 int_enable = USBINTR_RESUME; 300 wakeup_enable = 1; 301 302 /* 303 * In auto-stop mode, we must be able to detect new connections. 304 * The user can force us to poll by disabling remote wakeup; 305 * otherwise we will use the EGSM/RD mechanism. 306 */ 307 if (auto_stop) { 308 if (!device_may_wakeup(&rhdev->dev)) 309 egsm_enable = int_enable = 0; 310 } 311 312#ifdef CONFIG_PM 313 /* 314 * In bus-suspend mode, we use the wakeup setting specified 315 * for the root hub. 316 */ 317 else { 318 if (!rhdev->do_remote_wakeup) 319 wakeup_enable = 0; 320 } 321#endif 322 323 /* 324 * UHCI doesn't distinguish between wakeup requests from downstream 325 * devices and local connect/disconnect events. There's no way to 326 * enable one without the other; both are controlled by EGSM. Thus 327 * if wakeups are disallowed then EGSM must be turned off -- in which 328 * case remote wakeup requests from downstream during system sleep 329 * will be lost. 330 * 331 * In addition, if EGSM is broken then we can't use it. Likewise, 332 * if Resume-Detect interrupts are broken then we can't use them. 333 * 334 * Finally, neither EGSM nor RD is useful by itself. Without EGSM, 335 * the RD status bit will never get set. Without RD, the controller 336 * won't generate interrupts to tell the system about wakeup events. 337 */ 338 if (!wakeup_enable || global_suspend_mode_is_broken(uhci) || 339 resume_detect_interrupts_are_broken(uhci)) 340 egsm_enable = int_enable = 0; 341 342 uhci->RD_enable = !!int_enable; 343 uhci_writew(uhci, int_enable, USBINTR); 344 uhci_writew(uhci, egsm_enable | USBCMD_CF, USBCMD); 345 mb(); 346 udelay(5); 347 348 /* If we're auto-stopping then no devices have been attached 349 * for a while, so there shouldn't be any active URBs and the 350 * controller should stop after a few microseconds. Otherwise 351 * we will give the controller one frame to stop. 352 */ 353 if (!auto_stop && !(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) { 354 uhci->rh_state = UHCI_RH_SUSPENDING; 355 spin_unlock_irq(&uhci->lock); 356 msleep(1); 357 spin_lock_irq(&uhci->lock); 358 if (uhci->dead) 359 return; 360 } 361 if (!(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) 362 dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); 363 364 uhci_get_current_frame_number(uhci); 365 366 uhci->rh_state = new_state; 367 uhci->is_stopped = UHCI_IS_STOPPED; 368 369 /* 370 * If remote wakeup is enabled but either EGSM or RD interrupts 371 * doesn't work, then we won't get an interrupt when a wakeup event 372 * occurs. Thus the suspended root hub needs to be polled. 373 */ 374 if (wakeup_enable && (!int_enable || !egsm_enable)) 375 set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 376 else 377 clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 378 379 uhci_scan_schedule(uhci); 380 uhci_fsbr_off(uhci); 381} 382 383static void start_rh(struct uhci_hcd *uhci) 384{ 385 uhci->is_stopped = 0; 386 387 /* Mark it configured and running with a 64-byte max packet. 388 * All interrupts are enabled, even though RESUME won't do anything. 389 */ 390 uhci_writew(uhci, USBCMD_RS | USBCMD_CF | USBCMD_MAXP, USBCMD); 391 uhci_writew(uhci, USBINTR_TIMEOUT | USBINTR_RESUME | 392 USBINTR_IOC | USBINTR_SP, USBINTR); 393 mb(); 394 uhci->rh_state = UHCI_RH_RUNNING; 395 set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 396} 397 398static void wakeup_rh(struct uhci_hcd *uhci) 399__releases(uhci->lock) 400__acquires(uhci->lock) 401{ 402 dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, 403 "%s%s\n", __func__, 404 uhci->rh_state == UHCI_RH_AUTO_STOPPED ? 405 " (auto-start)" : ""); 406 407 /* If we are auto-stopped then no devices are attached so there's 408 * no need for wakeup signals. Otherwise we send Global Resume 409 * for 20 ms. 410 */ 411 if (uhci->rh_state == UHCI_RH_SUSPENDED) { 412 unsigned egsm; 413 414 /* Keep EGSM on if it was set before */ 415 egsm = uhci_readw(uhci, USBCMD) & USBCMD_EGSM; 416 uhci->rh_state = UHCI_RH_RESUMING; 417 uhci_writew(uhci, USBCMD_FGR | USBCMD_CF | egsm, USBCMD); 418 spin_unlock_irq(&uhci->lock); 419 msleep(20); 420 spin_lock_irq(&uhci->lock); 421 if (uhci->dead) 422 return; 423 424 /* End Global Resume and wait for EOP to be sent */ 425 uhci_writew(uhci, USBCMD_CF, USBCMD); 426 mb(); 427 udelay(4); 428 if (uhci_readw(uhci, USBCMD) & USBCMD_FGR) 429 dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); 430 } 431 432 start_rh(uhci); 433 434 /* Restart root hub polling */ 435 mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); 436} 437 438static irqreturn_t uhci_irq(struct usb_hcd *hcd) 439{ 440 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 441 unsigned short status; 442 443 /* 444 * Read the interrupt status, and write it back to clear the 445 * interrupt cause. Contrary to the UHCI specification, the 446 * "HC Halted" status bit is persistent: it is RO, not R/WC. 447 */ 448 status = uhci_readw(uhci, USBSTS); 449 if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ 450 return IRQ_NONE; 451 uhci_writew(uhci, status, USBSTS); /* Clear it */ 452 453 spin_lock(&uhci->lock); 454 if (unlikely(!uhci->is_initialized)) /* not yet configured */ 455 goto done; 456 457 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { 458 if (status & USBSTS_HSE) 459 dev_err(uhci_dev(uhci), 460 "host system error, PCI problems?\n"); 461 if (status & USBSTS_HCPE) 462 dev_err(uhci_dev(uhci), 463 "host controller process error, something bad happened!\n"); 464 if (status & USBSTS_HCH) { 465 if (uhci->rh_state >= UHCI_RH_RUNNING) { 466 dev_err(uhci_dev(uhci), 467 "host controller halted, very bad!\n"); 468 if (debug > 1 && errbuf) { 469 /* Print the schedule for debugging */ 470 uhci_sprint_schedule(uhci, errbuf, 471 ERRBUF_LEN - EXTRA_SPACE); 472 lprintk(errbuf); 473 } 474 uhci_hc_died(uhci); 475 usb_hc_died(hcd); 476 477 /* Force a callback in case there are 478 * pending unlinks */ 479 mod_timer(&hcd->rh_timer, jiffies); 480 } 481 } 482 } 483 484 if (status & USBSTS_RD) { 485 spin_unlock(&uhci->lock); 486 usb_hcd_poll_rh_status(hcd); 487 } else { 488 uhci_scan_schedule(uhci); 489 done: 490 spin_unlock(&uhci->lock); 491 } 492 493 return IRQ_HANDLED; 494} 495 496/* 497 * Store the current frame number in uhci->frame_number if the controller 498 * is running. Expand from 11 bits (of which we use only 10) to a 499 * full-sized integer. 500 * 501 * Like many other parts of the driver, this code relies on being polled 502 * more than once per second as long as the controller is running. 503 */ 504static void uhci_get_current_frame_number(struct uhci_hcd *uhci) 505{ 506 if (!uhci->is_stopped) { 507 unsigned delta; 508 509 delta = (uhci_readw(uhci, USBFRNUM) - uhci->frame_number) & 510 (UHCI_NUMFRAMES - 1); 511 uhci->frame_number += delta; 512 } 513} 514 515/* 516 * De-allocate all resources 517 */ 518static void release_uhci(struct uhci_hcd *uhci) 519{ 520 int i; 521 522 523 spin_lock_irq(&uhci->lock); 524 uhci->is_initialized = 0; 525 spin_unlock_irq(&uhci->lock); 526 527 debugfs_remove(uhci->dentry); 528 529 for (i = 0; i < UHCI_NUM_SKELQH; i++) 530 uhci_free_qh(uhci, uhci->skelqh[i]); 531 532 uhci_free_td(uhci, uhci->term_td); 533 534 dma_pool_destroy(uhci->qh_pool); 535 536 dma_pool_destroy(uhci->td_pool); 537 538 kfree(uhci->frame_cpu); 539 540 dma_free_coherent(uhci_dev(uhci), 541 UHCI_NUMFRAMES * sizeof(*uhci->frame), 542 uhci->frame, uhci->frame_dma_handle); 543} 544 545/* 546 * Allocate a frame list, and then setup the skeleton 547 * 548 * The hardware doesn't really know any difference 549 * in the queues, but the order does matter for the 550 * protocols higher up. The order in which the queues 551 * are encountered by the hardware is: 552 * 553 * - All isochronous events are handled before any 554 * of the queues. We don't do that here, because 555 * we'll create the actual TD entries on demand. 556 * - The first queue is the high-period interrupt queue. 557 * - The second queue is the period-1 interrupt and async 558 * (low-speed control, full-speed control, then bulk) queue. 559 * - The third queue is the terminating bandwidth reclamation queue, 560 * which contains no members, loops back to itself, and is present 561 * only when FSBR is on and there are no full-speed control or bulk QHs. 562 */ 563static int uhci_start(struct usb_hcd *hcd) 564{ 565 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 566 int retval = -EBUSY; 567 int i; 568 struct dentry __maybe_unused *dentry; 569 570 hcd->uses_new_polling = 1; 571 /* Accept arbitrarily long scatter-gather lists */ 572 if (!(hcd->driver->flags & HCD_LOCAL_MEM)) 573 hcd->self.sg_tablesize = ~0; 574 575 spin_lock_init(&uhci->lock); 576 setup_timer(&uhci->fsbr_timer, uhci_fsbr_timeout, 577 (unsigned long) uhci); 578 INIT_LIST_HEAD(&uhci->idle_qh_list); 579 init_waitqueue_head(&uhci->waitqh); 580 581#ifdef UHCI_DEBUG_OPS 582 dentry = debugfs_create_file(hcd->self.bus_name, 583 S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, 584 uhci, &uhci_debug_operations); 585 if (!dentry) { 586 dev_err(uhci_dev(uhci), "couldn't create uhci debugfs entry\n"); 587 return -ENOMEM; 588 } 589 uhci->dentry = dentry; 590#endif 591 592 uhci->frame = dma_alloc_coherent(uhci_dev(uhci), 593 UHCI_NUMFRAMES * sizeof(*uhci->frame), 594 &uhci->frame_dma_handle, GFP_KERNEL); 595 if (!uhci->frame) { 596 dev_err(uhci_dev(uhci), 597 "unable to allocate consistent memory for frame list\n"); 598 goto err_alloc_frame; 599 } 600 memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame)); 601 602 uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu), 603 GFP_KERNEL); 604 if (!uhci->frame_cpu) { 605 dev_err(uhci_dev(uhci), 606 "unable to allocate memory for frame pointers\n"); 607 goto err_alloc_frame_cpu; 608 } 609 610 uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), 611 sizeof(struct uhci_td), 16, 0); 612 if (!uhci->td_pool) { 613 dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); 614 goto err_create_td_pool; 615 } 616 617 uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), 618 sizeof(struct uhci_qh), 16, 0); 619 if (!uhci->qh_pool) { 620 dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); 621 goto err_create_qh_pool; 622 } 623 624 uhci->term_td = uhci_alloc_td(uhci); 625 if (!uhci->term_td) { 626 dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); 627 goto err_alloc_term_td; 628 } 629 630 for (i = 0; i < UHCI_NUM_SKELQH; i++) { 631 uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL); 632 if (!uhci->skelqh[i]) { 633 dev_err(uhci_dev(uhci), "unable to allocate QH\n"); 634 goto err_alloc_skelqh; 635 } 636 } 637 638 /* 639 * 8 Interrupt queues; link all higher int queues to int1 = async 640 */ 641 for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i) 642 uhci->skelqh[i]->link = LINK_TO_QH(uhci, uhci->skel_async_qh); 643 uhci->skel_async_qh->link = UHCI_PTR_TERM(uhci); 644 uhci->skel_term_qh->link = LINK_TO_QH(uhci, uhci->skel_term_qh); 645 646 /* This dummy TD is to work around a bug in Intel PIIX controllers */ 647 uhci_fill_td(uhci, uhci->term_td, 0, uhci_explen(0) | 648 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); 649 uhci->term_td->link = UHCI_PTR_TERM(uhci); 650 uhci->skel_async_qh->element = uhci->skel_term_qh->element = 651 LINK_TO_TD(uhci, uhci->term_td); 652 653 /* 654 * Fill the frame list: make all entries point to the proper 655 * interrupt queue. 656 */ 657 for (i = 0; i < UHCI_NUMFRAMES; i++) { 658 659 /* Only place we don't use the frame list routines */ 660 uhci->frame[i] = uhci_frame_skel_link(uhci, i); 661 } 662 663 /* 664 * Some architectures require a full mb() to enforce completion of 665 * the memory writes above before the I/O transfers in configure_hc(). 666 */ 667 mb(); 668 669 spin_lock_irq(&uhci->lock); 670 configure_hc(uhci); 671 uhci->is_initialized = 1; 672 start_rh(uhci); 673 spin_unlock_irq(&uhci->lock); 674 return 0; 675 676/* 677 * error exits: 678 */ 679err_alloc_skelqh: 680 for (i = 0; i < UHCI_NUM_SKELQH; i++) { 681 if (uhci->skelqh[i]) 682 uhci_free_qh(uhci, uhci->skelqh[i]); 683 } 684 685 uhci_free_td(uhci, uhci->term_td); 686 687err_alloc_term_td: 688 dma_pool_destroy(uhci->qh_pool); 689 690err_create_qh_pool: 691 dma_pool_destroy(uhci->td_pool); 692 693err_create_td_pool: 694 kfree(uhci->frame_cpu); 695 696err_alloc_frame_cpu: 697 dma_free_coherent(uhci_dev(uhci), 698 UHCI_NUMFRAMES * sizeof(*uhci->frame), 699 uhci->frame, uhci->frame_dma_handle); 700 701err_alloc_frame: 702 debugfs_remove(uhci->dentry); 703 704 return retval; 705} 706 707static void uhci_stop(struct usb_hcd *hcd) 708{ 709 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 710 711 spin_lock_irq(&uhci->lock); 712 if (HCD_HW_ACCESSIBLE(hcd) && !uhci->dead) 713 uhci_hc_died(uhci); 714 uhci_scan_schedule(uhci); 715 spin_unlock_irq(&uhci->lock); 716 synchronize_irq(hcd->irq); 717 718 del_timer_sync(&uhci->fsbr_timer); 719 release_uhci(uhci); 720} 721 722#ifdef CONFIG_PM 723static int uhci_rh_suspend(struct usb_hcd *hcd) 724{ 725 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 726 int rc = 0; 727 728 spin_lock_irq(&uhci->lock); 729 if (!HCD_HW_ACCESSIBLE(hcd)) 730 rc = -ESHUTDOWN; 731 else if (uhci->dead) 732 ; /* Dead controllers tell no tales */ 733 734 /* Once the controller is stopped, port resumes that are already 735 * in progress won't complete. Hence if remote wakeup is enabled 736 * for the root hub and any ports are in the middle of a resume or 737 * remote wakeup, we must fail the suspend. 738 */ 739 else if (hcd->self.root_hub->do_remote_wakeup && 740 uhci->resuming_ports) { 741 dev_dbg(uhci_dev(uhci), 742 "suspend failed because a port is resuming\n"); 743 rc = -EBUSY; 744 } else 745 suspend_rh(uhci, UHCI_RH_SUSPENDED); 746 spin_unlock_irq(&uhci->lock); 747 return rc; 748} 749 750static int uhci_rh_resume(struct usb_hcd *hcd) 751{ 752 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 753 int rc = 0; 754 755 spin_lock_irq(&uhci->lock); 756 if (!HCD_HW_ACCESSIBLE(hcd)) 757 rc = -ESHUTDOWN; 758 else if (!uhci->dead) 759 wakeup_rh(uhci); 760 spin_unlock_irq(&uhci->lock); 761 return rc; 762} 763 764#endif 765 766/* Wait until a particular device/endpoint's QH is idle, and free it */ 767static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, 768 struct usb_host_endpoint *hep) 769{ 770 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 771 struct uhci_qh *qh; 772 773 spin_lock_irq(&uhci->lock); 774 qh = (struct uhci_qh *) hep->hcpriv; 775 if (qh == NULL) 776 goto done; 777 778 while (qh->state != QH_STATE_IDLE) { 779 ++uhci->num_waiting; 780 spin_unlock_irq(&uhci->lock); 781 wait_event_interruptible(uhci->waitqh, 782 qh->state == QH_STATE_IDLE); 783 spin_lock_irq(&uhci->lock); 784 --uhci->num_waiting; 785 } 786 787 uhci_free_qh(uhci, qh); 788done: 789 spin_unlock_irq(&uhci->lock); 790} 791 792static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) 793{ 794 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 795 unsigned frame_number; 796 unsigned delta; 797 798 /* Minimize latency by avoiding the spinlock */ 799 frame_number = uhci->frame_number; 800 barrier(); 801 delta = (uhci_readw(uhci, USBFRNUM) - frame_number) & 802 (UHCI_NUMFRAMES - 1); 803 return frame_number + delta; 804} 805 806/* Determines number of ports on controller */ 807static int uhci_count_ports(struct usb_hcd *hcd) 808{ 809 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 810 unsigned io_size = (unsigned) hcd->rsrc_len; 811 int port; 812 813 /* The UHCI spec says devices must have 2 ports, and goes on to say 814 * they may have more but gives no way to determine how many there 815 * are. However according to the UHCI spec, Bit 7 of the port 816 * status and control register is always set to 1. So we try to 817 * use this to our advantage. Another common failure mode when 818 * a nonexistent register is addressed is to return all ones, so 819 * we test for that also. 820 */ 821 for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { 822 unsigned int portstatus; 823 824 portstatus = uhci_readw(uhci, USBPORTSC1 + (port * 2)); 825 if (!(portstatus & 0x0080) || portstatus == 0xffff) 826 break; 827 } 828 if (debug) 829 dev_info(uhci_dev(uhci), "detected %d ports\n", port); 830 831 /* Anything greater than 7 is weird so we'll ignore it. */ 832 if (port > UHCI_RH_MAXCHILD) { 833 dev_info(uhci_dev(uhci), 834 "port count misdetected? forcing to 2 ports\n"); 835 port = 2; 836 } 837 838 return port; 839} 840 841static const char hcd_name[] = "uhci_hcd"; 842 843#ifdef CONFIG_PCI 844#include "uhci-pci.c" 845#define PCI_DRIVER uhci_pci_driver 846#endif 847 848#ifdef CONFIG_SPARC_LEON 849#include "uhci-grlib.c" 850#define PLATFORM_DRIVER uhci_grlib_driver 851#endif 852 853#ifdef CONFIG_USB_UHCI_PLATFORM 854#include "uhci-platform.c" 855#define PLATFORM_DRIVER uhci_platform_driver 856#endif 857 858#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) 859#error "missing bus glue for uhci-hcd" 860#endif 861 862static int __init uhci_hcd_init(void) 863{ 864 int retval = -ENOMEM; 865 866 if (usb_disabled()) 867 return -ENODEV; 868 869 printk(KERN_INFO "uhci_hcd: " DRIVER_DESC "%s\n", 870 ignore_oc ? ", overcurrent ignored" : ""); 871 set_bit(USB_UHCI_LOADED, &usb_hcds_loaded); 872 873#ifdef CONFIG_DYNAMIC_DEBUG 874 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); 875 if (!errbuf) 876 goto errbuf_failed; 877 uhci_debugfs_root = debugfs_create_dir("uhci", usb_debug_root); 878 if (!uhci_debugfs_root) 879 goto debug_failed; 880#endif 881 882 uhci_up_cachep = kmem_cache_create("uhci_urb_priv", 883 sizeof(struct urb_priv), 0, 0, NULL); 884 if (!uhci_up_cachep) 885 goto up_failed; 886 887#ifdef PLATFORM_DRIVER 888 retval = platform_driver_register(&PLATFORM_DRIVER); 889 if (retval < 0) 890 goto clean0; 891#endif 892 893#ifdef PCI_DRIVER 894 retval = pci_register_driver(&PCI_DRIVER); 895 if (retval < 0) 896 goto clean1; 897#endif 898 899 return 0; 900 901#ifdef PCI_DRIVER 902clean1: 903#endif 904#ifdef PLATFORM_DRIVER 905 platform_driver_unregister(&PLATFORM_DRIVER); 906clean0: 907#endif 908 kmem_cache_destroy(uhci_up_cachep); 909 910up_failed: 911#if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) 912 debugfs_remove(uhci_debugfs_root); 913 914debug_failed: 915 kfree(errbuf); 916 917errbuf_failed: 918#endif 919 920 clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); 921 return retval; 922} 923 924static void __exit uhci_hcd_cleanup(void) 925{ 926#ifdef PLATFORM_DRIVER 927 platform_driver_unregister(&PLATFORM_DRIVER); 928#endif 929#ifdef PCI_DRIVER 930 pci_unregister_driver(&PCI_DRIVER); 931#endif 932 kmem_cache_destroy(uhci_up_cachep); 933 debugfs_remove(uhci_debugfs_root); 934#ifdef CONFIG_DYNAMIC_DEBUG 935 kfree(errbuf); 936#endif 937 clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); 938} 939 940module_init(uhci_hcd_init); 941module_exit(uhci_hcd_cleanup); 942 943MODULE_AUTHOR(DRIVER_AUTHOR); 944MODULE_DESCRIPTION(DRIVER_DESC); 945MODULE_LICENSE("GPL"); 946