1550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 2550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Copyright (C) 2005-2006 by Texas Instruments 3550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 4550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * This file implements a DMA interface using TI's CPPI DMA. 5550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * For now it's DaVinci-only, but CPPI isn't specific to DaVinci or USB. 6550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * The TUSB6020, using VLYNQ, has CPPI that looks much like DaVinci. 7550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 8550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 961af9c3f894a48297db3cc01aa38910bd6f92c27Reinhard Tartler#include <linux/module.h> 1091e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov#include <linux/platform_device.h> 115a0e3ad6af8660be21ca98a971cd00f331318c05Tejun Heo#include <linux/slab.h> 12550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include <linux/usb.h> 13550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 14550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include "musb_core.h" 15704a14854aaf9758a1248ea36a7d1b8cc42a4b3eHugo Villeneuve#include "musb_debug.h" 16550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include "cppi_dma.h" 17550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 18550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 19550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* CPPI DMA status 7-mar-2006: 20550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 21550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - See musb_{host,gadget}.c for more info 22550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 23550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - Correct RX DMA generally forces the engine into irq-per-packet mode, 24550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * which can easily saturate the CPU under non-mass-storage loads. 25550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 26550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * NOTES 24-aug-2006 (2.6.18-rc4): 27550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 28550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - peripheral RXDMA wedged in a test with packets of length 512/512/1. 29550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * evidently after the 1 byte packet was received and acked, the queue 30550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * of BDs got garbaged so it wouldn't empty the fifo. (rxcsr 0x2003, 31550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * and RX DMA0: 4 left, 80000000 8feff880, 8feff860 8feff860; 8f321401 32550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 004001ff 00000001 .. 8feff860) Host was just getting NAKed on tx 33550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * of its next (512 byte) packet. IRQ issues? 34550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 35550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT: the "transfer DMA" glue between CPPI and USB fifos will 36550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * evidently also directly update the RX and TX CSRs ... so audit all 37550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * host and peripheral side DMA code to avoid CSR access after DMA has 38550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * been started. 39550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 40550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 41550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* REVISIT now we can avoid preallocating these descriptors; or 42550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * more simply, switch to a global freelist not per-channel ones. 43550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Note: at full speed, 64 descriptors == 4K bulk data. 44550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 45550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define NUM_TXCHAN_BD 64 46550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define NUM_RXCHAN_BD 64 47550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 48550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline void cpu_drain_writebuffer(void) 49550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 50550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi wmb(); 51550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#ifdef CONFIG_CPU_ARM926T 52550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT this "should not be needed", 53550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * but lack of it sure seemed to hurt ... 54550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 55550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi asm("mcr p15, 0, r0, c7, c10, 4 @ drain write buffer\n"); 56550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#endif 57550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 58550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 59550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline struct cppi_descriptor *cppi_bd_alloc(struct cppi_channel *c) 60550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 61550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd = c->freelist; 62550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 63550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd) 64550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->freelist = bd->next; 65550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return bd; 66550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 67550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 68550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline void 69550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_bd_free(struct cppi_channel *c, struct cppi_descriptor *bd) 70550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 71550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!bd) 72550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return; 73550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->next = c->freelist; 74550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->freelist = bd; 75550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 76550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 77550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 78550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Start DMA controller 79550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 80550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Initialize the DMA controller as necessary. 81550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 82550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 83550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* zero out entire rx state RAM entry for the channel */ 84550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_reset_rx(struct cppi_rx_stateram __iomem *rx) 85550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 86550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_skipbytes, 0, 0); 87550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_head, 0, 0); 88550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_sop, 0, 0); 89550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_current, 0, 0); 90550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_buf_current, 0, 0); 91550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_len_len, 0, 0); 92550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_cnt_cnt, 0, 0); 93550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 94550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 95550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* zero out entire tx state RAM entry for the channel */ 96550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_reset_tx(struct cppi_tx_stateram __iomem *tx, u32 ptr) 97550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 98550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_head, 0, 0); 99550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_buf, 0, 0); 100550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_current, 0, 0); 101550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_buf_current, 0, 0); 102550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_info, 0, 0); 103550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_rem_len, 0, 0); 104550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* musb_writel(&tx->tx_dummy, 0, 0); */ 105550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_complete, 0, ptr); 106550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 107550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 108091a62c9b3d899d99dbf4e3dbebc8dfa3edbccddSergei Shtylyovstatic void cppi_pool_init(struct cppi *cppi, struct cppi_channel *c) 109550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 110550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int j; 111550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 112550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* initialize channel fields */ 113550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->head = NULL; 114550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->tail = NULL; 115550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->last_processed = NULL; 116550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->channel.status = MUSB_DMA_STATUS_UNKNOWN; 117550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->controller = cppi; 118550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->is_rndis = 0; 119550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->freelist = NULL; 120550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 121550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* build the BD Free list for the channel */ 122550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (j = 0; j < NUM_TXCHAN_BD + 1; j++) { 123550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 124550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t dma; 125550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 126550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = dma_pool_alloc(cppi->pool, GFP_KERNEL, &dma); 127550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->dma = dma; 128550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_bd_free(c, bd); 129550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 130550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 131550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 132550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic int cppi_channel_abort(struct dma_channel *); 133550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 134550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_pool_free(struct cppi_channel *c) 135550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 136550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *cppi = c->controller; 137550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 138550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 139550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi (void) cppi_channel_abort(&c->channel); 140550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->channel.status = MUSB_DMA_STATUS_UNKNOWN; 141550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->controller = NULL; 142550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 143550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* free all its bds */ 144550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = c->last_processed; 145550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi do { 146550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd) 147550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_pool_free(cppi->pool, bd, bd->dma); 148550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = cppi_bd_alloc(c); 149550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } while (bd); 150550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->last_processed = NULL; 151550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 152550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 15366c01883ef19bf4537b16931567b7d35c65356adSebastian Andrzej Siewiorstatic void cppi_controller_start(struct cppi *controller) 154550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 155550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; 156550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int i; 157550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 158550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* do whatever is necessary to start controller */ 159550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { 160550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->tx[i].transmit = true; 161550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->tx[i].index = i; 162550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 163550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->rx); i++) { 164550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->rx[i].transmit = false; 165550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->rx[i].index = i; 166550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 167550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 168550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* setup BD list on a per channel basis */ 169550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->tx); i++) 170550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_pool_init(controller, controller->tx + i); 171550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->rx); i++) 172550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_pool_init(controller, controller->rx + i); 173550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 174550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = controller->tibase; 175550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi INIT_LIST_HEAD(&controller->tx_complete); 176550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 177550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* initialise tx/rx channel head pointers to zero */ 178550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { 179550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *tx_ch = controller->tx + i; 180550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_tx_stateram __iomem *tx; 181550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 182550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi INIT_LIST_HEAD(&tx_ch->tx_complete); 183550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 184550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx = tibase + DAVINCI_TXCPPI_STATERAM_OFFSET(i); 185550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->state_ram = tx; 186550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_reset_tx(tx, 0); 187550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 188550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->rx); i++) { 189550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *rx_ch = controller->rx + i; 190550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_rx_stateram __iomem *rx; 191550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 192550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi INIT_LIST_HEAD(&rx_ch->tx_complete); 193550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 194550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx = tibase + DAVINCI_RXCPPI_STATERAM_OFFSET(i); 195550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx_ch->state_ram = rx; 196550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_reset_rx(rx); 197550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 198550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 199550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* enable individual cppi channels */ 200550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG, 201550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_DMA_ALL_CHANNELS_ENABLE); 202550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RXCPPI_INTENAB_REG, 203550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_DMA_ALL_CHANNELS_ENABLE); 204550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 205550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* enable tx/rx CPPI control */ 206550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE); 207550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE); 208550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 209550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* disable RNDIS mode, also host rx RNDIS autorequest */ 210550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RNDIS_REG, 0); 211550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_AUTOREQ_REG, 0); 212550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 213550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 214550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 215550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Stop DMA controller 216550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 217550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * De-Init the DMA controller as necessary. 218550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 219550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 22066c01883ef19bf4537b16931567b7d35c65356adSebastian Andrzej Siewiorstatic void cppi_controller_stop(struct cppi *controller) 221550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 222550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; 223550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int i; 224f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin struct musb *musb; 225550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 226f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin musb = controller->musb; 227550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 228550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = controller->tibase; 229550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* DISABLE INDIVIDUAL CHANNEL Interrupts */ 230550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG, 231550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_DMA_ALL_CHANNELS_ENABLE); 232550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG, 233550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_DMA_ALL_CHANNELS_ENABLE); 234550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 2355c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "Tearing down RX and TX Channels\n"); 236550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { 237550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FIXME restructure of txdma to use bds like rxdma */ 238550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->tx[i].last_processed = NULL; 239550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_pool_free(controller->tx + i); 240550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 241550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->rx); i++) 242550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_pool_free(controller->rx + i); 243550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 244550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* in Tx Case proper teardown is supported. We resort to disabling 245550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Tx/Rx CPPI after cleanup of Tx channels. Before TX teardown is 246550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * complete TX CPPI cannot be disabled. 247550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 248550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /*disable tx/rx cppi */ 249550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE); 250550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE); 251550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 252550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 253550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* While dma channel is allocated, we only want the core irqs active 254550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * for fault reports, otherwise we'd get irqs that we don't care about. 255550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Except for TX irqs, where dma done != fifo empty and reusable ... 256550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 257550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * NOTE: docs don't say either way, but irq masking **enables** irqs. 258550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 259550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT same issue applies to pure PIO usage too, and non-cppi dma... 260550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 261550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline void core_rxirq_disable(void __iomem *tibase, unsigned epnum) 262550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 263550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_USB_INT_MASK_CLR_REG, 1 << (epnum + 8)); 264550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 265550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 266550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline void core_rxirq_enable(void __iomem *tibase, unsigned epnum) 267550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 268550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_USB_INT_MASK_SET_REG, 1 << (epnum + 8)); 269550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 270550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 271550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 272550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 273550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Allocate a CPPI Channel for DMA. With CPPI, channels are bound to 274550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * each transfer direction of a non-control endpoint, so allocating 275550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (and deallocating) is mostly a way to notice bad housekeeping on 276550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the software side. We assume the irqs are always active. 277550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 278550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic struct dma_channel * 279550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_channel_allocate(struct dma_controller *c, 280550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct musb_hw_ep *ep, u8 transmit) 281550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 282550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 283550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u8 index; 284550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *cppi_ch; 285550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; 286f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin struct musb *musb; 287550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 288550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller = container_of(c, struct cppi, controller); 289550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = controller->tibase; 290f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin musb = controller->musb; 291550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 292550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* ep0 doesn't use DMA; remember cppi indices are 0..N-1 */ 293550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi index = ep->epnum - 1; 294550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 295550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* return the corresponding CPPI Channel Handle, and 296550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * probably disable the non-CPPI irq until we need it. 297550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 298550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (transmit) { 299550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (index >= ARRAY_SIZE(controller->tx)) { 3005c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'T', index); 301550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return NULL; 302550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 303550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch = controller->tx + index; 304550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 305550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (index >= ARRAY_SIZE(controller->rx)) { 3065c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'R', index); 307550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return NULL; 308550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 309550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch = controller->rx + index; 310550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi core_rxirq_disable(tibase, ep->epnum); 311550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 312550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 313550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT make this an error later once the same driver code works 314550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * with the other DMA engine too 315550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 316550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (cppi_ch->hw_ep) 3175c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "re-allocating DMA%d %cX channel %p\n", 318550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi index, transmit ? 'T' : 'R', cppi_ch); 319550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->hw_ep = ep; 320550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->channel.status = MUSB_DMA_STATUS_FREE; 32166af83ddf7b5a4ea94e79cbeadaa0aeed4def5f7Ming Lei cppi_ch->channel.max_len = 0x7fffffff; 322550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 3235c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R'); 324550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return &cppi_ch->channel; 325550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 326550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 327550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Release a CPPI Channel. */ 328550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_channel_release(struct dma_channel *channel) 329550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 330550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *c; 331550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; 332550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 333550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT: for paranoia, check state and abort if needed... */ 334550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 335550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c = container_of(channel, struct cppi_channel, channel); 336550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = c->controller->tibase; 337550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!c->hw_ep) 338f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin dev_dbg(c->controller->musb->controller, 339f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin "releasing idle DMA channel %p\n", c); 340550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else if (!c->transmit) 341550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi core_rxirq_enable(tibase, c->index + 1); 342550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 343550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* for now, leave its cppi IRQ enabled (we won't trigger it) */ 344550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->hw_ep = NULL; 345550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi channel->status = MUSB_DMA_STATUS_UNKNOWN; 346550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 347550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 348550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Context: controller irqlocked */ 349550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void 350550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_dump_rx(int level, struct cppi_channel *c, const char *tag) 351550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 352550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *base = c->controller->mregs; 353550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_rx_stateram __iomem *rx = c->state_ram; 354550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 355550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_ep_select(base, c->index + 1); 356550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 357f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin dev_dbg(c->controller->musb->controller, 358f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin "RX DMA%d%s: %d left, csr %04x, " 359f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin "%08x H%08x S%08x C%08x, " 360f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin "B%08x L%08x %08x .. %08x" 361f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin "\n", 362550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->index, tag, 363550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(c->controller->tibase, 364550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + 4 * c->index), 365550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readw(c->hw_ep->regs, MUSB_RXCSR), 366550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 367550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_skipbytes, 0), 368550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_head, 0), 369550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_sop, 0), 370550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_current, 0), 371550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 372550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_buf_current, 0), 373550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_len_len, 0), 374550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_cnt_cnt, 0), 375550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_complete, 0) 376550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi ); 377550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 378550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 379550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Context: controller irqlocked */ 380550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void 381550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_dump_tx(int level, struct cppi_channel *c, const char *tag) 382550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 383550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *base = c->controller->mregs; 384550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_tx_stateram __iomem *tx = c->state_ram; 385550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 386550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_ep_select(base, c->index + 1); 387550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 388f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin dev_dbg(c->controller->musb->controller, 389f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin "TX DMA%d%s: csr %04x, " 390f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin "H%08x S%08x C%08x %08x, " 391f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin "F%08x L%08x .. %08x" 392f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin "\n", 393550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->index, tag, 394550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readw(c->hw_ep->regs, MUSB_TXCSR), 395550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 396550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_head, 0), 397550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_buf, 0), 398550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_current, 0), 399550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_buf_current, 0), 400550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 401550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_info, 0), 402550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_rem_len, 0), 403550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* dummy/unused word 6 */ 404550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_complete, 0) 405550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi ); 406550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 407550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 408550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Context: controller irqlocked */ 409550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline void 410550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_rndis_update(struct cppi_channel *c, int is_rx, 411550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase, int is_rndis) 412550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 413550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* we may need to change the rndis flag for this cppi channel */ 414550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (c->is_rndis != is_rndis) { 415550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 value = musb_readl(tibase, DAVINCI_RNDIS_REG); 416550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 temp = 1 << (c->index); 417550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 418550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_rx) 419550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi temp <<= 16; 420550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_rndis) 421550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value |= temp; 422550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 423550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value &= ~temp; 424550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RNDIS_REG, value); 425550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->is_rndis = is_rndis; 426550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 427550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 428550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 429550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_dump_rxbd(const char *tag, struct cppi_descriptor *bd) 430550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 431550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi pr_debug("RXBD/%s %08x: " 432550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "nxt %08x buf %08x off.blen %08x opt.plen %08x\n", 433550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tag, bd->dma, 434550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_next, bd->hw_bufp, bd->hw_off_len, 435550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options); 436550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 437550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 438550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_dump_rxq(int level, const char *tag, struct cppi_channel *rx) 439550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 440550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 441550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 442550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rx(level, rx, tag); 443550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (rx->last_processed) 444550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rxbd("last", rx->last_processed); 445550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (bd = rx->head; bd; bd = bd->next) 446550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rxbd("active", bd); 447550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 448550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 449550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 450550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* NOTE: DaVinci autoreq is ignored except for host side "RNDIS" mode RX; 451550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * so we won't ever use it (see "CPPI RX Woes" below). 452550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 453550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline int cppi_autoreq_update(struct cppi_channel *rx, 454550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase, int onepacket, unsigned n_bds) 455550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 456550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 val; 457550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 458550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#ifdef RNDIS_RX_IS_USABLE 459550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 tmp; 460550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* assert(is_host_active(musb)) */ 461550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 462550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* start from "AutoReq never" */ 463550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG); 464550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val = tmp & ~((0x3) << (rx->index * 2)); 465550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 466550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* HCD arranged reqpkt for packet #1. we arrange int 467550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * for all but the last one, maybe in two segments. 468550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 469550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!onepacket) { 470550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#if 0 471550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* use two segments, autoreq "all" then the last "never" */ 472550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val |= ((0x3) << (rx->index * 2)); 473550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds--; 474550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#else 475550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* one segment, autoreq "all-but-last" */ 476550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val |= ((0x1) << (rx->index * 2)); 477550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#endif 478550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 479550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 480550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (val != tmp) { 481550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int n = 100; 482550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 483550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* make sure that autoreq is updated before continuing */ 484550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_AUTOREQ_REG, val); 485550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi do { 486550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG); 487550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (tmp == val) 488550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 489550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cpu_relax(); 490550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } while (n-- > 0); 491550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 492550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#endif 493550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 494550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REQPKT is turned off after each segment */ 495550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (n_bds && rx->channel.actual_len) { 496550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *regs = rx->hw_ep->regs; 497550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 498550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val = musb_readw(regs, MUSB_RXCSR); 499550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!(val & MUSB_RXCSR_H_REQPKT)) { 500550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS; 501550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writew(regs, MUSB_RXCSR, val); 50290802ed9c3dbab2e067bd9fc67a30e66e6774e8fPaul Bolle /* flush writebuffer */ 503550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val = musb_readw(regs, MUSB_RXCSR); 504550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 505550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 506550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return n_bds; 507550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 508550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 509550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 510550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Buffer enqueuing Logic: 511550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 512550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - RX builds new queues each time, to help handle routine "early 513550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * termination" cases (faults, including errors and short reads) 514550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * more correctly. 515550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 516550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - for now, TX reuses the same queue of BDs every time 517550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 518550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT long term, we want a normal dynamic model. 519550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * ... the goal will be to append to the 520550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * existing queue, processing completed "dma buffers" (segments) on the fly. 521550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 522550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Otherwise we force an IRQ latency between requests, which slows us a lot 523550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (especially in "transparent" dma). Unfortunately that model seems to be 524550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * inherent in the DMA model from the Mentor code, except in the rare case 525550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * of transfers big enough (~128+ KB) that we could append "middle" segments 526550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * in the TX paths. (RX can't do this, see below.) 527550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 528550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * That's true even in the CPPI- friendly iso case, where most urbs have 529550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * several small segments provided in a group and where the "packet at a time" 530550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * "transparent" DMA model is always correct, even on the RX side. 531550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 532550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 533550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 534550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * CPPI TX: 535550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * ======== 536550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * TX is a lot more reasonable than RX; it doesn't need to run in 537550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * irq-per-packet mode very often. RNDIS mode seems to behave too 538550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (except how it handles the exactly-N-packets case). Building a 539550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * txdma queue with multiple requests (urb or usb_request) looks 540550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * like it would work ... but fault handling would need much testing. 541550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 542550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * The main issue with TX mode RNDIS relates to transfer lengths that 543550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * are an exact multiple of the packet length. It appears that there's 544550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * a hiccup in that case (maybe the DMA completes before the ZLP gets 545550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * written?) boiling down to not being able to rely on CPPI writing any 546550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * terminating zero length packet before the next transfer is written. 547550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * So that's punted to PIO; better yet, gadget drivers can avoid it. 548550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 549550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Plus, there's allegedly an undocumented constraint that rndis transfer 550550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * length be a multiple of 64 bytes ... but the chip doesn't act that 551550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * way, and we really don't _want_ that behavior anyway. 552550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 553550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * On TX, "transparent" mode works ... although experiments have shown 554550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * problems trying to use the SOP/EOP bits in different USB packets. 555550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 556550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT try to handle terminating zero length packets using CPPI 557550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * instead of doing it by PIO after an IRQ. (Meanwhile, make Ethernet 558550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * links avoid that issue by forcing them to avoid zlps.) 559550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 560550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void 561550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx) 562550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 563550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned maxpacket = tx->maxpacket; 564550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t addr = tx->buf_dma + tx->offset; 565550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi size_t length = tx->buf_len - tx->offset; 566550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 567550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned n_bds; 568550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned i; 569550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_tx_stateram __iomem *tx_ram = tx->state_ram; 570550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int rndis; 571550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 572550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* TX can use the CPPI "rndis" mode, where we can probably fit this 573550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * transfer in one BD and one IRQ. The only time we would NOT want 574550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * to use it is when hardware constraints prevent it, or if we'd 575550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * trigger the "send a ZLP?" confusion. 576550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 577550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rndis = (maxpacket & 0x3f) == 0 5786b6e97107f12f3a9f7b5b43a6c3b94409240bcffSergei Shtylyov && length > maxpacket 579550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && length < 0xffff 580550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && (length % maxpacket) != 0; 581550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 582550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (rndis) { 583550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi maxpacket = length; 584550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = 1; 585550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 586550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = length / maxpacket; 587550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!length || (length % maxpacket)) 588550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds++; 589550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = min(n_bds, (unsigned) NUM_TXCHAN_BD); 590550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi length = min(n_bds * maxpacket, length); 591550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 592550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 5935c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n", 594550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->index, 595550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi maxpacket, 596550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rndis ? "rndis" : "transparent", 597550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds, 5982fbcf3fa43af809ebf4e4ad33c2f0a17e903385cDan Carpenter (unsigned long long)addr, length); 599550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 600550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_rndis_update(tx, 0, musb->ctrl_base, rndis); 601550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 602550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* assuming here that channel_program is called during 603550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * transfer initiation ... current code maintains state 604550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * for one outstanding request only (no queues, not even 605550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the implicit ones of an iso urb). 606550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 607550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 608550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = tx->freelist; 609550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->head = bd; 610550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->last_processed = NULL; 611550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 612550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FIXME use BD pool like RX side does, and just queue 613550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the minimum number for this request. 614550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 615550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 616550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Prepare queue of BDs first, then hand it to hardware. 617550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * All BDs except maybe the last should be of full packet 618550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * size; for RNDIS there _is_ only that last packet. 619550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 620550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < n_bds; ) { 621550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (++i < n_bds && bd->next) 622550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_next = bd->next->dma; 623550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 624550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_next = 0; 625550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 626550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_bufp = tx->buf_dma + tx->offset; 627550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 628550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FIXME set EOP only on the last packet, 629550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * SOP only on the first ... avoid IRQs 630550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 631550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if ((tx->offset + maxpacket) <= tx->buf_len) { 632550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->offset += maxpacket; 633550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len = maxpacket; 634550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options = CPPI_SOP_SET | CPPI_EOP_SET 635550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi | CPPI_OWN_SET | maxpacket; 636550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 637550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* only this one may be a partial USB Packet */ 638550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 partial_len; 639550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 640550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi partial_len = tx->buf_len - tx->offset; 641550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->offset = tx->buf_len; 642550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len = partial_len; 643550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 644550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options = CPPI_SOP_SET | CPPI_EOP_SET 645550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi | CPPI_OWN_SET | partial_len; 646550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (partial_len == 0) 647550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options |= CPPI_ZERO_SET; 648550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 649550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 6505c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n", 651550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd, bd->hw_next, bd->hw_bufp, 652550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len, bd->hw_options); 653550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 654550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* update the last BD enqueued to the list */ 655550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->tail = bd; 656550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = bd->next; 657550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 658550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 659550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* BDs live in DMA-coherent memory, but writes might be pending */ 660550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cpu_drain_writebuffer(); 661550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 662550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Write to the HeadPtr in state RAM to trigger */ 663550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx_ram->tx_head, 0, (u32)tx->freelist->dma); 664550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 665550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_tx(5, tx, "/S"); 666550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 667550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 668550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 669550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * CPPI RX Woes: 670550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * ============= 671550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Consider a 1KB bulk RX buffer in two scenarios: (a) it's fed two 300 byte 672550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * packets back-to-back, and (b) it's fed two 512 byte packets back-to-back. 673550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (Full speed transfers have similar scenarios.) 674550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 675550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * The correct behavior for Linux is that (a) fills the buffer with 300 bytes, 676550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * and the next packet goes into a buffer that's queued later; while (b) fills 677550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the buffer with 1024 bytes. How to do that with CPPI? 678550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 679550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - RX queues in "rndis" mode -- one single BD -- handle (a) correctly, but 680550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (b) loses **BADLY** because nothing (!) happens when that second packet 681550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * fills the buffer, much less when a third one arrives. (Which makes this 682550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * not a "true" RNDIS mode. In the RNDIS protocol short-packet termination 683550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * is optional, and it's fine if peripherals -- not hosts! -- pad messages 684550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * out to end-of-buffer. Standard PCI host controller DMA descriptors 685550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * implement that mode by default ... which is no accident.) 686550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 687550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - RX queues in "transparent" mode -- two BDs with 512 bytes each -- have 688550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * converse problems: (b) is handled right, but (a) loses badly. CPPI RX 689550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * ignores SOP/EOP markings and processes both of those BDs; so both packets 690550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * are loaded into the buffer (with a 212 byte gap between them), and the next 691550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * buffer queued will NOT get its 300 bytes of data. (It seems like SOP/EOP 692550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * are intended as outputs for RX queues, not inputs...) 693550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 694550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - A variant of "transparent" mode -- one BD at a time -- is the only way to 695550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * reliably make both cases work, with software handling both cases correctly 696550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * and at the significant penalty of needing an IRQ per packet. (The lack of 697550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * I/O overlap can be slightly ameliorated by enabling double buffering.) 698550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 699550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * So how to get rid of IRQ-per-packet? The transparent multi-BD case could 700550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * be used in special cases like mass storage, which sets URB_SHORT_NOT_OK 701550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (or maybe its peripheral side counterpart) to flag (a) scenarios as errors 702550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * with guaranteed driver level fault recovery and scrubbing out what's left 703550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * of that garbaged datastream. 704550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 705550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * But there seems to be no way to identify the cases where CPPI RNDIS mode 706550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * is appropriate -- which do NOT include RNDIS host drivers, but do include 707550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the CDC Ethernet driver! -- and the documentation is incomplete/wrong. 708550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * So we can't _ever_ use RX RNDIS mode ... except by using a heuristic 709550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * that applies best on the peripheral side (and which could fail rudely). 710550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 711550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Leaving only "transparent" mode; we avoid multi-bd modes in almost all 712550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * cases other than mass storage class. Otherwise we're correct but slow, 713550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * since CPPI penalizes our need for a "true RNDIS" default mode. 714550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 715550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 716550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 717550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Heuristic, intended to kick in for ethernet/rndis peripheral ONLY 718550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 719550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * IFF 720550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (a) peripheral mode ... since rndis peripherals could pad their 721550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * writes to hosts, causing i/o failure; or we'd have to cope with 722550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * a largely unknowable variety of host side protocol variants 723550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (b) and short reads are NOT errors ... since full reads would 724550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * cause those same i/o failures 725550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (c) and read length is 726550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - less than 64KB (max per cppi descriptor) 727550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - not a multiple of 4096 (g_zero default, full reads typical) 728550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - N (>1) packets long, ditto (full reads not EXPECTED) 729550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * THEN 730550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * try rx rndis mode 731550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 732550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Cost of heuristic failing: RXDMA wedges at the end of transfers that 733550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * fill out the whole buffer. Buggy host side usb network drivers could 734550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * trigger that, but "in the field" such bugs seem to be all but unknown. 735550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 736550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * So this module parameter lets the heuristic be disabled. When using 737550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * gadgetfs, the heuristic will probably need to be disabled. 738550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 73990ab5ee94171b3e28de6bb42ee30b527014e0be7Rusty Russellstatic bool cppi_rx_rndis = 1; 740550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 741550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbimodule_param(cppi_rx_rndis, bool, 0); 742550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe BalbiMODULE_PARM_DESC(cppi_rx_rndis, "enable/disable RX RNDIS heuristic"); 743550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 744550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 745550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/** 746550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * cppi_next_rx_segment - dma read for the next chunk of a buffer 747550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @musb: the controller 748550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @rx: dma channel 749550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @onepacket: true unless caller treats short reads as errors, and 750550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * performs fault recovery above usbcore. 751550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Context: controller irqlocked 752550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 753550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * See above notes about why we can't use multi-BD RX queues except in 754550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * rare cases (mass storage class), and can never use the hardware "rndis" 755550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * mode (since it's not a "true" RNDIS mode) with complete safety.. 756550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 757550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * It's ESSENTIAL that callers specify "onepacket" mode unless they kick in 758550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * code to recover from corrupted datastreams after each short transfer. 759550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 760550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void 761550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket) 762550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 763550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned maxpacket = rx->maxpacket; 764550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t addr = rx->buf_dma + rx->offset; 765550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi size_t length = rx->buf_len - rx->offset; 766550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd, *tail; 767550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned n_bds; 768550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned i; 769550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase = musb->ctrl_base; 770550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int is_rndis = 0; 771550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_rx_stateram __iomem *rx_ram = rx->state_ram; 7722daf5966d140d23d1b5ba347b53d102eeb029d2cFabio Baltieri struct cppi_descriptor *d; 773550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 774550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (onepacket) { 775550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* almost every USB driver, host or peripheral side */ 776550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = 1; 777550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 778550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* maybe apply the heuristic above */ 779550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (cppi_rx_rndis 780550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && is_peripheral_active(musb) 781550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && length > maxpacket 782550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && (length & ~0xffff) == 0 783550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && (length & 0x0fff) != 0 784550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && (length & (maxpacket - 1)) == 0) { 785550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi maxpacket = length; 786550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi is_rndis = 1; 787550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 788550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 789550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* virtually nothing except mass storage class */ 790550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (length > 0xffff) { 791550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = 0xffff / maxpacket; 792550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi length = n_bds * maxpacket; 793550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 794550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = length / maxpacket; 795550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (length % maxpacket) 796550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds++; 797550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 798550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (n_bds == 1) 799550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi onepacket = 1; 800550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 801550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = min(n_bds, (unsigned) NUM_RXCHAN_BD); 802550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 803550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 804550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* In host mode, autorequest logic can generate some IN tokens; it's 805550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * tricky since we can't leave REQPKT set in RXCSR after the transfer 806550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * finishes. So: multipacket transfers involve two or more segments. 807550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * And always at least two IRQs ... RNDIS mode is not an option. 808550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 809550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_host_active(musb)) 810550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = cppi_autoreq_update(rx, tibase, onepacket, n_bds); 811550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 812550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_rndis_update(rx, 1, musb->ctrl_base, is_rndis); 813550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 814550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi length = min(n_bds * maxpacket, length); 815550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 8165c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) " 8172fbcf3fa43af809ebf4e4ad33c2f0a17e903385cDan Carpenter "dma 0x%llx len %u %u/%u\n", 818550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->index, maxpacket, 819550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi onepacket 820550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi ? (is_rndis ? "rndis" : "onepacket") 821550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi : "multipacket", 822550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds, 823550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(tibase, 824550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) 825550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi & 0xffff, 8262fbcf3fa43af809ebf4e4ad33c2f0a17e903385cDan Carpenter (unsigned long long)addr, length, 8272fbcf3fa43af809ebf4e4ad33c2f0a17e903385cDan Carpenter rx->channel.actual_len, rx->buf_len); 828550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 829550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* only queue one segment at a time, since the hardware prevents 830550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * correct queue shutdown after unexpected short packets 831550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 832550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = cppi_bd_alloc(rx); 833550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->head = bd; 834550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 835550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Build BDs for all packets in this segment */ 836550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0, tail = NULL; bd && i < n_bds; i++, tail = bd) { 837550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 bd_len; 838550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 839550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (i) { 840550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = cppi_bd_alloc(rx); 841550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!bd) 842550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 843550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->next = bd; 844550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->hw_next = bd->dma; 845550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 846550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_next = 0; 847550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 848550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* all but the last packet will be maxpacket size */ 849550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (maxpacket < length) 850550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd_len = maxpacket; 851550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 852550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd_len = length; 853550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 854550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_bufp = addr; 855550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi addr += bd_len; 856550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->offset += bd_len; 857550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 858550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len = (0 /*offset*/ << 16) + bd_len; 859550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->buflen = bd_len; 860550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 861550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options = CPPI_OWN_SET | (i == 0 ? length : 0); 862550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi length -= bd_len; 863550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 864550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 865550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* we always expect at least one reusable BD! */ 866550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!tail) { 867550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi WARNING("rx dma%d -- no BDs? need %d\n", rx->index, n_bds); 868550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return; 869550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else if (i < n_bds) 870550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi WARNING("rx dma%d -- only %d of %d BDs\n", rx->index, i, n_bds); 871550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 872550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->next = NULL; 873550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->hw_next = 0; 874550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 875550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = rx->head; 876550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->tail = tail; 877550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 878550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* short reads and other faults should terminate this entire 879550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * dma segment. we want one "dma packet" per dma segment, not 880550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * one per USB packet, terminating the whole queue at once... 881550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * NOTE that current hardware seems to ignore SOP and EOP. 882550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 883550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options |= CPPI_SOP_SET; 884550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->hw_options |= CPPI_EOP_SET; 885550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 8862daf5966d140d23d1b5ba347b53d102eeb029d2cFabio Baltieri for (d = rx->head; d; d = d->next) 8872daf5966d140d23d1b5ba347b53d102eeb029d2cFabio Baltieri cppi_dump_rxbd("S", d); 888550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 889550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* in case the preceding transfer left some state... */ 890550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail = rx->last_processed; 891550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (tail) { 892550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->next = bd; 893550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->hw_next = bd->dma; 894550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 895550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 896550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi core_rxirq_enable(tibase, rx->index + 1); 897550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 898550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* BDs live in DMA-coherent memory, but writes might be pending */ 899550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cpu_drain_writebuffer(); 900550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 901550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT specs say to write this AFTER the BUFCNT register 902550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * below ... but that loses badly. 903550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 904550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx_ram->rx_head, 0, bd->dma); 905550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 906550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* bufferCount must be at least 3, and zeroes on completion 907550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * unless it underflows below zero, or stops at two, or keeps 908550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * growing ... grr. 909550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 910550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi i = musb_readl(tibase, 911550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) 912550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi & 0xffff; 913550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 914550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!i) 915550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, 916550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), 917550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds + 2); 918550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else if (n_bds > (i - 3)) 919550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, 920550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), 921550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds - (i - 3)); 922550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 923550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi i = musb_readl(tibase, 924550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) 925550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi & 0xffff; 926550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (i < (2 + n_bds)) { 9275c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "bufcnt%d underrun - %d (for %d)\n", 928550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->index, i, n_bds); 929550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, 930550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), 931550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds + 2); 932550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 933550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 934550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rx(4, rx, "/S"); 935550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 936550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 937550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/** 938550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * cppi_channel_program - program channel for data transfer 939550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @ch: the channel 940550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @maxpacket: max packet size 941550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @mode: For RX, 1 unless the usb protocol driver promised to treat 942550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * all short reads as errors and kick in high level fault recovery. 943550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * For TX, ignored because of RNDIS mode races/glitches. 944550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @dma_addr: dma address of buffer 945550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @len: length of buffer 946550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Context: controller irqlocked 947550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 948550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic int cppi_channel_program(struct dma_channel *ch, 949550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u16 maxpacket, u8 mode, 950550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t dma_addr, u32 len) 951550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 952550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *cppi_ch; 953550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 954550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct musb *musb; 955550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 956550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch = container_of(ch, struct cppi_channel, channel); 957550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller = cppi_ch->controller; 958550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb = controller->musb; 959550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 960550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi switch (ch->status) { 961550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_BUS_ABORT: 962550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_CORE_ABORT: 963550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* fault irq handler should have handled cleanup */ 964550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi WARNING("%cX DMA%d not cleaned up after abort!\n", 965550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->transmit ? 'T' : 'R', 966550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->index); 967550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* WARN_ON(1); */ 968550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 969550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_BUSY: 970550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi WARNING("program active channel? %cX DMA%d\n", 971550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->transmit ? 'T' : 'R', 972550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->index); 973550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* WARN_ON(1); */ 974550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 975550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_UNKNOWN: 9765c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "%cX DMA%d not allocated!\n", 977550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->transmit ? 'T' : 'R', 978550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->index); 979550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FALLTHROUGH */ 980550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_FREE: 981550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 982550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 983550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 984550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi ch->status = MUSB_DMA_STATUS_BUSY; 985550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 986550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* set transfer parameters, then queue up its first segment */ 987550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->buf_dma = dma_addr; 988550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->offset = 0; 989550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->maxpacket = maxpacket; 990550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->buf_len = len; 991191b776616838f035c2fe7eecc882b5c1f134353Swaminathan S cppi_ch->channel.actual_len = 0; 992550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 993550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* TX channel? or RX? */ 994550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (cppi_ch->transmit) 995550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_next_tx_segment(musb, cppi_ch); 996550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 997550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_next_rx_segment(musb, cppi_ch, mode); 998550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 999550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return true; 1000550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1001550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1002550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic bool cppi_rx_scan(struct cppi *cppi, unsigned ch) 1003550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 1004550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *rx = &cppi->rx[ch]; 1005550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_rx_stateram __iomem *state = rx->state_ram; 1006550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 1007550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *last = rx->last_processed; 1008550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bool completed = false; 1009550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bool acked = false; 1010550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int i; 1011550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t safe2ack; 1012550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *regs = rx->hw_ep->regs; 1013f847a79ab3c1faca3022061045cd22e4678c1b1cPer Forlin struct musb *musb = cppi->musb; 1014550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1015550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rx(6, rx, "/K"); 1016550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1017550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = last ? last->next : rx->head; 1018550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!bd) 1019550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return false; 1020550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1021550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* run through all completed BDs */ 1022550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0, safe2ack = musb_readl(&state->rx_complete, 0); 1023550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi (safe2ack || completed) && bd && i < NUM_RXCHAN_BD; 1024550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi i++, bd = bd->next) { 1025550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u16 len; 1026550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1027550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* catch latest BD writes from CPPI */ 1028550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rmb(); 1029550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!completed && (bd->hw_options & CPPI_OWN_SET)) 1030550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 1031550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 10325c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "C/RXBD %llx: nxt %08x buf %08x " 1033550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "off.len %08x opt.len %08x (%d)\n", 10342fbcf3fa43af809ebf4e4ad33c2f0a17e903385cDan Carpenter (unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp, 1035550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len, bd->hw_options, 1036550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->channel.actual_len); 1037550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1038550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* actual packet received length */ 1039550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if ((bd->hw_options & CPPI_SOP_SET) && !completed) 1040550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi len = bd->hw_off_len & CPPI_RECV_PKTLEN_MASK; 1041550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 1042550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi len = 0; 1043550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1044550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->hw_options & CPPI_EOQ_MASK) 1045550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi completed = true; 1046550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1047550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!completed && len < bd->buflen) { 1048550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* NOTE: when we get a short packet, RXCSR_H_REQPKT 1049550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * must have been cleared, and no more DMA packets may 1050550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * active be in the queue... TI docs didn't say, but 1051550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * CPPI ignores those BDs even though OWN is still set. 1052550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1053550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi completed = true; 10545c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "rx short %d/%d (%d)\n", 1055550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi len, bd->buflen, 1056550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->channel.actual_len); 1057550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1058550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1059550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* If we got here, we expect to ack at least one BD; meanwhile 1060550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * CPPI may completing other BDs while we scan this list... 1061550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1062550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * RACE: we can notice OWN cleared before CPPI raises the 1063550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * matching irq by writing that BD as the completion pointer. 1064550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * In such cases, stop scanning and wait for the irq, avoiding 1065550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * lost acks and states where BD ownership is unclear. 1066550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1067550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->dma == safe2ack) { 1068550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&state->rx_complete, 0, safe2ack); 1069550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi safe2ack = musb_readl(&state->rx_complete, 0); 1070550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi acked = true; 1071550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->dma == safe2ack) 1072550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi safe2ack = 0; 1073550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1074550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1075550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->channel.actual_len += len; 1076550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1077550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_bd_free(rx, last); 1078550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi last = bd; 1079550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1080550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* stop scanning on end-of-segment */ 1081550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->hw_next == 0) 1082550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi completed = true; 1083550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1084550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->last_processed = last; 1085550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1086550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* dma abort, lost ack, or ... */ 1087550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!acked && last) { 1088550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int csr; 1089550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1090550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (safe2ack == 0 || safe2ack == rx->last_processed->dma) 1091550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&state->rx_complete, 0, safe2ack); 1092550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (safe2ack == 0) { 1093550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_bd_free(rx, last); 1094550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->last_processed = NULL; 1095550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1096550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* if we land here on the host side, H_REQPKT will 1097550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * be clear and we need to restart the queue... 1098550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1099550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi WARN_ON(rx->head); 1100550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1101550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_ep_select(cppi->mregs, rx->index + 1); 1102550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr = musb_readw(regs, MUSB_RXCSR); 1103550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (csr & MUSB_RXCSR_DMAENAB) { 11045c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n", 1105550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->index, 1106550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->head, rx->tail, 1107550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->last_processed 11082fbcf3fa43af809ebf4e4ad33c2f0a17e903385cDan Carpenter ? (unsigned long long) 11092fbcf3fa43af809ebf4e4ad33c2f0a17e903385cDan Carpenter rx->last_processed->dma 1110550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi : 0, 1111550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi completed ? ", completed" : "", 1112550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr); 1113550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rxq(4, "/what?", rx); 1114550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1115550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1116550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!completed) { 1117550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int csr; 1118550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1119550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->head = bd; 1120550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1121550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT seems like "autoreq all but EOP" doesn't... 1122550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * setting it here "should" be racey, but seems to work 1123550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1124550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR); 1125550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_host_active(cppi->musb) 1126550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && bd 1127550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && !(csr & MUSB_RXCSR_H_REQPKT)) { 1128550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr |= MUSB_RXCSR_H_REQPKT; 1129550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writew(regs, MUSB_RXCSR, 1130550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi MUSB_RXCSR_H_WZC_BITS | csr); 1131550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR); 1132550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1133550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 1134550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->head = NULL; 1135550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->tail = NULL; 1136550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1137550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1138550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rx(6, rx, completed ? "/completed" : "/cleaned"); 1139550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return completed; 1140550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1141550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 114291e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyovirqreturn_t cppi_interrupt(int irq, void *dev_id) 1143550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 114491e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov struct musb *musb = dev_id; 1145550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *cppi; 114691e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov void __iomem *tibase; 1147550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct musb_hw_ep *hw_ep = NULL; 114891e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov u32 rx, tx; 114991e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov int i, index; 11502f8d5cd6bcf814411ec356bcdbc666d07bbc6026Jon Povey unsigned long uninitialized_var(flags); 1151550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1152550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi = container_of(musb->dma_controller, struct cppi, controller); 115393aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S if (cppi->irq) 115493aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S spin_lock_irqsave(&musb->lock, flags); 1155550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1156550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = musb->ctrl_base; 1157550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 115891e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG); 115991e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG); 116091e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 1161ec63bf6c06b01ceeb6048a2b9fa9e73060259307Dan Carpenter if (!tx && !rx) { 1162ec63bf6c06b01ceeb6048a2b9fa9e73060259307Dan Carpenter if (cppi->irq) 1163ec63bf6c06b01ceeb6048a2b9fa9e73060259307Dan Carpenter spin_unlock_irqrestore(&musb->lock, flags); 116491e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov return IRQ_NONE; 1165ec63bf6c06b01ceeb6048a2b9fa9e73060259307Dan Carpenter } 116691e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 11675c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "CPPI IRQ Tx%x Rx%x\n", tx, rx); 116891e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 1169550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* process TX channels */ 1170550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (index = 0; tx; tx = tx >> 1, index++) { 1171550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *tx_ch; 1172550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_tx_stateram __iomem *tx_ram; 1173550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bool completed = false; 1174550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 1175550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1176550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!(tx & 1)) 1177550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi continue; 1178550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1179550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch = cppi->tx + index; 1180550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ram = tx_ch->state_ram; 1181550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1182550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FIXME need a cppi_tx_scan() routine, which 1183550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * can also be called from abort code 1184550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1185550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1186550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_tx(5, tx_ch, "/E"); 1187550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1188550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = tx_ch->head; 1189550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1190565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S /* 1191565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S * If Head is null then this could mean that a abort interrupt 1192565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S * that needs to be acknowledged. 1193565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S */ 1194550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (NULL == bd) { 11955c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "null BD\n"); 11962e10f5e70f670d981f789075e3ebc394f5bb51e3Dan Carpenter musb_writel(&tx_ram->tx_complete, 0, 0); 1197550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi continue; 1198550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1199550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1200550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* run through all completed BDs */ 1201550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; !completed && bd && i < NUM_TXCHAN_BD; 1202550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi i++, bd = bd->next) { 1203550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u16 len; 1204550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1205550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* catch latest BD writes from CPPI */ 1206550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rmb(); 1207550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->hw_options & CPPI_OWN_SET) 1208550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 1209550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 12105c8a86e10a7c164f44537fabdc169fd8b4e7a440Felipe Balbi dev_dbg(musb->controller, "C/TXBD %p n %x b %x off %x opt %x\n", 1211550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd, bd->hw_next, bd->hw_bufp, 1212550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len, bd->hw_options); 1213550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1214550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi len = bd->hw_off_len & CPPI_BUFFER_LEN_MASK; 1215550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->channel.actual_len += len; 1216550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1217550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->last_processed = bd; 1218550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1219550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* write completion register to acknowledge 1220550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * processing of completed BDs, and possibly 1221550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * release the IRQ; EOQ might not be set ... 1222550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1223550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT use the same ack strategy as rx 1224550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1225550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT have observed bit 18 set; huh?? 1226550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1227550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* if ((bd->hw_options & CPPI_EOQ_MASK)) */ 1228550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx_ram->tx_complete, 0, bd->dma); 1229550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1230550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* stop scanning on end-of-segment */ 1231550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->hw_next == 0) 1232550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi completed = true; 1233550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1234550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1235550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* on end of segment, maybe go to next one */ 1236550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (completed) { 1237550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* cppi_dump_tx(4, tx_ch, "/complete"); */ 1238550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1239550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* transfer more, or report completion */ 1240550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (tx_ch->offset >= tx_ch->buf_len) { 1241550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->head = NULL; 1242550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->tail = NULL; 1243550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->channel.status = MUSB_DMA_STATUS_FREE; 1244550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1245550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi hw_ep = tx_ch->hw_ep; 1246550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1247c7bbc056a92476b3b3d70a8df7cc746ac5d56de7Sergei Shtylyov musb_dma_completion(musb, index + 1, 1); 1248550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1249550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 1250550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Bigger transfer than we could fit in 1251550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * that first batch of descriptors... 1252550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1253550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_next_tx_segment(musb, tx_ch); 1254550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1255550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else 1256550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->head = bd; 1257550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1258550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1259550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Start processing the RX block */ 1260550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (index = 0; rx; rx = rx >> 1, index++) { 1261550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1262550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (rx & 1) { 1263550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *rx_ch; 1264550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1265550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx_ch = cppi->rx + index; 1266550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1267550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* let incomplete dma segments finish */ 1268550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!cppi_rx_scan(cppi, index)) 1269550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi continue; 1270550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1271550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* start another dma segment if needed */ 1272550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (rx_ch->channel.actual_len != rx_ch->buf_len 1273550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && rx_ch->channel.actual_len 1274550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi == rx_ch->offset) { 1275550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_next_rx_segment(musb, rx_ch, 1); 1276550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi continue; 1277550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1278550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1279550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* all segments completed! */ 1280550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx_ch->channel.status = MUSB_DMA_STATUS_FREE; 1281550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1282550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi hw_ep = rx_ch->hw_ep; 1283550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1284550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi core_rxirq_disable(tibase, index + 1); 1285550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_dma_completion(musb, index + 1, 0); 1286550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1287550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1288550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1289550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* write to CPPI EOI register to re-enable interrupts */ 1290550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0); 129191e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 129293aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S if (cppi->irq) 129393aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S spin_unlock_irqrestore(&musb->lock, flags); 129493aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S 129591e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov return IRQ_HANDLED; 1296550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 12978b416b0b25d5d8ddb3a91c1d20e1373582c50405Sergei ShtylyovEXPORT_SYMBOL_GPL(cppi_interrupt); 1298550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1299550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Instantiate a software object representing a DMA controller. */ 130041ac7b3ab7fe1d6175839947a877fdf95cbd2211Bill Pembertonstruct dma_controller *dma_controller_create(struct musb *musb, void __iomem *mregs) 1301550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 1302550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 130391e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov struct device *dev = musb->controller; 130491e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov struct platform_device *pdev = to_platform_device(dev); 1305fcf173e4511193b1efeccb0f22a8c641b464353bHema Kalliguddi int irq = platform_get_irq_byname(pdev, "dma"); 1306550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1307550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller = kzalloc(sizeof *controller, GFP_KERNEL); 1308550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!controller) 1309550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return NULL; 1310550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1311550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->mregs = mregs; 1312550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->tibase = mregs - DAVINCI_BASE_OFFSET; 1313550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1314550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->musb = musb; 1315550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->controller.channel_alloc = cppi_channel_allocate; 1316550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->controller.channel_release = cppi_channel_release; 1317550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->controller.channel_program = cppi_channel_program; 1318550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->controller.channel_abort = cppi_channel_abort; 1319550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1320550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* NOTE: allocating from on-chip SRAM would give the least 1321550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * contention for memory access, if that ever matters here. 1322550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1323550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1324550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* setup BufferPool */ 1325550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->pool = dma_pool_create("cppi", 1326550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->musb->controller, 1327550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi sizeof(struct cppi_descriptor), 1328550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi CPPI_DESCRIPTOR_ALIGN, 0); 1329550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!controller->pool) { 1330550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi kfree(controller); 1331550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return NULL; 1332550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1333550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 133491e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov if (irq > 0) { 133591e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) { 133691e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov dev_err(dev, "request_irq %d failed!\n", irq); 133791e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov dma_controller_destroy(&controller->controller); 133891e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov return NULL; 133991e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov } 134091e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov controller->irq = irq; 134191e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov } 134291e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 134366c01883ef19bf4537b16931567b7d35c65356adSebastian Andrzej Siewior cppi_controller_start(controller); 1344550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return &controller->controller; 1345550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1346550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1347550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 1348550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Destroy a previously-instantiated DMA controller. 1349550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1350550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbivoid dma_controller_destroy(struct dma_controller *c) 1351550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 1352550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *cppi; 1353550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1354550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi = container_of(c, struct cppi, controller); 1355550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 135666c01883ef19bf4537b16931567b7d35c65356adSebastian Andrzej Siewior cppi_controller_stop(cppi); 135766c01883ef19bf4537b16931567b7d35c65356adSebastian Andrzej Siewior 135891e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov if (cppi->irq) 135991e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov free_irq(cppi->irq, cppi->musb); 136091e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 1361550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* assert: caller stopped the controller first */ 1362550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_pool_destroy(cppi->pool); 1363550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1364550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi kfree(cppi); 1365550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1366550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1367550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 1368550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Context: controller irqlocked, endpoint selected 1369550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1370550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic int cppi_channel_abort(struct dma_channel *channel) 1371550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 1372550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *cppi_ch; 1373550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 1374550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *mbase; 1375550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; 1376550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *regs; 1377550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 value; 1378550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *queue; 1379550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1380550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch = container_of(channel, struct cppi_channel, channel); 1381550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1382550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller = cppi_ch->controller; 1383550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1384550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi switch (channel->status) { 1385550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_BUS_ABORT: 1386550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_CORE_ABORT: 1387550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* from RX or TX fault irq handler */ 1388550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_BUSY: 1389550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* the hardware needs shutting down */ 1390550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi regs = cppi_ch->hw_ep->regs; 1391550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 1392550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_UNKNOWN: 1393550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_FREE: 1394550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return 0; 1395550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi default: 1396550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return -EINVAL; 1397550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1398550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1399550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!cppi_ch->transmit && cppi_ch->head) 1400550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rxq(3, "/abort", cppi_ch); 1401550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1402550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi mbase = controller->mregs; 1403550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = controller->tibase; 1404550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1405550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi queue = cppi_ch->head; 1406550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->head = NULL; 1407550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->tail = NULL; 1408550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1409550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT should rely on caller having done this, 1410550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * and caller should rely on us not changing it. 1411550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * peripheral code is safe ... check host too. 1412550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1413550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_ep_select(mbase, cppi_ch->index + 1); 1414550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1415550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (cppi_ch->transmit) { 1416550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_tx_stateram __iomem *tx_ram; 1417550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT put timeouts on these controller handshakes */ 1418550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1419550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_tx(6, cppi_ch, " (teardown)"); 1420550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1421550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* teardown DMA engine then usb core */ 1422550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi do { 1423550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value = musb_readl(tibase, DAVINCI_TXCPPI_TEAR_REG); 1424550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } while (!(value & CPPI_TEAR_READY)); 1425550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_TXCPPI_TEAR_REG, cppi_ch->index); 1426550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1427550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ram = cppi_ch->state_ram; 1428550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi do { 1429550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value = musb_readl(&tx_ram->tx_complete, 0); 1430550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } while (0xFFFFFFFC != value); 1431550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1432550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FIXME clean up the transfer state ... here? 1433550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the completion routine should get called with 1434550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * an appropriate status code. 1435550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1436550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1437550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value = musb_readw(regs, MUSB_TXCSR); 1438550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value &= ~MUSB_TXCSR_DMAENAB; 1439550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value |= MUSB_TXCSR_FLUSHFIFO; 1440550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writew(regs, MUSB_TXCSR, value); 1441550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writew(regs, MUSB_TXCSR, value); 1442550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1443565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S /* 1444550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1. Write to completion Ptr value 0x1(bit 0 set) 1445550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (write back mode) 1446565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S * 2. Wait for abort interrupt and then put the channel in 1447565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S * compare mode by writing 1 to the tx_complete register. 1448550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1449550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_reset_tx(tx_ram, 1); 1450aca7f353219abfb7b8a1530fbba1b1acf0e30da4Dan Carpenter cppi_ch->head = NULL; 1451565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S musb_writel(&tx_ram->tx_complete, 0, 1); 1452550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_tx(5, cppi_ch, " (done teardown)"); 1453550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1454550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT tx side _should_ clean up the same way 1455550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * as the RX side ... this does no cleanup at all! 1456550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1457550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1458550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else /* RX */ { 1459550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u16 csr; 1460550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1461550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* NOTE: docs don't guarantee any of this works ... we 1462550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * expect that if the usb core stops telling the cppi core 1463550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * to pull more data from it, then it'll be safe to flush 1464550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * current RX DMA state iff any pending fifo transfer is done. 1465550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1466550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1467550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi core_rxirq_disable(tibase, cppi_ch->index + 1); 1468550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1469550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* for host, ensure ReqPkt is never set again */ 1470550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_host_active(cppi_ch->controller->musb)) { 1471550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value = musb_readl(tibase, DAVINCI_AUTOREQ_REG); 1472550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value &= ~((0x3) << (cppi_ch->index * 2)); 1473550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_AUTOREQ_REG, value); 1474550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1475550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1476550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr = musb_readw(regs, MUSB_RXCSR); 1477550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1478550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* for host, clear (just) ReqPkt at end of current packet(s) */ 1479550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_host_active(cppi_ch->controller->musb)) { 1480550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr |= MUSB_RXCSR_H_WZC_BITS; 1481550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr &= ~MUSB_RXCSR_H_REQPKT; 1482550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else 1483550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr |= MUSB_RXCSR_P_WZC_BITS; 1484550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1485550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* clear dma enable */ 1486550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr &= ~(MUSB_RXCSR_DMAENAB); 1487550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writew(regs, MUSB_RXCSR, csr); 1488550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr = musb_readw(regs, MUSB_RXCSR); 1489550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1490550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Quiesce: wait for current dma to finish (if not cleanup). 1491550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * We can't use bit zero of stateram->rx_sop, since that 1492550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * refers to an entire "DMA packet" not just emptying the 1493550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * current fifo. Most segments need multiple usb packets. 1494550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1495550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (channel->status == MUSB_DMA_STATUS_BUSY) 1496550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi udelay(50); 1497550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1498550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* scan the current list, reporting any data that was 1499550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * transferred and acking any IRQ 1500550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1501550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_rx_scan(controller, cppi_ch->index); 1502550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1503550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* clobber the existing state once it's idle 1504550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1505550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * NOTE: arguably, we should also wait for all the other 1506550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * RX channels to quiesce (how??) and then temporarily 1507550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * disable RXCPPI_CTRL_REG ... but it seems that we can 1508550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * rely on the controller restarting from state ram, with 1509550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * only RXCPPI_BUFCNT state being bogus. BUFCNT will 1510550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * correct itself after the next DMA transfer though. 1511550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1512550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT does using rndis mode change that? 1513550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1514550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_reset_rx(cppi_ch->state_ram); 1515550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1516550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* next DMA request _should_ load cppi head ptr */ 1517550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1518550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* ... we don't "free" that list, only mutate it in place. */ 1519550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rx(5, cppi_ch, " (done abort)"); 1520550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1521550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* clean up previously pending bds */ 1522550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_bd_free(cppi_ch, cppi_ch->last_processed); 1523550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->last_processed = NULL; 1524550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1525550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi while (queue) { 1526550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *tmp = queue->next; 1527550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1528550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_bd_free(cppi_ch, queue); 1529550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi queue = tmp; 1530550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1531550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1532550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1533550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi channel->status = MUSB_DMA_STATUS_FREE; 1534550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->buf_dma = 0; 1535550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->offset = 0; 1536550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->buf_len = 0; 1537550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->maxpacket = 0; 1538550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return 0; 1539550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1540550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1541550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* TBD Queries: 1542550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1543550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Power Management ... probably turn off cppi during suspend, restart; 1544550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * check state ram? Clocking is presumably shared with usb core. 1545550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1546