cppi_dma.c revision 565969237ab6e73ce7192684d00d5b890ee308fa
1550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 2550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Copyright (C) 2005-2006 by Texas Instruments 3550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 4550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * This file implements a DMA interface using TI's CPPI DMA. 5550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * For now it's DaVinci-only, but CPPI isn't specific to DaVinci or USB. 6550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * The TUSB6020, using VLYNQ, has CPPI that looks much like DaVinci. 7550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 8550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 991e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov#include <linux/platform_device.h> 10550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include <linux/usb.h> 11550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 12550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include "musb_core.h" 13704a14854aaf9758a1248ea36a7d1b8cc42a4b3eHugo Villeneuve#include "musb_debug.h" 14550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include "cppi_dma.h" 15550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 16550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 17550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* CPPI DMA status 7-mar-2006: 18550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 19550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - See musb_{host,gadget}.c for more info 20550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 21550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - Correct RX DMA generally forces the engine into irq-per-packet mode, 22550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * which can easily saturate the CPU under non-mass-storage loads. 23550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 24550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * NOTES 24-aug-2006 (2.6.18-rc4): 25550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 26550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - peripheral RXDMA wedged in a test with packets of length 512/512/1. 27550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * evidently after the 1 byte packet was received and acked, the queue 28550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * of BDs got garbaged so it wouldn't empty the fifo. (rxcsr 0x2003, 29550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * and RX DMA0: 4 left, 80000000 8feff880, 8feff860 8feff860; 8f321401 30550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 004001ff 00000001 .. 8feff860) Host was just getting NAKed on tx 31550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * of its next (512 byte) packet. IRQ issues? 32550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 33550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT: the "transfer DMA" glue between CPPI and USB fifos will 34550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * evidently also directly update the RX and TX CSRs ... so audit all 35550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * host and peripheral side DMA code to avoid CSR access after DMA has 36550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * been started. 37550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 38550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 39550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* REVISIT now we can avoid preallocating these descriptors; or 40550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * more simply, switch to a global freelist not per-channel ones. 41550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Note: at full speed, 64 descriptors == 4K bulk data. 42550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 43550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define NUM_TXCHAN_BD 64 44550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define NUM_RXCHAN_BD 64 45550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 46550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline void cpu_drain_writebuffer(void) 47550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 48550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi wmb(); 49550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#ifdef CONFIG_CPU_ARM926T 50550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT this "should not be needed", 51550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * but lack of it sure seemed to hurt ... 52550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 53550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi asm("mcr p15, 0, r0, c7, c10, 4 @ drain write buffer\n"); 54550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#endif 55550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 56550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 57550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline struct cppi_descriptor *cppi_bd_alloc(struct cppi_channel *c) 58550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 59550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd = c->freelist; 60550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 61550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd) 62550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->freelist = bd->next; 63550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return bd; 64550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 65550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 66550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline void 67550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_bd_free(struct cppi_channel *c, struct cppi_descriptor *bd) 68550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 69550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!bd) 70550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return; 71550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->next = c->freelist; 72550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->freelist = bd; 73550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 74550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 75550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 76550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Start DMA controller 77550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 78550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Initialize the DMA controller as necessary. 79550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 80550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 81550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* zero out entire rx state RAM entry for the channel */ 82550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_reset_rx(struct cppi_rx_stateram __iomem *rx) 83550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 84550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_skipbytes, 0, 0); 85550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_head, 0, 0); 86550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_sop, 0, 0); 87550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_current, 0, 0); 88550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_buf_current, 0, 0); 89550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_len_len, 0, 0); 90550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx->rx_cnt_cnt, 0, 0); 91550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 92550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 93550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* zero out entire tx state RAM entry for the channel */ 94550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_reset_tx(struct cppi_tx_stateram __iomem *tx, u32 ptr) 95550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 96550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_head, 0, 0); 97550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_buf, 0, 0); 98550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_current, 0, 0); 99550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_buf_current, 0, 0); 100550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_info, 0, 0); 101550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_rem_len, 0, 0); 102550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* musb_writel(&tx->tx_dummy, 0, 0); */ 103550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx->tx_complete, 0, ptr); 104550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 105550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 106550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void __init cppi_pool_init(struct cppi *cppi, struct cppi_channel *c) 107550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 108550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int j; 109550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 110550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* initialize channel fields */ 111550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->head = NULL; 112550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->tail = NULL; 113550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->last_processed = NULL; 114550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->channel.status = MUSB_DMA_STATUS_UNKNOWN; 115550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->controller = cppi; 116550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->is_rndis = 0; 117550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->freelist = NULL; 118550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 119550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* build the BD Free list for the channel */ 120550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (j = 0; j < NUM_TXCHAN_BD + 1; j++) { 121550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 122550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t dma; 123550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 124550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = dma_pool_alloc(cppi->pool, GFP_KERNEL, &dma); 125550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->dma = dma; 126550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_bd_free(c, bd); 127550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 128550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 129550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 130550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic int cppi_channel_abort(struct dma_channel *); 131550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 132550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_pool_free(struct cppi_channel *c) 133550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 134550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *cppi = c->controller; 135550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 136550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 137550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi (void) cppi_channel_abort(&c->channel); 138550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->channel.status = MUSB_DMA_STATUS_UNKNOWN; 139550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->controller = NULL; 140550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 141550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* free all its bds */ 142550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = c->last_processed; 143550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi do { 144550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd) 145550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_pool_free(cppi->pool, bd, bd->dma); 146550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = cppi_bd_alloc(c); 147550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } while (bd); 148550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->last_processed = NULL; 149550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 150550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 151550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic int __init cppi_controller_start(struct dma_controller *c) 152550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 153550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 154550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; 155550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int i; 156550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 157550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller = container_of(c, struct cppi, controller); 158550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 159550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* do whatever is necessary to start controller */ 160550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { 161550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->tx[i].transmit = true; 162550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->tx[i].index = i; 163550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 164550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->rx); i++) { 165550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->rx[i].transmit = false; 166550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->rx[i].index = i; 167550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 168550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 169550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* setup BD list on a per channel basis */ 170550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->tx); i++) 171550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_pool_init(controller, controller->tx + i); 172550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->rx); i++) 173550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_pool_init(controller, controller->rx + i); 174550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 175550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = controller->tibase; 176550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi INIT_LIST_HEAD(&controller->tx_complete); 177550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 178550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* initialise tx/rx channel head pointers to zero */ 179550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { 180550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *tx_ch = controller->tx + i; 181550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_tx_stateram __iomem *tx; 182550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 183550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi INIT_LIST_HEAD(&tx_ch->tx_complete); 184550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 185550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx = tibase + DAVINCI_TXCPPI_STATERAM_OFFSET(i); 186550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->state_ram = tx; 187550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_reset_tx(tx, 0); 188550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 189550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->rx); i++) { 190550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *rx_ch = controller->rx + i; 191550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_rx_stateram __iomem *rx; 192550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 193550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi INIT_LIST_HEAD(&rx_ch->tx_complete); 194550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 195550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx = tibase + DAVINCI_RXCPPI_STATERAM_OFFSET(i); 196550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx_ch->state_ram = rx; 197550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_reset_rx(rx); 198550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 199550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 200550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* enable individual cppi channels */ 201550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG, 202550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_DMA_ALL_CHANNELS_ENABLE); 203550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RXCPPI_INTENAB_REG, 204550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_DMA_ALL_CHANNELS_ENABLE); 205550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 206550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* enable tx/rx CPPI control */ 207550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE); 208550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE); 209550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 210550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* disable RNDIS mode, also host rx RNDIS autorequest */ 211550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RNDIS_REG, 0); 212550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_AUTOREQ_REG, 0); 213550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 214550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return 0; 215550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 216550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 217550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 218550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Stop DMA controller 219550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 220550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * De-Init the DMA controller as necessary. 221550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 222550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 223550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic int cppi_controller_stop(struct dma_controller *c) 224550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 225550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 226550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; 227550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int i; 228550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 229550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller = container_of(c, struct cppi, controller); 230550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 231550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = controller->tibase; 232550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* DISABLE INDIVIDUAL CHANNEL Interrupts */ 233550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG, 234550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_DMA_ALL_CHANNELS_ENABLE); 235550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG, 236550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_DMA_ALL_CHANNELS_ENABLE); 237550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 238550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(1, "Tearing down RX and TX Channels\n"); 239550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { 240550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FIXME restructure of txdma to use bds like rxdma */ 241550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->tx[i].last_processed = NULL; 242550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_pool_free(controller->tx + i); 243550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 244550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < ARRAY_SIZE(controller->rx); i++) 245550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_pool_free(controller->rx + i); 246550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 247550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* in Tx Case proper teardown is supported. We resort to disabling 248550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Tx/Rx CPPI after cleanup of Tx channels. Before TX teardown is 249550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * complete TX CPPI cannot be disabled. 250550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 251550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /*disable tx/rx cppi */ 252550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE); 253550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE); 254550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 255550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return 0; 256550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 257550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 258550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* While dma channel is allocated, we only want the core irqs active 259550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * for fault reports, otherwise we'd get irqs that we don't care about. 260550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Except for TX irqs, where dma done != fifo empty and reusable ... 261550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 262550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * NOTE: docs don't say either way, but irq masking **enables** irqs. 263550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 264550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT same issue applies to pure PIO usage too, and non-cppi dma... 265550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 266550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline void core_rxirq_disable(void __iomem *tibase, unsigned epnum) 267550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 268550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_USB_INT_MASK_CLR_REG, 1 << (epnum + 8)); 269550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 270550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 271550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline void core_rxirq_enable(void __iomem *tibase, unsigned epnum) 272550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 273550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_USB_INT_MASK_SET_REG, 1 << (epnum + 8)); 274550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 275550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 276550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 277550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 278550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Allocate a CPPI Channel for DMA. With CPPI, channels are bound to 279550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * each transfer direction of a non-control endpoint, so allocating 280550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (and deallocating) is mostly a way to notice bad housekeeping on 281550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the software side. We assume the irqs are always active. 282550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 283550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic struct dma_channel * 284550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_channel_allocate(struct dma_controller *c, 285550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct musb_hw_ep *ep, u8 transmit) 286550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 287550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 288550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u8 index; 289550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *cppi_ch; 290550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; 291550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 292550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller = container_of(c, struct cppi, controller); 293550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = controller->tibase; 294550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 295550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* ep0 doesn't use DMA; remember cppi indices are 0..N-1 */ 296550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi index = ep->epnum - 1; 297550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 298550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* return the corresponding CPPI Channel Handle, and 299550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * probably disable the non-CPPI irq until we need it. 300550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 301550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (transmit) { 302550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (index >= ARRAY_SIZE(controller->tx)) { 303550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(1, "no %cX%d CPPI channel\n", 'T', index); 304550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return NULL; 305550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 306550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch = controller->tx + index; 307550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 308550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (index >= ARRAY_SIZE(controller->rx)) { 309550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(1, "no %cX%d CPPI channel\n", 'R', index); 310550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return NULL; 311550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 312550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch = controller->rx + index; 313550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi core_rxirq_disable(tibase, ep->epnum); 314550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 315550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 316550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT make this an error later once the same driver code works 317550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * with the other DMA engine too 318550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 319550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (cppi_ch->hw_ep) 320550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(1, "re-allocating DMA%d %cX channel %p\n", 321550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi index, transmit ? 'T' : 'R', cppi_ch); 322550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->hw_ep = ep; 323550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->channel.status = MUSB_DMA_STATUS_FREE; 324550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 325550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(4, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R'); 326550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return &cppi_ch->channel; 327550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 328550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 329550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Release a CPPI Channel. */ 330550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_channel_release(struct dma_channel *channel) 331550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 332550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *c; 333550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; 334550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 335550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT: for paranoia, check state and abort if needed... */ 336550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 337550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c = container_of(channel, struct cppi_channel, channel); 338550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = c->controller->tibase; 339550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!c->hw_ep) 340550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(1, "releasing idle DMA channel %p\n", c); 341550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else if (!c->transmit) 342550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi core_rxirq_enable(tibase, c->index + 1); 343550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 344550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* for now, leave its cppi IRQ enabled (we won't trigger it) */ 345550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->hw_ep = NULL; 346550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi channel->status = MUSB_DMA_STATUS_UNKNOWN; 347550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 348550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 349550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Context: controller irqlocked */ 350550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void 351550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_dump_rx(int level, struct cppi_channel *c, const char *tag) 352550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 353550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *base = c->controller->mregs; 354550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_rx_stateram __iomem *rx = c->state_ram; 355550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 356550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_ep_select(base, c->index + 1); 357550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 358550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(level, "RX DMA%d%s: %d left, csr %04x, " 359550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "%08x H%08x S%08x C%08x, " 360550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "B%08x L%08x %08x .. %08x" 361550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "\n", 362550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->index, tag, 363550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(c->controller->tibase, 364550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + 4 * c->index), 365550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readw(c->hw_ep->regs, MUSB_RXCSR), 366550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 367550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_skipbytes, 0), 368550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_head, 0), 369550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_sop, 0), 370550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_current, 0), 371550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 372550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_buf_current, 0), 373550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_len_len, 0), 374550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_cnt_cnt, 0), 375550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&rx->rx_complete, 0) 376550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi ); 377550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 378550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 379550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Context: controller irqlocked */ 380550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void 381550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_dump_tx(int level, struct cppi_channel *c, const char *tag) 382550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 383550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *base = c->controller->mregs; 384550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_tx_stateram __iomem *tx = c->state_ram; 385550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 386550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_ep_select(base, c->index + 1); 387550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 388550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(level, "TX DMA%d%s: csr %04x, " 389550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "H%08x S%08x C%08x %08x, " 390550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "F%08x L%08x .. %08x" 391550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "\n", 392550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->index, tag, 393550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readw(c->hw_ep->regs, MUSB_TXCSR), 394550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 395550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_head, 0), 396550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_buf, 0), 397550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_current, 0), 398550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_buf_current, 0), 399550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 400550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_info, 0), 401550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_rem_len, 0), 402550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* dummy/unused word 6 */ 403550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(&tx->tx_complete, 0) 404550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi ); 405550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 406550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 407550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Context: controller irqlocked */ 408550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline void 409550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_rndis_update(struct cppi_channel *c, int is_rx, 410550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase, int is_rndis) 411550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 412550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* we may need to change the rndis flag for this cppi channel */ 413550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (c->is_rndis != is_rndis) { 414550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 value = musb_readl(tibase, DAVINCI_RNDIS_REG); 415550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 temp = 1 << (c->index); 416550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 417550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_rx) 418550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi temp <<= 16; 419550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_rndis) 420550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value |= temp; 421550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 422550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value &= ~temp; 423550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_RNDIS_REG, value); 424550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi c->is_rndis = is_rndis; 425550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 426550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 427550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 428704a14854aaf9758a1248ea36a7d1b8cc42a4b3eHugo Villeneuve#ifdef CONFIG_USB_MUSB_DEBUG 429550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_dump_rxbd(const char *tag, struct cppi_descriptor *bd) 430550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 431550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi pr_debug("RXBD/%s %08x: " 432550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "nxt %08x buf %08x off.blen %08x opt.plen %08x\n", 433550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tag, bd->dma, 434550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_next, bd->hw_bufp, bd->hw_off_len, 435550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options); 436550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 437704a14854aaf9758a1248ea36a7d1b8cc42a4b3eHugo Villeneuve#endif 438550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 439550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void cppi_dump_rxq(int level, const char *tag, struct cppi_channel *rx) 440550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 441704a14854aaf9758a1248ea36a7d1b8cc42a4b3eHugo Villeneuve#ifdef CONFIG_USB_MUSB_DEBUG 442550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 443550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 444550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!_dbg_level(level)) 445550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return; 446550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rx(level, rx, tag); 447550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (rx->last_processed) 448550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rxbd("last", rx->last_processed); 449550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (bd = rx->head; bd; bd = bd->next) 450550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rxbd("active", bd); 451550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#endif 452550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 453550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 454550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 455550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* NOTE: DaVinci autoreq is ignored except for host side "RNDIS" mode RX; 456550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * so we won't ever use it (see "CPPI RX Woes" below). 457550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 458550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic inline int cppi_autoreq_update(struct cppi_channel *rx, 459550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase, int onepacket, unsigned n_bds) 460550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 461550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 val; 462550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 463550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#ifdef RNDIS_RX_IS_USABLE 464550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 tmp; 465550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* assert(is_host_active(musb)) */ 466550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 467550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* start from "AutoReq never" */ 468550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG); 469550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val = tmp & ~((0x3) << (rx->index * 2)); 470550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 471550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* HCD arranged reqpkt for packet #1. we arrange int 472550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * for all but the last one, maybe in two segments. 473550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 474550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!onepacket) { 475550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#if 0 476550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* use two segments, autoreq "all" then the last "never" */ 477550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val |= ((0x3) << (rx->index * 2)); 478550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds--; 479550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#else 480550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* one segment, autoreq "all-but-last" */ 481550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val |= ((0x1) << (rx->index * 2)); 482550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#endif 483550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 484550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 485550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (val != tmp) { 486550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int n = 100; 487550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 488550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* make sure that autoreq is updated before continuing */ 489550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_AUTOREQ_REG, val); 490550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi do { 491550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG); 492550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (tmp == val) 493550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 494550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cpu_relax(); 495550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } while (n-- > 0); 496550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 497550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#endif 498550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 499550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REQPKT is turned off after each segment */ 500550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (n_bds && rx->channel.actual_len) { 501550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *regs = rx->hw_ep->regs; 502550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 503550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val = musb_readw(regs, MUSB_RXCSR); 504550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!(val & MUSB_RXCSR_H_REQPKT)) { 505550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS; 506550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writew(regs, MUSB_RXCSR, val); 507550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* flush writebufer */ 508550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi val = musb_readw(regs, MUSB_RXCSR); 509550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 510550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 511550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return n_bds; 512550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 513550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 514550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 515550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Buffer enqueuing Logic: 516550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 517550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - RX builds new queues each time, to help handle routine "early 518550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * termination" cases (faults, including errors and short reads) 519550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * more correctly. 520550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 521550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - for now, TX reuses the same queue of BDs every time 522550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 523550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT long term, we want a normal dynamic model. 524550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * ... the goal will be to append to the 525550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * existing queue, processing completed "dma buffers" (segments) on the fly. 526550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 527550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Otherwise we force an IRQ latency between requests, which slows us a lot 528550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (especially in "transparent" dma). Unfortunately that model seems to be 529550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * inherent in the DMA model from the Mentor code, except in the rare case 530550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * of transfers big enough (~128+ KB) that we could append "middle" segments 531550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * in the TX paths. (RX can't do this, see below.) 532550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 533550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * That's true even in the CPPI- friendly iso case, where most urbs have 534550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * several small segments provided in a group and where the "packet at a time" 535550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * "transparent" DMA model is always correct, even on the RX side. 536550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 537550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 538550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 539550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * CPPI TX: 540550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * ======== 541550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * TX is a lot more reasonable than RX; it doesn't need to run in 542550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * irq-per-packet mode very often. RNDIS mode seems to behave too 543550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (except how it handles the exactly-N-packets case). Building a 544550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * txdma queue with multiple requests (urb or usb_request) looks 545550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * like it would work ... but fault handling would need much testing. 546550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 547550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * The main issue with TX mode RNDIS relates to transfer lengths that 548550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * are an exact multiple of the packet length. It appears that there's 549550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * a hiccup in that case (maybe the DMA completes before the ZLP gets 550550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * written?) boiling down to not being able to rely on CPPI writing any 551550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * terminating zero length packet before the next transfer is written. 552550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * So that's punted to PIO; better yet, gadget drivers can avoid it. 553550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 554550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Plus, there's allegedly an undocumented constraint that rndis transfer 555550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * length be a multiple of 64 bytes ... but the chip doesn't act that 556550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * way, and we really don't _want_ that behavior anyway. 557550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 558550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * On TX, "transparent" mode works ... although experiments have shown 559550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * problems trying to use the SOP/EOP bits in different USB packets. 560550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 561550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT try to handle terminating zero length packets using CPPI 562550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * instead of doing it by PIO after an IRQ. (Meanwhile, make Ethernet 563550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * links avoid that issue by forcing them to avoid zlps.) 564550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 565550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void 566550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_next_tx_segment(struct musb *musb, struct cppi_channel *tx) 567550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 568550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned maxpacket = tx->maxpacket; 569550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t addr = tx->buf_dma + tx->offset; 570550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi size_t length = tx->buf_len - tx->offset; 571550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 572550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned n_bds; 573550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned i; 574550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_tx_stateram __iomem *tx_ram = tx->state_ram; 575550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int rndis; 576550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 577550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* TX can use the CPPI "rndis" mode, where we can probably fit this 578550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * transfer in one BD and one IRQ. The only time we would NOT want 579550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * to use it is when hardware constraints prevent it, or if we'd 580550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * trigger the "send a ZLP?" confusion. 581550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 582550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rndis = (maxpacket & 0x3f) == 0 5836b6e97107f12f3a9f7b5b43a6c3b94409240bcffSergei Shtylyov && length > maxpacket 584550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && length < 0xffff 585550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && (length % maxpacket) != 0; 586550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 587550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (rndis) { 588550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi maxpacket = length; 589550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = 1; 590550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 591550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = length / maxpacket; 592550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!length || (length % maxpacket)) 593550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds++; 594550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = min(n_bds, (unsigned) NUM_TXCHAN_BD); 595550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi length = min(n_bds * maxpacket, length); 596550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 597550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 598550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(4, "TX DMA%d, pktSz %d %s bds %d dma 0x%x len %u\n", 599550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->index, 600550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi maxpacket, 601550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rndis ? "rndis" : "transparent", 602550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds, 603550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi addr, length); 604550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 605550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_rndis_update(tx, 0, musb->ctrl_base, rndis); 606550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 607550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* assuming here that channel_program is called during 608550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * transfer initiation ... current code maintains state 609550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * for one outstanding request only (no queues, not even 610550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the implicit ones of an iso urb). 611550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 612550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 613550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = tx->freelist; 614550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->head = bd; 615550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->last_processed = NULL; 616550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 617550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FIXME use BD pool like RX side does, and just queue 618550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the minimum number for this request. 619550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 620550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 621550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Prepare queue of BDs first, then hand it to hardware. 622550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * All BDs except maybe the last should be of full packet 623550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * size; for RNDIS there _is_ only that last packet. 624550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 625550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; i < n_bds; ) { 626550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (++i < n_bds && bd->next) 627550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_next = bd->next->dma; 628550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 629550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_next = 0; 630550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 631550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_bufp = tx->buf_dma + tx->offset; 632550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 633550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FIXME set EOP only on the last packet, 634550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * SOP only on the first ... avoid IRQs 635550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 636550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if ((tx->offset + maxpacket) <= tx->buf_len) { 637550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->offset += maxpacket; 638550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len = maxpacket; 639550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options = CPPI_SOP_SET | CPPI_EOP_SET 640550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi | CPPI_OWN_SET | maxpacket; 641550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 642550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* only this one may be a partial USB Packet */ 643550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 partial_len; 644550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 645550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi partial_len = tx->buf_len - tx->offset; 646550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->offset = tx->buf_len; 647550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len = partial_len; 648550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 649550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options = CPPI_SOP_SET | CPPI_EOP_SET 650550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi | CPPI_OWN_SET | partial_len; 651550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (partial_len == 0) 652550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options |= CPPI_ZERO_SET; 653550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 654550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 655550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(5, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n", 656550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd, bd->hw_next, bd->hw_bufp, 657550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len, bd->hw_options); 658550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 659550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* update the last BD enqueued to the list */ 660550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx->tail = bd; 661550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = bd->next; 662550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 663550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 664550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* BDs live in DMA-coherent memory, but writes might be pending */ 665550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cpu_drain_writebuffer(); 666550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 667550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Write to the HeadPtr in state RAM to trigger */ 668550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx_ram->tx_head, 0, (u32)tx->freelist->dma); 669550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 670550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_tx(5, tx, "/S"); 671550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 672550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 673550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 674550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * CPPI RX Woes: 675550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * ============= 676550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Consider a 1KB bulk RX buffer in two scenarios: (a) it's fed two 300 byte 677550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * packets back-to-back, and (b) it's fed two 512 byte packets back-to-back. 678550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (Full speed transfers have similar scenarios.) 679550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 680550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * The correct behavior for Linux is that (a) fills the buffer with 300 bytes, 681550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * and the next packet goes into a buffer that's queued later; while (b) fills 682550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the buffer with 1024 bytes. How to do that with CPPI? 683550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 684550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - RX queues in "rndis" mode -- one single BD -- handle (a) correctly, but 685550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (b) loses **BADLY** because nothing (!) happens when that second packet 686550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * fills the buffer, much less when a third one arrives. (Which makes this 687550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * not a "true" RNDIS mode. In the RNDIS protocol short-packet termination 688550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * is optional, and it's fine if peripherals -- not hosts! -- pad messages 689550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * out to end-of-buffer. Standard PCI host controller DMA descriptors 690550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * implement that mode by default ... which is no accident.) 691550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 692550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - RX queues in "transparent" mode -- two BDs with 512 bytes each -- have 693550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * converse problems: (b) is handled right, but (a) loses badly. CPPI RX 694550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * ignores SOP/EOP markings and processes both of those BDs; so both packets 695550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * are loaded into the buffer (with a 212 byte gap between them), and the next 696550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * buffer queued will NOT get its 300 bytes of data. (It seems like SOP/EOP 697550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * are intended as outputs for RX queues, not inputs...) 698550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 699550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - A variant of "transparent" mode -- one BD at a time -- is the only way to 700550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * reliably make both cases work, with software handling both cases correctly 701550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * and at the significant penalty of needing an IRQ per packet. (The lack of 702550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * I/O overlap can be slightly ameliorated by enabling double buffering.) 703550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 704550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * So how to get rid of IRQ-per-packet? The transparent multi-BD case could 705550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * be used in special cases like mass storage, which sets URB_SHORT_NOT_OK 706550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (or maybe its peripheral side counterpart) to flag (a) scenarios as errors 707550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * with guaranteed driver level fault recovery and scrubbing out what's left 708550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * of that garbaged datastream. 709550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 710550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * But there seems to be no way to identify the cases where CPPI RNDIS mode 711550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * is appropriate -- which do NOT include RNDIS host drivers, but do include 712550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the CDC Ethernet driver! -- and the documentation is incomplete/wrong. 713550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * So we can't _ever_ use RX RNDIS mode ... except by using a heuristic 714550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * that applies best on the peripheral side (and which could fail rudely). 715550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 716550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Leaving only "transparent" mode; we avoid multi-bd modes in almost all 717550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * cases other than mass storage class. Otherwise we're correct but slow, 718550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * since CPPI penalizes our need for a "true RNDIS" default mode. 719550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 720550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 721550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 722550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Heuristic, intended to kick in for ethernet/rndis peripheral ONLY 723550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 724550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * IFF 725550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (a) peripheral mode ... since rndis peripherals could pad their 726550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * writes to hosts, causing i/o failure; or we'd have to cope with 727550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * a largely unknowable variety of host side protocol variants 728550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (b) and short reads are NOT errors ... since full reads would 729550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * cause those same i/o failures 730550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (c) and read length is 731550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - less than 64KB (max per cppi descriptor) 732550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - not a multiple of 4096 (g_zero default, full reads typical) 733550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * - N (>1) packets long, ditto (full reads not EXPECTED) 734550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * THEN 735550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * try rx rndis mode 736550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 737550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Cost of heuristic failing: RXDMA wedges at the end of transfers that 738550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * fill out the whole buffer. Buggy host side usb network drivers could 739550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * trigger that, but "in the field" such bugs seem to be all but unknown. 740550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 741550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * So this module parameter lets the heuristic be disabled. When using 742550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * gadgetfs, the heuristic will probably need to be disabled. 743550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 744550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic int cppi_rx_rndis = 1; 745550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 746550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbimodule_param(cppi_rx_rndis, bool, 0); 747550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe BalbiMODULE_PARM_DESC(cppi_rx_rndis, "enable/disable RX RNDIS heuristic"); 748550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 749550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 750550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/** 751550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * cppi_next_rx_segment - dma read for the next chunk of a buffer 752550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @musb: the controller 753550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @rx: dma channel 754550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @onepacket: true unless caller treats short reads as errors, and 755550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * performs fault recovery above usbcore. 756550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Context: controller irqlocked 757550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 758550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * See above notes about why we can't use multi-BD RX queues except in 759550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * rare cases (mass storage class), and can never use the hardware "rndis" 760550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * mode (since it's not a "true" RNDIS mode) with complete safety.. 761550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 762550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * It's ESSENTIAL that callers specify "onepacket" mode unless they kick in 763550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * code to recover from corrupted datastreams after each short transfer. 764550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 765550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic void 766550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbicppi_next_rx_segment(struct musb *musb, struct cppi_channel *rx, int onepacket) 767550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 768550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned maxpacket = rx->maxpacket; 769550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t addr = rx->buf_dma + rx->offset; 770550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi size_t length = rx->buf_len - rx->offset; 771550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd, *tail; 772550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned n_bds; 773550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi unsigned i; 774550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase = musb->ctrl_base; 775550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int is_rndis = 0; 776550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_rx_stateram __iomem *rx_ram = rx->state_ram; 777550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 778550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (onepacket) { 779550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* almost every USB driver, host or peripheral side */ 780550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = 1; 781550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 782550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* maybe apply the heuristic above */ 783550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (cppi_rx_rndis 784550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && is_peripheral_active(musb) 785550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && length > maxpacket 786550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && (length & ~0xffff) == 0 787550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && (length & 0x0fff) != 0 788550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && (length & (maxpacket - 1)) == 0) { 789550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi maxpacket = length; 790550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi is_rndis = 1; 791550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 792550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 793550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* virtually nothing except mass storage class */ 794550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (length > 0xffff) { 795550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = 0xffff / maxpacket; 796550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi length = n_bds * maxpacket; 797550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 798550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = length / maxpacket; 799550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (length % maxpacket) 800550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds++; 801550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 802550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (n_bds == 1) 803550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi onepacket = 1; 804550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 805550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = min(n_bds, (unsigned) NUM_RXCHAN_BD); 806550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 807550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 808550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* In host mode, autorequest logic can generate some IN tokens; it's 809550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * tricky since we can't leave REQPKT set in RXCSR after the transfer 810550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * finishes. So: multipacket transfers involve two or more segments. 811550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * And always at least two IRQs ... RNDIS mode is not an option. 812550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 813550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_host_active(musb)) 814550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds = cppi_autoreq_update(rx, tibase, onepacket, n_bds); 815550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 816550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_rndis_update(rx, 1, musb->ctrl_base, is_rndis); 817550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 818550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi length = min(n_bds * maxpacket, length); 819550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 820550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(4, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) " 821550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "dma 0x%x len %u %u/%u\n", 822550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->index, maxpacket, 823550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi onepacket 824550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi ? (is_rndis ? "rndis" : "onepacket") 825550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi : "multipacket", 826550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds, 827550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_readl(tibase, 828550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) 829550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi & 0xffff, 830550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi addr, length, rx->channel.actual_len, rx->buf_len); 831550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 832550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* only queue one segment at a time, since the hardware prevents 833550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * correct queue shutdown after unexpected short packets 834550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 835550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = cppi_bd_alloc(rx); 836550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->head = bd; 837550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 838550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Build BDs for all packets in this segment */ 839550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0, tail = NULL; bd && i < n_bds; i++, tail = bd) { 840550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 bd_len; 841550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 842550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (i) { 843550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = cppi_bd_alloc(rx); 844550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!bd) 845550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 846550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->next = bd; 847550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->hw_next = bd->dma; 848550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 849550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_next = 0; 850550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 851550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* all but the last packet will be maxpacket size */ 852550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (maxpacket < length) 853550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd_len = maxpacket; 854550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 855550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd_len = length; 856550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 857550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_bufp = addr; 858550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi addr += bd_len; 859550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->offset += bd_len; 860550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 861550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len = (0 /*offset*/ << 16) + bd_len; 862550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->buflen = bd_len; 863550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 864550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options = CPPI_OWN_SET | (i == 0 ? length : 0); 865550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi length -= bd_len; 866550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 867550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 868550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* we always expect at least one reusable BD! */ 869550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!tail) { 870550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi WARNING("rx dma%d -- no BDs? need %d\n", rx->index, n_bds); 871550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return; 872550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else if (i < n_bds) 873550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi WARNING("rx dma%d -- only %d of %d BDs\n", rx->index, i, n_bds); 874550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 875550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->next = NULL; 876550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->hw_next = 0; 877550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 878550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = rx->head; 879550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->tail = tail; 880550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 881550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* short reads and other faults should terminate this entire 882550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * dma segment. we want one "dma packet" per dma segment, not 883550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * one per USB packet, terminating the whole queue at once... 884550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * NOTE that current hardware seems to ignore SOP and EOP. 885550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 886550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_options |= CPPI_SOP_SET; 887550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->hw_options |= CPPI_EOP_SET; 888550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 889704a14854aaf9758a1248ea36a7d1b8cc42a4b3eHugo Villeneuve#ifdef CONFIG_USB_MUSB_DEBUG 890704a14854aaf9758a1248ea36a7d1b8cc42a4b3eHugo Villeneuve if (_dbg_level(5)) { 891550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *d; 892550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 893550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (d = rx->head; d; d = d->next) 894550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rxbd("S", d); 895550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 896704a14854aaf9758a1248ea36a7d1b8cc42a4b3eHugo Villeneuve#endif 897550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 898550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* in case the preceding transfer left some state... */ 899550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail = rx->last_processed; 900550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (tail) { 901550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->next = bd; 902550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tail->hw_next = bd->dma; 903550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 904550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 905550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi core_rxirq_enable(tibase, rx->index + 1); 906550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 907550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* BDs live in DMA-coherent memory, but writes might be pending */ 908550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cpu_drain_writebuffer(); 909550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 910550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT specs say to write this AFTER the BUFCNT register 911550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * below ... but that loses badly. 912550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 913550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&rx_ram->rx_head, 0, bd->dma); 914550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 915550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* bufferCount must be at least 3, and zeroes on completion 916550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * unless it underflows below zero, or stops at two, or keeps 917550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * growing ... grr. 918550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 919550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi i = musb_readl(tibase, 920550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) 921550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi & 0xffff; 922550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 923550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!i) 924550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, 925550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), 926550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds + 2); 927550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else if (n_bds > (i - 3)) 928550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, 929550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), 930550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds - (i - 3)); 931550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 932550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi i = musb_readl(tibase, 933550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4)) 934550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi & 0xffff; 935550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (i < (2 + n_bds)) { 936550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(2, "bufcnt%d underrun - %d (for %d)\n", 937550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->index, i, n_bds); 938550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, 939550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4), 940550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi n_bds + 2); 941550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 942550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 943550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rx(4, rx, "/S"); 944550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 945550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 946550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/** 947550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * cppi_channel_program - program channel for data transfer 948550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @ch: the channel 949550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @maxpacket: max packet size 950550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @mode: For RX, 1 unless the usb protocol driver promised to treat 951550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * all short reads as errors and kick in high level fault recovery. 952550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * For TX, ignored because of RNDIS mode races/glitches. 953550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @dma_addr: dma address of buffer 954550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * @len: length of buffer 955550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Context: controller irqlocked 956550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 957550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic int cppi_channel_program(struct dma_channel *ch, 958550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u16 maxpacket, u8 mode, 959550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t dma_addr, u32 len) 960550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 961550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *cppi_ch; 962550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 963550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct musb *musb; 964550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 965550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch = container_of(ch, struct cppi_channel, channel); 966550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller = cppi_ch->controller; 967550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb = controller->musb; 968550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 969550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi switch (ch->status) { 970550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_BUS_ABORT: 971550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_CORE_ABORT: 972550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* fault irq handler should have handled cleanup */ 973550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi WARNING("%cX DMA%d not cleaned up after abort!\n", 974550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->transmit ? 'T' : 'R', 975550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->index); 976550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* WARN_ON(1); */ 977550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 978550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_BUSY: 979550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi WARNING("program active channel? %cX DMA%d\n", 980550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->transmit ? 'T' : 'R', 981550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->index); 982550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* WARN_ON(1); */ 983550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 984550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_UNKNOWN: 985550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(1, "%cX DMA%d not allocated!\n", 986550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->transmit ? 'T' : 'R', 987550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->index); 988550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FALLTHROUGH */ 989550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_FREE: 990550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 991550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 992550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 993550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi ch->status = MUSB_DMA_STATUS_BUSY; 994550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 995550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* set transfer parameters, then queue up its first segment */ 996550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->buf_dma = dma_addr; 997550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->offset = 0; 998550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->maxpacket = maxpacket; 999550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->buf_len = len; 1000191b776616838f035c2fe7eecc882b5c1f134353Swaminathan S cppi_ch->channel.actual_len = 0; 1001550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1002550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* TX channel? or RX? */ 1003550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (cppi_ch->transmit) 1004550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_next_tx_segment(musb, cppi_ch); 1005550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 1006550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_next_rx_segment(musb, cppi_ch, mode); 1007550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1008550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return true; 1009550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1010550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1011550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic bool cppi_rx_scan(struct cppi *cppi, unsigned ch) 1012550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 1013550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *rx = &cppi->rx[ch]; 1014550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_rx_stateram __iomem *state = rx->state_ram; 1015550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 1016550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *last = rx->last_processed; 1017550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bool completed = false; 1018550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bool acked = false; 1019550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int i; 1020550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t safe2ack; 1021550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *regs = rx->hw_ep->regs; 1022550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1023550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rx(6, rx, "/K"); 1024550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1025550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = last ? last->next : rx->head; 1026550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!bd) 1027550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return false; 1028550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1029550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* run through all completed BDs */ 1030550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0, safe2ack = musb_readl(&state->rx_complete, 0); 1031550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi (safe2ack || completed) && bd && i < NUM_RXCHAN_BD; 1032550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi i++, bd = bd->next) { 1033550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u16 len; 1034550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1035550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* catch latest BD writes from CPPI */ 1036550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rmb(); 1037550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!completed && (bd->hw_options & CPPI_OWN_SET)) 1038550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 1039550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1040550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(5, "C/RXBD %08x: nxt %08x buf %08x " 1041550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi "off.len %08x opt.len %08x (%d)\n", 1042550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->dma, bd->hw_next, bd->hw_bufp, 1043550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len, bd->hw_options, 1044550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->channel.actual_len); 1045550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1046550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* actual packet received length */ 1047550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if ((bd->hw_options & CPPI_SOP_SET) && !completed) 1048550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi len = bd->hw_off_len & CPPI_RECV_PKTLEN_MASK; 1049550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi else 1050550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi len = 0; 1051550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1052550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->hw_options & CPPI_EOQ_MASK) 1053550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi completed = true; 1054550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1055550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!completed && len < bd->buflen) { 1056550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* NOTE: when we get a short packet, RXCSR_H_REQPKT 1057550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * must have been cleared, and no more DMA packets may 1058550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * active be in the queue... TI docs didn't say, but 1059550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * CPPI ignores those BDs even though OWN is still set. 1060550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1061550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi completed = true; 1062550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(3, "rx short %d/%d (%d)\n", 1063550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi len, bd->buflen, 1064550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->channel.actual_len); 1065550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1066550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1067550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* If we got here, we expect to ack at least one BD; meanwhile 1068550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * CPPI may completing other BDs while we scan this list... 1069550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1070550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * RACE: we can notice OWN cleared before CPPI raises the 1071550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * matching irq by writing that BD as the completion pointer. 1072550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * In such cases, stop scanning and wait for the irq, avoiding 1073550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * lost acks and states where BD ownership is unclear. 1074550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1075550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->dma == safe2ack) { 1076550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&state->rx_complete, 0, safe2ack); 1077550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi safe2ack = musb_readl(&state->rx_complete, 0); 1078550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi acked = true; 1079550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->dma == safe2ack) 1080550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi safe2ack = 0; 1081550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1082550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1083550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->channel.actual_len += len; 1084550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1085550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_bd_free(rx, last); 1086550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi last = bd; 1087550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1088550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* stop scanning on end-of-segment */ 1089550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->hw_next == 0) 1090550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi completed = true; 1091550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1092550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->last_processed = last; 1093550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1094550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* dma abort, lost ack, or ... */ 1095550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!acked && last) { 1096550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int csr; 1097550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1098550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (safe2ack == 0 || safe2ack == rx->last_processed->dma) 1099550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&state->rx_complete, 0, safe2ack); 1100550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (safe2ack == 0) { 1101550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_bd_free(rx, last); 1102550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->last_processed = NULL; 1103550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1104550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* if we land here on the host side, H_REQPKT will 1105550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * be clear and we need to restart the queue... 1106550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1107550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi WARN_ON(rx->head); 1108550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1109550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_ep_select(cppi->mregs, rx->index + 1); 1110550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr = musb_readw(regs, MUSB_RXCSR); 1111550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (csr & MUSB_RXCSR_DMAENAB) { 1112550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(4, "list%d %p/%p, last %08x%s, csr %04x\n", 1113550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->index, 1114550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->head, rx->tail, 1115550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->last_processed 1116550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi ? rx->last_processed->dma 1117550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi : 0, 1118550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi completed ? ", completed" : "", 1119550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr); 1120550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rxq(4, "/what?", rx); 1121550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1122550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1123550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!completed) { 1124550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi int csr; 1125550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1126550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->head = bd; 1127550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1128550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT seems like "autoreq all but EOP" doesn't... 1129550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * setting it here "should" be racey, but seems to work 1130550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1131550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR); 1132550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_host_active(cppi->musb) 1133550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && bd 1134550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && !(csr & MUSB_RXCSR_H_REQPKT)) { 1135550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr |= MUSB_RXCSR_H_REQPKT; 1136550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writew(regs, MUSB_RXCSR, 1137550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi MUSB_RXCSR_H_WZC_BITS | csr); 1138550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR); 1139550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1140550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 1141550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->head = NULL; 1142550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx->tail = NULL; 1143550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1144550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1145550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rx(6, rx, completed ? "/completed" : "/cleaned"); 1146550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return completed; 1147550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1148550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 114991e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyovirqreturn_t cppi_interrupt(int irq, void *dev_id) 1150550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 115191e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov struct musb *musb = dev_id; 1152550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *cppi; 115391e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov void __iomem *tibase; 1154550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct musb_hw_ep *hw_ep = NULL; 115591e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov u32 rx, tx; 115691e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov int i, index; 115793aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S unsigned long flags; 1158550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1159550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi = container_of(musb->dma_controller, struct cppi, controller); 116093aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S if (cppi->irq) 116193aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S spin_lock_irqsave(&musb->lock, flags); 1162550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1163550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = musb->ctrl_base; 1164550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 116591e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG); 116691e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG); 116791e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 116891e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov if (!tx && !rx) 116991e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov return IRQ_NONE; 117091e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 117191e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx); 117291e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 1173550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* process TX channels */ 1174550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (index = 0; tx; tx = tx >> 1, index++) { 1175550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *tx_ch; 1176550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_tx_stateram __iomem *tx_ram; 1177550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bool completed = false; 1178550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *bd; 1179550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1180550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!(tx & 1)) 1181550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi continue; 1182550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1183550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch = cppi->tx + index; 1184550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ram = tx_ch->state_ram; 1185550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1186550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FIXME need a cppi_tx_scan() routine, which 1187550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * can also be called from abort code 1188550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1189550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1190550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_tx(5, tx_ch, "/E"); 1191550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1192550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd = tx_ch->head; 1193550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1194565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S /* 1195565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S * If Head is null then this could mean that a abort interrupt 1196565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S * that needs to be acknowledged. 1197565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S */ 1198550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (NULL == bd) { 1199550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(1, "null BD\n"); 1200565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S tx_ram->tx_complete = 0; 1201550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi continue; 1202550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1203550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1204550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* run through all completed BDs */ 1205550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (i = 0; !completed && bd && i < NUM_TXCHAN_BD; 1206550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi i++, bd = bd->next) { 1207550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u16 len; 1208550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1209550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* catch latest BD writes from CPPI */ 1210550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rmb(); 1211550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->hw_options & CPPI_OWN_SET) 1212550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 1213550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1214550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi DBG(5, "C/TXBD %p n %x b %x off %x opt %x\n", 1215550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd, bd->hw_next, bd->hw_bufp, 1216550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bd->hw_off_len, bd->hw_options); 1217550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1218550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi len = bd->hw_off_len & CPPI_BUFFER_LEN_MASK; 1219550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->channel.actual_len += len; 1220550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1221550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->last_processed = bd; 1222550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1223550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* write completion register to acknowledge 1224550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * processing of completed BDs, and possibly 1225550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * release the IRQ; EOQ might not be set ... 1226550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1227550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT use the same ack strategy as rx 1228550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1229550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT have observed bit 18 set; huh?? 1230550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1231550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* if ((bd->hw_options & CPPI_EOQ_MASK)) */ 1232550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(&tx_ram->tx_complete, 0, bd->dma); 1233550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1234550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* stop scanning on end-of-segment */ 1235550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (bd->hw_next == 0) 1236550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi completed = true; 1237550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1238550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1239550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* on end of segment, maybe go to next one */ 1240550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (completed) { 1241550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* cppi_dump_tx(4, tx_ch, "/complete"); */ 1242550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1243550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* transfer more, or report completion */ 1244550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (tx_ch->offset >= tx_ch->buf_len) { 1245550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->head = NULL; 1246550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->tail = NULL; 1247550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->channel.status = MUSB_DMA_STATUS_FREE; 1248550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1249550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi hw_ep = tx_ch->hw_ep; 1250550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1251c7bbc056a92476b3b3d70a8df7cc746ac5d56de7Sergei Shtylyov musb_dma_completion(musb, index + 1, 1); 1252550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1253550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else { 1254550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Bigger transfer than we could fit in 1255550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * that first batch of descriptors... 1256550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1257550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_next_tx_segment(musb, tx_ch); 1258550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1259550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else 1260550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ch->head = bd; 1261550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1262550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1263550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Start processing the RX block */ 1264550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi for (index = 0; rx; rx = rx >> 1, index++) { 1265550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1266550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (rx & 1) { 1267550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *rx_ch; 1268550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1269550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx_ch = cppi->rx + index; 1270550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1271550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* let incomplete dma segments finish */ 1272550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!cppi_rx_scan(cppi, index)) 1273550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi continue; 1274550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1275550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* start another dma segment if needed */ 1276550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (rx_ch->channel.actual_len != rx_ch->buf_len 1277550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi && rx_ch->channel.actual_len 1278550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi == rx_ch->offset) { 1279550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_next_rx_segment(musb, rx_ch, 1); 1280550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi continue; 1281550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1282550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1283550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* all segments completed! */ 1284550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi rx_ch->channel.status = MUSB_DMA_STATUS_FREE; 1285550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1286550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi hw_ep = rx_ch->hw_ep; 1287550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1288550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi core_rxirq_disable(tibase, index + 1); 1289550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_dma_completion(musb, index + 1, 0); 1290550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1291550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1292550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1293550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* write to CPPI EOI register to re-enable interrupts */ 1294550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0); 129591e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 129693aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S if (cppi->irq) 129793aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S spin_unlock_irqrestore(&musb->lock, flags); 129893aa3dab008421789aa0f8865a62a52ae13269a3Swaminathan S 129991e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov return IRQ_HANDLED; 1300550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1301550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1302550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Instantiate a software object representing a DMA controller. */ 1303550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistruct dma_controller *__init 1304550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbidma_controller_create(struct musb *musb, void __iomem *mregs) 1305550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 1306550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 130791e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov struct device *dev = musb->controller; 130891e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov struct platform_device *pdev = to_platform_device(dev); 130991e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov int irq = platform_get_irq(pdev, 1); 1310550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1311550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller = kzalloc(sizeof *controller, GFP_KERNEL); 1312550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!controller) 1313550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return NULL; 1314550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1315550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->mregs = mregs; 1316550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->tibase = mregs - DAVINCI_BASE_OFFSET; 1317550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1318550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->musb = musb; 1319550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->controller.start = cppi_controller_start; 1320550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->controller.stop = cppi_controller_stop; 1321550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->controller.channel_alloc = cppi_channel_allocate; 1322550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->controller.channel_release = cppi_channel_release; 1323550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->controller.channel_program = cppi_channel_program; 1324550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->controller.channel_abort = cppi_channel_abort; 1325550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1326550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* NOTE: allocating from on-chip SRAM would give the least 1327550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * contention for memory access, if that ever matters here. 1328550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1329550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1330550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* setup BufferPool */ 1331550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->pool = dma_pool_create("cppi", 1332550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller->musb->controller, 1333550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi sizeof(struct cppi_descriptor), 1334550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi CPPI_DESCRIPTOR_ALIGN, 0); 1335550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!controller->pool) { 1336550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi kfree(controller); 1337550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return NULL; 1338550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1339550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 134091e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov if (irq > 0) { 134191e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) { 134291e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov dev_err(dev, "request_irq %d failed!\n", irq); 134391e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov dma_controller_destroy(&controller->controller); 134491e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov return NULL; 134591e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov } 134691e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov controller->irq = irq; 134791e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov } 134891e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 1349550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return &controller->controller; 1350550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1351550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1352550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 1353550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Destroy a previously-instantiated DMA controller. 1354550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1355550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbivoid dma_controller_destroy(struct dma_controller *c) 1356550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 1357550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *cppi; 1358550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1359550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi = container_of(c, struct cppi, controller); 1360550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 136191e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov if (cppi->irq) 136291e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov free_irq(cppi->irq, cppi->musb); 136391e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 1364550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* assert: caller stopped the controller first */ 1365550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_pool_destroy(cppi->pool); 1366550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1367550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi kfree(cppi); 1368550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1369550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1370550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 1371550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Context: controller irqlocked, endpoint selected 1372550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1373550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistatic int cppi_channel_abort(struct dma_channel *channel) 1374550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi{ 1375550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_channel *cppi_ch; 1376550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 1377550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *mbase; 1378550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; 1379550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *regs; 1380550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 value; 1381550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *queue; 1382550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1383550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch = container_of(channel, struct cppi_channel, channel); 1384550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1385550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi controller = cppi_ch->controller; 1386550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1387550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi switch (channel->status) { 1388550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_BUS_ABORT: 1389550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_CORE_ABORT: 1390550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* from RX or TX fault irq handler */ 1391550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_BUSY: 1392550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* the hardware needs shutting down */ 1393550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi regs = cppi_ch->hw_ep->regs; 1394550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi break; 1395550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_UNKNOWN: 1396550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi case MUSB_DMA_STATUS_FREE: 1397550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return 0; 1398550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi default: 1399550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return -EINVAL; 1400550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1401550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1402550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (!cppi_ch->transmit && cppi_ch->head) 1403550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rxq(3, "/abort", cppi_ch); 1404550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1405550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi mbase = controller->mregs; 1406550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tibase = controller->tibase; 1407550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1408550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi queue = cppi_ch->head; 1409550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->head = NULL; 1410550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->tail = NULL; 1411550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1412550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT should rely on caller having done this, 1413550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * and caller should rely on us not changing it. 1414550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * peripheral code is safe ... check host too. 1415550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1416550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_ep_select(mbase, cppi_ch->index + 1); 1417550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1418550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (cppi_ch->transmit) { 1419550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_tx_stateram __iomem *tx_ram; 1420550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT put timeouts on these controller handshakes */ 1421550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1422550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_tx(6, cppi_ch, " (teardown)"); 1423550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1424550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* teardown DMA engine then usb core */ 1425550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi do { 1426550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value = musb_readl(tibase, DAVINCI_TXCPPI_TEAR_REG); 1427550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } while (!(value & CPPI_TEAR_READY)); 1428550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_TXCPPI_TEAR_REG, cppi_ch->index); 1429550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1430550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi tx_ram = cppi_ch->state_ram; 1431550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi do { 1432550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value = musb_readl(&tx_ram->tx_complete, 0); 1433550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } while (0xFFFFFFFC != value); 1434550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1435550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* FIXME clean up the transfer state ... here? 1436550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * the completion routine should get called with 1437550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * an appropriate status code. 1438550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1439550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1440550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value = musb_readw(regs, MUSB_TXCSR); 1441550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value &= ~MUSB_TXCSR_DMAENAB; 1442550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value |= MUSB_TXCSR_FLUSHFIFO; 1443550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writew(regs, MUSB_TXCSR, value); 1444550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writew(regs, MUSB_TXCSR, value); 1445550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1446565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S /* 1447550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1. Write to completion Ptr value 0x1(bit 0 set) 1448550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * (write back mode) 1449565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S * 2. Wait for abort interrupt and then put the channel in 1450565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S * compare mode by writing 1 to the tx_complete register. 1451550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1452550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_reset_tx(tx_ram, 1); 1453565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S cppi_ch->head = 0; 1454565969237ab6e73ce7192684d00d5b890ee308faSwaminathan S musb_writel(&tx_ram->tx_complete, 0, 1); 1455550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_tx(5, cppi_ch, " (done teardown)"); 1456550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1457550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* REVISIT tx side _should_ clean up the same way 1458550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * as the RX side ... this does no cleanup at all! 1459550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1460550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1461550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else /* RX */ { 1462550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u16 csr; 1463550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1464550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* NOTE: docs don't guarantee any of this works ... we 1465550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * expect that if the usb core stops telling the cppi core 1466550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * to pull more data from it, then it'll be safe to flush 1467550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * current RX DMA state iff any pending fifo transfer is done. 1468550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1469550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1470550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi core_rxirq_disable(tibase, cppi_ch->index + 1); 1471550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1472550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* for host, ensure ReqPkt is never set again */ 1473550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_host_active(cppi_ch->controller->musb)) { 1474550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value = musb_readl(tibase, DAVINCI_AUTOREQ_REG); 1475550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi value &= ~((0x3) << (cppi_ch->index * 2)); 1476550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writel(tibase, DAVINCI_AUTOREQ_REG, value); 1477550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1478550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1479550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr = musb_readw(regs, MUSB_RXCSR); 1480550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1481550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* for host, clear (just) ReqPkt at end of current packet(s) */ 1482550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (is_host_active(cppi_ch->controller->musb)) { 1483550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr |= MUSB_RXCSR_H_WZC_BITS; 1484550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr &= ~MUSB_RXCSR_H_REQPKT; 1485550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } else 1486550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr |= MUSB_RXCSR_P_WZC_BITS; 1487550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1488550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* clear dma enable */ 1489550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr &= ~(MUSB_RXCSR_DMAENAB); 1490550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi musb_writew(regs, MUSB_RXCSR, csr); 1491550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi csr = musb_readw(regs, MUSB_RXCSR); 1492550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1493550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* Quiesce: wait for current dma to finish (if not cleanup). 1494550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * We can't use bit zero of stateram->rx_sop, since that 1495550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * refers to an entire "DMA packet" not just emptying the 1496550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * current fifo. Most segments need multiple usb packets. 1497550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1498550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi if (channel->status == MUSB_DMA_STATUS_BUSY) 1499550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi udelay(50); 1500550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1501550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* scan the current list, reporting any data that was 1502550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * transferred and acking any IRQ 1503550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1504550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_rx_scan(controller, cppi_ch->index); 1505550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1506550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* clobber the existing state once it's idle 1507550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1508550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * NOTE: arguably, we should also wait for all the other 1509550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * RX channels to quiesce (how??) and then temporarily 1510550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * disable RXCPPI_CTRL_REG ... but it seems that we can 1511550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * rely on the controller restarting from state ram, with 1512550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * only RXCPPI_BUFCNT state being bogus. BUFCNT will 1513550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * correct itself after the next DMA transfer though. 1514550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1515550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * REVISIT does using rndis mode change that? 1516550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1517550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_reset_rx(cppi_ch->state_ram); 1518550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1519550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* next DMA request _should_ load cppi head ptr */ 1520550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1521550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* ... we don't "free" that list, only mutate it in place. */ 1522550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_dump_rx(5, cppi_ch, " (done abort)"); 1523550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1524550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* clean up previously pending bds */ 1525550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_bd_free(cppi_ch, cppi_ch->last_processed); 1526550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->last_processed = NULL; 1527550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1528550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi while (queue) { 1529550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *tmp = queue->next; 1530550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1531550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_bd_free(cppi_ch, queue); 1532550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi queue = tmp; 1533550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1534550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi } 1535550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1536550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi channel->status = MUSB_DMA_STATUS_FREE; 1537550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->buf_dma = 0; 1538550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->offset = 0; 1539550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->buf_len = 0; 1540550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi cppi_ch->maxpacket = 0; 1541550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi return 0; 1542550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} 1543550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 1544550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* TBD Queries: 1545550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 1546550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Power Management ... probably turn off cppi during suspend, restart; 1547550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * check state ram? Clocking is presumably shared with usb core. 1548550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 1549