1/*
2 * MUSB OTG driver DMA controller abstraction
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35#ifndef __MUSB_DMA_H__
36#define __MUSB_DMA_H__
37
38struct musb_hw_ep;
39
40/*
41 * DMA Controller Abstraction
42 *
43 * DMA Controllers are abstracted to allow use of a variety of different
44 * implementations of DMA, as allowed by the Inventra USB cores.  On the
45 * host side, usbcore sets up the DMA mappings and flushes caches; on the
46 * peripheral side, the gadget controller driver does.  Responsibilities
47 * of a DMA controller driver include:
48 *
49 *  - Handling the details of moving multiple USB packets
50 *    in cooperation with the Inventra USB core, including especially
51 *    the correct RX side treatment of short packets and buffer-full
52 *    states (both of which terminate transfers).
53 *
54 *  - Knowing the correlation between dma channels and the
55 *    Inventra core's local endpoint resources and data direction.
56 *
57 *  - Maintaining a list of allocated/available channels.
58 *
59 *  - Updating channel status on interrupts,
60 *    whether shared with the Inventra core or separate.
61 */
62
63#define	DMA_ADDR_INVALID	(~(dma_addr_t)0)
64
65#ifdef CONFIG_MUSB_PIO_ONLY
66#define	is_dma_capable()	(0)
67#else
68#define	is_dma_capable()	(1)
69#endif
70
71#if defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TI_CPPI41_DMA)
72#define	is_cppi_enabled()	1
73#else
74#define	is_cppi_enabled()	0
75#endif
76
77#ifdef CONFIG_USB_TUSB_OMAP_DMA
78#define tusb_dma_omap()			1
79#else
80#define tusb_dma_omap()			0
81#endif
82
83/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
84 *	Only allow DMA mode 1 to be used when the USB will actually generate the
85 *	interrupts we expect.
86 */
87#ifdef CONFIG_BLACKFIN
88# undef USE_MODE1
89# if !ANOMALY_05000456
90#  define USE_MODE1
91# endif
92#endif
93
94/*
95 * DMA channel status ... updated by the dma controller driver whenever that
96 * status changes, and protected by the overall controller spinlock.
97 */
98enum dma_channel_status {
99	/* unallocated */
100	MUSB_DMA_STATUS_UNKNOWN,
101	/* allocated ... but not busy, no errors */
102	MUSB_DMA_STATUS_FREE,
103	/* busy ... transactions are active */
104	MUSB_DMA_STATUS_BUSY,
105	/* transaction(s) aborted due to ... dma or memory bus error */
106	MUSB_DMA_STATUS_BUS_ABORT,
107	/* transaction(s) aborted due to ... core error or USB fault */
108	MUSB_DMA_STATUS_CORE_ABORT
109};
110
111struct dma_controller;
112
113/**
114 * struct dma_channel - A DMA channel.
115 * @private_data: channel-private data
116 * @max_len: the maximum number of bytes the channel can move in one
117 *	transaction (typically representing many USB maximum-sized packets)
118 * @actual_len: how many bytes have been transferred
119 * @status: current channel status (updated e.g. on interrupt)
120 * @desired_mode: true if mode 1 is desired; false if mode 0 is desired
121 *
122 * channels are associated with an endpoint for the duration of at least
123 * one usb transfer.
124 */
125struct dma_channel {
126	void			*private_data;
127	/* FIXME not void* private_data, but a dma_controller * */
128	size_t			max_len;
129	size_t			actual_len;
130	enum dma_channel_status	status;
131	bool			desired_mode;
132	bool			rx_packet_done;
133};
134
135/*
136 * dma_channel_status - return status of dma channel
137 * @c: the channel
138 *
139 * Returns the software's view of the channel status.  If that status is BUSY
140 * then it's possible that the hardware has completed (or aborted) a transfer,
141 * so the driver needs to update that status.
142 */
143static inline enum dma_channel_status
144dma_channel_status(struct dma_channel *c)
145{
146	return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
147}
148
149/**
150 * struct dma_controller - A DMA Controller.
151 * @start: call this to start a DMA controller;
152 *	return 0 on success, else negative errno
153 * @stop: call this to stop a DMA controller
154 *	return 0 on success, else negative errno
155 * @channel_alloc: call this to allocate a DMA channel
156 * @channel_release: call this to release a DMA channel
157 * @channel_abort: call this to abort a pending DMA transaction,
158 *	returning it to FREE (but allocated) state
159 *
160 * Controllers manage dma channels.
161 */
162struct dma_controller {
163	struct dma_channel	*(*channel_alloc)(struct dma_controller *,
164					struct musb_hw_ep *, u8 is_tx);
165	void			(*channel_release)(struct dma_channel *);
166	int			(*channel_program)(struct dma_channel *channel,
167							u16 maxpacket, u8 mode,
168							dma_addr_t dma_addr,
169							u32 length);
170	int			(*channel_abort)(struct dma_channel *);
171	int			(*is_compatible)(struct dma_channel *channel,
172							u16 maxpacket,
173							void *buf, u32 length);
174};
175
176/* called after channel_program(), may indicate a fault */
177extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
178
179#ifdef CONFIG_MUSB_PIO_ONLY
180static inline struct dma_controller *dma_controller_create(struct musb *m,
181		void __iomem *io)
182{
183	return NULL;
184}
185
186static inline void dma_controller_destroy(struct dma_controller *d) { }
187
188#else
189
190extern struct dma_controller *dma_controller_create(struct musb *, void __iomem *);
191
192extern void dma_controller_destroy(struct dma_controller *);
193#endif
194
195#endif	/* __MUSB_DMA_H__ */
196