musb_dsps.c revision deeeb9ee1ed5b06864f530c6123976209badd489
1/* 2 * Texas Instruments DSPS platforms "glue layer" 3 * 4 * Copyright (C) 2012, by Texas Instruments 5 * 6 * Based on the am35x "glue layer" code. 7 * 8 * This file is part of the Inventra Controller Driver for Linux. 9 * 10 * The Inventra Controller Driver for Linux is free software; you 11 * can redistribute it and/or modify it under the terms of the GNU 12 * General Public License version 2 as published by the Free Software 13 * Foundation. 14 * 15 * The Inventra Controller Driver for Linux is distributed in 16 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 17 * without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 * License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with The Inventra Controller Driver for Linux ; if not, 23 * write to the Free Software Foundation, Inc., 59 Temple Place, 24 * Suite 330, Boston, MA 02111-1307 USA 25 * 26 * musb_dsps.c will be a common file for all the TI DSPS platforms 27 * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x. 28 * For now only ti81x is using this and in future davinci.c, am35x.c 29 * da8xx.c would be merged to this file after testing. 30 */ 31 32#include <linux/init.h> 33#include <linux/io.h> 34#include <linux/of.h> 35#include <linux/err.h> 36#include <linux/platform_device.h> 37#include <linux/dma-mapping.h> 38#include <linux/pm_runtime.h> 39#include <linux/module.h> 40#include <linux/usb/nop-usb-xceiv.h> 41#include <linux/platform_data/usb-omap.h> 42 43#include <linux/of.h> 44#include <linux/of_device.h> 45#include <linux/of_address.h> 46 47#include "musb_core.h" 48 49#ifdef CONFIG_OF 50static const struct of_device_id musb_dsps_of_match[]; 51#endif 52 53/** 54 * avoid using musb_readx()/musb_writex() as glue layer should not be 55 * dependent on musb core layer symbols. 56 */ 57static inline u8 dsps_readb(const void __iomem *addr, unsigned offset) 58 { return __raw_readb(addr + offset); } 59 60static inline u32 dsps_readl(const void __iomem *addr, unsigned offset) 61 { return __raw_readl(addr + offset); } 62 63static inline void dsps_writeb(void __iomem *addr, unsigned offset, u8 data) 64 { __raw_writeb(data, addr + offset); } 65 66static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data) 67 { __raw_writel(data, addr + offset); } 68 69/** 70 * DSPS musb wrapper register offset. 71 * FIXME: This should be expanded to have all the wrapper registers from TI DSPS 72 * musb ips. 73 */ 74struct dsps_musb_wrapper { 75 u16 revision; 76 u16 control; 77 u16 status; 78 u16 eoi; 79 u16 epintr_set; 80 u16 epintr_clear; 81 u16 epintr_status; 82 u16 coreintr_set; 83 u16 coreintr_clear; 84 u16 coreintr_status; 85 u16 phy_utmi; 86 u16 mode; 87 88 /* bit positions for control */ 89 unsigned reset:5; 90 91 /* bit positions for interrupt */ 92 unsigned usb_shift:5; 93 u32 usb_mask; 94 u32 usb_bitmap; 95 unsigned drvvbus:5; 96 97 unsigned txep_shift:5; 98 u32 txep_mask; 99 u32 txep_bitmap; 100 101 unsigned rxep_shift:5; 102 u32 rxep_mask; 103 u32 rxep_bitmap; 104 105 /* bit positions for phy_utmi */ 106 unsigned otg_disable:5; 107 108 /* bit positions for mode */ 109 unsigned iddig:5; 110 /* miscellaneous stuff */ 111 u32 musb_core_offset; 112 u8 poll_seconds; 113 /* number of musb instances */ 114 u8 instances; 115}; 116 117/** 118 * DSPS glue structure. 119 */ 120struct dsps_glue { 121 struct device *dev; 122 struct platform_device *musb[2]; /* child musb pdev */ 123 const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */ 124 struct timer_list timer[2]; /* otg_workaround timer */ 125 unsigned long last_timer[2]; /* last timer data for each instance */ 126 u32 __iomem *usb_ctrl[2]; 127}; 128 129#define DSPS_AM33XX_CONTROL_MODULE_PHYS_0 0x44e10620 130#define DSPS_AM33XX_CONTROL_MODULE_PHYS_1 0x44e10628 131 132static const resource_size_t dsps_control_module_phys[] = { 133 DSPS_AM33XX_CONTROL_MODULE_PHYS_0, 134 DSPS_AM33XX_CONTROL_MODULE_PHYS_1, 135}; 136 137#define USBPHY_CM_PWRDN (1 << 0) 138#define USBPHY_OTG_PWRDN (1 << 1) 139#define USBPHY_OTGVDET_EN (1 << 19) 140#define USBPHY_OTGSESSEND_EN (1 << 20) 141 142/** 143 * musb_dsps_phy_control - phy on/off 144 * @glue: struct dsps_glue * 145 * @id: musb instance 146 * @on: flag for phy to be switched on or off 147 * 148 * This is to enable the PHY using usb_ctrl register in system control 149 * module space. 150 * 151 * XXX: This function will be removed once we have a seperate driver for 152 * control module 153 */ 154static void musb_dsps_phy_control(struct dsps_glue *glue, u8 id, u8 on) 155{ 156 u32 usbphycfg; 157 158 usbphycfg = readl(glue->usb_ctrl[id]); 159 160 if (on) { 161 usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN); 162 usbphycfg |= USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN; 163 } else { 164 usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN; 165 } 166 167 writel(usbphycfg, glue->usb_ctrl[id]); 168} 169/** 170 * dsps_musb_enable - enable interrupts 171 */ 172static void dsps_musb_enable(struct musb *musb) 173{ 174 struct device *dev = musb->controller; 175 struct platform_device *pdev = to_platform_device(dev->parent); 176 struct dsps_glue *glue = platform_get_drvdata(pdev); 177 const struct dsps_musb_wrapper *wrp = glue->wrp; 178 void __iomem *reg_base = musb->ctrl_base; 179 u32 epmask, coremask; 180 181 /* Workaround: setup IRQs through both register sets. */ 182 epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) | 183 ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift); 184 coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF); 185 186 dsps_writel(reg_base, wrp->epintr_set, epmask); 187 dsps_writel(reg_base, wrp->coreintr_set, coremask); 188 /* Force the DRVVBUS IRQ so we can start polling for ID change. */ 189 dsps_writel(reg_base, wrp->coreintr_set, 190 (1 << wrp->drvvbus) << wrp->usb_shift); 191} 192 193/** 194 * dsps_musb_disable - disable HDRC and flush interrupts 195 */ 196static void dsps_musb_disable(struct musb *musb) 197{ 198 struct device *dev = musb->controller; 199 struct platform_device *pdev = to_platform_device(dev->parent); 200 struct dsps_glue *glue = platform_get_drvdata(pdev); 201 const struct dsps_musb_wrapper *wrp = glue->wrp; 202 void __iomem *reg_base = musb->ctrl_base; 203 204 dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); 205 dsps_writel(reg_base, wrp->epintr_clear, 206 wrp->txep_bitmap | wrp->rxep_bitmap); 207 dsps_writeb(musb->mregs, MUSB_DEVCTL, 0); 208 dsps_writel(reg_base, wrp->eoi, 0); 209} 210 211static void otg_timer(unsigned long _musb) 212{ 213 struct musb *musb = (void *)_musb; 214 void __iomem *mregs = musb->mregs; 215 struct device *dev = musb->controller; 216 struct platform_device *pdev = to_platform_device(dev); 217 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 218 const struct dsps_musb_wrapper *wrp = glue->wrp; 219 u8 devctl; 220 unsigned long flags; 221 222 /* 223 * We poll because DSPS IP's won't expose several OTG-critical 224 * status change events (from the transceiver) otherwise. 225 */ 226 devctl = dsps_readb(mregs, MUSB_DEVCTL); 227 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, 228 otg_state_string(musb->xceiv->state)); 229 230 spin_lock_irqsave(&musb->lock, flags); 231 switch (musb->xceiv->state) { 232 case OTG_STATE_A_WAIT_BCON: 233 devctl &= ~MUSB_DEVCTL_SESSION; 234 dsps_writeb(musb->mregs, MUSB_DEVCTL, devctl); 235 236 devctl = dsps_readb(musb->mregs, MUSB_DEVCTL); 237 if (devctl & MUSB_DEVCTL_BDEVICE) { 238 musb->xceiv->state = OTG_STATE_B_IDLE; 239 MUSB_DEV_MODE(musb); 240 } else { 241 musb->xceiv->state = OTG_STATE_A_IDLE; 242 MUSB_HST_MODE(musb); 243 } 244 break; 245 case OTG_STATE_A_WAIT_VFALL: 246 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 247 dsps_writel(musb->ctrl_base, wrp->coreintr_set, 248 MUSB_INTR_VBUSERROR << wrp->usb_shift); 249 break; 250 case OTG_STATE_B_IDLE: 251 devctl = dsps_readb(mregs, MUSB_DEVCTL); 252 if (devctl & MUSB_DEVCTL_BDEVICE) 253 mod_timer(&glue->timer[pdev->id], 254 jiffies + wrp->poll_seconds * HZ); 255 else 256 musb->xceiv->state = OTG_STATE_A_IDLE; 257 break; 258 default: 259 break; 260 } 261 spin_unlock_irqrestore(&musb->lock, flags); 262} 263 264static void dsps_musb_try_idle(struct musb *musb, unsigned long timeout) 265{ 266 struct device *dev = musb->controller; 267 struct platform_device *pdev = to_platform_device(dev); 268 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 269 270 if (timeout == 0) 271 timeout = jiffies + msecs_to_jiffies(3); 272 273 /* Never idle if active, or when VBUS timeout is not set as host */ 274 if (musb->is_active || (musb->a_wait_bcon == 0 && 275 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { 276 dev_dbg(musb->controller, "%s active, deleting timer\n", 277 otg_state_string(musb->xceiv->state)); 278 del_timer(&glue->timer[pdev->id]); 279 glue->last_timer[pdev->id] = jiffies; 280 return; 281 } 282 283 if (time_after(glue->last_timer[pdev->id], timeout) && 284 timer_pending(&glue->timer[pdev->id])) { 285 dev_dbg(musb->controller, 286 "Longer idle timer already pending, ignoring...\n"); 287 return; 288 } 289 glue->last_timer[pdev->id] = timeout; 290 291 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", 292 otg_state_string(musb->xceiv->state), 293 jiffies_to_msecs(timeout - jiffies)); 294 mod_timer(&glue->timer[pdev->id], timeout); 295} 296 297static irqreturn_t dsps_interrupt(int irq, void *hci) 298{ 299 struct musb *musb = hci; 300 void __iomem *reg_base = musb->ctrl_base; 301 struct device *dev = musb->controller; 302 struct platform_device *pdev = to_platform_device(dev); 303 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 304 const struct dsps_musb_wrapper *wrp = glue->wrp; 305 unsigned long flags; 306 irqreturn_t ret = IRQ_NONE; 307 u32 epintr, usbintr; 308 309 spin_lock_irqsave(&musb->lock, flags); 310 311 /* Get endpoint interrupts */ 312 epintr = dsps_readl(reg_base, wrp->epintr_status); 313 musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift; 314 musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift; 315 316 if (epintr) 317 dsps_writel(reg_base, wrp->epintr_status, epintr); 318 319 /* Get usb core interrupts */ 320 usbintr = dsps_readl(reg_base, wrp->coreintr_status); 321 if (!usbintr && !epintr) 322 goto eoi; 323 324 musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift; 325 if (usbintr) 326 dsps_writel(reg_base, wrp->coreintr_status, usbintr); 327 328 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", 329 usbintr, epintr); 330 /* 331 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for 332 * DSPS IP's missing ID change IRQ. We need an ID change IRQ to 333 * switch appropriately between halves of the OTG state machine. 334 * Managing DEVCTL.SESSION per Mentor docs requires that we know its 335 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. 336 * Also, DRVVBUS pulses for SRP (but not at 5V) ... 337 */ 338 if (usbintr & MUSB_INTR_BABBLE) 339 pr_info("CAUTION: musb: Babble Interrupt Occurred\n"); 340 341 if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) { 342 int drvvbus = dsps_readl(reg_base, wrp->status); 343 void __iomem *mregs = musb->mregs; 344 u8 devctl = dsps_readb(mregs, MUSB_DEVCTL); 345 int err; 346 347 err = musb->int_usb & MUSB_INTR_VBUSERROR; 348 if (err) { 349 /* 350 * The Mentor core doesn't debounce VBUS as needed 351 * to cope with device connect current spikes. This 352 * means it's not uncommon for bus-powered devices 353 * to get VBUS errors during enumeration. 354 * 355 * This is a workaround, but newer RTL from Mentor 356 * seems to allow a better one: "re"-starting sessions 357 * without waiting for VBUS to stop registering in 358 * devctl. 359 */ 360 musb->int_usb &= ~MUSB_INTR_VBUSERROR; 361 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 362 mod_timer(&glue->timer[pdev->id], 363 jiffies + wrp->poll_seconds * HZ); 364 WARNING("VBUS error workaround (delay coming)\n"); 365 } else if (drvvbus) { 366 musb->is_active = 1; 367 MUSB_HST_MODE(musb); 368 musb->xceiv->otg->default_a = 1; 369 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 370 del_timer(&glue->timer[pdev->id]); 371 } else { 372 musb->is_active = 0; 373 MUSB_DEV_MODE(musb); 374 musb->xceiv->otg->default_a = 0; 375 musb->xceiv->state = OTG_STATE_B_IDLE; 376 } 377 378 /* NOTE: this must complete power-on within 100 ms. */ 379 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", 380 drvvbus ? "on" : "off", 381 otg_state_string(musb->xceiv->state), 382 err ? " ERROR" : "", 383 devctl); 384 ret = IRQ_HANDLED; 385 } 386 387 if (musb->int_tx || musb->int_rx || musb->int_usb) 388 ret |= musb_interrupt(musb); 389 390 eoi: 391 /* EOI needs to be written for the IRQ to be re-asserted. */ 392 if (ret == IRQ_HANDLED || epintr || usbintr) 393 dsps_writel(reg_base, wrp->eoi, 1); 394 395 /* Poll for ID change */ 396 if (musb->xceiv->state == OTG_STATE_B_IDLE) 397 mod_timer(&glue->timer[pdev->id], 398 jiffies + wrp->poll_seconds * HZ); 399 400 spin_unlock_irqrestore(&musb->lock, flags); 401 402 return ret; 403} 404 405static int dsps_musb_init(struct musb *musb) 406{ 407 struct device *dev = musb->controller; 408 struct platform_device *pdev = to_platform_device(dev); 409 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 410 const struct dsps_musb_wrapper *wrp = glue->wrp; 411 void __iomem *reg_base = musb->ctrl_base; 412 u32 rev, val; 413 int status; 414 415 /* mentor core register starts at offset of 0x400 from musb base */ 416 musb->mregs += wrp->musb_core_offset; 417 418 /* NOP driver needs change if supporting dual instance */ 419 usb_nop_xceiv_register(); 420 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 421 if (IS_ERR_OR_NULL(musb->xceiv)) 422 return -ENODEV; 423 424 /* Returns zero if e.g. not clocked */ 425 rev = dsps_readl(reg_base, wrp->revision); 426 if (!rev) { 427 status = -ENODEV; 428 goto err0; 429 } 430 431 setup_timer(&glue->timer[pdev->id], otg_timer, (unsigned long) musb); 432 433 /* Reset the musb */ 434 dsps_writel(reg_base, wrp->control, (1 << wrp->reset)); 435 436 /* Start the on-chip PHY and its PLL. */ 437 musb_dsps_phy_control(glue, pdev->id, 1); 438 439 musb->isr = dsps_interrupt; 440 441 /* reset the otgdisable bit, needed for host mode to work */ 442 val = dsps_readl(reg_base, wrp->phy_utmi); 443 val &= ~(1 << wrp->otg_disable); 444 dsps_writel(musb->ctrl_base, wrp->phy_utmi, val); 445 446 /* clear level interrupt */ 447 dsps_writel(reg_base, wrp->eoi, 0); 448 449 return 0; 450err0: 451 usb_put_phy(musb->xceiv); 452 usb_nop_xceiv_unregister(); 453 return status; 454} 455 456static int dsps_musb_exit(struct musb *musb) 457{ 458 struct device *dev = musb->controller; 459 struct platform_device *pdev = to_platform_device(dev); 460 struct dsps_glue *glue = dev_get_drvdata(dev->parent); 461 462 del_timer_sync(&glue->timer[pdev->id]); 463 464 /* Shutdown the on-chip PHY and its PLL. */ 465 musb_dsps_phy_control(glue, pdev->id, 0); 466 467 /* NOP driver needs change if supporting dual instance */ 468 usb_put_phy(musb->xceiv); 469 usb_nop_xceiv_unregister(); 470 471 return 0; 472} 473 474static struct musb_platform_ops dsps_ops = { 475 .init = dsps_musb_init, 476 .exit = dsps_musb_exit, 477 478 .enable = dsps_musb_enable, 479 .disable = dsps_musb_disable, 480 481 .try_idle = dsps_musb_try_idle, 482}; 483 484static u64 musb_dmamask = DMA_BIT_MASK(32); 485 486static int dsps_create_musb_pdev(struct dsps_glue *glue, u8 id) 487{ 488 struct device *dev = glue->dev; 489 struct platform_device *pdev = to_platform_device(dev); 490 struct musb_hdrc_platform_data *pdata = dev->platform_data; 491 struct device_node *np = pdev->dev.of_node; 492 struct musb_hdrc_config *config; 493 struct platform_device *musb; 494 struct resource *res; 495 struct resource resources[2]; 496 char res_name[11]; 497 int ret; 498 499 resources[0].start = dsps_control_module_phys[id]; 500 resources[0].end = resources[0].start + SZ_4 - 1; 501 resources[0].flags = IORESOURCE_MEM; 502 503 glue->usb_ctrl[id] = devm_request_and_ioremap(&pdev->dev, resources); 504 if (glue->usb_ctrl[id] == NULL) { 505 dev_err(dev, "Failed to obtain usb_ctrl%d memory\n", id); 506 ret = -ENODEV; 507 goto err0; 508 } 509 510 /* first resource is for usbss, so start index from 1 */ 511 res = platform_get_resource(pdev, IORESOURCE_MEM, id + 1); 512 if (!res) { 513 dev_err(dev, "failed to get memory for instance %d\n", id); 514 ret = -ENODEV; 515 goto err0; 516 } 517 res->parent = NULL; 518 resources[0] = *res; 519 520 /* first resource is for usbss, so start index from 1 */ 521 res = platform_get_resource(pdev, IORESOURCE_IRQ, id + 1); 522 if (!res) { 523 dev_err(dev, "failed to get irq for instance %d\n", id); 524 ret = -ENODEV; 525 goto err0; 526 } 527 res->parent = NULL; 528 resources[1] = *res; 529 resources[1].name = "mc"; 530 531 /* allocate the child platform device */ 532 musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO); 533 if (!musb) { 534 dev_err(dev, "failed to allocate musb device\n"); 535 ret = -ENOMEM; 536 goto err0; 537 } 538 539 musb->dev.parent = dev; 540 musb->dev.dma_mask = &musb_dmamask; 541 musb->dev.coherent_dma_mask = musb_dmamask; 542 543 glue->musb[id] = musb; 544 545 ret = platform_device_add_resources(musb, resources, 2); 546 if (ret) { 547 dev_err(dev, "failed to add resources\n"); 548 goto err2; 549 } 550 551 if (np) { 552 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 553 if (!pdata) { 554 dev_err(&pdev->dev, 555 "failed to allocate musb platfrom data\n"); 556 ret = -ENOMEM; 557 goto err2; 558 } 559 560 config = devm_kzalloc(&pdev->dev, sizeof(*config), GFP_KERNEL); 561 if (!config) { 562 dev_err(&pdev->dev, 563 "failed to allocate musb hdrc config\n"); 564 goto err2; 565 } 566 567 of_property_read_u32(np, "num-eps", (u32 *)&config->num_eps); 568 of_property_read_u32(np, "ram-bits", (u32 *)&config->ram_bits); 569 snprintf(res_name, sizeof(res_name), "port%d-mode", id); 570 of_property_read_u32(np, res_name, (u32 *)&pdata->mode); 571 of_property_read_u32(np, "power", (u32 *)&pdata->power); 572 config->multipoint = of_property_read_bool(np, "multipoint"); 573 574 pdata->config = config; 575 } 576 577 pdata->platform_ops = &dsps_ops; 578 579 ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); 580 if (ret) { 581 dev_err(dev, "failed to add platform_data\n"); 582 goto err2; 583 } 584 585 ret = platform_device_add(musb); 586 if (ret) { 587 dev_err(dev, "failed to register musb device\n"); 588 goto err2; 589 } 590 591 return 0; 592 593err2: 594 platform_device_put(musb); 595err0: 596 return ret; 597} 598 599static int dsps_probe(struct platform_device *pdev) 600{ 601 struct device_node *np = pdev->dev.of_node; 602 const struct of_device_id *match; 603 const struct dsps_musb_wrapper *wrp; 604 struct dsps_glue *glue; 605 struct resource *iomem; 606 int ret, i; 607 608 match = of_match_node(musb_dsps_of_match, np); 609 if (!match) { 610 dev_err(&pdev->dev, "fail to get matching of_match struct\n"); 611 ret = -EINVAL; 612 goto err0; 613 } 614 wrp = match->data; 615 616 /* allocate glue */ 617 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 618 if (!glue) { 619 dev_err(&pdev->dev, "unable to allocate glue memory\n"); 620 ret = -ENOMEM; 621 goto err0; 622 } 623 624 /* get memory resource */ 625 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 626 if (!iomem) { 627 dev_err(&pdev->dev, "failed to get usbss mem resourse\n"); 628 ret = -ENODEV; 629 goto err1; 630 } 631 632 glue->dev = &pdev->dev; 633 634 glue->wrp = kmemdup(wrp, sizeof(*wrp), GFP_KERNEL); 635 if (!glue->wrp) { 636 dev_err(&pdev->dev, "failed to duplicate wrapper struct memory\n"); 637 ret = -ENOMEM; 638 goto err1; 639 } 640 platform_set_drvdata(pdev, glue); 641 642 /* enable the usbss clocks */ 643 pm_runtime_enable(&pdev->dev); 644 645 ret = pm_runtime_get_sync(&pdev->dev); 646 if (ret < 0) { 647 dev_err(&pdev->dev, "pm_runtime_get_sync FAILED"); 648 goto err2; 649 } 650 651 /* create the child platform device for all instances of musb */ 652 for (i = 0; i < wrp->instances ; i++) { 653 ret = dsps_create_musb_pdev(glue, i); 654 if (ret != 0) { 655 dev_err(&pdev->dev, "failed to create child pdev\n"); 656 /* release resources of previously created instances */ 657 for (i--; i >= 0 ; i--) 658 platform_device_unregister(glue->musb[i]); 659 goto err3; 660 } 661 } 662 663 return 0; 664 665err3: 666 pm_runtime_put(&pdev->dev); 667err2: 668 pm_runtime_disable(&pdev->dev); 669 kfree(glue->wrp); 670err1: 671 kfree(glue); 672err0: 673 return ret; 674} 675static int dsps_remove(struct platform_device *pdev) 676{ 677 struct dsps_glue *glue = platform_get_drvdata(pdev); 678 const struct dsps_musb_wrapper *wrp = glue->wrp; 679 int i; 680 681 /* delete the child platform device */ 682 for (i = 0; i < wrp->instances ; i++) 683 platform_device_unregister(glue->musb[i]); 684 685 /* disable usbss clocks */ 686 pm_runtime_put(&pdev->dev); 687 pm_runtime_disable(&pdev->dev); 688 kfree(glue->wrp); 689 kfree(glue); 690 return 0; 691} 692 693#ifdef CONFIG_PM_SLEEP 694static int dsps_suspend(struct device *dev) 695{ 696 struct platform_device *pdev = to_platform_device(dev->parent); 697 struct dsps_glue *glue = platform_get_drvdata(pdev); 698 const struct dsps_musb_wrapper *wrp = glue->wrp; 699 int i; 700 701 for (i = 0; i < wrp->instances; i++) 702 musb_dsps_phy_control(glue, i, 0); 703 704 return 0; 705} 706 707static int dsps_resume(struct device *dev) 708{ 709 struct platform_device *pdev = to_platform_device(dev->parent); 710 struct dsps_glue *glue = platform_get_drvdata(pdev); 711 const struct dsps_musb_wrapper *wrp = glue->wrp; 712 int i; 713 714 for (i = 0; i < wrp->instances; i++) 715 musb_dsps_phy_control(glue, i, 1); 716 717 return 0; 718} 719#endif 720 721static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume); 722 723static const struct dsps_musb_wrapper ti81xx_driver_data = { 724 .revision = 0x00, 725 .control = 0x14, 726 .status = 0x18, 727 .eoi = 0x24, 728 .epintr_set = 0x38, 729 .epintr_clear = 0x40, 730 .epintr_status = 0x30, 731 .coreintr_set = 0x3c, 732 .coreintr_clear = 0x44, 733 .coreintr_status = 0x34, 734 .phy_utmi = 0xe0, 735 .mode = 0xe8, 736 .reset = 0, 737 .otg_disable = 21, 738 .iddig = 8, 739 .usb_shift = 0, 740 .usb_mask = 0x1ff, 741 .usb_bitmap = (0x1ff << 0), 742 .drvvbus = 8, 743 .txep_shift = 0, 744 .txep_mask = 0xffff, 745 .txep_bitmap = (0xffff << 0), 746 .rxep_shift = 16, 747 .rxep_mask = 0xfffe, 748 .rxep_bitmap = (0xfffe << 16), 749 .musb_core_offset = 0x400, 750 .poll_seconds = 2, 751 .instances = 1, 752}; 753 754static const struct platform_device_id musb_dsps_id_table[] = { 755 { 756 .name = "musb-ti81xx", 757 .driver_data = (kernel_ulong_t) &ti81xx_driver_data, 758 }, 759 { }, /* Terminating Entry */ 760}; 761MODULE_DEVICE_TABLE(platform, musb_dsps_id_table); 762 763#ifdef CONFIG_OF 764static const struct of_device_id musb_dsps_of_match[] = { 765 { .compatible = "ti,musb-am33xx", 766 .data = (void *) &ti81xx_driver_data, }, 767 { }, 768}; 769MODULE_DEVICE_TABLE(of, musb_dsps_of_match); 770#endif 771 772static struct platform_driver dsps_usbss_driver = { 773 .probe = dsps_probe, 774 .remove = dsps_remove, 775 .driver = { 776 .name = "musb-dsps", 777 .pm = &dsps_pm_ops, 778 .of_match_table = of_match_ptr(musb_dsps_of_match), 779 }, 780 .id_table = musb_dsps_id_table, 781}; 782 783MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer"); 784MODULE_AUTHOR("Ravi B <ravibabu@ti.com>"); 785MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); 786MODULE_LICENSE("GPL v2"); 787 788static int __init dsps_init(void) 789{ 790 return platform_driver_register(&dsps_usbss_driver); 791} 792subsys_initcall(dsps_init); 793 794static void __exit dsps_exit(void) 795{ 796 platform_driver_unregister(&dsps_usbss_driver); 797} 798module_exit(dsps_exit); 799