musb_host.c revision 74bb35083d889c696a0f54be76ffe85a66dcbdc1
1/* 2 * MUSB OTG driver host support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35#include <linux/module.h> 36#include <linux/kernel.h> 37#include <linux/delay.h> 38#include <linux/sched.h> 39#include <linux/slab.h> 40#include <linux/errno.h> 41#include <linux/init.h> 42#include <linux/list.h> 43 44#include "musb_core.h" 45#include "musb_host.h" 46 47 48/* MUSB HOST status 22-mar-2006 49 * 50 * - There's still lots of partial code duplication for fault paths, so 51 * they aren't handled as consistently as they need to be. 52 * 53 * - PIO mostly behaved when last tested. 54 * + including ep0, with all usbtest cases 9, 10 55 * + usbtest 14 (ep0out) doesn't seem to run at all 56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest 57 * configurations, but otherwise double buffering passes basic tests. 58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework. 59 * 60 * - DMA (CPPI) ... partially behaves, not currently recommended 61 * + about 1/15 the speed of typical EHCI implementations (PCI) 62 * + RX, all too often reqpkt seems to misbehave after tx 63 * + TX, no known issues (other than evident silicon issue) 64 * 65 * - DMA (Mentor/OMAP) ...has at least toggle update problems 66 * 67 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet 68 * starvation ... nothing yet for TX, interrupt, or bulk. 69 * 70 * - Not tested with HNP, but some SRP paths seem to behave. 71 * 72 * NOTE 24-August-2006: 73 * 74 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an 75 * extra endpoint for periodic use enabling hub + keybd + mouse. That 76 * mostly works, except that with "usbnet" it's easy to trigger cases 77 * with "ping" where RX loses. (a) ping to davinci, even "ping -f", 78 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses 79 * although ARP RX wins. (That test was done with a full speed link.) 80 */ 81 82 83/* 84 * NOTE on endpoint usage: 85 * 86 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN 87 * and OUT endpoints ... hardware is dedicated for those "async" queue(s). 88 * (Yes, bulk _could_ use more of the endpoints than that, and would even 89 * benefit from it.) 90 * 91 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. 92 * So far that scheduling is both dumb and optimistic: the endpoint will be 93 * "claimed" until its software queue is no longer refilled. No multiplexing 94 * of transfers between endpoints, or anything clever. 95 */ 96 97 98static void musb_ep_program(struct musb *musb, u8 epnum, 99 struct urb *urb, unsigned int nOut, 100 u8 *buf, u32 len); 101 102/* 103 * Clear TX fifo. Needed to avoid BABBLE errors. 104 */ 105static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 106{ 107 void __iomem *epio = ep->regs; 108 u16 csr; 109 u16 lastcsr = 0; 110 int retries = 1000; 111 112 csr = musb_readw(epio, MUSB_TXCSR); 113 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 114 if (csr != lastcsr) 115 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr); 116 lastcsr = csr; 117 csr |= MUSB_TXCSR_FLUSHFIFO; 118 musb_writew(epio, MUSB_TXCSR, csr); 119 csr = musb_readw(epio, MUSB_TXCSR); 120 if (WARN(retries-- < 1, 121 "Could not flush host TX%d fifo: csr: %04x\n", 122 ep->epnum, csr)) 123 return; 124 mdelay(1); 125 } 126} 127 128/* 129 * Start transmit. Caller is responsible for locking shared resources. 130 * musb must be locked. 131 */ 132static inline void musb_h_tx_start(struct musb_hw_ep *ep) 133{ 134 u16 txcsr; 135 136 /* NOTE: no locks here; caller should lock and select EP */ 137 if (ep->epnum) { 138 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 139 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; 140 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 141 } else { 142 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; 143 musb_writew(ep->regs, MUSB_CSR0, txcsr); 144 } 145 146} 147 148static inline void cppi_host_txdma_start(struct musb_hw_ep *ep) 149{ 150 u16 txcsr; 151 152 /* NOTE: no locks here; caller should lock and select EP */ 153 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 154 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; 155 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 156} 157 158/* 159 * Start the URB at the front of an endpoint's queue 160 * end must be claimed from the caller. 161 * 162 * Context: controller locked, irqs blocked 163 */ 164static void 165musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) 166{ 167 u16 frame; 168 u32 len; 169 void *buf; 170 void __iomem *mbase = musb->mregs; 171 struct urb *urb = next_urb(qh); 172 struct musb_hw_ep *hw_ep = qh->hw_ep; 173 unsigned pipe = urb->pipe; 174 u8 address = usb_pipedevice(pipe); 175 int epnum = hw_ep->epnum; 176 177 /* initialize software qh state */ 178 qh->offset = 0; 179 qh->segsize = 0; 180 181 /* gather right source of data */ 182 switch (qh->type) { 183 case USB_ENDPOINT_XFER_CONTROL: 184 /* control transfers always start with SETUP */ 185 is_in = 0; 186 hw_ep->out_qh = qh; 187 musb->ep0_stage = MUSB_EP0_START; 188 buf = urb->setup_packet; 189 len = 8; 190 break; 191 case USB_ENDPOINT_XFER_ISOC: 192 qh->iso_idx = 0; 193 qh->frame = 0; 194 buf = urb->transfer_buffer + urb->iso_frame_desc[0].offset; 195 len = urb->iso_frame_desc[0].length; 196 break; 197 default: /* bulk, interrupt */ 198 /* actual_length may be nonzero on retry paths */ 199 buf = urb->transfer_buffer + urb->actual_length; 200 len = urb->transfer_buffer_length - urb->actual_length; 201 } 202 203 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", 204 qh, urb, address, qh->epnum, 205 is_in ? "in" : "out", 206 ({char *s; switch (qh->type) { 207 case USB_ENDPOINT_XFER_CONTROL: s = ""; break; 208 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; 209 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; 210 default: s = "-intr"; break; 211 }; s; }), 212 epnum, buf, len); 213 214 /* Configure endpoint */ 215 if (is_in || hw_ep->is_shared_fifo) 216 hw_ep->in_qh = qh; 217 else 218 hw_ep->out_qh = qh; 219 musb_ep_program(musb, epnum, urb, !is_in, buf, len); 220 221 /* transmit may have more work: start it when it is time */ 222 if (is_in) 223 return; 224 225 /* determine if the time is right for a periodic transfer */ 226 switch (qh->type) { 227 case USB_ENDPOINT_XFER_ISOC: 228 case USB_ENDPOINT_XFER_INT: 229 DBG(3, "check whether there's still time for periodic Tx\n"); 230 qh->iso_idx = 0; 231 frame = musb_readw(mbase, MUSB_FRAME); 232 /* FIXME this doesn't implement that scheduling policy ... 233 * or handle framecounter wrapping 234 */ 235 if ((urb->transfer_flags & URB_ISO_ASAP) 236 || (frame >= urb->start_frame)) { 237 /* REVISIT the SOF irq handler shouldn't duplicate 238 * this code; and we don't init urb->start_frame... 239 */ 240 qh->frame = 0; 241 goto start; 242 } else { 243 qh->frame = urb->start_frame; 244 /* enable SOF interrupt so we can count down */ 245 DBG(1, "SOF for %d\n", epnum); 246#if 1 /* ifndef CONFIG_ARCH_DAVINCI */ 247 musb_writeb(mbase, MUSB_INTRUSBE, 0xff); 248#endif 249 } 250 break; 251 default: 252start: 253 DBG(4, "Start TX%d %s\n", epnum, 254 hw_ep->tx_channel ? "dma" : "pio"); 255 256 if (!hw_ep->tx_channel) 257 musb_h_tx_start(hw_ep); 258 else if (is_cppi_enabled() || tusb_dma_omap()) 259 cppi_host_txdma_start(hw_ep); 260 } 261} 262 263/* caller owns controller lock, irqs are blocked */ 264static void 265__musb_giveback(struct musb *musb, struct urb *urb, int status) 266__releases(musb->lock) 267__acquires(musb->lock) 268{ 269 DBG(({ int level; switch (status) { 270 case 0: 271 level = 4; 272 break; 273 /* common/boring faults */ 274 case -EREMOTEIO: 275 case -ESHUTDOWN: 276 case -ECONNRESET: 277 case -EPIPE: 278 level = 3; 279 break; 280 default: 281 level = 2; 282 break; 283 }; level; }), 284 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", 285 urb, urb->complete, status, 286 usb_pipedevice(urb->pipe), 287 usb_pipeendpoint(urb->pipe), 288 usb_pipein(urb->pipe) ? "in" : "out", 289 urb->actual_length, urb->transfer_buffer_length 290 ); 291 292 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb); 293 spin_unlock(&musb->lock); 294 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status); 295 spin_lock(&musb->lock); 296} 297 298/* for bulk/interrupt endpoints only */ 299static inline void 300musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb) 301{ 302 struct usb_device *udev = urb->dev; 303 u16 csr; 304 void __iomem *epio = ep->regs; 305 struct musb_qh *qh; 306 307 /* FIXME: the current Mentor DMA code seems to have 308 * problems getting toggle correct. 309 */ 310 311 if (is_in || ep->is_shared_fifo) 312 qh = ep->in_qh; 313 else 314 qh = ep->out_qh; 315 316 if (!is_in) { 317 csr = musb_readw(epio, MUSB_TXCSR); 318 usb_settoggle(udev, qh->epnum, 1, 319 (csr & MUSB_TXCSR_H_DATATOGGLE) 320 ? 1 : 0); 321 } else { 322 csr = musb_readw(epio, MUSB_RXCSR); 323 usb_settoggle(udev, qh->epnum, 0, 324 (csr & MUSB_RXCSR_H_DATATOGGLE) 325 ? 1 : 0); 326 } 327} 328 329/* caller owns controller lock, irqs are blocked */ 330static struct musb_qh * 331musb_giveback(struct musb_qh *qh, struct urb *urb, int status) 332{ 333 struct musb_hw_ep *ep = qh->hw_ep; 334 struct musb *musb = ep->musb; 335 int is_in = usb_pipein(urb->pipe); 336 int ready = qh->is_ready; 337 338 /* save toggle eagerly, for paranoia */ 339 switch (qh->type) { 340 case USB_ENDPOINT_XFER_BULK: 341 case USB_ENDPOINT_XFER_INT: 342 musb_save_toggle(ep, is_in, urb); 343 break; 344 case USB_ENDPOINT_XFER_ISOC: 345 if (status == 0 && urb->error_count) 346 status = -EXDEV; 347 break; 348 } 349 350 qh->is_ready = 0; 351 __musb_giveback(musb, urb, status); 352 qh->is_ready = ready; 353 354 /* reclaim resources (and bandwidth) ASAP; deschedule it, and 355 * invalidate qh as soon as list_empty(&hep->urb_list) 356 */ 357 if (list_empty(&qh->hep->urb_list)) { 358 struct list_head *head; 359 360 if (is_in) 361 ep->rx_reinit = 1; 362 else 363 ep->tx_reinit = 1; 364 365 /* clobber old pointers to this qh */ 366 if (is_in || ep->is_shared_fifo) 367 ep->in_qh = NULL; 368 else 369 ep->out_qh = NULL; 370 qh->hep->hcpriv = NULL; 371 372 switch (qh->type) { 373 374 case USB_ENDPOINT_XFER_CONTROL: 375 case USB_ENDPOINT_XFER_BULK: 376 /* fifo policy for these lists, except that NAKing 377 * should rotate a qh to the end (for fairness). 378 */ 379 if (qh->mux == 1) { 380 head = qh->ring.prev; 381 list_del(&qh->ring); 382 kfree(qh); 383 qh = first_qh(head); 384 break; 385 } 386 387 case USB_ENDPOINT_XFER_ISOC: 388 case USB_ENDPOINT_XFER_INT: 389 /* this is where periodic bandwidth should be 390 * de-allocated if it's tracked and allocated; 391 * and where we'd update the schedule tree... 392 */ 393 kfree(qh); 394 qh = NULL; 395 break; 396 } 397 } 398 return qh; 399} 400 401/* 402 * Advance this hardware endpoint's queue, completing the specified urb and 403 * advancing to either the next urb queued to that qh, or else invalidating 404 * that qh and advancing to the next qh scheduled after the current one. 405 * 406 * Context: caller owns controller lock, irqs are blocked 407 */ 408static void 409musb_advance_schedule(struct musb *musb, struct urb *urb, 410 struct musb_hw_ep *hw_ep, int is_in) 411{ 412 struct musb_qh *qh; 413 414 if (is_in || hw_ep->is_shared_fifo) 415 qh = hw_ep->in_qh; 416 else 417 qh = hw_ep->out_qh; 418 419 if (urb->status == -EINPROGRESS) 420 qh = musb_giveback(qh, urb, 0); 421 else 422 qh = musb_giveback(qh, urb, urb->status); 423 424 if (qh != NULL && qh->is_ready) { 425 DBG(4, "... next ep%d %cX urb %p\n", 426 hw_ep->epnum, is_in ? 'R' : 'T', 427 next_urb(qh)); 428 musb_start_urb(musb, is_in, qh); 429 } 430} 431 432static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) 433{ 434 /* we don't want fifo to fill itself again; 435 * ignore dma (various models), 436 * leave toggle alone (may not have been saved yet) 437 */ 438 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; 439 csr &= ~(MUSB_RXCSR_H_REQPKT 440 | MUSB_RXCSR_H_AUTOREQ 441 | MUSB_RXCSR_AUTOCLEAR); 442 443 /* write 2x to allow double buffering */ 444 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 445 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 446 447 /* flush writebuffer */ 448 return musb_readw(hw_ep->regs, MUSB_RXCSR); 449} 450 451/* 452 * PIO RX for a packet (or part of it). 453 */ 454static bool 455musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) 456{ 457 u16 rx_count; 458 u8 *buf; 459 u16 csr; 460 bool done = false; 461 u32 length; 462 int do_flush = 0; 463 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 464 void __iomem *epio = hw_ep->regs; 465 struct musb_qh *qh = hw_ep->in_qh; 466 int pipe = urb->pipe; 467 void *buffer = urb->transfer_buffer; 468 469 /* musb_ep_select(mbase, epnum); */ 470 rx_count = musb_readw(epio, MUSB_RXCOUNT); 471 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, 472 urb->transfer_buffer, qh->offset, 473 urb->transfer_buffer_length); 474 475 /* unload FIFO */ 476 if (usb_pipeisoc(pipe)) { 477 int status = 0; 478 struct usb_iso_packet_descriptor *d; 479 480 if (iso_err) { 481 status = -EILSEQ; 482 urb->error_count++; 483 } 484 485 d = urb->iso_frame_desc + qh->iso_idx; 486 buf = buffer + d->offset; 487 length = d->length; 488 if (rx_count > length) { 489 if (status == 0) { 490 status = -EOVERFLOW; 491 urb->error_count++; 492 } 493 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); 494 do_flush = 1; 495 } else 496 length = rx_count; 497 urb->actual_length += length; 498 d->actual_length = length; 499 500 d->status = status; 501 502 /* see if we are done */ 503 done = (++qh->iso_idx >= urb->number_of_packets); 504 } else { 505 /* non-isoch */ 506 buf = buffer + qh->offset; 507 length = urb->transfer_buffer_length - qh->offset; 508 if (rx_count > length) { 509 if (urb->status == -EINPROGRESS) 510 urb->status = -EOVERFLOW; 511 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); 512 do_flush = 1; 513 } else 514 length = rx_count; 515 urb->actual_length += length; 516 qh->offset += length; 517 518 /* see if we are done */ 519 done = (urb->actual_length == urb->transfer_buffer_length) 520 || (rx_count < qh->maxpacket) 521 || (urb->status != -EINPROGRESS); 522 if (done 523 && (urb->status == -EINPROGRESS) 524 && (urb->transfer_flags & URB_SHORT_NOT_OK) 525 && (urb->actual_length 526 < urb->transfer_buffer_length)) 527 urb->status = -EREMOTEIO; 528 } 529 530 musb_read_fifo(hw_ep, length, buf); 531 532 csr = musb_readw(epio, MUSB_RXCSR); 533 csr |= MUSB_RXCSR_H_WZC_BITS; 534 if (unlikely(do_flush)) 535 musb_h_flush_rxfifo(hw_ep, csr); 536 else { 537 /* REVISIT this assumes AUTOCLEAR is never set */ 538 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); 539 if (!done) 540 csr |= MUSB_RXCSR_H_REQPKT; 541 musb_writew(epio, MUSB_RXCSR, csr); 542 } 543 544 return done; 545} 546 547/* we don't always need to reinit a given side of an endpoint... 548 * when we do, use tx/rx reinit routine and then construct a new CSR 549 * to address data toggle, NYET, and DMA or PIO. 550 * 551 * it's possible that driver bugs (especially for DMA) or aborting a 552 * transfer might have left the endpoint busier than it should be. 553 * the busy/not-empty tests are basically paranoia. 554 */ 555static void 556musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) 557{ 558 u16 csr; 559 560 /* NOTE: we know the "rx" fifo reinit never triggers for ep0. 561 * That always uses tx_reinit since ep0 repurposes TX register 562 * offsets; the initial SETUP packet is also a kind of OUT. 563 */ 564 565 /* if programmed for Tx, put it in RX mode */ 566 if (ep->is_shared_fifo) { 567 csr = musb_readw(ep->regs, MUSB_TXCSR); 568 if (csr & MUSB_TXCSR_MODE) { 569 musb_h_tx_flush_fifo(ep); 570 musb_writew(ep->regs, MUSB_TXCSR, 571 MUSB_TXCSR_FRCDATATOG); 572 } 573 /* clear mode (and everything else) to enable Rx */ 574 musb_writew(ep->regs, MUSB_TXCSR, 0); 575 576 /* scrub all previous state, clearing toggle */ 577 } else { 578 csr = musb_readw(ep->regs, MUSB_RXCSR); 579 if (csr & MUSB_RXCSR_RXPKTRDY) 580 WARNING("rx%d, packet/%d ready?\n", ep->epnum, 581 musb_readw(ep->regs, MUSB_RXCOUNT)); 582 583 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); 584 } 585 586 /* target addr and (for multipoint) hub addr/port */ 587 if (musb->is_multipoint) { 588 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); 589 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); 590 musb_write_rxhubport(ep->target_regs, qh->h_port_reg); 591 592 } else 593 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); 594 595 /* protocol/endpoint, interval/NAKlimit, i/o size */ 596 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); 597 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); 598 /* NOTE: bulk combining rewrites high bits of maxpacket */ 599 musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket); 600 601 ep->rx_reinit = 0; 602} 603 604 605/* 606 * Program an HDRC endpoint as per the given URB 607 * Context: irqs blocked, controller lock held 608 */ 609static void musb_ep_program(struct musb *musb, u8 epnum, 610 struct urb *urb, unsigned int is_out, 611 u8 *buf, u32 len) 612{ 613 struct dma_controller *dma_controller; 614 struct dma_channel *dma_channel; 615 u8 dma_ok; 616 void __iomem *mbase = musb->mregs; 617 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 618 void __iomem *epio = hw_ep->regs; 619 struct musb_qh *qh; 620 u16 packet_sz; 621 622 if (!is_out || hw_ep->is_shared_fifo) 623 qh = hw_ep->in_qh; 624 else 625 qh = hw_ep->out_qh; 626 627 packet_sz = qh->maxpacket; 628 629 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s " 630 "h_addr%02x h_port%02x bytes %d\n", 631 is_out ? "-->" : "<--", 632 epnum, urb, urb->dev->speed, 633 qh->addr_reg, qh->epnum, is_out ? "out" : "in", 634 qh->h_addr_reg, qh->h_port_reg, 635 len); 636 637 musb_ep_select(mbase, epnum); 638 639 /* candidate for DMA? */ 640 dma_controller = musb->dma_controller; 641 if (is_dma_capable() && epnum && dma_controller) { 642 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; 643 if (!dma_channel) { 644 dma_channel = dma_controller->channel_alloc( 645 dma_controller, hw_ep, is_out); 646 if (is_out) 647 hw_ep->tx_channel = dma_channel; 648 else 649 hw_ep->rx_channel = dma_channel; 650 } 651 } else 652 dma_channel = NULL; 653 654 /* make sure we clear DMAEnab, autoSet bits from previous run */ 655 656 /* OUT/transmit/EP0 or IN/receive? */ 657 if (is_out) { 658 u16 csr; 659 u16 int_txe; 660 u16 load_count; 661 662 csr = musb_readw(epio, MUSB_TXCSR); 663 664 /* disable interrupt in case we flush */ 665 int_txe = musb_readw(mbase, MUSB_INTRTXE); 666 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 667 668 /* general endpoint setup */ 669 if (epnum) { 670 /* ASSERT: TXCSR_DMAENAB was already cleared */ 671 672 /* flush all old state, set default */ 673 musb_h_tx_flush_fifo(hw_ep); 674 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT 675 | MUSB_TXCSR_DMAMODE 676 | MUSB_TXCSR_FRCDATATOG 677 | MUSB_TXCSR_H_RXSTALL 678 | MUSB_TXCSR_H_ERROR 679 | MUSB_TXCSR_TXPKTRDY 680 ); 681 csr |= MUSB_TXCSR_MODE; 682 683 if (usb_gettoggle(urb->dev, 684 qh->epnum, 1)) 685 csr |= MUSB_TXCSR_H_WR_DATATOGGLE 686 | MUSB_TXCSR_H_DATATOGGLE; 687 else 688 csr |= MUSB_TXCSR_CLRDATATOG; 689 690 /* twice in case of double packet buffering */ 691 musb_writew(epio, MUSB_TXCSR, csr); 692 /* REVISIT may need to clear FLUSHFIFO ... */ 693 musb_writew(epio, MUSB_TXCSR, csr); 694 csr = musb_readw(epio, MUSB_TXCSR); 695 } else { 696 /* endpoint 0: just flush */ 697 musb_writew(epio, MUSB_CSR0, 698 csr | MUSB_CSR0_FLUSHFIFO); 699 musb_writew(epio, MUSB_CSR0, 700 csr | MUSB_CSR0_FLUSHFIFO); 701 } 702 703 /* target addr and (for multipoint) hub addr/port */ 704 if (musb->is_multipoint) { 705 musb_write_txfunaddr(mbase, epnum, qh->addr_reg); 706 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); 707 musb_write_txhubport(mbase, epnum, qh->h_port_reg); 708/* FIXME if !epnum, do the same for RX ... */ 709 } else 710 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); 711 712 /* protocol/endpoint/interval/NAKlimit */ 713 if (epnum) { 714 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); 715 if (can_bulk_split(musb, qh->type)) 716 musb_writew(epio, MUSB_TXMAXP, 717 packet_sz 718 | ((hw_ep->max_packet_sz_tx / 719 packet_sz) - 1) << 11); 720 else 721 musb_writew(epio, MUSB_TXMAXP, 722 packet_sz); 723 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); 724 } else { 725 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); 726 if (musb->is_multipoint) 727 musb_writeb(epio, MUSB_TYPE0, 728 qh->type_reg); 729 } 730 731 if (can_bulk_split(musb, qh->type)) 732 load_count = min((u32) hw_ep->max_packet_sz_tx, 733 len); 734 else 735 load_count = min((u32) packet_sz, len); 736 737#ifdef CONFIG_USB_INVENTRA_DMA 738 if (dma_channel) { 739 740 /* clear previous state */ 741 csr = musb_readw(epio, MUSB_TXCSR); 742 csr &= ~(MUSB_TXCSR_AUTOSET 743 | MUSB_TXCSR_DMAMODE 744 | MUSB_TXCSR_DMAENAB); 745 csr |= MUSB_TXCSR_MODE; 746 musb_writew(epio, MUSB_TXCSR, 747 csr | MUSB_TXCSR_MODE); 748 749 qh->segsize = min(len, dma_channel->max_len); 750 751 if (qh->segsize <= packet_sz) 752 dma_channel->desired_mode = 0; 753 else 754 dma_channel->desired_mode = 1; 755 756 757 if (dma_channel->desired_mode == 0) { 758 csr &= ~(MUSB_TXCSR_AUTOSET 759 | MUSB_TXCSR_DMAMODE); 760 csr |= (MUSB_TXCSR_DMAENAB); 761 /* against programming guide */ 762 } else 763 csr |= (MUSB_TXCSR_AUTOSET 764 | MUSB_TXCSR_DMAENAB 765 | MUSB_TXCSR_DMAMODE); 766 767 musb_writew(epio, MUSB_TXCSR, csr); 768 769 dma_ok = dma_controller->channel_program( 770 dma_channel, packet_sz, 771 dma_channel->desired_mode, 772 urb->transfer_dma, 773 qh->segsize); 774 if (dma_ok) { 775 load_count = 0; 776 } else { 777 dma_controller->channel_release(dma_channel); 778 if (is_out) 779 hw_ep->tx_channel = NULL; 780 else 781 hw_ep->rx_channel = NULL; 782 dma_channel = NULL; 783 } 784 } 785#endif 786 787 /* candidate for DMA */ 788 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { 789 790 /* program endpoint CSRs first, then setup DMA. 791 * assume CPPI setup succeeds. 792 * defer enabling dma. 793 */ 794 csr = musb_readw(epio, MUSB_TXCSR); 795 csr &= ~(MUSB_TXCSR_AUTOSET 796 | MUSB_TXCSR_DMAMODE 797 | MUSB_TXCSR_DMAENAB); 798 csr |= MUSB_TXCSR_MODE; 799 musb_writew(epio, MUSB_TXCSR, 800 csr | MUSB_TXCSR_MODE); 801 802 dma_channel->actual_len = 0L; 803 qh->segsize = len; 804 805 /* TX uses "rndis" mode automatically, but needs help 806 * to identify the zero-length-final-packet case. 807 */ 808 dma_ok = dma_controller->channel_program( 809 dma_channel, packet_sz, 810 (urb->transfer_flags 811 & URB_ZERO_PACKET) 812 == URB_ZERO_PACKET, 813 urb->transfer_dma, 814 qh->segsize); 815 if (dma_ok) { 816 load_count = 0; 817 } else { 818 dma_controller->channel_release(dma_channel); 819 hw_ep->tx_channel = NULL; 820 dma_channel = NULL; 821 822 /* REVISIT there's an error path here that 823 * needs handling: can't do dma, but 824 * there's no pio buffer address... 825 */ 826 } 827 } 828 829 if (load_count) { 830 /* ASSERT: TXCSR_DMAENAB was already cleared */ 831 832 /* PIO to load FIFO */ 833 qh->segsize = load_count; 834 musb_write_fifo(hw_ep, load_count, buf); 835 csr = musb_readw(epio, MUSB_TXCSR); 836 csr &= ~(MUSB_TXCSR_DMAENAB 837 | MUSB_TXCSR_DMAMODE 838 | MUSB_TXCSR_AUTOSET); 839 /* write CSR */ 840 csr |= MUSB_TXCSR_MODE; 841 842 if (epnum) 843 musb_writew(epio, MUSB_TXCSR, csr); 844 } 845 846 /* re-enable interrupt */ 847 musb_writew(mbase, MUSB_INTRTXE, int_txe); 848 849 /* IN/receive */ 850 } else { 851 u16 csr; 852 853 if (hw_ep->rx_reinit) { 854 musb_rx_reinit(musb, qh, hw_ep); 855 856 /* init new state: toggle and NYET, maybe DMA later */ 857 if (usb_gettoggle(urb->dev, qh->epnum, 0)) 858 csr = MUSB_RXCSR_H_WR_DATATOGGLE 859 | MUSB_RXCSR_H_DATATOGGLE; 860 else 861 csr = 0; 862 if (qh->type == USB_ENDPOINT_XFER_INT) 863 csr |= MUSB_RXCSR_DISNYET; 864 865 } else { 866 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 867 868 if (csr & (MUSB_RXCSR_RXPKTRDY 869 | MUSB_RXCSR_DMAENAB 870 | MUSB_RXCSR_H_REQPKT)) 871 ERR("broken !rx_reinit, ep%d csr %04x\n", 872 hw_ep->epnum, csr); 873 874 /* scrub any stale state, leaving toggle alone */ 875 csr &= MUSB_RXCSR_DISNYET; 876 } 877 878 /* kick things off */ 879 880 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { 881 /* candidate for DMA */ 882 if (dma_channel) { 883 dma_channel->actual_len = 0L; 884 qh->segsize = len; 885 886 /* AUTOREQ is in a DMA register */ 887 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 888 csr = musb_readw(hw_ep->regs, 889 MUSB_RXCSR); 890 891 /* unless caller treats short rx transfers as 892 * errors, we dare not queue multiple transfers. 893 */ 894 dma_ok = dma_controller->channel_program( 895 dma_channel, packet_sz, 896 !(urb->transfer_flags 897 & URB_SHORT_NOT_OK), 898 urb->transfer_dma, 899 qh->segsize); 900 if (!dma_ok) { 901 dma_controller->channel_release( 902 dma_channel); 903 hw_ep->rx_channel = NULL; 904 dma_channel = NULL; 905 } else 906 csr |= MUSB_RXCSR_DMAENAB; 907 } 908 } 909 910 csr |= MUSB_RXCSR_H_REQPKT; 911 DBG(7, "RXCSR%d := %04x\n", epnum, csr); 912 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 913 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 914 } 915} 916 917 918/* 919 * Service the default endpoint (ep0) as host. 920 * Return true until it's time to start the status stage. 921 */ 922static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) 923{ 924 bool more = false; 925 u8 *fifo_dest = NULL; 926 u16 fifo_count = 0; 927 struct musb_hw_ep *hw_ep = musb->control_ep; 928 struct musb_qh *qh = hw_ep->in_qh; 929 struct usb_ctrlrequest *request; 930 931 switch (musb->ep0_stage) { 932 case MUSB_EP0_IN: 933 fifo_dest = urb->transfer_buffer + urb->actual_length; 934 fifo_count = min_t(size_t, len, urb->transfer_buffer_length - 935 urb->actual_length); 936 if (fifo_count < len) 937 urb->status = -EOVERFLOW; 938 939 musb_read_fifo(hw_ep, fifo_count, fifo_dest); 940 941 urb->actual_length += fifo_count; 942 if (len < qh->maxpacket) { 943 /* always terminate on short read; it's 944 * rarely reported as an error. 945 */ 946 } else if (urb->actual_length < 947 urb->transfer_buffer_length) 948 more = true; 949 break; 950 case MUSB_EP0_START: 951 request = (struct usb_ctrlrequest *) urb->setup_packet; 952 953 if (!request->wLength) { 954 DBG(4, "start no-DATA\n"); 955 break; 956 } else if (request->bRequestType & USB_DIR_IN) { 957 DBG(4, "start IN-DATA\n"); 958 musb->ep0_stage = MUSB_EP0_IN; 959 more = true; 960 break; 961 } else { 962 DBG(4, "start OUT-DATA\n"); 963 musb->ep0_stage = MUSB_EP0_OUT; 964 more = true; 965 } 966 /* FALLTHROUGH */ 967 case MUSB_EP0_OUT: 968 fifo_count = min_t(size_t, qh->maxpacket, 969 urb->transfer_buffer_length - 970 urb->actual_length); 971 if (fifo_count) { 972 fifo_dest = (u8 *) (urb->transfer_buffer 973 + urb->actual_length); 974 DBG(3, "Sending %d byte%s to ep0 fifo %p\n", 975 fifo_count, 976 (fifo_count == 1) ? "" : "s", 977 fifo_dest); 978 musb_write_fifo(hw_ep, fifo_count, fifo_dest); 979 980 urb->actual_length += fifo_count; 981 more = true; 982 } 983 break; 984 default: 985 ERR("bogus ep0 stage %d\n", musb->ep0_stage); 986 break; 987 } 988 989 return more; 990} 991 992/* 993 * Handle default endpoint interrupt as host. Only called in IRQ time 994 * from musb_interrupt(). 995 * 996 * called with controller irqlocked 997 */ 998irqreturn_t musb_h_ep0_irq(struct musb *musb) 999{ 1000 struct urb *urb; 1001 u16 csr, len; 1002 int status = 0; 1003 void __iomem *mbase = musb->mregs; 1004 struct musb_hw_ep *hw_ep = musb->control_ep; 1005 void __iomem *epio = hw_ep->regs; 1006 struct musb_qh *qh = hw_ep->in_qh; 1007 bool complete = false; 1008 irqreturn_t retval = IRQ_NONE; 1009 1010 /* ep0 only has one queue, "in" */ 1011 urb = next_urb(qh); 1012 1013 musb_ep_select(mbase, 0); 1014 csr = musb_readw(epio, MUSB_CSR0); 1015 len = (csr & MUSB_CSR0_RXPKTRDY) 1016 ? musb_readb(epio, MUSB_COUNT0) 1017 : 0; 1018 1019 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", 1020 csr, qh, len, urb, musb->ep0_stage); 1021 1022 /* if we just did status stage, we are done */ 1023 if (MUSB_EP0_STATUS == musb->ep0_stage) { 1024 retval = IRQ_HANDLED; 1025 complete = true; 1026 } 1027 1028 /* prepare status */ 1029 if (csr & MUSB_CSR0_H_RXSTALL) { 1030 DBG(6, "STALLING ENDPOINT\n"); 1031 status = -EPIPE; 1032 1033 } else if (csr & MUSB_CSR0_H_ERROR) { 1034 DBG(2, "no response, csr0 %04x\n", csr); 1035 status = -EPROTO; 1036 1037 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { 1038 DBG(2, "control NAK timeout\n"); 1039 1040 /* NOTE: this code path would be a good place to PAUSE a 1041 * control transfer, if another one is queued, so that 1042 * ep0 is more likely to stay busy. That's already done 1043 * for bulk RX transfers. 1044 * 1045 * if (qh->ring.next != &musb->control), then 1046 * we have a candidate... NAKing is *NOT* an error 1047 */ 1048 musb_writew(epio, MUSB_CSR0, 0); 1049 retval = IRQ_HANDLED; 1050 } 1051 1052 if (status) { 1053 DBG(6, "aborting\n"); 1054 retval = IRQ_HANDLED; 1055 if (urb) 1056 urb->status = status; 1057 complete = true; 1058 1059 /* use the proper sequence to abort the transfer */ 1060 if (csr & MUSB_CSR0_H_REQPKT) { 1061 csr &= ~MUSB_CSR0_H_REQPKT; 1062 musb_writew(epio, MUSB_CSR0, csr); 1063 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; 1064 musb_writew(epio, MUSB_CSR0, csr); 1065 } else { 1066 csr |= MUSB_CSR0_FLUSHFIFO; 1067 musb_writew(epio, MUSB_CSR0, csr); 1068 musb_writew(epio, MUSB_CSR0, csr); 1069 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; 1070 musb_writew(epio, MUSB_CSR0, csr); 1071 } 1072 1073 musb_writeb(epio, MUSB_NAKLIMIT0, 0); 1074 1075 /* clear it */ 1076 musb_writew(epio, MUSB_CSR0, 0); 1077 } 1078 1079 if (unlikely(!urb)) { 1080 /* stop endpoint since we have no place for its data, this 1081 * SHOULD NEVER HAPPEN! */ 1082 ERR("no URB for end 0\n"); 1083 1084 musb_writew(epio, MUSB_CSR0, MUSB_CSR0_FLUSHFIFO); 1085 musb_writew(epio, MUSB_CSR0, MUSB_CSR0_FLUSHFIFO); 1086 musb_writew(epio, MUSB_CSR0, 0); 1087 1088 goto done; 1089 } 1090 1091 if (!complete) { 1092 /* call common logic and prepare response */ 1093 if (musb_h_ep0_continue(musb, len, urb)) { 1094 /* more packets required */ 1095 csr = (MUSB_EP0_IN == musb->ep0_stage) 1096 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; 1097 } else { 1098 /* data transfer complete; perform status phase */ 1099 if (usb_pipeout(urb->pipe) 1100 || !urb->transfer_buffer_length) 1101 csr = MUSB_CSR0_H_STATUSPKT 1102 | MUSB_CSR0_H_REQPKT; 1103 else 1104 csr = MUSB_CSR0_H_STATUSPKT 1105 | MUSB_CSR0_TXPKTRDY; 1106 1107 /* flag status stage */ 1108 musb->ep0_stage = MUSB_EP0_STATUS; 1109 1110 DBG(5, "ep0 STATUS, csr %04x\n", csr); 1111 1112 } 1113 musb_writew(epio, MUSB_CSR0, csr); 1114 retval = IRQ_HANDLED; 1115 } else 1116 musb->ep0_stage = MUSB_EP0_IDLE; 1117 1118 /* call completion handler if done */ 1119 if (complete) 1120 musb_advance_schedule(musb, urb, hw_ep, 1); 1121done: 1122 return retval; 1123} 1124 1125 1126#ifdef CONFIG_USB_INVENTRA_DMA 1127 1128/* Host side TX (OUT) using Mentor DMA works as follows: 1129 submit_urb -> 1130 - if queue was empty, Program Endpoint 1131 - ... which starts DMA to fifo in mode 1 or 0 1132 1133 DMA Isr (transfer complete) -> TxAvail() 1134 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens 1135 only in musb_cleanup_urb) 1136 - TxPktRdy has to be set in mode 0 or for 1137 short packets in mode 1. 1138*/ 1139 1140#endif 1141 1142/* Service a Tx-Available or dma completion irq for the endpoint */ 1143void musb_host_tx(struct musb *musb, u8 epnum) 1144{ 1145 int pipe; 1146 bool done = false; 1147 u16 tx_csr; 1148 size_t wLength = 0; 1149 u8 *buf = NULL; 1150 struct urb *urb; 1151 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1152 void __iomem *epio = hw_ep->regs; 1153 struct musb_qh *qh = hw_ep->is_shared_fifo ? hw_ep->in_qh 1154 : hw_ep->out_qh; 1155 u32 status = 0; 1156 void __iomem *mbase = musb->mregs; 1157 struct dma_channel *dma; 1158 1159 urb = next_urb(qh); 1160 1161 musb_ep_select(mbase, epnum); 1162 tx_csr = musb_readw(epio, MUSB_TXCSR); 1163 1164 /* with CPPI, DMA sometimes triggers "extra" irqs */ 1165 if (!urb) { 1166 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1167 goto finish; 1168 } 1169 1170 pipe = urb->pipe; 1171 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; 1172 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, 1173 dma ? ", dma" : ""); 1174 1175 /* check for errors */ 1176 if (tx_csr & MUSB_TXCSR_H_RXSTALL) { 1177 /* dma was disabled, fifo flushed */ 1178 DBG(3, "TX end %d stall\n", epnum); 1179 1180 /* stall; record URB status */ 1181 status = -EPIPE; 1182 1183 } else if (tx_csr & MUSB_TXCSR_H_ERROR) { 1184 /* (NON-ISO) dma was disabled, fifo flushed */ 1185 DBG(3, "TX 3strikes on ep=%d\n", epnum); 1186 1187 status = -ETIMEDOUT; 1188 1189 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { 1190 DBG(6, "TX end=%d device not responding\n", epnum); 1191 1192 /* NOTE: this code path would be a good place to PAUSE a 1193 * transfer, if there's some other (nonperiodic) tx urb 1194 * that could use this fifo. (dma complicates it...) 1195 * That's already done for bulk RX transfers. 1196 * 1197 * if (bulk && qh->ring.next != &musb->out_bulk), then 1198 * we have a candidate... NAKing is *NOT* an error 1199 */ 1200 musb_ep_select(mbase, epnum); 1201 musb_writew(epio, MUSB_TXCSR, 1202 MUSB_TXCSR_H_WZC_BITS 1203 | MUSB_TXCSR_TXPKTRDY); 1204 goto finish; 1205 } 1206 1207 if (status) { 1208 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1209 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1210 (void) musb->dma_controller->channel_abort(dma); 1211 } 1212 1213 /* do the proper sequence to abort the transfer in the 1214 * usb core; the dma engine should already be stopped. 1215 */ 1216 musb_h_tx_flush_fifo(hw_ep); 1217 tx_csr &= ~(MUSB_TXCSR_AUTOSET 1218 | MUSB_TXCSR_DMAENAB 1219 | MUSB_TXCSR_H_ERROR 1220 | MUSB_TXCSR_H_RXSTALL 1221 | MUSB_TXCSR_H_NAKTIMEOUT 1222 ); 1223 1224 musb_ep_select(mbase, epnum); 1225 musb_writew(epio, MUSB_TXCSR, tx_csr); 1226 /* REVISIT may need to clear FLUSHFIFO ... */ 1227 musb_writew(epio, MUSB_TXCSR, tx_csr); 1228 musb_writeb(epio, MUSB_TXINTERVAL, 0); 1229 1230 done = true; 1231 } 1232 1233 /* second cppi case */ 1234 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1235 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1236 goto finish; 1237 1238 } 1239 1240 /* REVISIT this looks wrong... */ 1241 if (!status || dma || usb_pipeisoc(pipe)) { 1242 if (dma) 1243 wLength = dma->actual_len; 1244 else 1245 wLength = qh->segsize; 1246 qh->offset += wLength; 1247 1248 if (usb_pipeisoc(pipe)) { 1249 struct usb_iso_packet_descriptor *d; 1250 1251 d = urb->iso_frame_desc + qh->iso_idx; 1252 d->actual_length = qh->segsize; 1253 if (++qh->iso_idx >= urb->number_of_packets) { 1254 done = true; 1255 } else { 1256 d++; 1257 buf = urb->transfer_buffer + d->offset; 1258 wLength = d->length; 1259 } 1260 } else if (dma) { 1261 done = true; 1262 } else { 1263 /* see if we need to send more data, or ZLP */ 1264 if (qh->segsize < qh->maxpacket) 1265 done = true; 1266 else if (qh->offset == urb->transfer_buffer_length 1267 && !(urb->transfer_flags 1268 & URB_ZERO_PACKET)) 1269 done = true; 1270 if (!done) { 1271 buf = urb->transfer_buffer 1272 + qh->offset; 1273 wLength = urb->transfer_buffer_length 1274 - qh->offset; 1275 } 1276 } 1277 } 1278 1279 /* urb->status != -EINPROGRESS means request has been faulted, 1280 * so we must abort this transfer after cleanup 1281 */ 1282 if (urb->status != -EINPROGRESS) { 1283 done = true; 1284 if (status == 0) 1285 status = urb->status; 1286 } 1287 1288 if (done) { 1289 /* set status */ 1290 urb->status = status; 1291 urb->actual_length = qh->offset; 1292 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); 1293 1294 } else if (!(tx_csr & MUSB_TXCSR_DMAENAB)) { 1295 /* WARN_ON(!buf); */ 1296 1297 /* REVISIT: some docs say that when hw_ep->tx_double_buffered, 1298 * (and presumably, fifo is not half-full) we should write TWO 1299 * packets before updating TXCSR ... other docs disagree ... 1300 */ 1301 /* PIO: start next packet in this URB */ 1302 if (wLength > qh->maxpacket) 1303 wLength = qh->maxpacket; 1304 musb_write_fifo(hw_ep, wLength, buf); 1305 qh->segsize = wLength; 1306 1307 musb_ep_select(mbase, epnum); 1308 musb_writew(epio, MUSB_TXCSR, 1309 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); 1310 } else 1311 DBG(1, "not complete, but dma enabled?\n"); 1312 1313finish: 1314 return; 1315} 1316 1317 1318#ifdef CONFIG_USB_INVENTRA_DMA 1319 1320/* Host side RX (IN) using Mentor DMA works as follows: 1321 submit_urb -> 1322 - if queue was empty, ProgramEndpoint 1323 - first IN token is sent out (by setting ReqPkt) 1324 LinuxIsr -> RxReady() 1325 /\ => first packet is received 1326 | - Set in mode 0 (DmaEnab, ~ReqPkt) 1327 | -> DMA Isr (transfer complete) -> RxReady() 1328 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) 1329 | - if urb not complete, send next IN token (ReqPkt) 1330 | | else complete urb. 1331 | | 1332 --------------------------- 1333 * 1334 * Nuances of mode 1: 1335 * For short packets, no ack (+RxPktRdy) is sent automatically 1336 * (even if AutoClear is ON) 1337 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent 1338 * automatically => major problem, as collecting the next packet becomes 1339 * difficult. Hence mode 1 is not used. 1340 * 1341 * REVISIT 1342 * All we care about at this driver level is that 1343 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; 1344 * (b) termination conditions are: short RX, or buffer full; 1345 * (c) fault modes include 1346 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. 1347 * (and that endpoint's dma queue stops immediately) 1348 * - overflow (full, PLUS more bytes in the terminal packet) 1349 * 1350 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would 1351 * thus be a great candidate for using mode 1 ... for all but the 1352 * last packet of one URB's transfer. 1353 */ 1354 1355#endif 1356 1357/* Schedule next QH from musb->in_bulk and move the current qh to 1358 * the end; avoids starvation for other endpoints. 1359 */ 1360static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep) 1361{ 1362 struct dma_channel *dma; 1363 struct urb *urb; 1364 void __iomem *mbase = musb->mregs; 1365 void __iomem *epio = ep->regs; 1366 struct musb_qh *cur_qh, *next_qh; 1367 u16 rx_csr; 1368 1369 musb_ep_select(mbase, ep->epnum); 1370 dma = is_dma_capable() ? ep->rx_channel : NULL; 1371 1372 /* clear nak timeout bit */ 1373 rx_csr = musb_readw(epio, MUSB_RXCSR); 1374 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1375 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1376 musb_writew(epio, MUSB_RXCSR, rx_csr); 1377 1378 cur_qh = first_qh(&musb->in_bulk); 1379 if (cur_qh) { 1380 urb = next_urb(cur_qh); 1381 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1382 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1383 musb->dma_controller->channel_abort(dma); 1384 urb->actual_length += dma->actual_len; 1385 dma->actual_len = 0L; 1386 } 1387 musb_save_toggle(ep, 1, urb); 1388 1389 /* move cur_qh to end of queue */ 1390 list_move_tail(&cur_qh->ring, &musb->in_bulk); 1391 1392 /* get the next qh from musb->in_bulk */ 1393 next_qh = first_qh(&musb->in_bulk); 1394 1395 /* set rx_reinit and schedule the next qh */ 1396 ep->rx_reinit = 1; 1397 musb_start_urb(musb, 1, next_qh); 1398 } 1399} 1400 1401/* 1402 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, 1403 * and high-bandwidth IN transfer cases. 1404 */ 1405void musb_host_rx(struct musb *musb, u8 epnum) 1406{ 1407 struct urb *urb; 1408 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1409 void __iomem *epio = hw_ep->regs; 1410 struct musb_qh *qh = hw_ep->in_qh; 1411 size_t xfer_len; 1412 void __iomem *mbase = musb->mregs; 1413 int pipe; 1414 u16 rx_csr, val; 1415 bool iso_err = false; 1416 bool done = false; 1417 u32 status; 1418 struct dma_channel *dma; 1419 1420 musb_ep_select(mbase, epnum); 1421 1422 urb = next_urb(qh); 1423 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; 1424 status = 0; 1425 xfer_len = 0; 1426 1427 rx_csr = musb_readw(epio, MUSB_RXCSR); 1428 val = rx_csr; 1429 1430 if (unlikely(!urb)) { 1431 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least 1432 * usbtest #11 (unlinks) triggers it regularly, sometimes 1433 * with fifo full. (Only with DMA??) 1434 */ 1435 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, 1436 musb_readw(epio, MUSB_RXCOUNT)); 1437 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1438 return; 1439 } 1440 1441 pipe = urb->pipe; 1442 1443 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", 1444 epnum, rx_csr, urb->actual_length, 1445 dma ? dma->actual_len : 0); 1446 1447 /* check for errors, concurrent stall & unlink is not really 1448 * handled yet! */ 1449 if (rx_csr & MUSB_RXCSR_H_RXSTALL) { 1450 DBG(3, "RX end %d STALL\n", epnum); 1451 1452 /* stall; record URB status */ 1453 status = -EPIPE; 1454 1455 } else if (rx_csr & MUSB_RXCSR_H_ERROR) { 1456 DBG(3, "end %d RX proto error\n", epnum); 1457 1458 status = -EPROTO; 1459 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1460 1461 } else if (rx_csr & MUSB_RXCSR_DATAERROR) { 1462 1463 if (USB_ENDPOINT_XFER_ISOC != qh->type) { 1464 DBG(6, "RX end %d NAK timeout\n", epnum); 1465 1466 /* NOTE: NAKing is *NOT* an error, so we want to 1467 * continue. Except ... if there's a request for 1468 * another QH, use that instead of starving it. 1469 * 1470 * Devices like Ethernet and serial adapters keep 1471 * reads posted at all times, which will starve 1472 * other devices without this logic. 1473 */ 1474 if (usb_pipebulk(urb->pipe) 1475 && qh->mux == 1 1476 && !list_is_singular(&musb->in_bulk)) { 1477 musb_bulk_rx_nak_timeout(musb, hw_ep); 1478 return; 1479 } 1480 musb_ep_select(mbase, epnum); 1481 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1482 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1483 musb_writew(epio, MUSB_RXCSR, rx_csr); 1484 1485 goto finish; 1486 } else { 1487 DBG(4, "RX end %d ISO data error\n", epnum); 1488 /* packet error reported later */ 1489 iso_err = true; 1490 } 1491 } 1492 1493 /* faults abort the transfer */ 1494 if (status) { 1495 /* clean up dma and collect transfer count */ 1496 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1497 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1498 (void) musb->dma_controller->channel_abort(dma); 1499 xfer_len = dma->actual_len; 1500 } 1501 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1502 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1503 done = true; 1504 goto finish; 1505 } 1506 1507 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { 1508 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ 1509 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); 1510 goto finish; 1511 } 1512 1513 /* thorough shutdown for now ... given more precise fault handling 1514 * and better queueing support, we might keep a DMA pipeline going 1515 * while processing this irq for earlier completions. 1516 */ 1517 1518 /* FIXME this is _way_ too much in-line logic for Mentor DMA */ 1519 1520#ifndef CONFIG_USB_INVENTRA_DMA 1521 if (rx_csr & MUSB_RXCSR_H_REQPKT) { 1522 /* REVISIT this happened for a while on some short reads... 1523 * the cleanup still needs investigation... looks bad... 1524 * and also duplicates dma cleanup code above ... plus, 1525 * shouldn't this be the "half full" double buffer case? 1526 */ 1527 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1528 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1529 (void) musb->dma_controller->channel_abort(dma); 1530 xfer_len = dma->actual_len; 1531 done = true; 1532 } 1533 1534 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, 1535 xfer_len, dma ? ", dma" : ""); 1536 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 1537 1538 musb_ep_select(mbase, epnum); 1539 musb_writew(epio, MUSB_RXCSR, 1540 MUSB_RXCSR_H_WZC_BITS | rx_csr); 1541 } 1542#endif 1543 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { 1544 xfer_len = dma->actual_len; 1545 1546 val &= ~(MUSB_RXCSR_DMAENAB 1547 | MUSB_RXCSR_H_AUTOREQ 1548 | MUSB_RXCSR_AUTOCLEAR 1549 | MUSB_RXCSR_RXPKTRDY); 1550 musb_writew(hw_ep->regs, MUSB_RXCSR, val); 1551 1552#ifdef CONFIG_USB_INVENTRA_DMA 1553 if (usb_pipeisoc(pipe)) { 1554 struct usb_iso_packet_descriptor *d; 1555 1556 d = urb->iso_frame_desc + qh->iso_idx; 1557 d->actual_length = xfer_len; 1558 1559 /* even if there was an error, we did the dma 1560 * for iso_frame_desc->length 1561 */ 1562 if (d->status != EILSEQ && d->status != -EOVERFLOW) 1563 d->status = 0; 1564 1565 if (++qh->iso_idx >= urb->number_of_packets) 1566 done = true; 1567 else 1568 done = false; 1569 1570 } else { 1571 /* done if urb buffer is full or short packet is recd */ 1572 done = (urb->actual_length + xfer_len >= 1573 urb->transfer_buffer_length 1574 || dma->actual_len < qh->maxpacket); 1575 } 1576 1577 /* send IN token for next packet, without AUTOREQ */ 1578 if (!done) { 1579 val |= MUSB_RXCSR_H_REQPKT; 1580 musb_writew(epio, MUSB_RXCSR, 1581 MUSB_RXCSR_H_WZC_BITS | val); 1582 } 1583 1584 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, 1585 done ? "off" : "reset", 1586 musb_readw(epio, MUSB_RXCSR), 1587 musb_readw(epio, MUSB_RXCOUNT)); 1588#else 1589 done = true; 1590#endif 1591 } else if (urb->status == -EINPROGRESS) { 1592 /* if no errors, be sure a packet is ready for unloading */ 1593 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { 1594 status = -EPROTO; 1595 ERR("Rx interrupt with no errors or packet!\n"); 1596 1597 /* FIXME this is another "SHOULD NEVER HAPPEN" */ 1598 1599/* SCRUB (RX) */ 1600 /* do the proper sequence to abort the transfer */ 1601 musb_ep_select(mbase, epnum); 1602 val &= ~MUSB_RXCSR_H_REQPKT; 1603 musb_writew(epio, MUSB_RXCSR, val); 1604 goto finish; 1605 } 1606 1607 /* we are expecting IN packets */ 1608#ifdef CONFIG_USB_INVENTRA_DMA 1609 if (dma) { 1610 struct dma_controller *c; 1611 u16 rx_count; 1612 int ret, length; 1613 dma_addr_t buf; 1614 1615 rx_count = musb_readw(epio, MUSB_RXCOUNT); 1616 1617 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n", 1618 epnum, rx_count, 1619 urb->transfer_dma 1620 + urb->actual_length, 1621 qh->offset, 1622 urb->transfer_buffer_length); 1623 1624 c = musb->dma_controller; 1625 1626 if (usb_pipeisoc(pipe)) { 1627 int status = 0; 1628 struct usb_iso_packet_descriptor *d; 1629 1630 d = urb->iso_frame_desc + qh->iso_idx; 1631 1632 if (iso_err) { 1633 status = -EILSEQ; 1634 urb->error_count++; 1635 } 1636 if (rx_count > d->length) { 1637 if (status == 0) { 1638 status = -EOVERFLOW; 1639 urb->error_count++; 1640 } 1641 DBG(2, "** OVERFLOW %d into %d\n",\ 1642 rx_count, d->length); 1643 1644 length = d->length; 1645 } else 1646 length = rx_count; 1647 d->status = status; 1648 buf = urb->transfer_dma + d->offset; 1649 } else { 1650 length = rx_count; 1651 buf = urb->transfer_dma + 1652 urb->actual_length; 1653 } 1654 1655 dma->desired_mode = 0; 1656#ifdef USE_MODE1 1657 /* because of the issue below, mode 1 will 1658 * only rarely behave with correct semantics. 1659 */ 1660 if ((urb->transfer_flags & 1661 URB_SHORT_NOT_OK) 1662 && (urb->transfer_buffer_length - 1663 urb->actual_length) 1664 > qh->maxpacket) 1665 dma->desired_mode = 1; 1666 if (rx_count < hw_ep->max_packet_sz_rx) { 1667 length = rx_count; 1668 dma->bDesiredMode = 0; 1669 } else { 1670 length = urb->transfer_buffer_length; 1671 } 1672#endif 1673 1674/* Disadvantage of using mode 1: 1675 * It's basically usable only for mass storage class; essentially all 1676 * other protocols also terminate transfers on short packets. 1677 * 1678 * Details: 1679 * An extra IN token is sent at the end of the transfer (due to AUTOREQ) 1680 * If you try to use mode 1 for (transfer_buffer_length - 512), and try 1681 * to use the extra IN token to grab the last packet using mode 0, then 1682 * the problem is that you cannot be sure when the device will send the 1683 * last packet and RxPktRdy set. Sometimes the packet is recd too soon 1684 * such that it gets lost when RxCSR is re-set at the end of the mode 1 1685 * transfer, while sometimes it is recd just a little late so that if you 1686 * try to configure for mode 0 soon after the mode 1 transfer is 1687 * completed, you will find rxcount 0. Okay, so you might think why not 1688 * wait for an interrupt when the pkt is recd. Well, you won't get any! 1689 */ 1690 1691 val = musb_readw(epio, MUSB_RXCSR); 1692 val &= ~MUSB_RXCSR_H_REQPKT; 1693 1694 if (dma->desired_mode == 0) 1695 val &= ~MUSB_RXCSR_H_AUTOREQ; 1696 else 1697 val |= MUSB_RXCSR_H_AUTOREQ; 1698 val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB; 1699 1700 musb_writew(epio, MUSB_RXCSR, 1701 MUSB_RXCSR_H_WZC_BITS | val); 1702 1703 /* REVISIT if when actual_length != 0, 1704 * transfer_buffer_length needs to be 1705 * adjusted first... 1706 */ 1707 ret = c->channel_program( 1708 dma, qh->maxpacket, 1709 dma->desired_mode, buf, length); 1710 1711 if (!ret) { 1712 c->channel_release(dma); 1713 hw_ep->rx_channel = NULL; 1714 dma = NULL; 1715 /* REVISIT reset CSR */ 1716 } 1717 } 1718#endif /* Mentor DMA */ 1719 1720 if (!dma) { 1721 done = musb_host_packet_rx(musb, urb, 1722 epnum, iso_err); 1723 DBG(6, "read %spacket\n", done ? "last " : ""); 1724 } 1725 } 1726 1727finish: 1728 urb->actual_length += xfer_len; 1729 qh->offset += xfer_len; 1730 if (done) { 1731 if (urb->status == -EINPROGRESS) 1732 urb->status = status; 1733 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); 1734 } 1735} 1736 1737/* schedule nodes correspond to peripheral endpoints, like an OHCI QH. 1738 * the software schedule associates multiple such nodes with a given 1739 * host side hardware endpoint + direction; scheduling may activate 1740 * that hardware endpoint. 1741 */ 1742static int musb_schedule( 1743 struct musb *musb, 1744 struct musb_qh *qh, 1745 int is_in) 1746{ 1747 int idle; 1748 int best_diff; 1749 int best_end, epnum; 1750 struct musb_hw_ep *hw_ep = NULL; 1751 struct list_head *head = NULL; 1752 1753 /* use fixed hardware for control and bulk */ 1754 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { 1755 head = &musb->control; 1756 hw_ep = musb->control_ep; 1757 goto success; 1758 } 1759 1760 /* else, periodic transfers get muxed to other endpoints */ 1761 1762 /* 1763 * We know this qh hasn't been scheduled, so all we need to do 1764 * is choose which hardware endpoint to put it on ... 1765 * 1766 * REVISIT what we really want here is a regular schedule tree 1767 * like e.g. OHCI uses. 1768 */ 1769 best_diff = 4096; 1770 best_end = -1; 1771 1772 for (epnum = 1, hw_ep = musb->endpoints + 1; 1773 epnum < musb->nr_endpoints; 1774 epnum++, hw_ep++) { 1775 int diff; 1776 1777 if (is_in || hw_ep->is_shared_fifo) { 1778 if (hw_ep->in_qh != NULL) 1779 continue; 1780 } else if (hw_ep->out_qh != NULL) 1781 continue; 1782 1783 if (hw_ep == musb->bulk_ep) 1784 continue; 1785 1786 if (is_in) 1787 diff = hw_ep->max_packet_sz_rx - qh->maxpacket; 1788 else 1789 diff = hw_ep->max_packet_sz_tx - qh->maxpacket; 1790 1791 if (diff >= 0 && best_diff > diff) { 1792 best_diff = diff; 1793 best_end = epnum; 1794 } 1795 } 1796 /* use bulk reserved ep1 if no other ep is free */ 1797 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { 1798 hw_ep = musb->bulk_ep; 1799 if (is_in) 1800 head = &musb->in_bulk; 1801 else 1802 head = &musb->out_bulk; 1803 1804 /* Enable bulk RX NAK timeout scheme when bulk requests are 1805 * multiplexed. This scheme doen't work in high speed to full 1806 * speed scenario as NAK interrupts are not coming from a 1807 * full speed device connected to a high speed device. 1808 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and 1809 * 4 (8 frame or 8ms) for FS device. 1810 */ 1811 if (is_in && qh->dev) 1812 qh->intv_reg = 1813 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; 1814 goto success; 1815 } else if (best_end < 0) { 1816 return -ENOSPC; 1817 } 1818 1819 idle = 1; 1820 qh->mux = 0; 1821 hw_ep = musb->endpoints + best_end; 1822 DBG(4, "qh %p periodic slot %d\n", qh, best_end); 1823success: 1824 if (head) { 1825 idle = list_empty(head); 1826 list_add_tail(&qh->ring, head); 1827 qh->mux = 1; 1828 } 1829 qh->hw_ep = hw_ep; 1830 qh->hep->hcpriv = qh; 1831 if (idle) 1832 musb_start_urb(musb, is_in, qh); 1833 return 0; 1834} 1835 1836static int musb_urb_enqueue( 1837 struct usb_hcd *hcd, 1838 struct urb *urb, 1839 gfp_t mem_flags) 1840{ 1841 unsigned long flags; 1842 struct musb *musb = hcd_to_musb(hcd); 1843 struct usb_host_endpoint *hep = urb->ep; 1844 struct musb_qh *qh; 1845 struct usb_endpoint_descriptor *epd = &hep->desc; 1846 int ret; 1847 unsigned type_reg; 1848 unsigned interval; 1849 1850 /* host role must be active */ 1851 if (!is_host_active(musb) || !musb->is_active) 1852 return -ENODEV; 1853 1854 spin_lock_irqsave(&musb->lock, flags); 1855 ret = usb_hcd_link_urb_to_ep(hcd, urb); 1856 qh = ret ? NULL : hep->hcpriv; 1857 if (qh) 1858 urb->hcpriv = qh; 1859 spin_unlock_irqrestore(&musb->lock, flags); 1860 1861 /* DMA mapping was already done, if needed, and this urb is on 1862 * hep->urb_list now ... so we're done, unless hep wasn't yet 1863 * scheduled onto a live qh. 1864 * 1865 * REVISIT best to keep hep->hcpriv valid until the endpoint gets 1866 * disabled, testing for empty qh->ring and avoiding qh setup costs 1867 * except for the first urb queued after a config change. 1868 */ 1869 if (qh || ret) 1870 return ret; 1871 1872 /* Allocate and initialize qh, minimizing the work done each time 1873 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. 1874 * 1875 * REVISIT consider a dedicated qh kmem_cache, so it's harder 1876 * for bugs in other kernel code to break this driver... 1877 */ 1878 qh = kzalloc(sizeof *qh, mem_flags); 1879 if (!qh) { 1880 spin_lock_irqsave(&musb->lock, flags); 1881 usb_hcd_unlink_urb_from_ep(hcd, urb); 1882 spin_unlock_irqrestore(&musb->lock, flags); 1883 return -ENOMEM; 1884 } 1885 1886 qh->hep = hep; 1887 qh->dev = urb->dev; 1888 INIT_LIST_HEAD(&qh->ring); 1889 qh->is_ready = 1; 1890 1891 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize); 1892 1893 /* no high bandwidth support yet */ 1894 if (qh->maxpacket & ~0x7ff) { 1895 ret = -EMSGSIZE; 1896 goto done; 1897 } 1898 1899 qh->epnum = usb_endpoint_num(epd); 1900 qh->type = usb_endpoint_type(epd); 1901 1902 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ 1903 qh->addr_reg = (u8) usb_pipedevice(urb->pipe); 1904 1905 /* precompute rxtype/txtype/type0 register */ 1906 type_reg = (qh->type << 4) | qh->epnum; 1907 switch (urb->dev->speed) { 1908 case USB_SPEED_LOW: 1909 type_reg |= 0xc0; 1910 break; 1911 case USB_SPEED_FULL: 1912 type_reg |= 0x80; 1913 break; 1914 default: 1915 type_reg |= 0x40; 1916 } 1917 qh->type_reg = type_reg; 1918 1919 /* Precompute RXINTERVAL/TXINTERVAL register */ 1920 switch (qh->type) { 1921 case USB_ENDPOINT_XFER_INT: 1922 /* 1923 * Full/low speeds use the linear encoding, 1924 * high speed uses the logarithmic encoding. 1925 */ 1926 if (urb->dev->speed <= USB_SPEED_FULL) { 1927 interval = max_t(u8, epd->bInterval, 1); 1928 break; 1929 } 1930 /* FALLTHROUGH */ 1931 case USB_ENDPOINT_XFER_ISOC: 1932 /* ISO always uses logarithmic encoding */ 1933 interval = min_t(u8, epd->bInterval, 16); 1934 break; 1935 default: 1936 /* REVISIT we actually want to use NAK limits, hinting to the 1937 * transfer scheduling logic to try some other qh, e.g. try 1938 * for 2 msec first: 1939 * 1940 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; 1941 * 1942 * The downside of disabling this is that transfer scheduling 1943 * gets VERY unfair for nonperiodic transfers; a misbehaving 1944 * peripheral could make that hurt. That's perfectly normal 1945 * for reads from network or serial adapters ... so we have 1946 * partial NAKlimit support for bulk RX. 1947 * 1948 * The upside of disabling it is simpler transfer scheduling. 1949 */ 1950 interval = 0; 1951 } 1952 qh->intv_reg = interval; 1953 1954 /* precompute addressing for external hub/tt ports */ 1955 if (musb->is_multipoint) { 1956 struct usb_device *parent = urb->dev->parent; 1957 1958 if (parent != hcd->self.root_hub) { 1959 qh->h_addr_reg = (u8) parent->devnum; 1960 1961 /* set up tt info if needed */ 1962 if (urb->dev->tt) { 1963 qh->h_port_reg = (u8) urb->dev->ttport; 1964 if (urb->dev->tt->hub) 1965 qh->h_addr_reg = 1966 (u8) urb->dev->tt->hub->devnum; 1967 if (urb->dev->tt->multi) 1968 qh->h_addr_reg |= 0x80; 1969 } 1970 } 1971 } 1972 1973 /* invariant: hep->hcpriv is null OR the qh that's already scheduled. 1974 * until we get real dma queues (with an entry for each urb/buffer), 1975 * we only have work to do in the former case. 1976 */ 1977 spin_lock_irqsave(&musb->lock, flags); 1978 if (hep->hcpriv) { 1979 /* some concurrent activity submitted another urb to hep... 1980 * odd, rare, error prone, but legal. 1981 */ 1982 kfree(qh); 1983 ret = 0; 1984 } else 1985 ret = musb_schedule(musb, qh, 1986 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); 1987 1988 if (ret == 0) { 1989 urb->hcpriv = qh; 1990 /* FIXME set urb->start_frame for iso/intr, it's tested in 1991 * musb_start_urb(), but otherwise only konicawc cares ... 1992 */ 1993 } 1994 spin_unlock_irqrestore(&musb->lock, flags); 1995 1996done: 1997 if (ret != 0) { 1998 spin_lock_irqsave(&musb->lock, flags); 1999 usb_hcd_unlink_urb_from_ep(hcd, urb); 2000 spin_unlock_irqrestore(&musb->lock, flags); 2001 kfree(qh); 2002 } 2003 return ret; 2004} 2005 2006 2007/* 2008 * abort a transfer that's at the head of a hardware queue. 2009 * called with controller locked, irqs blocked 2010 * that hardware queue advances to the next transfer, unless prevented 2011 */ 2012static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in) 2013{ 2014 struct musb_hw_ep *ep = qh->hw_ep; 2015 void __iomem *epio = ep->regs; 2016 unsigned hw_end = ep->epnum; 2017 void __iomem *regs = ep->musb->mregs; 2018 u16 csr; 2019 int status = 0; 2020 2021 musb_ep_select(regs, hw_end); 2022 2023 if (is_dma_capable()) { 2024 struct dma_channel *dma; 2025 2026 dma = is_in ? ep->rx_channel : ep->tx_channel; 2027 if (dma) { 2028 status = ep->musb->dma_controller->channel_abort(dma); 2029 DBG(status ? 1 : 3, 2030 "abort %cX%d DMA for urb %p --> %d\n", 2031 is_in ? 'R' : 'T', ep->epnum, 2032 urb, status); 2033 urb->actual_length += dma->actual_len; 2034 } 2035 } 2036 2037 /* turn off DMA requests, discard state, stop polling ... */ 2038 if (is_in) { 2039 /* giveback saves bulk toggle */ 2040 csr = musb_h_flush_rxfifo(ep, 0); 2041 2042 /* REVISIT we still get an irq; should likely clear the 2043 * endpoint's irq status here to avoid bogus irqs. 2044 * clearing that status is platform-specific... 2045 */ 2046 } else { 2047 musb_h_tx_flush_fifo(ep); 2048 csr = musb_readw(epio, MUSB_TXCSR); 2049 csr &= ~(MUSB_TXCSR_AUTOSET 2050 | MUSB_TXCSR_DMAENAB 2051 | MUSB_TXCSR_H_RXSTALL 2052 | MUSB_TXCSR_H_NAKTIMEOUT 2053 | MUSB_TXCSR_H_ERROR 2054 | MUSB_TXCSR_TXPKTRDY); 2055 musb_writew(epio, MUSB_TXCSR, csr); 2056 /* REVISIT may need to clear FLUSHFIFO ... */ 2057 musb_writew(epio, MUSB_TXCSR, csr); 2058 /* flush cpu writebuffer */ 2059 csr = musb_readw(epio, MUSB_TXCSR); 2060 } 2061 if (status == 0) 2062 musb_advance_schedule(ep->musb, urb, ep, is_in); 2063 return status; 2064} 2065 2066static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 2067{ 2068 struct musb *musb = hcd_to_musb(hcd); 2069 struct musb_qh *qh; 2070 struct list_head *sched; 2071 unsigned long flags; 2072 int ret; 2073 2074 DBG(4, "urb=%p, dev%d ep%d%s\n", urb, 2075 usb_pipedevice(urb->pipe), 2076 usb_pipeendpoint(urb->pipe), 2077 usb_pipein(urb->pipe) ? "in" : "out"); 2078 2079 spin_lock_irqsave(&musb->lock, flags); 2080 ret = usb_hcd_check_unlink_urb(hcd, urb, status); 2081 if (ret) 2082 goto done; 2083 2084 qh = urb->hcpriv; 2085 if (!qh) 2086 goto done; 2087 2088 /* Any URB not actively programmed into endpoint hardware can be 2089 * immediately given back; that's any URB not at the head of an 2090 * endpoint queue, unless someday we get real DMA queues. And even 2091 * if it's at the head, it might not be known to the hardware... 2092 * 2093 * Otherwise abort current transfer, pending dma, etc.; urb->status 2094 * has already been updated. This is a synchronous abort; it'd be 2095 * OK to hold off until after some IRQ, though. 2096 */ 2097 if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list) 2098 ret = -EINPROGRESS; 2099 else { 2100 switch (qh->type) { 2101 case USB_ENDPOINT_XFER_CONTROL: 2102 sched = &musb->control; 2103 break; 2104 case USB_ENDPOINT_XFER_BULK: 2105 if (qh->mux == 1) { 2106 if (usb_pipein(urb->pipe)) 2107 sched = &musb->in_bulk; 2108 else 2109 sched = &musb->out_bulk; 2110 break; 2111 } 2112 default: 2113 /* REVISIT when we get a schedule tree, periodic 2114 * transfers won't always be at the head of a 2115 * singleton queue... 2116 */ 2117 sched = NULL; 2118 break; 2119 } 2120 } 2121 2122 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ 2123 if (ret < 0 || (sched && qh != first_qh(sched))) { 2124 int ready = qh->is_ready; 2125 2126 ret = 0; 2127 qh->is_ready = 0; 2128 __musb_giveback(musb, urb, 0); 2129 qh->is_ready = ready; 2130 2131 /* If nothing else (usually musb_giveback) is using it 2132 * and its URB list has emptied, recycle this qh. 2133 */ 2134 if (ready && list_empty(&qh->hep->urb_list)) { 2135 qh->hep->hcpriv = NULL; 2136 list_del(&qh->ring); 2137 kfree(qh); 2138 } 2139 } else 2140 ret = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN); 2141done: 2142 spin_unlock_irqrestore(&musb->lock, flags); 2143 return ret; 2144} 2145 2146/* disable an endpoint */ 2147static void 2148musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) 2149{ 2150 u8 epnum = hep->desc.bEndpointAddress; 2151 unsigned long flags; 2152 struct musb *musb = hcd_to_musb(hcd); 2153 u8 is_in = epnum & USB_DIR_IN; 2154 struct musb_qh *qh; 2155 struct urb *urb; 2156 struct list_head *sched; 2157 2158 spin_lock_irqsave(&musb->lock, flags); 2159 2160 qh = hep->hcpriv; 2161 if (qh == NULL) 2162 goto exit; 2163 2164 switch (qh->type) { 2165 case USB_ENDPOINT_XFER_CONTROL: 2166 sched = &musb->control; 2167 break; 2168 case USB_ENDPOINT_XFER_BULK: 2169 if (qh->mux == 1) { 2170 if (is_in) 2171 sched = &musb->in_bulk; 2172 else 2173 sched = &musb->out_bulk; 2174 break; 2175 } 2176 default: 2177 /* REVISIT when we get a schedule tree, periodic transfers 2178 * won't always be at the head of a singleton queue... 2179 */ 2180 sched = NULL; 2181 break; 2182 } 2183 2184 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ 2185 2186 /* kick first urb off the hardware, if needed */ 2187 qh->is_ready = 0; 2188 if (!sched || qh == first_qh(sched)) { 2189 urb = next_urb(qh); 2190 2191 /* make software (then hardware) stop ASAP */ 2192 if (!urb->unlinked) 2193 urb->status = -ESHUTDOWN; 2194 2195 /* cleanup */ 2196 musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN); 2197 2198 /* Then nuke all the others ... and advance the 2199 * queue on hw_ep (e.g. bulk ring) when we're done. 2200 */ 2201 while (!list_empty(&hep->urb_list)) { 2202 urb = next_urb(qh); 2203 urb->status = -ESHUTDOWN; 2204 musb_advance_schedule(musb, urb, qh->hw_ep, is_in); 2205 } 2206 } else { 2207 /* Just empty the queue; the hardware is busy with 2208 * other transfers, and since !qh->is_ready nothing 2209 * will activate any of these as it advances. 2210 */ 2211 while (!list_empty(&hep->urb_list)) 2212 __musb_giveback(musb, next_urb(qh), -ESHUTDOWN); 2213 2214 hep->hcpriv = NULL; 2215 list_del(&qh->ring); 2216 kfree(qh); 2217 } 2218exit: 2219 spin_unlock_irqrestore(&musb->lock, flags); 2220} 2221 2222static int musb_h_get_frame_number(struct usb_hcd *hcd) 2223{ 2224 struct musb *musb = hcd_to_musb(hcd); 2225 2226 return musb_readw(musb->mregs, MUSB_FRAME); 2227} 2228 2229static int musb_h_start(struct usb_hcd *hcd) 2230{ 2231 struct musb *musb = hcd_to_musb(hcd); 2232 2233 /* NOTE: musb_start() is called when the hub driver turns 2234 * on port power, or when (OTG) peripheral starts. 2235 */ 2236 hcd->state = HC_STATE_RUNNING; 2237 musb->port1_status = 0; 2238 return 0; 2239} 2240 2241static void musb_h_stop(struct usb_hcd *hcd) 2242{ 2243 musb_stop(hcd_to_musb(hcd)); 2244 hcd->state = HC_STATE_HALT; 2245} 2246 2247static int musb_bus_suspend(struct usb_hcd *hcd) 2248{ 2249 struct musb *musb = hcd_to_musb(hcd); 2250 2251 if (musb->xceiv.state == OTG_STATE_A_SUSPEND) 2252 return 0; 2253 2254 if (is_host_active(musb) && musb->is_active) { 2255 WARNING("trying to suspend as %s is_active=%i\n", 2256 otg_state_string(musb), musb->is_active); 2257 return -EBUSY; 2258 } else 2259 return 0; 2260} 2261 2262static int musb_bus_resume(struct usb_hcd *hcd) 2263{ 2264 /* resuming child port does the work */ 2265 return 0; 2266} 2267 2268const struct hc_driver musb_hc_driver = { 2269 .description = "musb-hcd", 2270 .product_desc = "MUSB HDRC host driver", 2271 .hcd_priv_size = sizeof(struct musb), 2272 .flags = HCD_USB2 | HCD_MEMORY, 2273 2274 /* not using irq handler or reset hooks from usbcore, since 2275 * those must be shared with peripheral code for OTG configs 2276 */ 2277 2278 .start = musb_h_start, 2279 .stop = musb_h_stop, 2280 2281 .get_frame_number = musb_h_get_frame_number, 2282 2283 .urb_enqueue = musb_urb_enqueue, 2284 .urb_dequeue = musb_urb_dequeue, 2285 .endpoint_disable = musb_h_disable, 2286 2287 .hub_status_data = musb_hub_status_data, 2288 .hub_control = musb_hub_control, 2289 .bus_suspend = musb_bus_suspend, 2290 .bus_resume = musb_bus_resume, 2291 /* .start_port_reset = NULL, */ 2292 /* .hub_irq_enable = NULL, */ 2293}; 2294