1/*
2 * MUSB OTG driver - support for Mentor's DMA controller
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2007 by Texas Instruments
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33#include <linux/device.h>
34#include <linux/interrupt.h>
35#include <linux/platform_device.h>
36#include <linux/slab.h>
37#include "musb_core.h"
38#include "musbhsdma.h"
39
40static void dma_channel_release(struct dma_channel *channel);
41
42static void dma_controller_stop(struct musb_dma_controller *controller)
43{
44	struct musb *musb = controller->private_data;
45	struct dma_channel *channel;
46	u8 bit;
47
48	if (controller->used_channels != 0) {
49		dev_err(musb->controller,
50			"Stopping DMA controller while channel active\n");
51
52		for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
53			if (controller->used_channels & (1 << bit)) {
54				channel = &controller->channel[bit].channel;
55				dma_channel_release(channel);
56
57				if (!controller->used_channels)
58					break;
59			}
60		}
61	}
62}
63
64static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
65				struct musb_hw_ep *hw_ep, u8 transmit)
66{
67	struct musb_dma_controller *controller = container_of(c,
68			struct musb_dma_controller, controller);
69	struct musb_dma_channel *musb_channel = NULL;
70	struct dma_channel *channel = NULL;
71	u8 bit;
72
73	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
74		if (!(controller->used_channels & (1 << bit))) {
75			controller->used_channels |= (1 << bit);
76			musb_channel = &(controller->channel[bit]);
77			musb_channel->controller = controller;
78			musb_channel->idx = bit;
79			musb_channel->epnum = hw_ep->epnum;
80			musb_channel->transmit = transmit;
81			channel = &(musb_channel->channel);
82			channel->private_data = musb_channel;
83			channel->status = MUSB_DMA_STATUS_FREE;
84			channel->max_len = 0x100000;
85			/* Tx => mode 1; Rx => mode 0 */
86			channel->desired_mode = transmit;
87			channel->actual_len = 0;
88			break;
89		}
90	}
91
92	return channel;
93}
94
95static void dma_channel_release(struct dma_channel *channel)
96{
97	struct musb_dma_channel *musb_channel = channel->private_data;
98
99	channel->actual_len = 0;
100	musb_channel->start_addr = 0;
101	musb_channel->len = 0;
102
103	musb_channel->controller->used_channels &=
104		~(1 << musb_channel->idx);
105
106	channel->status = MUSB_DMA_STATUS_UNKNOWN;
107}
108
109static void configure_channel(struct dma_channel *channel,
110				u16 packet_sz, u8 mode,
111				dma_addr_t dma_addr, u32 len)
112{
113	struct musb_dma_channel *musb_channel = channel->private_data;
114	struct musb_dma_controller *controller = musb_channel->controller;
115	struct musb *musb = controller->private_data;
116	void __iomem *mbase = controller->base;
117	u8 bchannel = musb_channel->idx;
118	u16 csr = 0;
119
120	dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
121			channel, packet_sz, dma_addr, len, mode);
122
123	if (mode) {
124		csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
125		BUG_ON(len < packet_sz);
126	}
127	csr |= MUSB_HSDMA_BURSTMODE_INCR16
128				<< MUSB_HSDMA_BURSTMODE_SHIFT;
129
130	csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
131		| (1 << MUSB_HSDMA_ENABLE_SHIFT)
132		| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
133		| (musb_channel->transmit
134				? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
135				: 0);
136
137	/* address/count */
138	musb_write_hsdma_addr(mbase, bchannel, dma_addr);
139	musb_write_hsdma_count(mbase, bchannel, len);
140
141	/* control (this should start things) */
142	musb_writew(mbase,
143		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
144		csr);
145}
146
147static int dma_channel_program(struct dma_channel *channel,
148				u16 packet_sz, u8 mode,
149				dma_addr_t dma_addr, u32 len)
150{
151	struct musb_dma_channel *musb_channel = channel->private_data;
152	struct musb_dma_controller *controller = musb_channel->controller;
153	struct musb *musb = controller->private_data;
154
155	dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
156		musb_channel->epnum,
157		musb_channel->transmit ? "Tx" : "Rx",
158		packet_sz, dma_addr, len, mode);
159
160	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
161		channel->status == MUSB_DMA_STATUS_BUSY);
162
163	/* Let targets check/tweak the arguments */
164	if (musb->ops->adjust_channel_params) {
165		int ret = musb->ops->adjust_channel_params(channel,
166			packet_sz, &mode, &dma_addr, &len);
167		if (ret)
168			return ret;
169	}
170
171	/*
172	 * The DMA engine in RTL1.8 and above cannot handle
173	 * DMA addresses that are not aligned to a 4 byte boundary.
174	 * It ends up masking the last two bits of the address
175	 * programmed in DMA_ADDR.
176	 *
177	 * Fail such DMA transfers, so that the backup PIO mode
178	 * can carry out the transfer
179	 */
180	if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
181		return false;
182
183	channel->actual_len = 0;
184	musb_channel->start_addr = dma_addr;
185	musb_channel->len = len;
186	musb_channel->max_packet_sz = packet_sz;
187	channel->status = MUSB_DMA_STATUS_BUSY;
188
189	configure_channel(channel, packet_sz, mode, dma_addr, len);
190
191	return true;
192}
193
194static int dma_channel_abort(struct dma_channel *channel)
195{
196	struct musb_dma_channel *musb_channel = channel->private_data;
197	void __iomem *mbase = musb_channel->controller->base;
198
199	u8 bchannel = musb_channel->idx;
200	int offset;
201	u16 csr;
202
203	if (channel->status == MUSB_DMA_STATUS_BUSY) {
204		if (musb_channel->transmit) {
205			offset = MUSB_EP_OFFSET(musb_channel->epnum,
206						MUSB_TXCSR);
207
208			/*
209			 * The programming guide says that we must clear
210			 * the DMAENAB bit before the DMAMODE bit...
211			 */
212			csr = musb_readw(mbase, offset);
213			csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
214			musb_writew(mbase, offset, csr);
215			csr &= ~MUSB_TXCSR_DMAMODE;
216			musb_writew(mbase, offset, csr);
217		} else {
218			offset = MUSB_EP_OFFSET(musb_channel->epnum,
219						MUSB_RXCSR);
220
221			csr = musb_readw(mbase, offset);
222			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
223				 MUSB_RXCSR_DMAENAB |
224				 MUSB_RXCSR_DMAMODE);
225			musb_writew(mbase, offset, csr);
226		}
227
228		musb_writew(mbase,
229			MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
230			0);
231		musb_write_hsdma_addr(mbase, bchannel, 0);
232		musb_write_hsdma_count(mbase, bchannel, 0);
233		channel->status = MUSB_DMA_STATUS_FREE;
234	}
235
236	return 0;
237}
238
239static irqreturn_t dma_controller_irq(int irq, void *private_data)
240{
241	struct musb_dma_controller *controller = private_data;
242	struct musb *musb = controller->private_data;
243	struct musb_dma_channel *musb_channel;
244	struct dma_channel *channel;
245
246	void __iomem *mbase = controller->base;
247
248	irqreturn_t retval = IRQ_NONE;
249
250	unsigned long flags;
251
252	u8 bchannel;
253	u8 int_hsdma;
254
255	u32 addr, count;
256	u16 csr;
257
258	spin_lock_irqsave(&musb->lock, flags);
259
260	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
261
262#ifdef CONFIG_BLACKFIN
263	/* Clear DMA interrupt flags */
264	musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
265#endif
266
267	if (!int_hsdma) {
268		dev_dbg(musb->controller, "spurious DMA irq\n");
269
270		for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
271			musb_channel = (struct musb_dma_channel *)
272					&(controller->channel[bchannel]);
273			channel = &musb_channel->channel;
274			if (channel->status == MUSB_DMA_STATUS_BUSY) {
275				count = musb_read_hsdma_count(mbase, bchannel);
276
277				if (count == 0)
278					int_hsdma |= (1 << bchannel);
279			}
280		}
281
282		dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);
283
284		if (!int_hsdma)
285			goto done;
286	}
287
288	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
289		if (int_hsdma & (1 << bchannel)) {
290			musb_channel = (struct musb_dma_channel *)
291					&(controller->channel[bchannel]);
292			channel = &musb_channel->channel;
293
294			csr = musb_readw(mbase,
295					MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
296							MUSB_HSDMA_CONTROL));
297
298			if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
299				musb_channel->channel.status =
300					MUSB_DMA_STATUS_BUS_ABORT;
301			} else {
302				u8 devctl;
303
304				addr = musb_read_hsdma_addr(mbase,
305						bchannel);
306				channel->actual_len = addr
307					- musb_channel->start_addr;
308
309				dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
310					channel, musb_channel->start_addr,
311					addr, channel->actual_len,
312					musb_channel->len,
313					(channel->actual_len
314						< musb_channel->len) ?
315					"=> reconfig 0" : "=> complete");
316
317				devctl = musb_readb(mbase, MUSB_DEVCTL);
318
319				channel->status = MUSB_DMA_STATUS_FREE;
320
321				/* completed */
322				if ((devctl & MUSB_DEVCTL_HM)
323					&& (musb_channel->transmit)
324					&& ((channel->desired_mode == 0)
325					    || (channel->actual_len &
326					    (musb_channel->max_packet_sz - 1)))
327				    ) {
328					u8  epnum  = musb_channel->epnum;
329					int offset = MUSB_EP_OFFSET(epnum,
330								    MUSB_TXCSR);
331					u16 txcsr;
332
333					/*
334					 * The programming guide says that we
335					 * must clear DMAENAB before DMAMODE.
336					 */
337					musb_ep_select(mbase, epnum);
338					txcsr = musb_readw(mbase, offset);
339					txcsr &= ~(MUSB_TXCSR_DMAENAB
340							| MUSB_TXCSR_AUTOSET);
341					musb_writew(mbase, offset, txcsr);
342					/* Send out the packet */
343					txcsr &= ~MUSB_TXCSR_DMAMODE;
344					txcsr |=  MUSB_TXCSR_TXPKTRDY;
345					musb_writew(mbase, offset, txcsr);
346				}
347				musb_dma_completion(musb, musb_channel->epnum,
348						    musb_channel->transmit);
349			}
350		}
351	}
352
353	retval = IRQ_HANDLED;
354done:
355	spin_unlock_irqrestore(&musb->lock, flags);
356	return retval;
357}
358
359void dma_controller_destroy(struct dma_controller *c)
360{
361	struct musb_dma_controller *controller = container_of(c,
362			struct musb_dma_controller, controller);
363
364	dma_controller_stop(controller);
365
366	if (controller->irq)
367		free_irq(controller->irq, c);
368
369	kfree(controller);
370}
371
372struct dma_controller *dma_controller_create(struct musb *musb, void __iomem *base)
373{
374	struct musb_dma_controller *controller;
375	struct device *dev = musb->controller;
376	struct platform_device *pdev = to_platform_device(dev);
377	int irq = platform_get_irq_byname(pdev, "dma");
378
379	if (irq <= 0) {
380		dev_err(dev, "No DMA interrupt line!\n");
381		return NULL;
382	}
383
384	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
385	if (!controller)
386		return NULL;
387
388	controller->channel_count = MUSB_HSDMA_CHANNELS;
389	controller->private_data = musb;
390	controller->base = base;
391
392	controller->controller.channel_alloc = dma_channel_allocate;
393	controller->controller.channel_release = dma_channel_release;
394	controller->controller.channel_program = dma_channel_program;
395	controller->controller.channel_abort = dma_channel_abort;
396
397	if (request_irq(irq, dma_controller_irq, 0,
398			dev_name(musb->controller), &controller->controller)) {
399		dev_err(dev, "request_irq %d failed!\n", irq);
400		dma_controller_destroy(&controller->controller);
401
402		return NULL;
403	}
404
405	controller->irq = irq;
406
407	return &controller->controller;
408}
409