16995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu/* 26995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * MUSB OTG driver - support for Mentor's DMA controller 36995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * 46995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * Copyright 2005 Mentor Graphics Corporation 56995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * Copyright (C) 2005-2007 by Texas Instruments 66995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * 76995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * This program is free software; you can redistribute it and/or 86995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * modify it under the terms of the GNU General Public License 96995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * version 2 as published by the Free Software Foundation. 106995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * 116995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * This program is distributed in the hope that it will be useful, but 126995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * WITHOUT ANY WARRANTY; without even the implied warranty of 136995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 146995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * General Public License for more details. 156995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * 166995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * You should have received a copy of the GNU General Public License 176995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * along with this program; if not, write to the Free Software 186995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 196995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * 02110-1301 USA 206995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * 216995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 226995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 236995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 246995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 256995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 266995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 276995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 286995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 296995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 306995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 316995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu * 326995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu */ 336995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 346995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#ifndef CONFIG_BLACKFIN 356995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 366995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_BASE 0x200 376995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0) 386995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_CONTROL 0x4 396995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_ADDRESS 0x8 406995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_COUNT 0xc 416995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 426995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \ 436995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset) 446995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 456995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define musb_read_hsdma_addr(mbase, bchannel) \ 466995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu musb_readl(mbase, \ 476995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS)) 486995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 496995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define musb_write_hsdma_addr(mbase, bchannel, addr) \ 506995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu musb_writel(mbase, \ 516995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \ 526995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu addr) 536995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 54452f0394376d2cc882e4c4a593fc290c042799a9Anand Gadiyar#define musb_read_hsdma_count(mbase, bchannel) \ 55452f0394376d2cc882e4c4a593fc290c042799a9Anand Gadiyar musb_readl(mbase, \ 56452f0394376d2cc882e4c4a593fc290c042799a9Anand Gadiyar MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT)) 57452f0394376d2cc882e4c4a593fc290c042799a9Anand Gadiyar 586995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define musb_write_hsdma_count(mbase, bchannel, len) \ 596995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu musb_writel(mbase, \ 606995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \ 616995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu len) 626995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#else 636995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 646995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_BASE 0x400 656995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0) 666995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_CONTROL 0x04 676995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_ADDR_LOW 0x08 686995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_ADDR_HIGH 0x0C 696995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_COUNT_LOW 0x10 706995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_COUNT_HIGH 0x14 716995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 726995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \ 736995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset) 746995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 756995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wustatic inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel) 766995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu{ 776995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u32 addr = musb_readw(mbase, 786995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH)); 796995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 806995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu addr = addr << 16; 816995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 826995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu addr |= musb_readw(mbase, 836995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW)); 846995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 856995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu return addr; 866995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu} 876995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 886995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wustatic inline void musb_write_hsdma_addr(void __iomem *mbase, 896995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u8 bchannel, dma_addr_t dma_addr) 906995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu{ 916995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu musb_writew(mbase, 926995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW), 939c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu dma_addr); 946995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu musb_writew(mbase, 956995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH), 969c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu (dma_addr >> 16)); 976995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu} 986995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 99452f0394376d2cc882e4c4a593fc290c042799a9Anand Gadiyarstatic inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel) 100452f0394376d2cc882e4c4a593fc290c042799a9Anand Gadiyar{ 1019c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu u32 count = musb_readw(mbase, 102452f0394376d2cc882e4c4a593fc290c042799a9Anand Gadiyar MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH)); 1039c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu 1049c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu count = count << 16; 1059c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu 1069c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu count |= musb_readw(mbase, 1079c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW)); 1089c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu 1099c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu return count; 110452f0394376d2cc882e4c4a593fc290c042799a9Anand Gadiyar} 111452f0394376d2cc882e4c4a593fc290c042799a9Anand Gadiyar 1126995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wustatic inline void musb_write_hsdma_count(void __iomem *mbase, 1136995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u8 bchannel, u32 len) 1146995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu{ 1159c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu musb_writew(mbase, 1169c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),len); 1179c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu musb_writew(mbase, 1186995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH), 1199c668079c864c3b49d8deb56dafedf916b2a72d0Bob Liu (len >> 16)); 1206995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu} 1216995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 1226995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#endif /* CONFIG_BLACKFIN */ 1236995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 1246995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu/* control register (16-bit): */ 1256995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_ENABLE_SHIFT 0 1266995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_TRANSMIT_SHIFT 1 1276995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_MODE1_SHIFT 2 1286995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_IRQENABLE_SHIFT 3 1296995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_ENDPOINT_SHIFT 4 1306995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_BUSERROR_SHIFT 8 1316995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_BURSTMODE_SHIFT 9 1326995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT) 1336995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_BURSTMODE_UNSPEC 0 1346995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_BURSTMODE_INCR4 1 1356995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_BURSTMODE_INCR8 2 1366995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_BURSTMODE_INCR16 3 1376995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 1386995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu#define MUSB_HSDMA_CHANNELS 8 1396995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 1406995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wustruct musb_dma_controller; 1416995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 1426995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wustruct musb_dma_channel { 1436995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu struct dma_channel channel; 1446995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu struct musb_dma_controller *controller; 1456995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u32 start_addr; 1466995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u32 len; 1476995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u16 max_packet_sz; 1486995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u8 idx; 1496995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u8 epnum; 1506995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u8 transmit; 1516995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu}; 1526995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu 1536995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wustruct musb_dma_controller { 1546995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu struct dma_controller controller; 1556995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS]; 1566995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu void *private_data; 1576995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu void __iomem *base; 1586995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u8 channel_count; 1596995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u8 used_channels; 1606995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu u8 irq; 1616995eb68aab70e79eedb710d7d6d1f22d8aea4a7Bryan Wu}; 162