1550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* 2550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Definitions for TUSB6010 USB 2.0 OTG Dual Role controller 3550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 4550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Copyright (C) 2006 Nokia Corporation 5550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * Tony Lindgren <tony@atomide.com> 6550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * 7550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * This program is free software; you can redistribute it and/or modify 8550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * it under the terms of the GNU General Public License version 2 as 9550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * published by the Free Software Foundation. 10550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 11550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 12550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#ifndef __TUSB6010_H__ 13550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define __TUSB6010_H__ 14550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 15550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#ifdef CONFIG_USB_TUSB_OMAP_DMA 16550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define tusb_dma_omap() 1 17550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#else 18550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define tusb_dma_omap() 0 19550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#endif 20550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 21550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* VLYNQ control register. 32-bit at offset 0x000 */ 22550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_VLYNQ_CTRL 0x004 23550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 24550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */ 25550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_BASE_OFFSET 0x400 26550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 27550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* FIFO registers 32-bit at offset 0x600 */ 28550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_FIFO_BASE 0x600 29550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 30550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Device System & Control registers. 32-bit at offset 0x800 */ 31550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_SYS_REG_BASE 0x800 32550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 33550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000) 34550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16) 35550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15) 36550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_CONF_SOFT_ID (1 << 1) 37550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_CONF_ID_SEL (1 << 0) 38550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 39550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004) 40550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008) 41550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24) 42550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP (1 << 23) 43550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN (1 << 19) 44550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN (1 << 18) 45550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17) 46550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16) 47550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15) 48550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14) 49550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13) 50550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12) 51550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11) 52550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10) 53550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9) 54550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL(v) (((v) & 3) << 7) 55550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_PD (1 << 6) 56550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5) 57550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4) 58550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3) 59550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_RESET (1 << 2) 60550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1) 61550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0) 62550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 63550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/*OTG status register */ 64550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c) 65550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8) 66550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT_SESS_END (1 << 7) 67550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6) 68550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5) 69550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4) 70550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3) 71550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2) 72550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0) 73550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1) 74550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0) 75550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 76550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010) 77550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi# define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31) 78550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi# define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) 79550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014) 80550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 81550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* PRCM configuration register */ 82550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018) 83550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_CONF_SFW_CPEN (1 << 24) 84550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) 85550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 86550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* PRCM management register */ 87550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c) 88550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25) 89550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24) 90550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20) 91550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN (1 << 19) 92550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18) 93550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17) 94550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10) 95550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9) 96550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8) 97550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4) 98550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3) 99550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2) 100550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1) 101550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0) 102550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 103550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Wake-up source clear and mask registers */ 104550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020) 105550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028) 106550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c) 107550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13) 108550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WGPIO_7 (1 << 12) 109550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WGPIO_6 (1 << 11) 110550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WGPIO_5 (1 << 10) 111550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WGPIO_4 (1 << 9) 112550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WGPIO_3 (1 << 8) 113550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WGPIO_2 (1 << 7) 114550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WGPIO_1 (1 << 6) 115550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WGPIO_0 (1 << 5) 116550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */ 117550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */ 118550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */ 119550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */ 120550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */ 121550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 122550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030) 123550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034) 124550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038) 125550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c) 126550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040) 127550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044) 128550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048) 129550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c) 130550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050) 131550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054) 132550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058) 133550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c) 134550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060) 135550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064) 136550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068) 137550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c) 138550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 139550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* NOR flash interrupt source registers */ 140550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070) 141550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074) 142550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078) 143550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c) 144550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24) 145550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_CORE (1 << 17) 146550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16) 147550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15) 148550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14) 149550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_DEV_WAKEUP (1 << 13) 150550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_DEV_READY (1 << 12) 151550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_TX (1 << 9) 152550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_RX (1 << 8) 153550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7) 154550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6) 155550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_DISCON (1 << 5) 156550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_CONN (1 << 4) 157550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_SOF (1 << 3) 158550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2) 159550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_RESUME (1 << 1) 160550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0) 161550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 162550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* NOR flash interrupt registers reserved bits. Must be written as 0 */ 163550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_MASK_RESERVED_17 (0x3fff << 17) 164550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_MASK_RESERVED_13 (1 << 13) 165550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_MASK_RESERVED_8 (0xf << 8) 166550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_RESERVED_26 (0x1f << 26) 167550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_RESERVED_18 (0x3f << 18) 168550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_RESERVED_10 (0x03 << 10) 169550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 170550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Reserved bits for NOR flash interrupt mask and clear register */ 171550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_MASK_RESERVED_BITS (TUSB_INT_MASK_RESERVED_17 | \ 172550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi TUSB_INT_MASK_RESERVED_13 | \ 173550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi TUSB_INT_MASK_RESERVED_8) 174550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 175550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Reserved bits for NOR flash interrupt status register */ 176550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_SRC_RESERVED_BITS (TUSB_INT_SRC_RESERVED_26 | \ 177550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi TUSB_INT_SRC_RESERVED_18 | \ 178550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi TUSB_INT_SRC_RESERVED_10) 179550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 180550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080) 181550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084) 182550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100) 183550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104) 184550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108) 185550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148) 186550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 187550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Offsets from each ep base register */ 188550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_EP_TX_OFFSET 0x10c /* EP_IN in docs */ 189550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_EP_RX_OFFSET 0x14c /* EP_OUT in docs */ 190550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_EP_MAX_PACKET_SIZE_OFFSET 0x188 191550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 192550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8) 193550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4) 194550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8) 195550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 196550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Device System & Control register bitfields */ 197550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18) 198550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17) 199550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16) 200550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) 201550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) 202550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v) (((v) & 0x3f) << 20) 203550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v) (((v) & 0xf) << 16) 204550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_EP0_CONFIG_SW_EN (1 << 8) 205550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_EP0_CONFIG_DIR_TX (1 << 7) 206550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) 207550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_EP_CONFIG_SW_EN (1 << 31) 208550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) 209550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_PROD_TEST_RESET_VAL 0xa596 210550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_EP_FIFO(ep) (TUSB_FIFO_BASE + (ep) * 0x20) 211550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 212550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8) 213550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc) 214550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DIDR1_HI_CHIP_REV(v) (((v) >> 17) & 0xf) 215550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DIDR1_HI_REV_20 0 216550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DIDR1_HI_REV_30 1 217550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_DIDR1_HI_REV_31 2 218550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 219550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_REV_10 0x10 220550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_REV_20 0x20 221550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_REV_30 0x30 222550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define TUSB_REV_31 0x31 223550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 224550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#endif /* __TUSB6010_H__ */ 225